WO2013086908A1 - Unité de mémoire otp et procédé de fabrication de celle-ci - Google Patents

Unité de mémoire otp et procédé de fabrication de celle-ci Download PDF

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Publication number
WO2013086908A1
WO2013086908A1 PCT/CN2012/083975 CN2012083975W WO2013086908A1 WO 2013086908 A1 WO2013086908 A1 WO 2013086908A1 CN 2012083975 W CN2012083975 W CN 2012083975W WO 2013086908 A1 WO2013086908 A1 WO 2013086908A1
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WO
WIPO (PCT)
Prior art keywords
gate
dielectric layer
sidewall
otp memory
silicon nitride
Prior art date
Application number
PCT/CN2012/083975
Other languages
English (en)
Chinese (zh)
Inventor
蔡建祥
许宗能
杜鹏
周玮
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无锡华润上华科技有限公司
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Publication date
Application filed by 无锡华润上华科技有限公司 filed Critical 无锡华润上华科技有限公司
Publication of WO2013086908A1 publication Critical patent/WO2013086908A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/36—Gate programmed, e.g. different gate material or no gate
    • H10B20/367—Gate dielectric programmed, e.g. different thickness

Definitions

  • the present invention relates to a device structure of a memory and related fabrication processes, and more particularly to a one-time programmable (OTP, one time)
  • OTP one-time programmable
  • OTP memory has been widely used in recent years due to its low cost and compatibility with logic processes.
  • OTP memory is usually composed of an OTP memory cell array and a matching peripheral circuit.
  • the existing OTP memory cell is generally composed of a coupling capacitor (or NMOS strobe) plus a floating gate transistor (NMOS transistor), which can pass heat.
  • Electron injection (HCI, hot Carrier) is programmed to store electrons on the polysilicon floating gate, and then use the magnitude of the threshold voltage to determine whether there is electron injection on the floating gate, thereby characterizing 0 or 1 in one cell.
  • the technical problem to be solved by the present invention is to provide a novel OTP memory unit and a manufacturing method thereof.
  • the OTP memory unit has a small occupied area, a simple manufacturing method, and a low cost.
  • An OTP storage unit comprising:
  • a silicon nitride sidewall structure located around the gate
  • the silicon nitride sidewall structure is used for storing electrons.
  • the semiconductor substrate is a single crystal silicon substrate.
  • the material of the gate dielectric layer is silicon oxide or other high dielectric constant material.
  • the material of the gate is polysilicon.
  • the material of the sidewall dielectric layer is silicon oxide.
  • the silicon nitride sidewall structure has a thickness of 500-1000 nm.
  • the sidewall dielectric layer has a thickness of 50 to 100 nm.
  • a method for manufacturing an OTP storage unit includes the following steps:
  • Step 1 forming a gate dielectric layer on the semiconductor substrate, and forming a gate material layer on the gate dielectric layer;
  • Step 2 patterning the gate material layer to form a gate
  • Step 3 forming a sidewall dielectric layer on a sidewall of the gate
  • Step 4 depositing silicon nitride on the gate formed with the sidewall dielectric layer on the sidewall, so that the silicon nitride completely encapsulates the gate and the sidewall dielectric layer;
  • Step 5 removing excess silicon nitride by an etching process, and forming a silicon nitride sidewall structure around the gate of the sidewall formed with the sidewall dielectric layer;
  • Step 6 Form a source and a drain on both sides of the gate.
  • the semiconductor substrate is a single crystal silicon substrate; and the gate material layer is a polysilicon layer.
  • the gate material layer is patterned to form a gate using photolithography and etching processes.
  • the patterning operation of step 2 is performed, and after the step 6 is completed, the protective layer is removed to expose the gate for subsequent processing. Electrode connection.
  • a high temperature oxide layer is deposited on the surface of the gate material layer as the protective layer.
  • a sidewall dielectric layer is formed on the sidewall of the gate by thermal oxidation.
  • step 6 ion implantation is used to form a source and a drain in a semiconductor substrate which is not covered by the silicon nitride spacer structure on both sides of the gate.
  • the OTP memory cell of the present invention is different from the conventional floating gate OTP.
  • the hot electrons are not stored in the floating gate, but the sidewall dielectric structure is used to capture and store the electrons by adding a sidewall dielectric layer between the gate and the sidewall structure. . Therefore, the OTP memory cell of the present invention requires only one transistor structure, and data storage and reading can be realized without an additional strobe or coupling capacitor.
  • the memory structure has a small footprint compared to the conventional floating gate OTP. It is beneficial to increase the storage density of the memory, and the manufacturing method of the structure is compatible with the standard logic process, the process is simple, and the manufacturing cost can be greatly saved.
  • FIG. 1 is a schematic structural diagram of an OTP storage unit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of a principle of an OTP storage unit according to Embodiment 1 of the present invention.
  • FIG. 3 is an I-V characteristic curve of an OTP memory unit according to Embodiment 1 of the present invention.
  • 4a-4h are schematic diagrams showing a manufacturing process of an OTP storage unit according to Embodiment 2 of the present invention.
  • the inventor of the present invention deeply studied the structure and principle of the OTP memory, and designed an OTP with small occupied area, simple structure and low production cost. Storage unit.
  • the OTP memory cell includes: a semiconductor substrate 100; a gate dielectric layer 101 on the semiconductor substrate 100; a gate 102 on the gate dielectric layer 101; a surrounding silicon nitride sidewall structure 104; a sidewall dielectric layer 103 between the gate 102 and the silicon nitride sidewall structure 104; and a source 105 and a drain on both sides of the gate 102 Pole 106.
  • the semiconductor substrate 100 may be a common single crystal silicon substrate; the gate dielectric layer 101 may be a conventional dielectric material, such as silicon oxide. In other embodiments, the gate dielectric layer 101 may also be A high dielectric constant material such as SrTiO 3 , HfO 2 or ZrO 2 ; the material of the gate electrode 102 may preferably be polysilicon; the material of the sidewall dielectric layer 103 may preferably be silicon oxide.
  • the thickness of the silicon nitride sidewall structure 104 may be 500-1000 nm, which is determined according to the specific needs of the device, and serves as a memory unit for storing a core portion of the charge.
  • the sidewall dielectric layer 103 has a relatively thin thickness and may be 50-100 nm, which functions to isolate the silicon nitride sidewall structure from the gate. It should be noted that the dimensions and preferred materials mentioned in this embodiment are merely illustrative. In practical applications, the selection of device dimensions and materials should not be limited thereto.
  • the OTP memory cell can store electrons in the silicon nitride sidewall structure 104 by means of hot electron injection or the like due to the isolation of the sidewall dielectric layer 103, thereby realizing device programming.
  • the silicon nitride material used in the sidewall structure is due to the large number of electron traps in the silicon nitride.
  • the electron mobility in the silicon nitride is extremely low, and the hot electrons are easily trapped by the electron traps in the silicon nitride after being injected into the sidewall structure. Thereby, the hot electron capture efficiency of the OTP memory cell can be improved.
  • the source S and the substrate B are grounded, the drain D is connected to a high voltage (eg, 3-3.6V), and the gate G is connected to a high voltage (eg, 3- 3.6V); at this time, the channel is turned on, and electrons avalanche breakdown occurs in the depletion region near the drain D, so that high-energy hot electrons are injected into the sidewall structure, and silicon nitride captures these electrons to realize data storage. Since the threshold voltage of the device changes after trapping electrons in the sidewall structure, the magnitude of the threshold voltage can be used to determine whether or not electrons are injected into the sidewall structure, thereby characterizing 0 or 1 in one cell.
  • a high voltage eg, 3-3.6V
  • the gate G is connected to a high voltage (eg, 3- 3.6V)
  • the source S and the substrate B are grounded, the drain D is connected to a low voltage (eg, 1-1.8V), and the gate G is connected to a low voltage (eg, 1-1.8V), and is read. Data can be read by taking the threshold voltage.
  • I-V when the storage unit is reading information, I-V
  • the characteristic curve exhibits different output currents due to the presence or absence of stored electrons in the silicon nitride sidewall structure near the drain.
  • the curve (such as a dotted line) is significantly different from the absence of electrons (such as a solid line). In this way, different unit information is stored.
  • the high voltage mentioned in the write data in the present embodiment and the low voltage mentioned in the read data are only exemplified. In practical applications, the range of the operating voltage should not be limited to this, and only needs to be read.
  • the gate and drain access voltages at the time of data are lower than the gate and drain access voltages at the time of writing data.
  • the OTP memory cell can be fabricated as follows:
  • Step 1 as shown in FIG. 4a, a conventional single crystal silicon substrate is provided as the semiconductor substrate 200, and then a gate dielectric layer 201 is formed on the surface of the single crystal silicon substrate.
  • a gate oxide layer can be formed by thermal oxidation.
  • other dielectric materials may be formed by using a deposition method or the like as the gate dielectric layer 201, such as a high dielectric constant material such as SrTiO 3 , HfO 2 or ZrO 2 ; then a gate material is formed on the gate dielectric layer 201.
  • Layer 202 such as a polysilicon layer, is deposited as the gate material layer 202.
  • a protective layer 203 is formed on the surface of the gate material layer 202, for example, a high temperature oxide layer (HTO) is deposited; then, as shown in FIG. 4c, The gate material layer 202 is patterned using photolithography and etching processes to form a gate.
  • the protective layer 203 is used to protect the gate material from subsequent processes.
  • Step 3 silicon oxide is formed as a sidewall dielectric layer 204 on the sidewall of the gate by thermal oxidation.
  • the thickness of the sidewall dielectric layer 204 is preferably 50-100 nm.
  • Step 4 As shown in FIG. 4e, silicon nitride 205 is deposited on the gate of the sidewall formed with the sidewall dielectric layer 204, so that the silicon nitride 205 completely encapsulates the gate and sidewall dielectric layers 204.
  • Step 5 As shown in FIG. 4f, the excess silicon nitride 205 is removed by an etching process, and a silicon nitride sidewall structure 206 is formed around the gate of the sidewall formed with the sidewall dielectric layer 204.
  • the thickness of the silicon nitride sidewall structure 206 is preferably 500-1000 nm.
  • the removal of excess silicon nitride 205 can be reversed by a dry etching process, and the reverse etching process does not require a mask.
  • the result of the reverse etching is that most of the silicon oxide 205 is etched away, only at the gate. A portion of the silicon oxide 205 remains around the sidewalls, and the remaining silicon oxide 205 is the silicon nitride sidewall structure 206.
  • a source 207 and a drain 208 are formed on both sides of the gate.
  • the source 207 and the drain 208 are formed in the semiconductor substrate 200 not covered by the silicon nitride sidewall structure 206 on both sides of the gate by ion implantation.
  • the source-drain light doping (LDD) is not performed in the process of fabricating the memory cell, which can improve the injection efficiency of the hot electrons.
  • the protective layer 203 is removed to expose the gate for subsequent electrode connections.
  • a person skilled in the art can fabricate a memory cell array composed of the OTP memory cells and a peripheral circuit matched thereto, thereby forming a complete OTP memory.
  • Applying the OTP memory to the system integrated chip or the micro processing chip can improve the flexibility of the system coding and can greatly save the manufacturing cost.

Abstract

L'invention concerne une unité de mémoire programmable une seule fois (OTP) et un procédé de fabrication de celle-ci, l'unité de mémoire OTP comprenant : un substrat semiconducteur; une couche diélectrique de gâchette située sur le substrat semiconducteur; une électrode de gâchette (G) située sur la couche diélectrique de gâchette; une structure de paroi latérale en nitrure de silicium située autour de l'électrode de gâchette; une couche diélectrique de paroi latérale située entre l'électrode de gâchette et la structure de paroi latérale en nitrure de silicium; et une électrode de source (S) ainsi qu'une électrode de drain (D) situées des deux côtés de l'électrode de gâchette. L'unité de mémoire OTP ne stocke pas des électrons thermiques dans une gâchette flottante, mais utilise la structure de paroi latérale pour capturer et stocker les électrons. Le résultat est que les données peuvent être stockées et lues sans tube de gâchette ou condensateur de couplage supplémentaire. En comparaison des OTP traditionnelles à gâchette flottante, l'unité de mémoire OTP occupe une plus petite surface, ce qui améliore la densité de mémoire d'un dispositif de mémorisation. De plus, le procédé de fabrication de celle-ci est compatible avec la procédure logique standard et présente un processus simple, ce qui permet de réaliser des économies importantes au niveau des coûts de fabrication.
PCT/CN2012/083975 2011-12-13 2012-11-02 Unité de mémoire otp et procédé de fabrication de celle-ci WO2013086908A1 (fr)

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Application Number Priority Date Filing Date Title
CN201110413801.7A CN103165614B (zh) 2011-12-13 2011-12-13 一种otp存储单元及其制作方法
CN201110413801.7 2011-12-13

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WO2013086908A1 true WO2013086908A1 (fr) 2013-06-20

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US10127993B2 (en) 2015-07-29 2018-11-13 National Chiao Tung University Dielectric fuse memory circuit and operation method thereof

Citations (6)

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Publication number Priority date Publication date Assignee Title
US5401993A (en) * 1990-08-30 1995-03-28 Sharp Kabushiki Kaisha Non-volatile memory
US6518614B1 (en) * 2002-02-19 2003-02-11 International Business Machines Corporation Embedded one-time programmable non-volatile memory using prompt shift device
CN1551361A (zh) * 2003-05-15 2004-12-01 ������������ʽ���� 半导体存储装置及其制造方法、半导体装置、便携电子设备以及ic卡
CN1551362A (zh) * 2003-05-14 2004-12-01 ������������ʽ���� 半导体存储装置、半导体装置和便携电子设备
US20090027942A1 (en) * 2004-04-26 2009-01-29 Applied Interllectual Properties Semiconductor memory unit and array
US20100059812A1 (en) * 2008-09-11 2010-03-11 Jin Ha Park Flash memory device and method for manufacturing the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101621035B (zh) * 2008-07-02 2011-08-17 中芯国际集成电路制造(上海)有限公司 具有otp功能的非晶硅monos或mas存储单元结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5401993A (en) * 1990-08-30 1995-03-28 Sharp Kabushiki Kaisha Non-volatile memory
US6518614B1 (en) * 2002-02-19 2003-02-11 International Business Machines Corporation Embedded one-time programmable non-volatile memory using prompt shift device
CN1551362A (zh) * 2003-05-14 2004-12-01 ������������ʽ���� 半导体存储装置、半导体装置和便携电子设备
CN1551361A (zh) * 2003-05-15 2004-12-01 ������������ʽ���� 半导体存储装置及其制造方法、半导体装置、便携电子设备以及ic卡
US20090027942A1 (en) * 2004-04-26 2009-01-29 Applied Interllectual Properties Semiconductor memory unit and array
US20100059812A1 (en) * 2008-09-11 2010-03-11 Jin Ha Park Flash memory device and method for manufacturing the same

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CN103165614A (zh) 2013-06-19

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