WO2013086908A1

WO2013086908A1 - Otp memory unit and manufacturing method thereof

Info

Publication number: WO2013086908A1
Application number: PCT/CN2012/083975
Authority: WO
Inventors: 蔡建祥; 许宗能; 杜鹏; 周玮
Original assignee: 无锡华润上华科技有限公司
Priority date: 2011-12-13
Filing date: 2012-11-02
Publication date: 2013-06-20
Also published as: CN103165614B; CN103165614A

Abstract

A one time programmable (OTP) memory unit and manufacturing method thereof, the OTP memory unit comprising: a semiconductor substrate; a gate dielectric layer located on the semiconductor substrate; a gate electrode (G) located on the gate dielectric layer; a silicon nitride side wall structure located around the gate electrode; a side wall dielectric layer located between the gate electrode and the silicon nitride side wall structure; and a source electrode (S) and a drain electrode (D) located at the two sides of the gate electrode. The OTP memory unit does not store thermal electrons in a floating gate, but utilizes the side wall structure to capture and store the electrons. As a result, the data can be stored and read without an additional gate tube or coupling capacitor. Compared to traditional floating gate OTP, the OTP memory unit occupies a smaller area, thus improving the memory density of a memorizer. Furthermore, the manufacturing method thereof is compatible with standard logic procedure and has a simple process, thus greatly saving manufacturing cost.

Description

OTP storage unit and manufacturing method thereof

[Technical Field]

The present invention relates to a device structure of a memory and related fabrication processes, and more particularly to a one-time programmable (OTP, one time) The storage unit structure of the memory and the manufacturing method thereof belong to the field of semiconductor device manufacturing.

【Background technique】

At present, popular system integrated chips or micro-processing chips require a memory to store system code. Since the manufacturing process of logic and conventional memory is very different, the more conventional way is to introduce read-only memory (ROM) into the logic process. However, the production of read-only memory needs to be defined in the process of wafer splicing, which restricts the flexibility of system coding to some extent. For this shortcoming of read-only memory, the logic chip and the memory chip can be separately packaged by the circuit board, so that the system code can be changed by the change of the content of the memory chip. However, in this way, because two or more chips are required, the manufacturing cost is quite high, the cost of the package is also high, and the area of the chip is also large. At the same time, since the signal needs to be transmitted through the circuit board, it is easy to be received. Noise interference.

A one-time programmable (OTP) memory has been widely used in recent years due to its low cost and compatibility with logic processes. By adding an OTP memory to an integrated circuit chip instead of a conventional ROM read-only memory, the flexibility of the chip system code can be greatly improved. That is to say, when the wafer is finished, the code can be written into the OTP memory by means of coding, so that it can be differentiated for different customers and products, that is, different codes can be provided for different customers to achieve different The function. OTP memory is usually composed of an OTP memory cell array and a matching peripheral circuit. The existing OTP memory cell is generally composed of a coupling capacitor (or NMOS strobe) plus a floating gate transistor (NMOS transistor), which can pass heat. Electron injection (HCI, hot Carrier It is programmed to store electrons on the polysilicon floating gate, and then use the magnitude of the threshold voltage to determine whether there is electron injection on the floating gate, thereby characterizing 0 or 1 in one cell.

However, such an existing OTP memory cell requires a coupling capacitor for each floating gate transistor, and the capacitive coupling portion generally has a large area, which greatly occupies the area of the memory, and the manufacturing process thereof is also complicated.

[Summary of the Invention]

The technical problem to be solved by the present invention is to provide a novel OTP memory unit and a manufacturing method thereof. The OTP memory unit has a small occupied area, a simple manufacturing method, and a low cost.

In order to solve the above technical problem, the present invention adopts the following technical solutions:

An OTP storage unit comprising:

Semiconductor substrate

a gate dielectric layer on the semiconductor substrate;

a gate on the gate dielectric layer;

a silicon nitride sidewall structure located around the gate;

a sidewall dielectric layer between the gate and the silicon nitride sidewall structure;

And a source and a drain on both sides of the gate;

Wherein, the silicon nitride sidewall structure is used for storing electrons.

As a preferred aspect of the invention, the semiconductor substrate is a single crystal silicon substrate.

As a preferred embodiment of the present invention, the material of the gate dielectric layer is silicon oxide or other high dielectric constant material.

As a preferred embodiment of the present invention, the material of the gate is polysilicon.

As a preferred embodiment of the present invention, the material of the sidewall dielectric layer is silicon oxide.

As a preferred embodiment of the present invention, the silicon nitride sidewall structure has a thickness of 500-1000 nm.

As a preferred embodiment of the present invention, the sidewall dielectric layer has a thickness of 50 to 100 nm.

A method for manufacturing an OTP storage unit includes the following steps:

Step 1: forming a gate dielectric layer on the semiconductor substrate, and forming a gate material layer on the gate dielectric layer;

Step 2: patterning the gate material layer to form a gate;

Step 3, forming a sidewall dielectric layer on a sidewall of the gate;

Step 4, depositing silicon nitride on the gate formed with the sidewall dielectric layer on the sidewall, so that the silicon nitride completely encapsulates the gate and the sidewall dielectric layer;

Step 5: removing excess silicon nitride by an etching process, and forming a silicon nitride sidewall structure around the gate of the sidewall formed with the sidewall dielectric layer;

Step 6. Form a source and a drain on both sides of the gate.

As a preferred embodiment of the present invention, in the first step, the semiconductor substrate is a single crystal silicon substrate; and the gate material layer is a polysilicon layer.

As a preferred embodiment of the present invention, in step 2, the gate material layer is patterned to form a gate using photolithography and etching processes.

As a preferred embodiment of the present invention, after the protective layer is formed on the surface of the gate material layer, the patterning operation of step 2 is performed, and after the step 6 is completed, the protective layer is removed to expose the gate for subsequent processing. Electrode connection.

Further preferably, a high temperature oxide layer (HTO) is deposited on the surface of the gate material layer as the protective layer.

As a preferred embodiment of the present invention, in the third step, a sidewall dielectric layer is formed on the sidewall of the gate by thermal oxidation.

As a preferred embodiment of the present invention, in step 6, ion implantation is used to form a source and a drain in a semiconductor substrate which is not covered by the silicon nitride spacer structure on both sides of the gate.

The beneficial effects of the invention are:

The OTP memory cell of the present invention is different from the conventional floating gate OTP. The hot electrons are not stored in the floating gate, but the sidewall dielectric structure is used to capture and store the electrons by adding a sidewall dielectric layer between the gate and the sidewall structure. . Therefore, the OTP memory cell of the present invention requires only one transistor structure, and data storage and reading can be realized without an additional strobe or coupling capacitor. The memory structure has a small footprint compared to the conventional floating gate OTP. It is beneficial to increase the storage density of the memory, and the manufacturing method of the structure is compatible with the standard logic process, the process is simple, and the manufacturing cost can be greatly saved.

[Description of the Drawings]

1 is a schematic structural diagram of an OTP storage unit according to Embodiment 1 of the present invention;

2 is a schematic diagram of a principle of an OTP storage unit according to Embodiment 1 of the present invention;

3 is an I-V characteristic curve of an OTP memory unit according to Embodiment 1 of the present invention;

4a-4h are schematic diagrams showing a manufacturing process of an OTP storage unit according to Embodiment 2 of the present invention.

【detailed description】

The preferred embodiments of the present invention are further described with reference to the accompanying drawings.

In order to improve the OTP memory density, simplify the preparation process and reduce the production cost, the inventor of the present invention deeply studied the structure and principle of the OTP memory, and designed an OTP with small occupied area, simple structure and low production cost. Storage unit.

Embodiment 1

As shown in FIG. 1, the OTP memory cell includes: a semiconductor substrate 100; a gate dielectric layer 101 on the semiconductor substrate 100; a gate 102 on the gate dielectric layer 101; a surrounding silicon nitride sidewall structure 104; a sidewall dielectric layer 103 between the gate 102 and the silicon nitride sidewall structure 104; and a source 105 and a drain on both sides of the gate 102 Pole 106.

In this embodiment, the semiconductor substrate 100 may be a common single crystal silicon substrate; the gate dielectric layer 101 may be a conventional dielectric material, such as silicon oxide. In other embodiments, the gate dielectric layer 101 may also be A high dielectric constant material such as SrTiO ₃ , HfO ₂ or ZrO ₂ ; the material of the gate electrode 102 may preferably be polysilicon; the material of the sidewall dielectric layer 103 may preferably be silicon oxide. The thickness of the silicon nitride sidewall structure 104 may be 500-1000 nm, which is determined according to the specific needs of the device, and serves as a memory unit for storing a core portion of the charge. The sidewall dielectric layer 103 has a relatively thin thickness and may be 50-100 nm, which functions to isolate the silicon nitride sidewall structure from the gate. It should be noted that the dimensions and preferred materials mentioned in this embodiment are merely illustrative. In practical applications, the selection of device dimensions and materials should not be limited thereto.

The OTP memory cell can store electrons in the silicon nitride sidewall structure 104 by means of hot electron injection or the like due to the isolation of the sidewall dielectric layer 103, thereby realizing device programming. The silicon nitride material used in the sidewall structure is due to the large number of electron traps in the silicon nitride. The electron mobility in the silicon nitride is extremely low, and the hot electrons are easily trapped by the electron traps in the silicon nitride after being injected into the sidewall structure. Thereby, the hot electron capture efficiency of the OTP memory cell can be improved.

As shown in FIG. 2, when data is written to the OTP memory cell, the source S and the substrate B are grounded, the drain D is connected to a high voltage (eg, 3-3.6V), and the gate G is connected to a high voltage (eg, 3- 3.6V); at this time, the channel is turned on, and electrons avalanche breakdown occurs in the depletion region near the drain D, so that high-energy hot electrons are injected into the sidewall structure, and silicon nitride captures these electrons to realize data storage. Since the threshold voltage of the device changes after trapping electrons in the sidewall structure, the magnitude of the threshold voltage can be used to determine whether or not electrons are injected into the sidewall structure, thereby characterizing 0 or 1 in one cell. When reading data to the OTP memory cell, the source S and the substrate B are grounded, the drain D is connected to a low voltage (eg, 1-1.8V), and the gate G is connected to a low voltage (eg, 1-1.8V), and is read. Data can be read by taking the threshold voltage. As shown in Figure 3, when the storage unit is reading information, I-V The characteristic curve exhibits different output currents due to the presence or absence of stored electrons in the silicon nitride sidewall structure near the drain. When the cell stores electrons, the curve (such as a dotted line) is significantly different from the absence of electrons (such as a solid line). In this way, different unit information is stored. It should be noted that the high voltage mentioned in the write data in the present embodiment and the low voltage mentioned in the read data are only exemplified. In practical applications, the range of the operating voltage should not be limited to this, and only needs to be read. The gate and drain access voltages at the time of data are lower than the gate and drain access voltages at the time of writing data.

Embodiment 2

Referring to Figures 4a-4h, the OTP memory cell can be fabricated as follows:

Step 1, as shown in FIG. 4a, a conventional single crystal silicon substrate is provided as the semiconductor substrate 200, and then a gate dielectric layer 201 is formed on the surface of the single crystal silicon substrate. For example, a gate oxide layer can be formed by thermal oxidation. Of course, other dielectric materials may be formed by using a deposition method or the like as the gate dielectric layer 201, such as a high dielectric constant material such as SrTiO ₃ , HfO ₂ or ZrO ₂ ; then a gate material is formed on the gate dielectric layer 201. Layer 202, such as a polysilicon layer, is deposited as the gate material layer 202.

Step 2, as shown in FIG. 4b, in this embodiment, a protective layer 203 is formed on the surface of the gate material layer 202, for example, a high temperature oxide layer (HTO) is deposited; then, as shown in FIG. 4c, The gate material layer 202 is patterned using photolithography and etching processes to form a gate. The protective layer 203 is used to protect the gate material from subsequent processes.

Step 3: As shown in FIG. 4d, silicon oxide is formed as a sidewall dielectric layer 204 on the sidewall of the gate by thermal oxidation. The thickness of the sidewall dielectric layer 204 is preferably 50-100 nm.

Step 4: As shown in FIG. 4e, silicon nitride 205 is deposited on the gate of the sidewall formed with the sidewall dielectric layer 204, so that the silicon nitride 205 completely encapsulates the gate and sidewall dielectric layers 204.

Step 5: As shown in FIG. 4f, the excess silicon nitride 205 is removed by an etching process, and a silicon nitride sidewall structure 206 is formed around the gate of the sidewall formed with the sidewall dielectric layer 204. The thickness of the silicon nitride sidewall structure 206 is preferably 500-1000 nm. Among them, the removal of excess silicon nitride 205 can be reversed by a dry etching process, and the reverse etching process does not require a mask. The result of the reverse etching is that most of the silicon oxide 205 is etched away, only at the gate. A portion of the silicon oxide 205 remains around the sidewalls, and the remaining silicon oxide 205 is the silicon nitride sidewall structure 206.

Step 6. As shown in FIG. 4g, a source 207 and a drain 208 are formed on both sides of the gate. In the present embodiment, the source 207 and the drain 208 are formed in the semiconductor substrate 200 not covered by the silicon nitride sidewall structure 206 on both sides of the gate by ion implantation. It should be noted that the source-drain light doping (LDD) is not performed in the process of fabricating the memory cell, which can improve the injection efficiency of the hot electrons.

Finally, as shown in Figure 4h, the protective layer 203 is removed to expose the gate for subsequent electrode connections.

According to the above method, a person skilled in the art can fabricate a memory cell array composed of the OTP memory cells and a peripheral circuit matched thereto, thereby forming a complete OTP memory. Applying the OTP memory to the system integrated chip or the micro processing chip can improve the flexibility of the system coding and can greatly save the manufacturing cost.

It is to be understood that the term "comprises", "comprising" or any other variants thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device comprising a plurality of elements includes not only those elements. It also includes other elements that are not explicitly listed, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising", without limiting the invention, does not exclude the presence of additional elements in the process, method, article, or device.

The above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention should be as set forth in the claims.

Claims

An OTP storage unit, comprising:

Semiconductor substrate

a gate dielectric layer on the semiconductor substrate;

a gate on the gate dielectric layer;

a silicon nitride sidewall structure located around the gate;

a sidewall dielectric layer between the gate and the silicon nitride sidewall structure;

And a source and a drain on both sides of the gate;

Wherein, the silicon nitride sidewall structure is used for storing electrons.
The OTP memory cell of claim 1 wherein said semiconductor substrate is a single crystal silicon substrate.
The OTP memory cell of claim 1 wherein the material of the gate dielectric layer is silicon oxide or a high dielectric constant material.
The OTP memory cell of claim 1 wherein the material of the gate is polysilicon.
The OTP memory cell of claim 1 wherein the material of the sidewall dielectric layer is silicon oxide.
The OTP memory cell according to claim 1, wherein the silicon nitride spacer structure has a thickness of 500-1000 nm.
The OTP memory cell of claim 1 wherein said sidewall dielectric layer has a thickness of 50-100 nm.
A method for manufacturing an OTP storage unit, comprising the steps of:

Step 1: forming a gate dielectric layer on the semiconductor substrate, and forming a gate material layer on the gate dielectric layer;

Step 2: patterning the gate material layer to form a gate;

Step 3, forming a sidewall dielectric layer on a sidewall of the gate;

Step 4, depositing silicon nitride on the gate formed with the sidewall dielectric layer on the sidewall, so that the silicon nitride completely encapsulates the gate and the sidewall dielectric layer;

Step 5: removing excess silicon nitride by an etching process, and forming a silicon nitride sidewall structure around the gate of the sidewall formed with the sidewall dielectric layer;

Step 6. Form a source and a drain on both sides of the gate.
The method of fabricating an OTP memory cell according to claim 8, wherein in the first step, the semiconductor substrate is a single crystal silicon substrate; and the gate material layer is a polysilicon layer.
The method of fabricating an OTP memory cell according to claim 8, wherein in the second step, the gate material layer is patterned to form a gate by photolithography and etching processes.
The method for fabricating an OTP memory cell according to claim 8, wherein after the protective layer is formed on the surface of the gate material layer, the patterning operation of the second step is performed until the step 6 is completed. The protective layer exposes the gate for subsequent electrode connections.
The method of fabricating an OTP memory cell according to claim 11, wherein a high temperature oxide layer is deposited on the surface of the gate material layer as the protective layer.
The method of fabricating an OTP memory cell according to claim 8, wherein in the third step, a sidewall dielectric layer is formed on the sidewall of the gate by thermal oxidation.
The method of fabricating an OTP memory cell according to claim 8, wherein in step 6, ion implantation is used to form a source and a semiconductor substrate on both sides of the gate which are not covered by the silicon nitride sidewall structure. Drain.