CN103165614B - A kind of OTP memory cell and preparation method thereof - Google Patents
A kind of OTP memory cell and preparation method thereof Download PDFInfo
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- CN103165614B CN103165614B CN201110413801.7A CN201110413801A CN103165614B CN 103165614 B CN103165614 B CN 103165614B CN 201110413801 A CN201110413801 A CN 201110413801A CN 103165614 B CN103165614 B CN 103165614B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 66
- 239000000463 material Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000007667 floating Methods 0.000 abstract description 9
- 239000002784 hot electron Substances 0.000 abstract description 7
- 238000003860 storage Methods 0.000 abstract description 7
- 230000008878 coupling Effects 0.000 abstract description 5
- 238000010168 coupling process Methods 0.000 abstract description 5
- 238000005859 coupling reaction Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 9
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010893 electron trap Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 206010021703 Indifference Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005264 electron capture Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
- H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/36—Gate programmed, e.g. different gate material or no gate
- H10B20/367—Gate dielectric programmed, e.g. different thickness
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of OTP memory cell and preparation method thereof.This OTP memory cell, comprising: Semiconductor substrate; Be positioned at the gate dielectric layer in described Semiconductor substrate; Be positioned at the grid on described gate dielectric layer; Be positioned at the silicon nitride spacer structure around described grid; Side wall medium layer between described grid and described silicon nitride spacer structure; And be positioned at source electrode and the drain electrode of described grid both sides.This OTP memory cell hot electron is not be stored in floating boom, utilize sidewall structure to capture and store electrons, therefore, do not need extra gate tube or coupling capacitance can realize storage and the reading of data, for traditional floating boom OTP, area occupied is little, be conducive to the storage density improving memory, and its manufacture method is mutually compatible with standard logic processing procedure, technique is simple, can save manufacturing cost greatly.
Description
Technical field
The present invention relates to device architecture and the relative production technique of memory, particularly relate to memory cell structure of a kind of disposable programmable (OTP, one time programmable) memory and preparation method thereof, belong to field of manufacturing semiconductor devices.
Background technology
System integrated chip popular at present or micro-chip processor, a memory is all needed to carry out stocking system code, because the Making programme of logic and conventional memory is widely different, more traditional mode is in logic process, introduce read-only memory (ROM).But being produced in the process of wafer flow of read-only memory just needs definition, constrains the flexibility of system coding to a certain extent.For this shortcoming of read-only memory, can by circuit board respectively logic chip together with memory chip package, like this system code can be changed by the change of memory chip content.But such mode is because need two pieces or above chip, the height that manufacturing cost can be suitable, and the cost of encapsulation also can be very high, and the area of chip is also very large, meanwhile, because signal demand is transmitted by circuit board, is easy to be subject to noise interference.
A kind of disposable programmable (OTP) memory, because its cost is lower and mutually compatible with logic process, is widely used in recent years.Carrying out alternative traditional ROM read-only memory by adding otp memory in integrated circuit (IC) chip, the flexibility of chip system code can be improved greatly.That is, after wafer flow terminates, by the form of coding, code can be write otp memory, like this can for different clients and Realization of Product indifference, different code namely can be provided to realize different functions for different clients.Otp memory is made up of OTP memory cell array and the peripheral circuit that matches with it usually, existing OTP memory cell generally adds a floating transistor (nmos pass transistor) by a coupling capacitance (or NMOS gate tube) and forms, (HCI can be injected by hot electron, hotcarrier injection) etc. method it is programmed, make electron storage on multi-crystal silicon floating bar, then utilize the size of threshold voltage to judge on floating boom with or without injection electronics, go out 0 or 1 a cell attribute thus.
But this existing OTP memory cell each floating transistor corresponding needs a coupling capacitance, and the usual area of capacitive coupling part is comparatively large, occupy the area of memory greatly, and its manufacturing process is also more complicated.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of novel OTP memory cell and preparation method thereof, and this OTP memory cell area occupied is little, and manufacture method is comparatively simple, and cost is lower.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of OTP memory cell, comprising:
Semiconductor substrate;
Be positioned at the gate dielectric layer in described Semiconductor substrate;
Be positioned at the grid on described gate dielectric layer;
Be positioned at the silicon nitride spacer structure around described grid;
Side wall medium layer between described grid and described silicon nitride spacer structure;
And be positioned at source electrode and the drain electrode of described grid both sides;
Wherein, described silicon nitride spacer structure is used for store electrons.
As preferred version of the present invention, described Semiconductor substrate is monocrystalline substrate.
As preferred version of the present invention, the material of described gate dielectric layer is silica or other high dielectric constant materials.
As preferred version of the present invention, the material of described grid is polysilicon.
As preferred version of the present invention, the material of described side wall medium layer is silica.
As preferred version of the present invention, the thickness of described silicon nitride spacer structure is 500-1000nm.
As preferred version of the present invention, the thickness of described side wall medium layer is 50-100nm.
A manufacture method for OTP memory cell, comprises the following steps:
Step one, on a semiconductor substrate formation one deck gate dielectric layer, then one deck gate material layers is formed on described gate dielectric layer;
Step 2, described gate material layers is graphical, form grid;
Step 3, form side wall medium layer at the sidewall of described grid;
Step 4, be formed with side wall medium layer at sidewall grid on deposited silicon nitride, grid and side wall medium layer are wrapped up by silicon nitride completely;
Step 5, utilize etching technics to remove unnecessary silicon nitride, around the grid being formed with side wall medium layer at sidewall, form silicon nitride spacer structure;
Step 6, form source electrode and drain electrode in described grid both sides.
As preferred version of the present invention, in step one, described Semiconductor substrate is monocrystalline substrate; Described gate material layers is polysilicon layer.
As preferred version of the present invention, in step 2, utilize photoetching and etching technics that described gate material layers is graphically formed grid.
As preferred version of the present invention, first after described gate material layers surface forms protective layer, then carry out the graphical operation of step 2, until completing steps six removes described protective layer again, expose grid, to carry out follow-up Electrode connection.
Preferred further, described gate material layers surface deposition high temperature oxide layer (HTO) as described protective layer.
As preferred version of the present invention, in step 3, thermal oxidation method is utilized to form side wall medium layer at described gate lateral wall.
As preferred version of the present invention, in step 6, ion implantation is adopted to form source electrode and drain electrode in the Semiconductor substrate that described grid both sides are not covered by silicon nitride spacer structure.
Beneficial effect of the present invention is:
OTP memory cell of the present invention is different from traditional floating boom OTP, and hot electron is not be stored in floating boom, but by setting up side wall medium layer between grid and sidewall structure, utilizes sidewall structure to capture and store electrons.Therefore, OTP memory cell of the present invention only needs a transistor arrangement, do not need extra gate tube or coupling capacitance can realize storage and the reading of data, this storage organization is for traditional floating boom OTP, area occupied is little, be conducive to the storage density improving memory, and the manufacture method of this structure is mutually compatible with standard logic processing procedure, technique is simple, can save manufacturing cost greatly.
Accompanying drawing explanation
Fig. 1 is the structural representation of OTP memory cell in the embodiment of the present invention one;
Fig. 2 is the principle schematic of OTP memory cell in the embodiment of the present invention one;
Fig. 3 is the I-V characteristic curve of OTP memory cell in the embodiment of the present invention one;
Fig. 4 a-4h is the Making programme schematic diagram of OTP memory cell in the embodiment of the present invention two.
Embodiment
The preferred embodiment of the present invention is further illustrated, in order to the accompanying drawing that facilitates illustrated proportionally is not drawn below in conjunction with accompanying drawing.
The present inventor is in order to improve otp memory density, simplify preparation technology, reduce production cost, carried out in depth studying to the structure of otp memory and principle, have devised the OTP memory cell that a kind of area occupied is little, structure simple, cost of manufacture is lower.
Embodiment one
As shown in Figure 1, this OTP memory cell comprises: Semiconductor substrate 100; Be positioned at the gate dielectric layer 101 in described Semiconductor substrate 100; Be positioned at the grid 102 on described gate dielectric layer 101; Be positioned at the silicon nitride spacer structure 104 around described grid 102; Side wall medium layer 103 between described grid 102 and described silicon nitride spacer structure 104; And be positioned at source electrode 105 and the drain electrode 106 of described grid 102 both sides.
In the present embodiment, the monocrystalline substrate that Semiconductor substrate 100 can be preferably common; Described gate dielectric layer 101 can select conventional dielectric material, such as silica, and gate dielectric layer 101 described in other embodiments can also be the high dielectric constant materials such as SrTiO3, HfO2 or ZrO2; The material of described grid 102 can be preferably polysilicon; The material of described side wall medium layer 103 can be preferably silica.The thickness of described silicon nitride spacer structure 104 can be 500-1000nm, and this thickness is determined according to the concrete needs to device, is used for the core position of stored charge as memory cell.The thinner thickness of described side wall medium layer 103 can be 50-100nm, plays the effect of isolation silicon nitride spacer structure and grid.It should be noted that, the size mentioned in the present embodiment and preferred material be exemplarily property explanation only, in actual applications, should be not limited only to this to device size and selecting of material.
This OTP memory cell, due to the buffer action of side wall medium layer 103, by methods such as hot electron injections in silicon nitride spacer structure 104 store electrons, thus can realize device programming.Here sidewall structure selects silicon nitride material to be owing to having a large amount of electron traps in silicon nitride, electronics in silicon nitride mobility is extremely low, hot electron is easily caught by the electron trap of silicon nitride after injecting sidewall structure, thus can improve the hot electron capture rate of OTP memory cell.
As shown in Figure 2, when to this OTP memory cell write data, source S and substrate B ground connection, drain D connects high voltage (as 3-3.6V), and grid G connects high voltage (as 3-3.6V); Now raceway groove conducting, there is avalanche breakdown in the depletion region of electronics near drain D, make high-energy hot electron be injected in sidewall structure, silicon nitride is caught these electronics thus realized the storage of data.Because the threshold voltage of device after trapped electron in sidewall structure can change, therefore can utilize the size of threshold voltage to judge in sidewall structure with or without injection electronics, go out 0 or 1 a cell attribute thus.When reading data to this OTP memory cell, source S and substrate B ground connection, drain D connects low-voltage (as 1-1.8V), and grid G connects low-voltage (as 1-1.8V), gets final product sense data by read threshold voltages.As shown in Figure 3, time memory cell is read information, I-V characteristic curve presents different output currents due to the presence or absence of the silicon nitride spacer structure store electrons near drain electrode, when unit store electrons time, curve (as dotted line) from not have electronics (as solid line) to present significant different, can store different unit informations with this.It should be noted that, high voltage that data mention and the low-voltage only exemplarily property explanation that sense data is mentioned is write in the present embodiment, in actual applications, should be not limited only to this to the scope of operating voltage, grid when only needing read data, drain electrode access voltage are lower than grid during write data, drain electrode access voltage.
Embodiment two
Consult Fig. 4 a-4h, this OTP memory cell can adopt following method to make:
Step one, as shown in fig. 4 a, there is provided conventional monocrystalline substrate as Semiconductor substrate 200, then one deck gate dielectric layer 201 is formed on this monocrystalline substrate surface, thermal oxidation method such as can be adopted to form grid oxide layer, the methods such as deposition can certainly be adopted to form other dielectric materials as gate dielectric layer 201, as high dielectric constant materials such as SrTiO3, HfO2 or ZrO2; Then on described gate dielectric layer 201, form one deck gate material layers 202, such as deposition of polysilicon layer is as described gate material layers 202.
Step 2, as shown in Figure 4 b, the present embodiment preferably, first forms protective layer 203 on described gate material layers 202 surface, such as, deposition one deck high temperature oxide layer (HTO); Then, as illustrated in fig. 4 c, utilize photoetching and etching technics by described gate material layers 202 graphically, form grid.This protective layer 203, for the protection of grid material, avoids subsequent technique to impact it.
Step 3, as shown in figure 4d, utilizes thermal oxidation method to form silica as side wall medium layer 204 at described gate lateral wall.The thickness of described side wall medium layer 204 is preferably 50-100nm.
Step 4, as shown in fig 4e, deposited silicon nitride 205 on the grid being formed with side wall medium layer 204 at sidewall, makes silicon nitride 205 grid and side wall medium layer 204 be wrapped up completely.
Step 5, as shown in fig. 4f, utilize etching technics to remove unnecessary silicon nitride 205, around the grid being formed with side wall medium layer 204 at sidewall, form silicon nitride spacer structure 206.The thickness of described silicon nitride spacer structure 206 is preferably 500-1000nm.Wherein, removing unnecessary silicon nitride 205 can utilize dry etch process to anti-carve, the process that anti-carves does not need mask, the result anti-carved has etched away most silica 205, only remain a part of silica 205 at the lateral wall circumference of grid, the silica 205 remained is silicon nitride spacer structure 206.
Step 6, as shown in figure 4g, forms source electrode 207 and drain electrode 208 in described grid both sides.In the present embodiment, adopt ion implantation in the Semiconductor substrate 200 that described grid both sides are not covered by silicon nitride spacer structure 206, form source electrode 207 and drain electrode 208.It should be noted that in the process that this memory cell makes and do not carry out source and drain light dope (LDD), thermionic injection efficiency can be improved like this.
Finally, as shown in figure 4h, remove described protective layer 203, expose grid, to carry out follow-up Electrode connection.
Those skilled in the art, according to said method, can produce the memory cell array be made up of this OTP memory cell, and the peripheral circuit matched with it, can form complete otp memory thus.This otp memory is applied to the flexibility that can improve system coding in system integrated chip or micro-chip processor, and manufacturing cost can be saved greatly.
It should be noted that, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Above-described embodiment only listing property illustrates principle of the present invention and effect, but not for limiting the present invention.Any person skilled in the art person all can without departing from the spirit and scope of the present invention, modify to above-described embodiment.Therefore, the scope of the present invention, should listed by claims.
Claims (14)
1. an OTP memory cell, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the gate dielectric layer in described Semiconductor substrate;
Be positioned at the grid on described gate dielectric layer;
To be positioned at around described grid and the silicon nitride spacer structure directly contacted with described substrate;
Side wall medium layer between described grid and described silicon nitride spacer structure;
And be positioned at source electrode and the drain electrode of described grid both sides;
Wherein, described silicon nitride spacer structure is used for store electrons.
2. OTP memory cell according to claim 1, is characterized in that: described Semiconductor substrate is monocrystalline substrate.
3. OTP memory cell according to claim 1, is characterized in that: the material of described gate dielectric layer is silica or high dielectric constant material.
4. OTP memory cell according to claim 1, is characterized in that: the material of described grid is polysilicon.
5. OTP memory cell according to claim 1, is characterized in that: the material of described side wall medium layer is silica.
6. OTP memory cell according to claim 1, is characterized in that: the thickness of described silicon nitride spacer structure is 500-1000nm.
7. OTP memory cell according to claim 1, is characterized in that: the thickness of described side wall medium layer is 50-100nm.
8. a manufacture method for OTP memory cell, is characterized in that, comprises the following steps:
Step one, on a semiconductor substrate formation one deck gate dielectric layer, then one deck gate material layers is formed on described gate dielectric layer;
Step 2, described gate material layers is graphical, form grid;
Step 3, form side wall medium layer at the sidewall of described grid;
Step 4, be formed with side wall medium layer at sidewall grid on deposited silicon nitride, grid and side wall medium layer are wrapped up by silicon nitride completely;
Step 5, utilize etching technics to remove unnecessary silicon nitride, form silicon nitride spacer structure around the grid being formed with side wall medium layer at sidewall, and described silicon nitride spacer structure directly contacts with described substrate;
Step 6, form source electrode and drain electrode in described grid both sides.
9. the manufacture method of OTP memory cell according to claim 8, is characterized in that: in step one, and described Semiconductor substrate is monocrystalline substrate; Described gate material layers is polysilicon layer.
10. the manufacture method of OTP memory cell according to claim 8, is characterized in that: in step 2, utilizes photoetching and etching technics that described gate material layers is graphically formed grid.
The manufacture method of 11. OTP memory cell according to claim 8; it is characterized in that: first after described gate material layers surface forms protective layer; carry out the graphical operation of step 2 again; until completing steps six removes described protective layer again; expose grid, to carry out follow-up Electrode connection.
The manufacture method of 12. OTP memory cell according to claim 11, is characterized in that: at described gate material layers surface deposition high temperature oxide layer as described protective layer.
The manufacture method of 13. OTP memory cell according to claim 8, is characterized in that: in step 3, utilizes thermal oxidation method to form side wall medium layer at described gate lateral wall.
The manufacture method of 14. OTP memory cell according to claim 8, is characterized in that: in step 6, adopts ion implantation to form source electrode and drain electrode in the Semiconductor substrate that described grid both sides are not covered by silicon nitride spacer structure.
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| CN201110413801.7A CN103165614B (en) | 2011-12-13 | 2011-12-13 | A kind of OTP memory cell and preparation method thereof |
| PCT/CN2012/083975 WO2013086908A1 (en) | 2011-12-13 | 2012-11-02 | Otp memory unit and manufacturing method thereof |
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| CN201110413801.7A CN103165614B (en) | 2011-12-13 | 2011-12-13 | A kind of OTP memory cell and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10127993B2 (en) | 2015-07-29 | 2018-11-13 | National Chiao Tung University | Dielectric fuse memory circuit and operation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101621035A (en) * | 2008-07-02 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | Amorphous silicon MONOS or MAS memory cell structure with OTP function |
| US20100059812A1 (en) * | 2008-09-11 | 2010-03-11 | Jin Ha Park | Flash memory device and method for manufacturing the same |
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| JP2597741B2 (en) * | 1990-08-30 | 1997-04-09 | シャープ株式会社 | Non-volatile memory device |
| US6518614B1 (en) * | 2002-02-19 | 2003-02-11 | International Business Machines Corporation | Embedded one-time programmable non-volatile memory using prompt shift device |
| JP2004342767A (en) * | 2003-05-14 | 2004-12-02 | Sharp Corp | Semiconductor memory, semiconductor device, and portable electronic equipment |
| US7129539B2 (en) * | 2003-05-15 | 2006-10-31 | Sharp Kabushiki Kaisha | Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card |
| US20090027942A1 (en) * | 2004-04-26 | 2009-01-29 | Applied Interllectual Properties | Semiconductor memory unit and array |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101621035A (en) * | 2008-07-02 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | Amorphous silicon MONOS or MAS memory cell structure with OTP function |
| US20100059812A1 (en) * | 2008-09-11 | 2010-03-11 | Jin Ha Park | Flash memory device and method for manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10127993B2 (en) | 2015-07-29 | 2018-11-13 | National Chiao Tung University | Dielectric fuse memory circuit and operation method thereof |
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| WO2013086908A1 (en) | 2013-06-20 |
| CN103165614A (en) | 2013-06-19 |
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