WO2013086729A1 - 测试系统 - Google Patents

测试系统 Download PDF

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Publication number
WO2013086729A1
WO2013086729A1 PCT/CN2011/084100 CN2011084100W WO2013086729A1 WO 2013086729 A1 WO2013086729 A1 WO 2013086729A1 CN 2011084100 W CN2011084100 W CN 2011084100W WO 2013086729 A1 WO2013086729 A1 WO 2013086729A1
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WO
WIPO (PCT)
Prior art keywords
electrode
thin film
test
film transistor
pads
Prior art date
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PCT/CN2011/084100
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English (en)
French (fr)
Inventor
陈政鸿
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/381,071 priority Critical patent/US9293073B2/en
Publication of WO2013086729A1 publication Critical patent/WO2013086729A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07385—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Definitions

  • the present invention relates to the field of testing technology, and in particular to a testing system capable of reducing testing costs.
  • the liquid crystal display device mainly includes a liquid crystal panel and a backlight module.
  • the liquid crystal panel includes a thin film transistor (Thin Film) Transistor, TFT) substrate, a color filter (Color Filter, a CF substrate and a liquid crystal layer disposed between the thin film transistor substrate and the color filter substrate.
  • TFT Thin Film Transistor
  • Polymer Stabilization Vertical Align Polymer Stabilization Vertical Align
  • array process array process
  • assembly process cell
  • the thin film transistor substrate must be tested to check whether components on the thin film transistor substrate, such as thin film transistors, are functioning properly.
  • FIG. 1 is a schematic diagram of a test system in the prior art.
  • the test system includes a probe frame (probe Frame) 10, a plurality of probes 12 and a thin film transistor substrate (Thin Film Transistor, TFT) 14.
  • the probe 12 is disposed on the probe frame 10 and is made of a resilient metal material.
  • a plurality of pads P1 to P5 must be formed on the thin film transistor substrate, and components (not shown) that require an input signal are electrically connected to the pads P1 to P5, respectively.
  • the probe 12 of the probe frame 10 is aligned with and in contact with the corresponding pads P1 to P5 to check whether the components on the thin film transistor substrate 14 are functioning normally.
  • FIG. 2 is a schematic diagram of another test system in the prior art.
  • the test system of FIG. 2 includes pads P1 ⁇ P5 and P1' ⁇ P5', and the pads P1 ⁇ P5 are electrically connected to the pads P1' ⁇ P5', respectively. That is, the number of pads of FIG. 2 is twice the number of pads of FIG.
  • the pads P1 and P1' as an example, when testing is performed, one of the pads P1 and P1' can be arbitrarily selected to apply a test signal through another pair of the pads P1 and P1'.
  • the detection is performed to determine whether there is a problem of poor contact.
  • the alignment of the probe 12 of the probe frame 10 with the corresponding pads P1 ⁇ P5 and P1' ⁇ P5' is adjusted. Or adjust the position of the thin film transistor substrate 14.
  • the number of pads and the number of probes of the test system of FIG. 2 are twice the number of pads and the number of probes of the test system of FIG. 1, increasing the cost of the test system and the complexity of the circuit configuration on the thin film transistor substrate 14.
  • the present invention provides a test system including a thin film transistor substrate and a plurality of probes.
  • the thin film transistor substrate includes a plurality of thin film transistors and a plurality of connection pads, each of the thin film transistors including a first electrode and a second electrode.
  • the thin film transistor substrate further includes a test pad, and one of the first electrode and the second electrode of each thin film transistor is electrically connected to one of the connection pads, and each of the thin film transistors The other of the first electrode and the second electrode and the third electrode are electrically connected to the test pads, and the probes are respectively correspondingly contacted with the connection pads and the test pads, the test welding
  • the pad has a DC voltage, and it is determined whether the connection pads and the corresponding probes are in poor contact by detecting whether the connection pads have the DC voltage.
  • the first electrode is a source
  • the second electrode is a drain
  • the third electrode is a gate
  • the present invention further provides a test system including a thin film transistor substrate, the thin film transistor substrate includes a plurality of thin film transistors and a plurality of connection pads, each of the thin film transistors including a first electrode and a second An electrode and a third electrode, the thin film transistor substrate further includes a test pad, one of the first electrode and the second electrode of each thin film transistor being electrically connected to one of the connection pads, each thin film transistor The other of the first electrode and the second electrode and the third electrode are electrically connected to the test pad.
  • the test system further includes a plurality of probes that are respectively in contact with the connection pads and the test pads.
  • a test signal is applied to the test pad via a probe in contact with the test pad, and the connection solder is judged by respectively detecting whether the connection pads have the test signal. Whether the pad is in poor contact with the corresponding probe.
  • the first electrode is a source
  • the second electrode is a drain
  • the third electrode is a gate
  • Another object of the present invention is to provide a test system to solve the problems of high cost and complicated circuit configuration of the test system in the prior art.
  • the present invention provides a test system including a thin film transistor substrate, the thin film transistor substrate including a plurality of thin film transistors and a plurality of connection pads, each of the thin film transistors including a first electrode and a second electrode And a third electrode, the thin film transistor substrate further includes a first test pad and a second test pad, wherein one of the first electrode and the second electrode of each thin film transistor is electrically connected to the first Testing the pad, the other of the first electrode and the second electrode of each of the thin film transistors being electrically connected to one of the connection pads, and the third electrode of each thin film transistor is electrically connected to the second test pad .
  • the test system further includes a plurality of probes that are respectively in contact with the connection pads, the first test pads, and the second test pads.
  • a first test signal is applied to the first test pad via a probe in contact with the first test pad, and a second test signal is passed through the second test.
  • a probe in contact with the pad is applied to the second test pad, and whether the connection pads are in contact with the corresponding probe is determined by detecting whether the connection pads have the first test signal.
  • the first electrode is a source
  • the second electrode is a drain
  • the third electrode is a gate
  • the present invention solves the problems of high cost and complicated circuit configuration of the test system in the prior art.
  • FIG. 1 is a schematic diagram of a test system in the prior art
  • FIG. 3 is a schematic diagram of a test system in accordance with a preferred embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a test system in accordance with another preferred embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a test system in accordance with a preferred embodiment of the present invention.
  • the test system includes a thin film transistor substrate 30 including a plurality of thin film transistors T1 to T5, a plurality of connection pads R1 to R5, and a test pad TP.
  • Each of the thin film transistors T1 to T5 includes a first electrode, a second electrode, and a third electrode.
  • the first electrode is a source S (source)
  • the second electrode is a drain D (drain)
  • the third electrode is a gate G (gate).
  • the thin film transistors T1 to T5 are elements to be tested on the thin film transistor substrate 30.
  • the drains D of the thin film transistors T1 to T5 are electrically connected to the connection pads R1 to R5, and the source S and the gate G of each of the thin film transistors T1 to T5 are electrically connected to The test pad TP.
  • the test system further includes a plurality of probes 31-36.
  • the probes 31-35 are respectively in contact with the connection pads R1 R R5, and the probes 36 are in contact with the test pads TP.
  • the process of determining whether the pads R1 to R5 are in poor contact with the corresponding probes 31 to 35 is as follows. First, a test signal is applied to the test pad TP via a probe 36 that is in contact with the test pad TP, and whether the connection pads R1 to R5 that are in contact with the probes 31 to 35 are respectively detected. The test signal is provided to determine whether the connection pads R1 R R5 and the corresponding probes 31 to 35 are in poor contact.
  • the test signal is, for example, a DC voltage of 10 volts. It is determined whether the connection pads R1 R R5 and the corresponding probes 31 535 are in poor contact by detecting whether the connection pads R1 R R5 are equal to 10 volts. For example, when the connection pad R1 does not detect 10 volts, it indicates that the connection pad R1 is in poor contact with the corresponding probe 31. Therefore, the pads R1 to R5 and the corresponding probes 31 to 35 need to be re-adjusted. The alignment or repositioning of the thin film transistor substrate 30.
  • the subsequent processes such as the polymer stable vertical alignment process, the array process, the assembly process, or other processes are performed on the thin film transistors T1 to T5. Test results can be guaranteed to be correct.
  • the drains D of the thin film transistors T1 to T5 are electrically connected to the connection pads R1 to R5, respectively, and the gates G and the source S of the thin film transistors T1 to T5 are electrically connected to The test pad TP.
  • the source S of each of the thin film transistors T1 to T5 can be used.
  • the gate G and the drain D of each of the thin film transistors T1 to T5 are electrically connected to the test pads TP, respectively, and are electrically connected to the connection pads R1 to R5.
  • FIG. 4 is a schematic diagram of a test system in accordance with another preferred embodiment of the present invention.
  • the test system includes a thin film transistor substrate 40 including a plurality of thin film transistors T1 to T5, a plurality of connection pads R1 to R5, a first test pad TP1, and a second test pad TP2. .
  • the thin film transistors T1 to T5 and the connection pads R1 to R5 are the same as those of FIG. 3, and the drains D of the thin film transistors T1 to T5 are electrically connected to the connection pads R1 to R5 correspondingly to FIG. This is not to be repeated.
  • Each of the thin film transistors T1 to T5 is an element to be tested on the thin film transistor substrate 40.
  • the thin film transistor substrate 40 of FIG. 4 includes two test pads, that is, the first test pad TP1 and the second test pad TP2, and the thin film transistors T1 ⁇ T5
  • the electrical connection between the gate G and the source S and the first test pad TP1 and the second test pad TP2 is also different from that of FIG. 3.
  • the source S of each of the thin film transistors T1 to T5 is electrically connected to the first test pad TP1, and the gate G of each of the thin film transistors T1 to T5 is electrically connected to the second test pad. TP2.
  • the test system further includes a plurality of probes 31-35 and 46-47, and the probes 31-35 are the same as those of FIG. 3, respectively correspondingly contacting the connection pads R1 R R5, the probes 46 and The first test pad TP1 is in contact, and the probe 47 is in contact with the second test pad TP2.
  • the process of determining whether the pads R1 to R5 are in poor contact with the corresponding probes 31 to 35 is as follows. First, a first test signal is applied to the first test pad TP1 via a probe 46 in contact with the first test pad TP1, and a second test signal is contacted via the second test pad TP2. The probe 47 is applied to the second test pad TP2 to determine the connection by detecting whether the connection pads R1 R R5 in contact with the probes 31 - 35 have the first test signal. Whether the pads R1 to R5 are in poor contact with the corresponding probes 31 to 35.
  • the first test signal is a DC voltage of 10 volts
  • the second test signal is a DC voltage of 5 volts, which is determined by detecting whether the connection pads R1 R R5 are equal to 10 volts respectively. Whether the connection pads R1 to R5 are in poor contact with the corresponding probes 31 to 35. For example, when the connection pad R2 does not detect 10 volts, it indicates that the connection pad R2 is in poor contact with the corresponding probe 32, so the pads R1 to R5 and the corresponding probes 31 to 35 need to be re-adjusted. The alignment or repositioning of the thin film transistor substrate 40.
  • the subsequent processes such as the polymer stable vertical alignment process, the array process, the assembly process, or other processes are performed on the thin film transistors T1 to T5. Test results can be guaranteed to be correct.
  • the drains D of the thin film transistors T1 T T5 are electrically connected to the connection pads R1 R R5 , respectively, and the source S of each of the thin film transistors T1 T T5 is electrically connected to the first The pad TP1 is tested, and the gate G of each of the thin film transistors T1 to T5 is electrically connected to the second test pad TP2. It should be noted that since the drain D and the source S of each of the thin film transistors T1 to T5 can be used in reverse according to the applied test signal, in another embodiment, the source S of each of the thin film transistors T1 to T5 can be used.
  • connection pads R1 R R5 Correspondingly electrically connected to the connection pads R1 R R5, the drain D of each of the thin film transistors T1 T T5 is electrically connected to the first test pad TP1, and the gate G of each of the thin film transistors T1 T T5 is electrically connected. Connecting to the second test pad TP2, a function equivalent to that of FIG. 4 can also be achieved.
  • the thin film transistor substrates 30 and 40 of the present invention need only be added one (as shown in FIG. 3) or two (as shown in FIG. 4).
  • the test pad can achieve the function of judging whether the connection pads R1 to R5 and the probes 31 to 35 are in poor contact, thereby greatly reducing the complexity of the circuit arrangement on the thin film transistor substrate.
  • the number of probes can be reduced, which in turn reduces the cost of the test system.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

本发明公开了一种测试系统，包括一薄膜晶体管基板，所述薄膜晶体管基板包括若干个薄膜晶体管以及若干个连接焊垫，各薄膜晶体管包括一第一电极、一第二电极以及一第三电极，所述薄膜晶体管基板还包括一测试焊垫，各薄膜晶体管的第一电极及第二电极的其中一者电性连接至这些连接焊垫的其中一者，各薄膜晶体管的第一电极及第二电极的另一者以及所述第三电极电性连接至所述测试焊垫。本发明的测试系统能降低测试系统的成本及电路配置复杂的复杂度。

Description

测试系统 技术领域
本发明涉及测试技术领域，特别涉及一种能降低测试成本的测试系统。
 背景技术
液晶显示装置主要包括一液晶面板以及一背光模块。所述液晶面板包括一薄膜晶体管(Thin Film Transistor, TFT)基板、一彩色滤光片(Color Filter, CF)基板以及一设置于所述薄膜晶体管基板与所述彩色滤光片基板之间的液晶层。
在高分子聚合物稳定型垂直配向(Polymer Stabilization Vertical Align, PSVA)制程、阵列制程(array process)、组立制程(cell process)或其它制程中，必须对薄膜晶体管基板进行测试，检查薄膜晶体管基板上的元件例如薄膜晶体管是否功能正常。
请参阅图1，其为现有技术中测试系统的示意图。测试系统包括一探针框架(probe frame)10、若干个探针12以及一薄膜晶体管基板(Thin Film Transistor, TFT) 14。所述探针12是设置于所述探针框架10上且由具弹性的金属材质制成。在测试之前，必须先在薄膜晶体管基板上制作若干个焊垫P1~P5，将需要输入信号的元件(未图示)分别电性连接至所述焊垫P1~P5，进行测试时，将所述探针框架10的探针12与对应的焊垫P1~P5对齐并接触，检查薄膜晶体管基板14上的元件是否功能正常。
然而所述探针框架10的探针12与对应的焊垫P1~P5对齐时可能会产生对位误差或所述探针12长期使用导致无法完全弹性恢复而造成长度不同，造成所述探针12与对应的焊垫P1~P5接触不良，使得测试结果有误。
为了改善上述接触不良的问题，请参阅图2，其为现有技术中另一种测试系统的示意图。与图1的测试系统不同的是图2的测试系统包括焊垫P1~P5及P1’~P5’，所述焊垫P1~P5分别与所述焊垫P1’~P5’电性连接，亦即图2的焊垫数量为图1的焊垫数量的两倍。以所述焊垫P1与P1’为例，进行测试时，可任意地选择所述焊垫P1与P1’的其中一者来施加测试信号，通过对所述焊垫P1与P1’的另一者进行侦测来判断有无接触不良的问题，当判断有接触不良的问题时，调整所述探针框架10的探针12与对应的焊垫P1~P5及P1’~P5’的对位或是调整薄膜晶体管基板14的位置。
然而图2的测试系统的焊垫数量及探针数量是图1的测试系统的焊垫数量及探针数量的两倍，增加测试系统的成本及薄膜晶体管基板14上电路配置的复杂度。
因此，需要对上述现有测试系统的问题提出解决方法。
 技术问题
本发明的一个目的在于提供一种测试系统，以解决现有技术中测试系统的成本过高及电路配置复杂的问题。
 技术解决方案
本发明提供了一种测试系统，包括一薄膜晶体管基板以及若干个探针，所述薄膜晶体管基板包括若干个薄膜晶体管以及若干个连接焊垫，各薄膜晶体管包括一第一电极、一第二电极以及一第三电极，所述薄膜晶体管基板还包括一测试焊垫，各薄膜晶体管的第一电极及第二电极的其中一者电性连接至这些连接焊垫的其中一者，各薄膜晶体管的第一电极及第二电极的另一者以及所述第三电极电性连接至所述测试焊垫，这些探针分别对应地与这些连接焊垫及所述测试焊垫接触，所述测试焊垫具有一直流电压，通过分别侦测这些连接焊垫是否具有所述直流电压来判断这些连接焊垫与对应的探针是否接触不良。
在本发明的测试系统中，所述第一电极为源极，所述第二电极为漏极，所述第三电极为闸极。
为解决上述问题，本发明还提供了一种测试系统，包括一薄膜晶体管基板，所述薄膜晶体管基板包括若干个薄膜晶体管以及若干个连接焊垫，各薄膜晶体管包括一第一电极、一第二电极以及一第三电极，所述薄膜晶体管基板还包括一测试焊垫，各薄膜晶体管的第一电极及第二电极的其中一者电性连接至这些连接焊垫的其中一者，各薄膜晶体管的第一电极及第二电极的另一者以及所述第三电极电性连接至所述测试焊垫。
在本发明的测试系统中，所述测试系统还包括若干个探针，这些探针分别对应地与这些连接焊垫及所述测试焊垫接触。
在本发明的测试系统中，将一测试信号经由与所述测试焊垫接触的探针施加至所述测试焊垫，通过分别侦测这些连接焊垫是否具有所述测试信号来判断这些连接焊垫与对应的探针是否接触不良。
在本发明的测试系统中，所述第一电极为源极，所述第二电极为漏极，所述第三电极为闸极。
本发明的另一个目的在于提供一种测试系统，以解决现有技术中测试系统的成本过高及电路配置复杂的问题。
为解决上述问题，本发明提供了一种测试系统，包括一薄膜晶体管基板，所述薄膜晶体管基板包括若干个薄膜晶体管以及若干个连接焊垫，各薄膜晶体管包括一第一电极、一第二电极以及一第三电极，所述薄膜晶体管基板还包括一第一测试焊垫以及一第二测试焊垫，各薄膜晶体管的第一电极及第二电极的其中一者电性连接至所述第一测试焊垫，各薄膜晶体管的第一电极及第二电极的另一者电性连接至这些连接焊垫的其中一者，各薄膜晶体管的第三电极电性连接至所述第二测试焊垫。
在本发明的测试系统中，所述测试系统还包括若干个探针，这些探针分别对应地与这些连接焊垫、所述第一测试焊垫及所述第二测试焊垫接触。
在本发明的测试系统中，将一第一测试信号经由与所述第一测试焊垫接触的探针施加至所述第一测试焊垫，将一第二测试信号经由与所述第二测试焊垫接触的探针施加至所述第二测试焊垫，通过分别侦测这些连接焊垫是否具有所述第一测试信号来判断这些连接焊垫与对应的探针是否接触不良。
在本发明的测试系统中，所述第一电极为源极，所述第二电极为漏极，所述第三电极为闸极。
 有益效果
本发明相对于现有技术，解决了现有技术中测试系统的成本过高及电路配置复杂的问题。
 附图说明
图1为现有技术中测试系统的示意图；
图2为现有技术中另一种测试系统的示意图；
图3为根据本发明较佳实施例中测试系统的示意图；
图4为根据本发明另一较佳实施例中测试系统的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
请参阅图3，其为根据本发明较佳实施例中测试系统的示意图。
所述测试系统包括一薄膜晶体管基板30，所述薄膜晶体管基板30包括若干个薄膜晶体管T1~T5、若干个连接焊垫R1~R5以及一测试焊垫TP。各薄膜晶体管T1~T5包括一第一电极、一第二电极以及一第三电极。于本实施例中，所述第一电极为源极S(source)，所述第二电极为漏极D(drain)，所述第三电极为闸极G(gate)。薄膜晶体管T1~T5为所述薄膜晶体管基板30上需要测试的元件。
本发明的测试系统中，各薄膜晶体管T1~T5的漏极D对应地电性连接至所述连接焊垫R1~R5，各薄膜晶体管T1~T5的源极S及闸极G电性连接至所述测试焊垫TP。
所述测试系统还包括若干个探针31~36，所述探针31~35分别对应地与所述连接焊垫R1~R5接触，所述探针36与所述测试焊垫TP接触。
判断所述焊垫R1~R5与对应的探针31~35是否接触不良的过程如下。首先将一测试信号经由与所述测试焊垫TP接触的探针36施加至所述测试焊垫TP，通过分别侦测与所述探针31~35接触的所述连接焊垫R1~R5是否具有所述测试信号来判断所述连接焊垫R1~R5与对应的探针31~35是否接触不良。
所述测试信号例如是10伏特的直流电压，通过分别侦测所述连接焊垫R1~R5是否等于10伏特来判断所述连接焊垫R1~R5与对应的探针31~35是否接触不良。例如所述连接焊垫R1未侦测到10伏特时，表示所述连接焊垫R1与对应的探针31接触不良，因此需要重新调整所述焊垫R1~R5与对应的探针31~35的对位或是重新调整薄膜晶体管基板30的位置。
确认所述焊垫R1~R5与对应的探针31~35接触良好后，后续制程例如高分子聚合物稳定型垂直配向制程、阵列制程、组立制程或其它制程中对薄膜晶体管T1~T5的测试结果才能确保无误。
于本实施例中，各薄膜晶体管T1~T5的漏极D分别对应地电性连接至所述连接焊垫R1~R5，各薄膜晶体管T1~T5的闸极G以及源极S电性连接至所述测试焊垫TP。要注意的是，由于各薄膜晶体管T1~T5的漏极D以及源极S可根据施加的测试信号而对调使用，因此于另一实施例中，可以将各薄膜晶体管T1~T5的源极S分别对应地电性连接至所述连接焊垫R1~R5，将各薄膜晶体管T1~T5的闸极G以及漏极D电性连接至所述测试焊垫TP，也可达成等同于图3的功能。
请参阅图4，其为根据本发明另一较佳实施例中测试系统的示意图。
所述测试系统包括一薄膜晶体管基板40，所述薄膜晶体管基板40包括若干个薄膜晶体管T1~T5、若干个连接焊垫R1~R5、一第一测试焊垫TP1以及一第二测试焊垫TP2。所述薄膜晶体管T1~T5及所述连接焊垫R1~R5与图3相同，各薄膜晶体管T1~T5的漏极D对应地电性连接至所述连接焊垫R1~R5也与图3相同，此不多加赘述。各薄膜晶体管T1~T5为所述薄膜晶体管基板40上需要测试的元件。
图3与图4的不同处在于图4的薄膜晶体管基板40包括两个测试焊垫，即所述第一测试焊垫TP1以及所述第二测试焊垫TP2，且所述薄膜晶体管T1~T5的闸极G、源极S与所述第一测试焊垫TP1以及所述第二测试焊垫TP2的电性连接也与图3不同。
如图4所示，各薄膜晶体管T1~T5的源极S电性连接至所述第一测试焊垫TP1，各薄膜晶体管T1~T5的闸极G电性连接至所述第二测试焊垫TP2。
所述测试系统还包括若干个探针31~35及46~47，所述探针31~35与图3相同，分别对应地与所述连接焊垫R1~R5接触，所述探针46与所述第一测试焊垫TP1接触，所述探针47与所述第二测试焊垫TP2接触。
判断所述焊垫R1~R5与对应的探针31~35是否接触不良的过程如下。首先将一第一测试信号经由与所述第一测试焊垫TP1接触的探针46施加至所述第一测试焊垫TP1，将一第二测试信号经由与所述第二测试焊垫TP2接触的探针47施加至所述第二测试焊垫TP2，通过分别侦测与所述探针31~35接触的所述连接焊垫R1~R5是否具有所述第一测试信号来判断所述连接焊垫R1~R5与对应的探针31~35是否接触不良。
举例来说，所述第一测试信号是10伏特的直流电压，所述第二测试信号是5伏特的直流电压，通过分别侦测所述连接焊垫R1~R5是否等于10伏特来判断所述连接焊垫R1~R5与对应的探针31~35是否接触不良。例如所述连接焊垫R2未侦测到10伏特时，表示所述连接焊垫R2与对应的探针32接触不良，因此需要重新调整所述焊垫R1~R5与对应的探针31~35的对位或是重新调整薄膜晶体管基板40的位置。
确认所述焊垫R1~R5与对应的探针31~35接触良好后，后续制程例如高分子聚合物稳定型垂直配向制程、阵列制程、组立制程或其它制程中对薄膜晶体管T1~T5的测试结果才能确保无误。
于本实施例中，各薄膜晶体管T1~T5的漏极D分别对应地电性连接至所述连接焊垫R1~R5，各薄膜晶体管T1~T5的源极S电性连接至所述第一测试焊垫TP1，各薄膜晶体管T1~T5的闸极G电性连接至所述第二测试焊垫TP2。要注意的是，由于各薄膜晶体管T1~T5的漏极D以及源极S可根据施加的测试信号而对调使用，因此于另一实施例中，可以将各薄膜晶体管T1~T5的源极S对应地电性连接至所述连接焊垫R1~R5，各薄膜晶体管T1~T5的漏极D电性连接至所述第一测试焊垫TP1，各薄膜晶体管T1~T5的闸极G电性连接至所述第二测试焊垫TP2，也可达成等同于图4的功能。
与图2现有薄膜晶体管基板14需要额外增加一组的焊垫P1’~P5’相比，本发明的薄膜晶体管基板30、40只需要增加一个(如图3)或两个(如图4)测试焊垫就能达到判断连接焊垫R1~R5与探针31~35之间是否接触不良的功能，因此大幅地降低所述薄膜晶体管基板上电路配置的复杂度。再者，由于只需要增加一个(如图3)或两个(如图4)测试焊垫，探针数量也可以减少，进而降低测试系统的成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (10)

  1. 一种测试系统，包括一薄膜晶体管基板以及若干个探针，所述薄膜晶体管基板包括若干个薄膜晶体管以及若干个连接焊垫，各薄膜晶体管包括一第一电极、一第二电极以及一第三电极，其中所述薄膜晶体管基板还包括一测试焊垫，各薄膜晶体管的第一电极及第二电极的其中一者电性连接至这些连接焊垫的其中一者，各薄膜晶体管的第一电极及第二电极的另一者以及所述第三电极电性连接至所述测试焊垫，这些探针分别对应地与这些连接焊垫及所述测试焊垫接触，
    所述测试焊垫具有一直流电压，通过分别侦测这些连接焊垫是否具有所述直流电压来判断这些连接焊垫与对应的探针是否接触不良。
  2. 根据权利要求1所述的测试系统，其中所述第一电极为源极，所述第二电极为漏极，所述第三电极为闸极。
  3. 一种测试系统，包括一薄膜晶体管基板，所述薄膜晶体管基板包括若干个薄膜晶体管以及若干个连接焊垫，各薄膜晶体管包括一第一电极、一第二电极以及一第三电极，其中所述薄膜晶体管基板还包括一测试焊垫，各薄膜晶体管的第一电极及第二电极的其中一者电性连接至这些连接焊垫的其中一者，各薄膜晶体管的第一电极及第二电极的另一者以及所述第三电极电性连接至所述测试焊垫。
  4. 根据权利要求3所述的测试系统，还包括若干个探针，这些探针分别对应地与这些连接焊垫及所述测试焊垫接触。
  5. 根据权利要求4所述的测试系统，其中将一测试信号经由与所述测试焊垫接触的探针施加至所述测试焊垫，通过分别侦测这些连接焊垫是否具有所述测试信号来判断这些连接焊垫与对应的探针是否接触不良。
  6. 根据权利要求3所述的测试系统，其中所述第一电极为源极，所述第二电极为漏极，所述第三电极为闸极。
  7. 一种测试系统，包括一薄膜晶体管基板，所述薄膜晶体管基板包括若干个薄膜晶体管以及若干个连接焊垫，各薄膜晶体管包括一第一电极、一第二电极以及一第三电极，其中所述薄膜晶体管基板还包括一第一测试焊垫以及一第二测试焊垫，各薄膜晶体管的第一电极及第二电极的其中一者电性连接至所述第一测试焊垫，各薄膜晶体管的第一电极及第二电极的另一者电性连接至这些连接焊垫的其中一者，各薄膜晶体管的第三电极电性连接至所述第二测试焊垫。
  8. 根据权利要求7所述的测试系统，还包括若干个探针，这些探针分别对应地与这些连接焊垫、所述第一测试焊垫及所述第二测试焊垫接触。
  9. 根据权利要求8所述的测试系统，其中将一第一测试信号经由与所述第一测试焊垫接触的探针施加至所述第一测试焊垫，将一第二测试信号经由与所述第二测试焊垫接触的探针施加至所述第二测试焊垫，通过分别侦测这些连接焊垫是否具有所述第一测试信号来判断这些连接焊垫与对应的探针是否接触不良。
  10. 根据权利要求7所述的测试系统，其中所述第一电极为源极，所述第二电极为漏极，所述第三电极为闸极。
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