WO2013078641A1 - 搭桥晶粒多晶硅薄膜晶体管及其制造方法 - Google Patents

搭桥晶粒多晶硅薄膜晶体管及其制造方法 Download PDF

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WO2013078641A1
WO2013078641A1 PCT/CN2011/083233 CN2011083233W WO2013078641A1 WO 2013078641 A1 WO2013078641 A1 WO 2013078641A1 CN 2011083233 W CN2011083233 W CN 2011083233W WO 2013078641 A1 WO2013078641 A1 WO 2013078641A1
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region
source
active layer
drain
active
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PCT/CN2011/083233
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English (en)
French (fr)
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周玮
赵淑云
郭海成
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广东中显科技有限公司
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Priority to PCT/CN2011/083233 priority Critical patent/WO2013078641A1/zh
Publication of WO2013078641A1 publication Critical patent/WO2013078641A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention generally relates to a multi-die thin film transistor (TFT), and more particularly to a polysilicon thin film transistor having a bridged die structure without source-drain doping and a method of fabricating the same.
  • TFT multi-die thin film transistor
  • a highly crystalline polycrystalline silicon film is required. It needs to meet the following requirements: Low temperature processing, high glass area lining, low manufacturing cost, stable manufacturing process, high performance, consistent characteristics, and high reliability of crystalline silicon TFTs.
  • High temperature polysilicon technology can be used to implement high performance TFTs, but it cannot be used with conventional glass substrates used in commercial display panels.
  • Low temperature polysilicon (LTPS) must be used in such cases.
  • SPC solid phase crystallization
  • ELC excimer laser crystallization
  • MIC metal induced crystallization
  • the grains of the film are substantially randomly distributed in size, crystal orientation and shape. Grain boundaries are also generally detrimental to the formation of good TFTs when the polycrystalline film is used In the case of an active layer in a TFT, the electrical characteristics depend on how many grains and grain boundaries are present in the active channel.
  • a common problem with all prior art is that they form many grains in the TFT active channel in an unpredictable mode.
  • the distribution of the crystal grains is random, so that the electrical characteristics of the TFT are somewhat uneven on the substrate. This wide distribution of electrical characteristics is detrimental to the performance of the display and causes problems such as mura defects and uneven brightness.
  • the crystal grains of the polycrystalline thin film transistor form a random network. This is true for any semiconductor material such as silicon, germanium, silicon germanium alloys, tri-five compound semiconductors, and organic semiconductors.
  • the conduction inside the grains is almost the same as that of the crystalline material, and the conduction across the grain boundaries is worse and causes a loss of mobility, an overall loss and an increased threshold voltage.
  • TFT thin film transistor
  • the grain structure is almost a two-dimensional random network. Randomness and corresponding variable conductance adversely affect display performance and image quality.
  • the low temperature polysilicon film 101 includes the die 102. There is a distinct grain boundary 103 between adjacent grains 102. Each of the crystal grains 102 has a length ranging from several tens of nanometers to several micrometers and is considered to be a single crystal. Many dislocations, stacking faults, and dangling bond defects are distributed in the grain boundaries 103. Due to the different preparation methods, the grains 102 inside the low temperature polysilicon film 101 may be randomly distributed or in a defined orientation. As for the conventional low temperature polysilicon film 101, there are serious defects in the grain boundary 103 as shown in FIG. A severe defect in the grain boundary 103 will introduce a high barrier 104.
  • the barrier 104 (or the vertical component of the slope barrier) perpendicular to the direction of transport of the carriers 105 will affect the initial state and capability of the carriers.
  • the threshold voltage and the field effect mobility are limited by the grain boundary barrier 104.
  • the grain boundary 103 distributed in the junction region also causes a large leak current.
  • a single gate covers the entire active channel including doped lines to control the flow of current.
  • the source and drain regions of the BG TFT require further secondary heavily doping.
  • 2 is a schematic diagram of source and drain implantation of a polysilicon thin film transistor of a bridged die (BG) structure.
  • BG bridged die
  • a boron ion 903 having a dose of 4 * 10 14 /cm 2 is implanted into the channel by using the gate electrode 802 as an ion barrier layer.
  • Source and drain 902 are formed.
  • the channel 901 under the gate electrode 802 is undoped.
  • the TFT is designed such that current flows vertically through parallel lines in the crystalline region of the channel, and the influence of grain boundaries can be reduced.
  • the reliability, uniformity and electrical properties of the BG polysilicon TFT are significantly improved. Summary of the invention
  • the object of the present invention is to provide a better layout and to simplify the fabrication process of BG polysilicon thin film transistors.
  • source/drain doping processing is not necessary. This simplifies the manufacturing process and manufacturing cycle and reduces costs. Since there is no source/drain doping process, the doping activation process is also unnecessary. Therefore, the source/drain dopant activation problem of the n-type TFT having a metal gate is also solved.
  • the present application discloses a new structure of a bridged crystalline polysilicon thin film transistor and a manufacturing process thereof.
  • the bridge thyristor thin film transistor comprises an active layer composed of a low temperature polysilicon semiconductor material, and has a plurality of lateral conductive bridges in the active layer; the position of the lateral conductive bridge is perpendicular to the flow direction of the current required in the channel region At the same time, the position of the lateral conductive bridge is parallel to the source/drain regions The direction of flow of the current required inside.
  • the manufacturing process of forming the bridged GaN polysilicon thin film transistor comprises the following steps: Step 1: manufacturing a polysilicon film to form an active region; Step 2, manufacturing a plurality of substantially parallel wires; the position of the wire is perpendicular to the active region trench The direction of flow of the current required in the track region; at the same time, the position of the wire is parallel to the direction of flow of the desired current in the source/drain regions of the active region.
  • the two ion implantation processes disclosed in the BG TFT can be reduced to one.
  • the present invention provides the following advantages: improved electrical performance; improved field effect mobility; improved uniformity of on-current. Reduce cost; reduce threshold voltage and leakage current; decrease randomness of grain mobility and grain boundary resistance; lower barrier and improve carrier mobility in "on” state; in "off” state Reduced leakage current; simplifies process and reduces processing time; no activation of source and drain dopants is required after metal gate formation.
  • Figure la is a typical polysilicon structure in the prior art
  • Figure lb is a diagram of the corresponding barrier of Figure la;
  • FIG. 2 is a schematic illustration of source and drain implants of a US 2010/0171546 A1 polysilicon thin film transistor
  • Figure 3 is an anisotropic test structure layout of the conductivity of the BG line
  • Figure 4 is the test result of the conductivity of the BG line
  • Figure 5 is a first embodiment of a layout of a bridged die polysilicon thin film transistor
  • FIG. 6 is a second embodiment of a layout of a bridged die polysilicon thin film transistor
  • Figure 7 is a transmission characteristic of the first embodiment of the bridged-die polysilicon thin film transistor layout
  • Figure 8 is a transmission characteristic of the second embodiment of the bridged-die polysilicon thin film transistor layout.
  • a bridged-die polysilicon thin film transistor without source-drain doping treatment and a method for fabricating the same according to the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
  • the invented BG TFTs layout utilizes the anisotropy of BG line conductivity (the current is parallel to the BG line direction and the electrical current is perpendicular to the BG line direction) to eliminate the US patent number US
  • the BG line is a doped region along the Y-axis direction.
  • a voltage is applied along the BG line, there is no energy barrier in the current flow path. Therefore, the BG structure exhibits a lower resistivity.
  • a voltage is applied across several pairs of BG lines, a high resistivity occurs in the BG structure because a semiconductor contact junction formed by a series of doped BG lines (301) and undoped regions (30 2 ) is formed there.
  • Figure 3 shows the conductivity of the BG structure.
  • a novel bridged-die polysilicon thin film transistor active layer layout is designed, wherein the bridged-die silicon polysilicon thin film transistor includes an active layer composed of a low-temperature polysilicon semiconductor material.
  • the layer has a plurality of lateral conductive bridges in the active layer. Wherein the position of the lateral conductive bridge is perpendicular to the direction of flow of the desired current in the channel region; at the same time, the position of the lateral conductive bridge is parallel to the direction of flow of the desired current in the source/drain region.
  • a zigzag active layer is proposed, that is, the source region and the drain region in the active layer are configured as an asymmetrical position, and the channel region is respectively connected to one end of the source region and the drain region. One end, thereby designing the active layer into a zigzag shape.
  • the lateral conductive bridge has a width smaller than ⁇ ⁇ ⁇ ⁇ , and the pitch is smaller than ⁇ ⁇ ⁇ ⁇ ; the lateral conductive bridge is formed by doping the channel layer; more preferably, the semiconductor of the low temperature polysilicon semiconductor material is laser Low temperature polysilicon material formed by annealing, solid phase crystallization or metal induced crystallization.
  • the semiconductor material is supported by a glass substrate and covers a large portion of the active channel with a gate, including a plurality of high resistance and low resistance crossing regions, and the gate is insulated from the active channel.
  • the traversing region may preferably be doped to form parallel lines, and the dose per unit area of the traversing region dopant may be selected from the range of 1 10"/cm 2 to 1 X 10 16 /cm 2 , preferably 2 ⁇ 10 15 /cm 2 —4 ⁇ l O'Vcm 2 ;
  • the doped region is formed by ion implantation. Taking a p-channel device as an example, a negative bias on the gate turns on the TFT and a negative voltage is applied to the drain.
  • the current flows from the source to the channel region along the BG line.
  • the negative bias on the gate induces an active layer inversion.
  • the channel is thus conductive and current flows into the drain region along the BG line.
  • Solid arrows represent source/drain Current flow in the region.
  • a positive bias voltage is applied to the gate and the channel is not conductive.
  • a series of reverse biases hinder the current. As a result, current cannot flow through the channel region i or.
  • the anisotropy of the conductivity of the BG wire is fully utilized.
  • the direction of current flow is parallel to the BG line.
  • the direction of current flow is perpendicular to the BG line.
  • the resistance is small in the direction along the length of the BG line, and the conductivity of the BG line is high. Therefore, in the source-drain region, if the current flows in a direction parallel to the BG line, the resistance of the path is small, so that it is not necessary to perform the second ion implantation process for doping.
  • the direction of the control current flowing in the opposite direction to the BG line is achieved by the newly designed active layer shape (Z-type and C-type) (relative to the conventional rectangular active layer design). .
  • a new active layer layout of a bridged polysilicon thin film transistor is designed, as shown in FIG.
  • a C-shaped active layer is proposed.
  • the active layer is configured such that the source/drain regions are vertically symmetrical, and the channel region is located on the left side of the source/drain regions to connect the source/drain regions, thereby designing the active layer into C-shaped.
  • the working principle of the second embodiment is the same as that of the Z-shaped device designed in the first embodiment of the present invention.
  • the solid arrows represent the direction of current flow in the source/drain regions.
  • the dashed arrows represent the direction of current flow in the channel.
  • the bridge thyristor thin film transistor includes an active layer composed of a low temperature polysilicon semiconductor material and a plurality of lateral conductive bridges in the active layer. Wherein the position of the lateral conductive bridge is perpendicular to the direction of flow of the desired current in the channel region; at the same time, the position of the lateral conductive bridge is parallel to the direction of flow of the desired current in the source/drain region.
  • the lateral conductive bridge width is less than 1 0 ⁇ ⁇ , the pitch is less than ⁇ ⁇ ⁇ ⁇ ; the lateral conductive bridge is formed by doping the channel layer; more preferably, the semiconductor of the low temperature polysilicon semiconductor material is laser annealed, solid phase crystallized or metal induced crystallization A low temperature polysilicon material is formed. At the same time, the semiconductor material is supported by a glass substrate and covers a large portion of the active channel with a gate, including a plurality of crossing regions of high resistance and low resistance, and the gate is insulated from the active channel.
  • the traversing region may preferably be doped to form parallel lines, and the unit area dose of the plurality of traversing region dopants may be selected from the range of 1 10"/cm 2 to 1 X 10 16 /cm 2 , preferably 2 xl 0 15 /cm 2 - 4 xl 0 15 /cm 2 ;
  • the doped region is formed by ion implantation.
  • the application of the new layout of the TFT, the device manufacturing process is almost the same as the invention of the BG TFT in the U.S. Patent No. US 2010/0171546 A1.
  • the invention does not have a source/drain doping process or a doping activation process after etching into a gate electrode.
  • a zigzag active layer or a C-shaped active layer is formed in the embodiment 12, this is only a preferred embodiment, and can be understood according to the specification and the drawings.
  • the present invention provides a method of fabricating a polycrystalline silicon semiconductor film according to the above-described novel bridging thyristor active layer layout, which first produces a polysilicon film to form an active region; and then fabricates a plurality of substantially parallel to each other a wire; wherein the position of the wire is perpendicular to the flow direction of the current required in the channel region of the active region; and the position of the wire is parallel to the flow direction of the current required in the source/drain region of the active region.
  • the wire is a lateral conductive bridge; wherein the source region and the drain region in the active layer are configured as one a symmetrical position, the channel region is respectively connected to one end of the source region and the other end of the drain region, thereby designing the active layer into a zigzag shape; or constructing the active layer as a source/drain region symmetrical, and the channel The region is located on the left side of the source/drain region to connect the source/drain regions, thereby designing the active layer into a C-shape.
  • the wire width is less than ⁇ ⁇ ⁇ ⁇ spacing less than 10 ⁇ ⁇ .
  • the order in which the polycrystalline silicon thin film is formed from the amorphous silicon film and the plurality of wires are formed can be reversed. And, when a polycrystalline silicon semiconductor film is formed, a polysilicon film is doped to form a wiring.
  • the doping process may use a lithography technique of a reticle, a lithography technique of optical wave interference of two coherent laser beams, or a nanoimprint process.
  • the large area grating manufacturing technique or the electron beam direct writing of the patterned semiconductor film forms an active region with the doped lateral region, and the current flow direction crosses the lateral region.
  • a source/drain region is formed, a current flow direction is along the lateral region; an insulating layer is deposited on the active region and then a gate is formed on top of the active region; the gate pattern is covered for forming at both ends of the thin film transistor All active channels of the source and drain regions; the lithographic insulating layer forms source and drain electrical contacts.
  • the source or drain regions after gate formation do not require additional doping or activation.
  • a TFT having the structure designed above was fabricated and tested.
  • the material as the active layer is solid phase crystalline polycrystalline silicon having a thickness of 100 nm.
  • the gate dielectric is 70 to allow thick low temperature LPCVD precipitated silica.
  • the device transmission characteristics using the first embodiment and the second embodiment are as shown in Figs. 7 and 8, respectively.
  • the inventive TFT structure and manufacturing process improve various aspects of the device performance.
  • the threshold voltage is reduced by about 3V
  • SS is reduced by about 600mV/dec
  • the switching ratio is improved by about an order of magnitude
  • the field effect mobility ( ⁇ TM) is increased by 2.5 to 3 times.

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Abstract

一种搭桥晶粒多晶硅薄膜晶体管，包括一个由低温多晶硅半导体材料构成的有源层，有源层中具有多个横向导电桥；横向导电桥的位置垂直于沟道区域内所需电流的流动方向，同时横向导电桥的位置平行于源/漏极区域内所需电流的流动方向。利用横向导电桥导电性的各向异性，能不进行源/漏掺杂处理，简化制造过程。

Description

搭桥晶粒多晶硅薄膜晶体管及其制造方法
技术领域
本发明总的涉及多晶粒薄膜晶体管 （TFT ) ， 更具体地， 涉及一种没有 源漏极掺杂处理的搭桥晶粒结构的多晶硅薄膜晶体管及其制造方法。
背景技术
为实现多晶硅 TFT有源矩阵显示器面板的工业化制造， 需要很高质的多 晶硅膜。 它需要满足以下要求： 低温加工、 可以在大面积玻璃衬上实现、 低 制造成本、 稳定的制造工艺、 高性能、 一致的特性、 以及晶硅 TFT 的高可靠 性。
高温多晶硅技术可以用来实现高性能 TFT , 但是它不能用于商业显示器 面板中使用的普通玻璃衬底。在这样的情形下必须使用低温多晶硅 （LTPS )。 有三种主要的 LTPS 技术： （ 1 )通过在 600 °C 长时间退火的固相结晶 ( SPC ) ； ( 2 ) 准分子激光晶化（ ELC )或闪光灯退火； 以及 （ 3 )金 属诱导结晶（ MIC )及其有关变体。 ELC 产生最好的结果但是昂贵， SPC 成 本最低但是花的时间长， 这些技术都不能满足上述低成本和高性能的所有要 求。
所有多晶薄膜材料所共有的是， 膜的晶粒在尺寸、 晶体取向和形状上基 本上随机分布。 晶界通常也对优良 TFT 的形成有害， 当该多晶薄膜被用作 TFT 中的有源层时， 电特性取决于在有源沟道中存在多少晶粒和晶界。
所有现有技术的共同问题是，它们以不可预料的模式（ pa t tern )在 TFT 有源沟道内形成许多晶粒。 晶粒的分布是随机的， 使得 TFT 的电特性在衬底 上有些不均匀。 该电特性的宽分布对显示器的性能有害并且导致问题， 例如 mura 缺陷和亮度不均匀。
多晶薄膜晶体管的晶粒形成随机的网络。 对于任何半导体材料例如硅、 锗、 硅锗合金、 三五族化合物半导体、 以及有机半导体来说， 事实都是如此。 晶粒内部的传导几乎与晶体材料相同， 而跨过晶界的传导更差并且造成迁移 率的， 总体损失并且增加的阈值电压。 在由这种多晶薄膜制成的薄膜晶体管 ( TFT ) 的有源沟道内部， 晶粒结构几乎是二维随机网络。 随机性以及相应 而生的可变电导不利地影响显示器性能和图像质量。
如图 la 所示的典型多晶硅结构， 低温多晶硅膜 101 包括晶粒 102 。 在相邻的晶粒 102 之间有明显的晶界 103 。 每个晶粒 102 的长度大小从数 十纳米到几微米， 并且被认为是单晶。 许多位错、 堆垛层错以及悬挂键的缺 陷分布在所述晶界 103 中。 由于不同的制备方法， 低温多晶硅膜 101 内部 的晶粒 102 可以随机分布或沿确定的取向。 至于常规的低温多晶硅膜 101 , 在晶界 103 中有严重的缺陷， 如图 lb 中所示。 在晶界 103 中的严重缺陷 将引入高势垒 104 。 垂直于载流子 105 传输方向的所述势垒 104 (或倾斜 势垒的垂直分量）将影响载流子的初始状态和能力。 对于在该低温多晶硅膜 101 上制造的薄膜晶体管， 阈值电压和场效应迁移率受晶界势垒 104 限制。 当高的反向栅电压施加在 TFT 中时，分布在结区域中的晶界 103 也引起大的 漏电流。 在美国专利 US 201 0/ 0171546 A1 (该专利的全部内容均作为背景技术援 引于此） , 披露了一种搭桥晶粒（BG )结构的多晶硅薄膜晶体管 （TFT ) 。 釆 用掺杂 BG多晶硅线， 本征或轻掺杂通道被分隔成多个区域。 单个栅极覆盖了 整个包括掺杂线的有源通道， 用来控制电流的流动。 BG TFT的源漏极区域需 要进一步的二次重掺杂处理。 图 2是搭桥晶粒（BG )结构的多晶硅薄膜晶体 管的源和漏注入的示意图。 如图 2 中所示， 剂量为 4 * 1 014/cm2 的硼离子 903 利用栅电极 802 作为离子阻挡层被注入沟道。 源和漏 902 被形成。 栅电极 802 下面的沟道 901 未掺杂。使用 BG多晶硅作为有源层， TFT被设计成使电 流垂直流过在通道结晶区域的平行线， 晶界的影响可以减少。 与传统的低温 多晶硅 TFT相比， BG多晶硅 TFT的可靠性， 均匀性和电学性能都得到显著的 改善。 发明内容
本发明的目的是为了提供更好的布局和简化 BG多晶硅薄膜晶体管的制造 工艺。 利用所披露的新布局， 源 /漏极掺杂处理是没有必要的。 从而简化了制 造工艺和制造周期，降低了成本。 由于没有源 /漏极掺杂过程， 掺杂活化的处 理也是没有必要的。 因此， 有着金属栅极的 n型 TFT的源 /漏极掺杂物激活问 题也迎刃而解了。
本申请公开了一种新结构的架桥结晶多晶硅薄膜晶体管及其制造过程。 其中该搭桥晶粒多晶硅薄膜晶体管包括一个由低温多晶硅半导体材料构 成的有源层， 在有源层中具有多个横向导电桥； 横向导电桥的位置垂直于沟 道区域内所需电流的流动方向； 同时， 横向导电桥的位置平行于源 /漏极区域 内所需电流的流动方向。
该形成搭桥晶粒多晶硅薄膜晶体管的制造过程， 包括如下步骤： 步骤一、 制造多晶硅薄膜， 形成一个有源区域； 步骤二、 制造多个彼此大致平行导线； 导线的位置垂直于有源区域中沟道区域内所需电流的流动方向； 同时， 导线 的位置平行于有源区域中源 /漏极区域内所需电流的流动方向。
通过应用所披露的新结构， 源 / 漏极掺杂处理不再是必要的。 在传统的
BG TFT中所披露的两个离子注入过程， 可以减少到一个。
通过上述技术方案， 本发明提供下列优点：改善电性能； 改善场效应迁移 率； 改善接通电流的均勾性。 降低成本； 减小阈值电压和漏电流； 晶粒迁移 率和晶界电阻的随机性减小； 在 "接通" 状态中降低势垒和改善载流子迁移 率； 在 "关断" 状态中减小漏电流； 简化工艺和缩短了处理时间； 在形成金 属栅极之后不再需要对源漏极掺杂物进行激活。 附图说明
图 la是现有技术中典型多晶硅结构；
图 lb是图 la 的相应势垒的图；
图 2是美国专利 US 2010/0171546 A1多晶硅薄膜晶体管的源和漏注入的示 意图；
图 3是 BG线的导电性的各向异性测试结构布局；
图 4是 BG线电导率的测试结果；
图 5是搭桥晶粒多晶硅薄膜晶体管布局的第一实施例；
图 6是搭桥晶粒多晶硅薄膜晶体管布局的第二实施例； 图 7是搭桥晶粒多晶硅薄膜晶体管布局的第一实施例的传输特性； 图 8是搭桥晶粒多晶硅薄膜晶体管布局的第二实施例的传输特性。 具体实施方式
下面结合附图和具体实施例对本发明提供的一种没有源漏极掺杂处理的 搭桥晶粒多晶硅薄膜晶体管及其制造方法进行详细描述。
同时在这里做以说明的是，为了使实施例更加详尽，下面的实施例为最佳、 行实施； 同时， 附图并不是按比例严格绘制， 其重点仅是放在公开的原理上。
所发明的 BG TFTs布局利用 BG线导电性的各向异性（电流平行于 BG线 方向与电流垂直于 BG 线方向的电学特性不相同） ，以消除美国专利号为 US
201 0/ 0171 546 A1的专利中的源极 /漏极掺杂过程。
BG线是沿 Y轴方向的掺杂区域。 当沿着 BG线施加电压， 在电流流动路径 就没有能量势垒。 因此， BG结构表现出较低的电阻率。 相反， 当跨过几对 BG 线施加电压时， BG结构就会出现高电阻率， 因为那里形成了由一系列掺杂 BG 线（ 301 )和未掺杂区域（ 302 )形成的半导体接触结。 图 3给出了 BG结构导 电率的测试。
测试步骤和结果如图 4所示。 当在电极 1 1和 1 2之间施加电压， 则测量 到 pA量级范围的电流。 当在电极 1 1和 21之间施加电压， 则测量结果为 mA 量级范围的电流。 此结果说明， 平行和垂直 BG线的方向， 电阻率有艮大的区 别。 在平行于 BG线的方向， 电阻艮小。 而在垂直于 BG线的方向， 电阻极大。 两方向的电阻率相差达 9个数量级。 基于以上这样的事实，根据本发明第一实施例，设计出一种新的搭桥晶粒 多晶硅薄膜晶体管有源层布局， 其中该搭桥晶粒多晶硅薄膜晶体管包括一个 由低温多晶硅半导体材料构成的有源层， 在有源层中具有多个横向导电桥。 其中横向导电桥的位置垂直于沟道区域内所需电流的流动方向； 同时， 横向 导电桥的位置平行于源 /漏极区域内所需电流的流动方向。
在图 5 中， 提出一个 Z字形有源层， 即将有源层中的源极区与漏极区构 造为一不对称的位置， 沟道区域分别连接源极区的一端与漏极区的另一端， 从而将有源层设计成 Z字形。 优选的， 该横向导电桥宽度小于 Ι Ο μ ηι, 间距小 于 Ι Ο μ ηι; 横向导电桥是通过对沟道层掺杂形成； 更为优选的是， 其中低温多 晶硅半导体材料的半导体是由激光退火、 固相晶化或金属诱导晶化形成的低 温多晶硅材料。
同时， 釆用玻璃衬底支撑上述半导体材料， 并以栅极覆盖了有源沟道的 大部分， 包括多个高电阻和低电阻的横穿区域， 并且栅极与上述有源沟道绝 缘。 其中的横穿区域可优选为掺杂形成平行线， 上述横穿区域掺杂剂的单位 面积剂量的选取范围为 1 10"/ cm2 — 1 X 1016/cm2, 优选为 2 χ 1015/cm2 —4 χ l O'Vcm2; 掺杂区域是以离子注入方式形成的。 以 p型沟道的器件为例， 栅极 上的一个负偏压开启 TFT, 漏极加负电压。 电流沿着 BG线从源极流向沟道区 域。 栅极上的负偏压诱导有源层反型。 沟道因此导电且电流沿着 BG线流入漏 极区域。 实心箭头代表源极 /漏极区域中电流流向。 在器件关闭状态， 正偏电 压施于栅极， 沟道不导电。 一系列反偏结阻碍了电流。 结果， 电流不能流经 沟道区 i或。
本设计与美国专利 US 2010/0171546 A1的主要区别在于: 在美国专利 US 201 0/ 0171546 A1 中， BG线在器件沟道及源极漏极区域 中都是垂直于电流流动方向的。 源极漏极的形成是由另外的离子注入工艺进 行二次掺杂来实现的。
在本设计中， 充分利用了 BG线的导电性的各向异性。 在源极漏极区域， 使电流的流动方向与 BG线平行。 而在器件沟道中， 使电流流动方向与 BG线 垂直。
前文已经证实， 在沿着 BG线长度的方向， 电阻很小， BG线的导电性很高。 因此在源极漏极区域， 如果电流沿着与 BG线平行方向流动， 此路径的电阻很 小， 因此不需要再进行第二次离子注入工艺进行掺杂。
而在器件沟道区域， 电流的方向是与 BG线垂直的。 这样设计使得本专利 设计的器件保持了美国专利 US 201 0/ 0171546 A1所提及的所有优点。
在本发明的具体实施例中， 控制电流的流向与 BG线的相对方向， 是由全 新设计有源层的形状（ Z型和 C型）来实现的（相对于传统的矩形有源层设计）。
根据本发明第二实施例，设计出一种新的搭桥晶粒多晶硅薄膜晶体管有 源层布局， 如图 6所示。 提出一个 C形有源层， 将有源层构造为源 /漏极区域 上下对称， 而沟道区域位于源 /漏极区域左侧， 以连接源 /漏极区域， 从而将 有源层设计成 C字形。第二实施例的工作原理与本发明的第一实施例设计的 Z 形设备相同。 实心箭头代表源极 /漏极区域中电流的流向。 虚线箭头代表沟道 中电流的流向。 其中该搭桥晶粒多晶硅薄膜晶体管包括一个由低温多晶硅半 导体材料构成的有源层， 在有源层中具有多个横向导电桥。 其中横向导电桥 的位置垂直于沟道区域内所需电流的流动方向； 同时， 横向导电桥的位置平 行于源 /漏极区域内所需电流的流动方向。优选的， 该横向导电桥宽度小于 1 0 μ ηι, 间距小于 Ι Ο μ ηι; 横向导电桥是通过对沟道层掺杂形成； 更为优选的是， 其中低温多晶硅半导体材料的半导体是由激光退火、 固相晶化或金属诱导晶 化形成的低温多晶硅材料。 同时， 釆用玻璃衬底支撑上述半导体材料， 并以 栅极覆盖了有源沟道的大部分， 包括高电阻和低电阻的多个横穿区域， 并且 栅极与上述有源沟道绝缘。 其中的横穿区域可优选为掺杂形成平行线， 上述 多个横穿区域掺杂剂的单位面积剂量的选取范围为 1 10"/cm2 - 1 X 1016/cm2, 优选为 2 x l 015/cm2 — 4 x l 015/cm2; 掺杂区域是以离子注入方式形成的。
上述两种实施例中 TFT新布局的应用， 设备制造工艺几乎与美国专利号 为美国专利 US 2010/ 0171546 A1 中 BG TFT发明相同。 唯一的区别是在刻蚀 成栅极电极后该发明没有源极 /漏极掺杂过程或者掺杂激活过程。 同时对于本 领域技术人员可以理解的是，虽然在实施例一二中形成的是 Z字形有源层或 C 字形有源层， 然而这仅是较佳实施例， 根据说明书及其附图可以理解任何实 施例的其他变形对于本领域技术人员也是显而易见的， 诸如其他非对称有源 层； 或 U字形、 以及反向 C字形等， 也均可以实现本发明。 当然， 为了增加 布线的方便性， 也可以做成 H字形或工字线， 把对角或位于沟道一侧的做为 源漏极即可。
接下来， 本发明根据上述新的搭桥晶粒多晶硅薄膜晶体管有源层布局， 提供了一种制造形成多晶硅半导体薄膜的方法， 首先制造多晶硅薄膜， 形成 一个有源区域； 然后制造多个彼此大致平行导线； 其中导线的位置垂直于有 源区域中沟道区域内所需电流的流动方向； 同时， 导线的位置平行于有源区 域中源 /漏极区域内所需电流的流动方向。
该导线为横向导电桥； 其中即将有源层中的源极区与漏极区构造为一不 对称的位置， 沟道区域分别连接源极区的一端与漏极区的另一端， 从而将有 源层设计成 z字形； 或将有源层构造为源 /漏极区域上下对称， 而沟道区域位 于源 /漏极区域左侧， 以连接源 /漏极区域， 从而将有源层设计成 C字形。 所 述导线宽度小于 Ι Ο μ ηκ 间距小于 10 μ ηι。
由非晶硅薄膜形成多晶硅薄膜和制造多个导线的次序可以调换。 并且在 形成多晶硅半导体薄膜时进行掺杂多晶硅薄膜从而形成导线。 其中的掺杂过 程可以选用掩模板的光刻技术、 两束相干激光束的光波干涉的光刻技术、 或 者利用纳米压印过程。
更进一步的， 在制造形成多晶硅半导体薄膜的方法中， 釆用大面积光栅 制造技术或电子束直接写入图案化半导体薄膜与掺杂的横向区域形成一个有 源区域， 电流流动方向跨过横向区域； 同时， 形成源极 /漏极区域， 电流流动 方向沿着横向区域； 在有源区域上沉积绝缘层然后在有源区域顶部形成栅极； 上述栅极图案覆盖除了薄膜晶体管两端用于形成源极和漏极区域的全部有源 沟道； 光刻绝缘层形成源极和漏极电接触。 栅极形成后源极或漏极区域不需 要额外的掺杂或激活。
以下各段会给出实验结果并进行分析。
实验结果
具有上文所设计结构的 TFT被制造出来且进行测试。 用于示范， 作为有 源层的材料是 l OOnm厚的固相结晶多晶硅。 栅介质是 70讓厚的低温 LPCVD沉 淀二氧化硅。
运用第一实施例和第二实施例的设备传输特性分别如图 7和图 8所示。 晶体管的尺寸是 W=24 m， Ll=L2=L3=2 ( m， W和 L1—L3定义在图 5和图 6中标 记。
为了方便比较， 没有 BG 线但具有源极 /漏极离子植入过程的具有相同尺
Figure imgf000012_0001
从以上表格可以清楚看到， 所发明的 TFT结构和制造工艺改进了设备各 方面性能。 阈值电压减小 3V左右， SS减小了 600mV/dec左右， 开关比率改进 了约一个数量级， 且场效应迁移率（μ™)提高了 2. 5到 3倍。
在具体实施例中的各步骤中包括一些优选的、 更详尽的实施步骤， 但并 非必要步骤。
最后应说明的是， 以上实施例仅用以描述本发明的技术方案而不是对本 技术方法进行限制， 本发明在应用上可以延伸为其他的修改、 变化、 应用和 实施例， 并且因此认为所有这样的修改、 变化、 应用、 实施例都在本发明的 精神和教导范围内。

Claims

权 利 要 求
1、 一种搭桥晶粒多晶硅薄膜晶体管， 包括一个由低温多晶硅半导体材料 构成的有源层， 有源层中具有多个横向导电桥； 其特征在于， 横向导电桥的 位置垂直于沟道区域内所需电流的流动方向； 同时， 横向导电桥的位置平行 于源 /漏极区域内所需电流的流动方向。
2、 如权利要求 1所述的晶体管， 其特征在于， 有源层中的源极区与漏极 区构造为一不对称的位置， 沟道区域分别连接源极区的一端与漏极区的另一 端， 有源层设计成 Z字形。
3、 如权利要求 1所述的晶体管， 其特征在于， 有源层构造为源 /漏极区 域上下对称， 沟道区域位于源 /漏极区域左侧以连接源 /漏极区域， 有源层设 计成 C字形。
4、 如权利要求 1 所述的晶体管， 其特征在于， 有源层中的横向导电桥 宽度小于 Ι Ο μ ηι, 间距小于 10 μ ηι。
5、 如权利要求 1所述的晶体管， 其特征在于， 横向导电桥通过对沟道层 掺杂形成。
6、 如权利要求 1所述的晶体管， 其特征在于， 半导体是由激光退火、 固 相晶化或金属诱导晶化形成的低温多晶硅材料。
7、 如权利要求 1所述的晶体管， 其特征在于， 还包括支撑上述半导体材 料的玻璃衬底。
8、 如权利要求 1所述的晶体管， 其特征在于， 栅极覆盖上述有源沟道的 大部分， 包括多个高电阻和低电阻的横穿区域， 并且栅极与上述有源沟道绝
9、如权利要求 8所述的晶体管，其特征在于，横穿区域掺杂形成平行线。
10、 如权利要求 8所述的晶体管， 其特征在于， 横穿区域掺杂剂的单位 面积剂量为 1 1014/cm2 - 1 X 1 016/cm2 , 优选为 2 x 1015/cm2 —4 x 1015/cm2。
11、 如权利要求 8所述的晶体管， 其特征在于， 掺杂区域以离子注入方式 形成。
12、 如权利要求 1所述的晶体管， 其特征在于， 控制终端控制载流子在源 极 /漏极区域沿着导电线流动， 并穿越多晶硅半导体沟道。
1 3、 如权利要求 12所述的晶体管， 其特征在于， 所述源极 /漏极和所述半 导体区域成型于一个由低温多晶硅构成的共同层。
14、 一个形成多晶硅半导体薄膜的方法， 包括如下步骤：
步骤一、 制造多晶硅薄膜， 形成一个有源区域；
步骤二、 制造多个彼此大致平行导线； 导线的位置垂直于有源区域中沟 道区域内所需电流的流动方向； 同时， 导线的位置平行于有源区域中源 /漏极 区 i或内所需电流的流动方向。
15、 如权利要求 14所述的方法， 其特征在于， 该导线为横向导电桥。
16、 如权利要求 14所述的方法， 其特征在于， 在所述步骤一中， 将有源 层中的源极区与漏极区构造为一不对称的位置， 沟道区域分别连接源极区的 一端与漏极区的另一端， 从而将有源层设计成 Z字形。
17、 如权利要求 14所述的方法， 其特征在于， 在所述步骤一中， 将有 源层构造为源 /漏极区域上下对称， 而沟道区域位于源 /漏极区域左侧， 以连 接源 /漏极区域， 从而将有源层设计成 C字形。
18、 如权利要求 14所述的方法， 其特征在于， 所述导线宽度小于 Ι Ο μ ηκ 间 巨小于 10 μ ιη。
19、 如权利要求 14所述的方法， 其特征在于， 由非晶硅薄膜形成多晶硅 薄膜和制造多个导线的次序可以调换。
20、 如权利要求 14所述的方法， 其特征在于， 该方法釆用掺杂多晶硅薄 膜从而形成所述导线的步骤。
21、 如权利要求 20所述的方法， 其特征在于， 掺杂过程利用使用掩模板 的光刻技术。
22、 如权利要求 20所述的方法， 其特征在于， 掺杂过程利用使用两束相 干激光束的光波干涉的光刻技术。
23、 如权利要求 20所述的方法， 其特征在于， 掺杂过程利用纳米压印过 程。
24、 如权利要求 14所述的方法， 其特征在于， 其中： 釆用大面积光栅制 造技术或电子束直接写入图案化半导体薄膜与掺杂的横向区域形成该有源区 域， 在有源区域上沉积绝缘层然后在有源区域顶部形成栅极； 上述栅极图案 覆盖除了薄膜晶体管两端用于形成源极和漏极区域的全部有源沟道； 光刻绝 缘层形成源极和漏极电接触；横穿区域掺杂剂的单位面积剂量为 1 X 1014/cm2 - 1 X 1016/cm2 , 优选为 2 X 1 015/cm2 一 4 χ 1015/cm2。
25、 如权利要求 21所述的方法， 其特征是在栅极形成后源极或漏极区域 不需要额外的掺杂或激活。
PCT/CN2011/083233 2011-11-30 2011-11-30 搭桥晶粒多晶硅薄膜晶体管及其制造方法 WO2013078641A1 (zh)

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CN1421935A (zh) * 2001-11-27 2003-06-04 三星Sdi株式会社 薄膜晶体管的多晶硅层及其显示器
CN1649174A (zh) * 2003-11-22 2005-08-03 三星Sdi株式会社 薄膜晶体管及其制造方法
CN101681930A (zh) * 2007-06-22 2010-03-24 香港科技大学 具有搭桥晶粒结构的多晶硅薄膜晶体管

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JPS5783047A (en) * 1980-11-10 1982-05-24 Matsushita Electric Ind Co Ltd Polycrystalline semiconductor resistor
JPH06104438A (ja) * 1992-09-22 1994-04-15 Casio Comput Co Ltd 薄膜トランジスタ
US5930609A (en) * 1996-03-22 1999-07-27 U.S. Philips Corporation Electronic device manufacture
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