WO2013076932A1 - Procédé de fabrication d'un dispositif de circuit - Google Patents

Procédé de fabrication d'un dispositif de circuit Download PDF

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Publication number
WO2013076932A1
WO2013076932A1 PCT/JP2012/007260 JP2012007260W WO2013076932A1 WO 2013076932 A1 WO2013076932 A1 WO 2013076932A1 JP 2012007260 W JP2012007260 W JP 2012007260W WO 2013076932 A1 WO2013076932 A1 WO 2013076932A1
Authority
WO
WIPO (PCT)
Prior art keywords
sealing resin
resin
mold
circuit board
sealing
Prior art date
Application number
PCT/JP2012/007260
Other languages
English (en)
Japanese (ja)
Inventor
英行 坂本
安藤　守
坂本　則明
Original Assignee
セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー filed Critical セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー
Publication of WO2013076932A1 publication Critical patent/WO2013076932A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

L'invention concerne un procédé de fabrication pour un dispositif de circuit, selon lequel une étape de scellement de résine pour un scellement avec une couche mince de résine sur une surface arrière d'un substrat de circuit ayant un élément de circuit intégré sur une surface supérieure de celui-ci est réalisée à faible coût. Dans la présente invention, une surface supérieure et une surface latérale d'un substrat de circuit (14) ayant un circuit intégré hybride sont revêtues par une première résine de scellement (18) formée par moulage par transfert, et une surface inférieure de substrat de circuit (14), et une surface inférieure et une surface latérale de la première résine de scellement (18) sont par la suite revêtues par une seconde résine de scellement (20). De plus, dans une étape de formation de la seconde résine de scellement (20), un moulage par transfert stable est réalisé par fixation de la position de la pièce à travailler de telle sorte que les parties faisant saillie de résine (12), obtenues en faisant en sorte que la première résine de scellement (18) fasse saillie partiellement vers le bas, sont en contact avec une paroi interne d'une seconde filière (50).
PCT/JP2012/007260 2011-11-25 2012-11-13 Procédé de fabrication d'un dispositif de circuit WO2013076932A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-257967 2011-11-25
JP2011257967A JP2013115133A (ja) 2011-11-25 2011-11-25 回路装置の製造方法

Publications (1)

Publication Number Publication Date
WO2013076932A1 true WO2013076932A1 (fr) 2013-05-30

Family

ID=48469402

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/007260 WO2013076932A1 (fr) 2011-11-25 2012-11-13 Procédé de fabrication d'un dispositif de circuit

Country Status (2)

Country Link
JP (1) JP2013115133A (fr)
WO (1) WO2013076932A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57154161U (fr) * 1981-03-20 1982-09-28
JPH06209054A (ja) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp 半導体装置
JPH0727166U (ja) * 1993-10-15 1995-05-19 サンケン電気株式会社 樹脂封止型回路装置
JPH11330317A (ja) * 1997-07-03 1999-11-30 Sanyo Electric Co Ltd 混成集積回路装置およびその製造方法
JP2006100759A (ja) * 2004-08-31 2006-04-13 Sanyo Electric Co Ltd 回路装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57154161U (fr) * 1981-03-20 1982-09-28
JPH06209054A (ja) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp 半導体装置
JPH0727166U (ja) * 1993-10-15 1995-05-19 サンケン電気株式会社 樹脂封止型回路装置
JPH11330317A (ja) * 1997-07-03 1999-11-30 Sanyo Electric Co Ltd 混成集積回路装置およびその製造方法
JP2006100759A (ja) * 2004-08-31 2006-04-13 Sanyo Electric Co Ltd 回路装置およびその製造方法

Also Published As

Publication number Publication date
JP2013115133A (ja) 2013-06-10

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