WO2013075355A1 - 一种薄膜晶体管、阵列基板及装置和一种制备方法 - Google Patents

一种薄膜晶体管、阵列基板及装置和一种制备方法 Download PDF

Info

Publication number
WO2013075355A1
WO2013075355A1 PCT/CN2011/083338 CN2011083338W WO2013075355A1 WO 2013075355 A1 WO2013075355 A1 WO 2013075355A1 CN 2011083338 W CN2011083338 W CN 2011083338W WO 2013075355 A1 WO2013075355 A1 WO 2013075355A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
layer
metal layer
oxide layer
Prior art date
Application number
PCT/CN2011/083338
Other languages
English (en)
French (fr)
Inventor
寇浩
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/376,188 priority Critical patent/US20130126870A1/en
Publication of WO2013075355A1 publication Critical patent/WO2013075355A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a thin film transistor, an array substrate and device, and a method of fabricating the same.
  • the liquid crystal display device comprises an array substrate provided with a thin film transistor and a color filter plate provided with a common electrode.
  • the current array substrate is generally prepared by a conventional four- or five-mask process, and the process is performed by using a multilayer film deposition process for performing a yellow light process.
  • the corresponding pattern is etched in the corresponding film layer, and the multilayer film is repeatedly deposited in multiple chambers of physical vapor deposition (PVD) and plasma enhanced chemical vapor deposition (PECVD), and then the respective layers are etched accordingly.
  • PVD physical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the process is complicated: after preparing the metal layer, it is necessary to prepare a non-metal layer to hinder the short circuit between the metal and protect the metal layer.
  • the preparation of the non-metal barrier layer requires the machine and material cost; since the non-metal layer is covered as a whole, It has higher requirements for light penetration, and therefore higher requirements for process control;
  • Mo metal which is widely used at present, is a heavy metal and has a great impact on the environment.
  • the technical problem to be solved by the present invention is to provide a process cartridge, a low cost thin film transistor, an array substrate and device, and a preparation method.
  • a thin film transistor comprising a conductive metal layer, the surface of which is formed with an insulating oxide layer.
  • the metal layer is A1
  • the oxide layer is A1 2 0 3 .
  • A1 2 0 3 has good insulating properties and its dielectric constant is close to that of existing silicon nitride. It is very suitable for replacing silicon nitride as a metal layer. Insulation Materials.
  • the metal layer is one or more of a gate electrode, a source and a drain of the thin film transistor. This is a specific form of the metal layer.
  • An array substrate comprising the above-described thin film transistor.
  • a liquid crystal display device comprising the above array substrate.
  • a method of fabricating a thin film transistor comprising the step of: processing an insulating oxide layer on a surface of a metal layer of the thin film transistor array substrate.
  • the oxide layer is formed by a micro-arc oxidation method.
  • Micro-arc oxidation is generally used to form a dense oxide layer on the surface of the metal to enhance the wear resistance and corrosion resistance of the metal, and is mostly used for the porcelain treatment of the inner surface of the cylinder of an automobile engine.
  • the inventors have found through research that the dense ceramic layer has good insulating properties and can be used as a specific oxide layer manufacturing method, and the process is simple and low in cost.
  • the surface layer of the metal layer is sufficiently oxidized by prolonging the action time of the electrolytic solution to form a dense oxide layer.
  • the dense oxide layer can be more firmly fixed on the surface of the metal layer, which is not easy to fall off, and the insulation effect is better.
  • the metal layer is one or more of a gate electrode, a source and a drain of the thin film transistor. This is a specific form of the metal layer.
  • the metal layer is A1
  • the oxide layer is A1 2 0 3 .
  • A1 2 0 3 has good insulating properties and its dielectric constant is close to that of existing silicon nitride. It is very suitable for replacing silicon nitride as a metal layer. Insulation Materials.
  • a method for preparing a thin film transistor includes the following steps:
  • A1 a gate electrode of a thin film transistor in which a metal is formed on a glass substrate;
  • A2 forming an insulating oxide layer on the metal surface of the gate electrode by using a micro-arc oxidation method
  • A3 continuously depositing an amorphous silicon layer and doping an amorphous silicon layer on the oxide layer of the gate electrode
  • A4 a source electrode and a drain electrode of a thin film transistor forming a metal on the doped amorphous silicon layer;
  • A5 An insulating oxide layer is formed on the metal surfaces of the source and drain electrodes, respectively, by a micro-arc oxidation method.
  • This is a specific technical solution for performing oxidation treatment on the surface of the gate electrode, the source electrode, and the drain electrode of the thin film transistor.
  • the invention oxidizes the surface of the metal layer to form an insulating oxide layer, which can replace silicon nitride as a barrier layer of the thin film transistor, and requires an apparatus and a material cost compared to the preparation of the silicon nitride barrier layer to prepare an oxide layer.
  • the equipment is cheap and does not require additional materials, so it can save costs.
  • the oxide layer exists only on the surface of the metal layer, and the light is less hindered, and the penetration rate is not high. Therefore, the process control is relatively simple, and the cost can be further reduced.
  • Figure 1 is a schematic view of a thin film transistor of the present invention
  • FIG. 2 is a schematic view showing the steps of a method for preparing a thin film transistor of the present invention
  • FIG. 3 is a schematic view showing the second step of the method for preparing the thin film transistor of the present invention.
  • FIG. 4 is a schematic view showing the third step of the method for preparing the thin film transistor of the present invention.
  • FIG. 5 is a schematic view showing the fourth step of the method for preparing the thin film transistor of the present invention.
  • FIG. 6 is a schematic view showing the fifth step of the method for preparing the thin film transistor of the present invention.
  • FIG. 7 is a schematic view showing the sixth step of the method for preparing the thin film transistor of the present invention.
  • FIG. 8 is a schematic view showing the seventh step of the method for preparing the thin film transistor of the present invention.
  • a liquid crystal display device includes an array substrate including a thin film transistor. As shown in FIG. 1 , the thin film transistor is disposed on a glass substrate 1 , and the upper surface is a gate electrode 2 , and the metal oxide layer (ie, the first ceramic layer 3 ) which is a metal electrode treated by the gate electrode 2 is an amorphous silicon layer. 4. The doped amorphous silicon layer 5, the source 6, the drain 7, and the metal oxide layer (ie, the second ceramic layer 8) which is processed after the source/drain 7 metal layer is processed, the contact window 9, and the pixel Electrode 10. The pixel electrode 10 is in contact Window 9 is connected to drain 7.
  • the gate electrode 2, the source electrode 6, and the drain electrode 7 are metal layers, and the first ceramic layer 3 and the second ceramic layer 8 form an oxide layer formed on the surface of the metal layer. Further, by prolonging the working time of the electrolyte, the surface grains of the metal layer are sufficiently oxidized to form a dense oxide layer, so that the oxide layer can be firmly covered on the surface of the metal layer, is not easy to fall off, and the insulating property is also better;
  • the existing thin film transistor uses silicon nitride as the insulating material on the surface of the metal layer. In order to ensure the insulation performance, the capacitance between the metal layers can reliably drive the liquid crystal, so the dielectric constant of the material of the oxide layer is selected from silicon nitride. It will be better to be close. The following is a detailed description of the preparation method of the thin film transistor array substrate of the present invention by taking the metal layer as A1 and the oxide layer as A1 2 0 3 as an example.
  • Step 1 As shown in FIG. 2, the gate electrode 2 is first deposited on the glass substrate 1 by metal A1.
  • Step 2 As shown in FIG. 3, the surface of the metal A1 of the gate electrode 2 is oxidized to form A1 2 by the micro-arc oxidation method. 0 3 , a first ceramic layer 3 serving as an insulating layer, a barrier layer, and a dielectric layer.
  • Step 3 As shown in FIG. 4, the amorphous silicon layer 4 and the doped amorphous silicon layer 5 are successively deposited on the A1 2 0 3 oxide layer of the gate electrode 2.
  • Step 4 As shown in FIG. 5, a metal A1 is used to deposit the source electrode and the drain electrode on the doped amorphous silicon layer 4, and a pattern such as a channel is etched.
  • Step 5 As shown in FIG. 6, the surface of the metal A1 of the source electrode and the drain electrode is oxidized to form A1 2 0 3 by using a micro-arc oxidation method, and serves as a second ceramic layer 8 of an insulating layer, a barrier layer and a dielectric layer.
  • Step 6 As shown in FIG. 7, a through hole is formed by dry etching on the formed ceramic layer to form a contact window 9.
  • Step 7 As shown in FIG. 8, the pixel electrode 10 is deposited and patterned on the A1 2 0 3 oxide layer corresponding to the drain 7.
  • the above is a further detailed description of the present invention in conjunction with a specific preferred embodiment.
  • the metal layer of the present invention is not limited to the use of the metal A1. Accordingly, the oxide layer is not limited to A1 2 0 3 , and all of them have electrical conductivity and can A metal forming an insulating oxide layer can be applied to the present invention.
  • the invention patent CN1252321C discloses an electrolytic solution of micro-arc oxidation treatment of aluminum alloy castings on April 19, 2006.
  • the electrolyte layer of the invention can be used for the oxidation layer.
  • Preparations, specific technical solutions are not described again, of course, other metal oxidation techniques may also be used within the protection scope of the present invention, and those skilled in the art to which the present invention pertains, without departing from the inventive concept, It is also possible to make a number of cartridge deductions or replacements, all of which are considered to be within the scope of the invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管、阵列基板及装置和一种制备方法，所述薄膜晶体管，包括导电金属层（2、6、7），所述金属层（2、6、7）表面形成有绝缘的氧化层（3、8）。由于对金属层（2、6、7）表面进行氧化处理，形成绝缘的氧化层（3、8），该氧化层（3、8）可以替代氮化硅作为薄膜晶体管的阻挡层，相比制备氮化硅阻挡层需要机台及物料成本，制备氧化层（3、8）的设备便宜、而且无需增加额外的物料，因此可以节约成本。另外氧化层（3、8）只存在于金属层（2、6、7）表面，对光线的阻隔少，对穿透率要求不高，因此工艺控制相对简单，可以进一步降低成本。

Description

【技术领域】
本发明涉及液晶显示领域， 更具体的说， 涉及一种薄膜晶体管、 阵列基板 及装置和一种制备方法。
【背景技术】
液晶显示装置包括设有薄膜晶体管的阵列基板和设有公共电极的彩色滤光 板， 目前的阵列基板一般采用常规的四道或五道光罩制程制备， 制程均采用多 层薄膜沉积后进行黄光工艺在对应膜层刻蚀出相应的图形， 需要分别在物理气 相沉积（PVD )、 等离子体增强化学气相沉积（PECVD )多个腔室中反复沉积多 层薄膜随后在对各层进行相应的刻蚀； 目前采用的工艺有明显几点不足：
1. 工艺流程复杂： 在制备金属层后均需要制备非金属层起到阻碍金属间短 路及保护金属层作用， 制备非金属阻挡层需要机台及物料成本； 由于非金属层 为整体覆盖， 因此对其光线穿透性要求较高， 因而也对工艺控制提出较高要求；
2. 设备投入高： 各层薄膜均需要单独成膜， PVD及 PECVD等需要多个腔 室， 提高设备投入；
3. 重金属污染： 目前广泛采用的 Mo金属为重金属， 对环境有较大影响。
【发明内容】
本发明所要解决的技术问题是提供一种工艺筒单、 低成本的薄膜晶体管、 阵列基板及装置和一种制备方法。
本发明的目的是通过以下技术方案来实现的：
一种薄膜晶体管， 包括导电金属层， 所述金属层表面形成有绝缘的氧化层。 优选的， 所述金属层为 A1, 所述氧化层为 A1203。 此为一种具体的金属层和 氧化层材料， A1203作为氧化层， 绝缘性能好，且其介电常数跟现有氮化硅接近， 很适合替代氮化硅作为金属层之间的绝缘材料。 优选的， 所述金属层为所述薄膜晶体管的栅电极、 源极、 漏极中的一种或 多种。 此为金属层的具体形式。
一种阵列基板， 包括上述的一种薄膜晶体管。
一种液晶显示装置， 包括上述的一种阵列基板。
一种薄膜晶体管的制备方法， 包括步骤 A: 在所述薄膜晶体管阵列基板的 金属层表面加工出绝缘的氧化层的步骤。
优选的， 所述步骤 A中， 氧化层采用微弧氧化方法制成。 微弧氧化一般用 于在金属表面形成致密的氧化层， 增强金属的耐磨、 耐腐蚀特性， 多用于汽车 发动机气缸内表面的瓷化处理。 发明人通过研究发现该致密的陶瓷层具有良好 的绝缘性能， 可作为一种具体的氧化层制作方法， 而且其工艺筒单， 成本较低。
优选的， 所述步骤 A中， 通过延长电解溶液的作用时间， 将所述金属层表 面晶粒充分氧化， 形成致密的氧化层。 致密的氧化层可以更牢固的固定在金属 层表面， 不易脱落， 绝缘效果也更好。
优选的， 所述步骤 A中， 金属层为所述薄膜晶体管的栅电极、 源极、 漏极 中的一种或多种。 此为金属层的具体形式。
优选的， 所述金属层为 A1, 所述氧化层为 A1203。 此为一种具体的金属层和 氧化层材料， A1203作为氧化层， 绝缘性能好，且其介电常数跟现有氮化硅接近， 很适合替代氮化硅作为金属层之间的绝缘材料。
一种薄膜晶体管的制备方法， 包括以下步骤：
A1 : 在玻璃基板上形成金属的薄膜晶体管的栅电极；
A2: 采用微弧氧化方法， 在所述栅电极的金属表面形成绝缘的氧化层； A3: 在所述栅电极的氧化层上连续沉积非晶硅层及掺杂非晶硅层；
A4: 在掺杂非晶硅层上形成金属的薄膜晶体管的源电极和漏电极；
A5: 采用微弧氧化方法， 分别在所述源电极和漏电极的金属表面形成绝缘 的氧化层。 此为一种在薄膜晶体管的栅电极、 源电极、 漏电极表面都进行氧化 处理的具体技术方案。 本发明由于对金属层表面进行氧化处理， 形成绝缘的氧化层， 该氧化层可 以替代氮化硅作为薄膜晶体管的阻挡层， 相比制备氮化硅阻挡层需要机台及物 料成本， 制备氧化层的设备便宜、 而且无需增加额外的物料， 因此可以节约成 本。 另外氧化层只存在于金属层表面， 对光线的阻隔少， 对穿透率要求不高， 因此工艺控制相对筒单， 可以进一步降低成本。
【附图说明】
图 1是本发明的薄膜晶体管示意图；
图 2是本发明薄膜晶体管的制备方法的步骤一示意图；
图 3是本发明薄膜晶体管的制备方法的步骤二示意图；
图 4是本发明薄膜晶体管的制备方法的步骤三示意图；
图 5是本发明薄膜晶体管的制备方法的步骤四示意图；
图 6是本发明薄膜晶体管的制备方法的步骤五示意图；
图 7是本发明薄膜晶体管的制备方法的步骤六示意图；
图 8是本发明薄膜晶体管的制备方法的步骤七示意图；
其中： 1、 玻璃基板； 2、 栅电极； 3、 第一陶瓷层； 4、 非晶硅层； 5、 经过 掺杂的非晶硅层； 6、 源极； 7、 漏极； 8、 第二陶瓷层； 9、 接触窗口； 10、 像 素电极。
【具体实施方式】
下面结合附图和较佳的实施例对本发明作进一步说明。
一种液晶显示装置， 包括一种阵列基板， 该阵列基板包括薄膜晶体管。 如图 1所示， 所述薄膜晶体管设置在玻璃基板 1上， 上面依次为栅电极 2、 为栅电极 2金属经处理后的金属氧化层（即第一陶瓷层 3 )、 为非晶硅层 4、 经 过掺杂的非晶硅层 5、 源极 6、 漏极 7、 为源 /漏极 7金属层经处理后产生的金属 氧化层 (即第二陶瓷层 8)、接触窗口 9、像素电极 10。 所述像素电极 10通过接触 窗口 9跟漏极 7连接。 所述栅电极 2、 源极 6、 漏极 7为金属层， 所述第一陶瓷 层 3和第二陶瓷层 8位金属层表面形成的氧化层。 进一步的， 通过延长电解液 的作用时间， 将金属层表面晶粒充分氧化， 可以形成致密的氧化层， 这样氧化 层可以牢固地覆盖在金属层表面， 不易脱落， 而且绝缘性能也更好； 另外， 现 有的薄膜晶体管采用氮化硅作为金属层表面的绝缘材料， 为了保证绝缘性能的 同时， 金属层之间的电容能可靠驱动液晶， 因此氧化层的材质的介电常数选用 跟氮化硅接近的会更好。 下面以金属层为 A1, 氧化层为 A1203为例， 详细介绍 一下本发明薄膜晶体管阵列基板的制备方法。
步骤一： 如图 2所示， 先在玻璃基板 1上采用金属 A1沉积形成栅电极 2 步骤二： 如图 3所示， 采用微弧氧化方法， 在栅电极 2的金属 A1表面氧化 形成 A1203, 充当绝缘层、 阻挡层及介电层的第一陶瓷层 3。
步骤三： 如图 4所示， 在栅电极 2的 A1203氧化层上连续陆续沉积非晶硅层 4及经过掺杂的非晶硅层 5。
步骤四： 如图 5所示， 在掺杂非晶硅层 4上采用金属 A1沉积源电极及漏电 极并刻蚀出沟道等图形。
步骤五： 如图 6所示， 采用微弧氧化方法， 在源电极及漏电极的金属 A1表 面氧化形成 A1203, 充当绝缘层、 阻挡层及介电层的第二陶瓷层 8。
步骤六： 如图 7所示， 采用干刻在形成的陶瓷层上加工出通孔， 形成接触 窗口 9。
步骤七： 如图 8所示， 在漏极 7对应的 A1203氧化层上沉积并图形化像素电 极 10。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 本 发明的金属层不限于采用金属 A1, 相应的， 所述氧化层也不局限于 A1203, 凡是 具备导电性能并能形成绝缘氧化层的金属都能应用于本发明。
发明专利 CN1252321C于 2006年 4月 19 日公开了一种铝合金铸件微弧氧 化处理电解溶液， 本发明中氧化层的制备可选用该发明的电解液进行氧化层的 制备， 具体技术方案不再赘述， 当然也可以采用其他金属氧化技术也在本发明 的保护范围之内， 对于本发明所属技术领域的普通技术人员来说， 在不脱离本 发明构思的前提下， 还可以做出若干筒单推演或替换， 都应当视为属于本发明 的保护范围。

Claims

权利要求
1、 一种薄膜晶体管， 包括： 导电金属层， 所述金属层表面形成有绝缘 的氧化层。
2、 如权利要求 1所述的一种薄膜晶体管， 其特征在于， 所述金属层为 A1, 所述氧化层为 A1203。
3、 如权利要求 1所述的一种薄膜晶体管， 其特征在于， 所述金属层为 所述薄膜晶体管的栅电极、 源极、 漏极中的一种或多种。
4、 一种阵列基板， 包括如权利要求 1所述的一种薄膜晶体管， 所述薄 膜晶体管包括导电金属层， 所述金属层表面形成有绝缘的氧化层。
5、 如权利要求 4 所述的一种阵列基板， 其特征在于， 所述金属层为 A1, 所述氧化层为 A1203。
6、 如权利要求 4所述的一种阵列基板， 其特征在于， 所述金属层为所 述薄膜晶体管的栅电极、 源极、 漏极中的一种或多种。
7、 一种液晶显示装置， 包括如权利要求 4所述的一种阵列基板， 所述 阵列基板包括薄膜晶体管， 所述薄膜晶体管包括导电金属层， 所述金属层 表面形成有绝缘的氧化层。
8、 如权利要求 7所述的一种液晶显示装置， 其特征在于， 所述金属层 为 A1, 所述氧化层为 A1203。
9、 如权利要求 7所述的一种液晶显示装置， 其特征在于， 所述金属层 为所述薄膜晶体管的栅电极、 源极、 漏极中的一种或多种。
10、 一种薄膜晶体管的制备方法， 包括步骤 A: 在所述薄膜晶体管阵 列基板的金属层表面加工出绝缘的氧化层的步骤。
11、 如权利要求 10所述的一种薄膜晶体管的制备方法， 其特征在于， 所述步骤 A中， 氧化层采用微弧氧化方法制成。
12、 一种如权利要求 10所述的一种薄膜晶体管的制备方法， 其特征在 于， 所述步骤 A中， 通过延长电解溶液的作用时间， 将所述金属层表面晶 粒充分氧化， 形成致密的氧化层。
13、 如权利要求 10所述的一种薄膜晶体管的制备方法， 其特征在于， 所述步骤 A中， 金属层为所述薄膜晶体管的栅电极、 源极、 漏极中的一种 或多种。
14、 如权利要求 10所述的一种薄膜晶体管的制备方法， 其特征在于， 所述金属层为 A1, 所述氧化层为 A1203。
15、 一种薄膜晶体管的制备方法， 包括以下步骤：
A1 : 在玻璃基板上形成金属的薄膜晶体管的栅电极；
A2: 采用微弧氧化方法，在所述栅电极的金属表面形成绝缘的氧化层； A3: 在所述栅电极的氧化层上连续沉积非晶硅层及掺杂非晶硅层； A4: 在掺杂非晶硅层上形成金属的薄膜晶体管的源电极和漏电极； A5: 采用微弧氧化方法， 分别在所述源电极和漏电极的金属表面形成 绝缘的氧化层。
PCT/CN2011/083338 2011-11-23 2011-12-02 一种薄膜晶体管、阵列基板及装置和一种制备方法 WO2013075355A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/376,188 US20130126870A1 (en) 2011-11-23 2011-12-02 Thin Film Transistor, Array Substrate, Device and Manufacturing Method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110375847.4 2011-11-23
CN2011103758474A CN102386237A (zh) 2011-11-23 2011-11-23 一种薄膜晶体管、阵列基板及装置和一种制备方法

Publications (1)

Publication Number Publication Date
WO2013075355A1 true WO2013075355A1 (zh) 2013-05-30

Family

ID=45825458

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/083338 WO2013075355A1 (zh) 2011-11-23 2011-12-02 一种薄膜晶体管、阵列基板及装置和一种制备方法

Country Status (2)

Country Link
CN (1) CN102386237A (zh)
WO (1) WO2013075355A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230110228A1 (en) * 2020-03-19 2023-04-13 Fuzhou Boe Optoelectronics Technology Co., Ltd. Thin-film transistor and preparation method therefor, and display substrate and display panel

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334544A (en) * 1992-12-16 1994-08-02 Matsushita Electric Industrial Co., Ltd. Method of making thin film transistors
JPH1093105A (ja) * 1997-08-26 1998-04-10 Canon Inc アクティブマトリクス回路の製造法
CN1554807A (zh) * 2003-12-22 2004-12-15 西安理工大学 铝合金铸件微弧氧化处理电解溶液
CN1713409A (zh) * 2004-06-24 2005-12-28 三星Sdi株式会社 有机薄膜晶体管和制造其的方法
CN101681932A (zh) * 2007-06-05 2010-03-24 株式会社爱发科 薄膜晶体管制造方法、液晶显示装置制造方法、电极形成方法
CN102214698A (zh) * 2010-04-09 2011-10-12 索尼公司 薄膜晶体管、显示装置以及电子单元

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2781706B2 (ja) * 1991-09-25 1998-07-30 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
CN101005108B (zh) * 2006-01-16 2011-07-13 深圳大学 功率型发光二极管热沉及其方法
CN100495177C (zh) * 2006-04-30 2009-06-03 北京京东方光电科技有限公司 一种tft lcd阵列基板器件结构及其制造方法
CN100547736C (zh) * 2006-11-10 2009-10-07 台湾薄膜电晶体液晶显示器产业协会 薄膜晶体管及其有源层的制作方法与液晶显示器
CN100530607C (zh) * 2007-12-11 2009-08-19 西安交通大学 一种ZnO基透明薄膜晶体管阵列的制备方法
CN101634783B (zh) * 2008-07-23 2011-03-23 北京京东方光电科技有限公司 一种薄膜晶体管液晶显示面板像素结构及制造方法
CN101488459B (zh) * 2009-02-13 2010-09-22 北京大学深圳研究生院 一种自对准的金属氧化物薄膜晶体管的制作方法
CN101924175B (zh) * 2010-07-12 2013-11-20 深圳大学 一种发光二极管封装装置及封装方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334544A (en) * 1992-12-16 1994-08-02 Matsushita Electric Industrial Co., Ltd. Method of making thin film transistors
JPH1093105A (ja) * 1997-08-26 1998-04-10 Canon Inc アクティブマトリクス回路の製造法
CN1554807A (zh) * 2003-12-22 2004-12-15 西安理工大学 铝合金铸件微弧氧化处理电解溶液
CN1713409A (zh) * 2004-06-24 2005-12-28 三星Sdi株式会社 有机薄膜晶体管和制造其的方法
CN101681932A (zh) * 2007-06-05 2010-03-24 株式会社爱发科 薄膜晶体管制造方法、液晶显示装置制造方法、电极形成方法
CN102214698A (zh) * 2010-04-09 2011-10-12 索尼公司 薄膜晶体管、显示装置以及电子单元

Also Published As

Publication number Publication date
CN102386237A (zh) 2012-03-21

Similar Documents

Publication Publication Date Title
CN103354218B (zh) 阵列基板及其制作方法和显示装置
JP2012528488A5 (zh)
TW200503085A (en) Custom electrodes for molecular memory and logic devices
JP2014508373A (ja) 電極およびこれを含む電子素子
CN105633170A (zh) 金属氧化物薄膜晶体管及其制备方法以及阵列基板和显示装置
TW201128779A (en) Thin film transistor and method of forming the same
CN102646676A (zh) 一种tft阵列基板
RU2014134810A (ru) Емкостной преобразователь, полученный микрообработкой, и способ его изготовления
US20080151466A1 (en) Electrostatic chuck and method of forming
CN105097548A (zh) 氧化物薄膜晶体管、阵列基板及各自制备方法、显示装置
CN106129063B (zh) 薄膜晶体管阵列基板及其制造方法
KR101854197B1 (ko) 표시 기판 및 이의 제조 방법
CN204392205U (zh) 一种用于无线通信系统的多层压电薄膜体声波谐振器
CN103618004B (zh) 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN104362180B (zh) 一种薄膜晶体管及其制作方法、显示基板和显示装置
CN105990332B (zh) 薄膜晶体管基板及其显示面板
CN106409920B (zh) 一种薄膜晶体管、阵列基板及其制备方法、显示装置
KR102043082B1 (ko) 어레이 기판, 디스플레이 패널 및 이를 갖는 디스플레이 장치, 및 그 제조 방법
CN105629598A (zh) Ffs模式的阵列基板及制作方法
CN105765709B (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2013075355A1 (zh) 一种薄膜晶体管、阵列基板及装置和一种制备方法
WO2022196684A1 (ja) 薄膜トランジスタ、および、薄膜トランジスタの製造方法
CN107123686B (zh) 一种薄膜晶体管及其制作方法、显示面板、显示装置
CN111199956A (zh) 一种半导体器件及其形成方法
JP2020522118A (ja) 導電パターン構造及びその製造方法、アレイ基板、表示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13376188

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11876353

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11876353

Country of ref document: EP

Kind code of ref document: A1