WO2013071480A1 - 用于模拟电路移植的电路优化方法和装置 - Google Patents

用于模拟电路移植的电路优化方法和装置 Download PDF

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Publication number
WO2013071480A1
WO2013071480A1 PCT/CN2011/082184 CN2011082184W WO2013071480A1 WO 2013071480 A1 WO2013071480 A1 WO 2013071480A1 CN 2011082184 W CN2011082184 W CN 2011082184W WO 2013071480 A1 WO2013071480 A1 WO 2013071480A1
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circuit
path
target
optimization
target circuit
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PCT/CN2011/082184
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English (en)
French (fr)
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吴玉平
陈岚
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中国科学院微电子研究所
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Priority to PCT/CN2011/082184 priority Critical patent/WO2013071480A1/zh
Priority to US13/640,594 priority patent/US8516429B2/en
Publication of WO2013071480A1 publication Critical patent/WO2013071480A1/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/36Circuit design at the analogue level
    • G06F30/367Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Definitions

  • This invention relates to the field of integrated circuit design automation and, more particularly, to circuit optimization methods and apparatus for analog circuit migration. Background technique
  • the high degree of automation in digital integrated circuit design has greatly shortened the design cycle of digital integrated circuits.
  • the high degree of manual design of analog integrated circuits allows the design cycle of analog integrated circuits to be typically two to three times the design cycle of digital integrated circuits. Therefore, the design cycle of a mixed-signal integrated circuit is subject to the design cycle of the analog integrated circuit. If the automation of the analog integrated circuit design is improved, the design cycle of the analog integrated circuit can be shortened, and the design cycle of the mixed-signal integrated circuit can be significantly shortened, the design cost can be reduced, and the product competitiveness can be improved.
  • analog circuit migration is a common design method used to reuse source circuits for target circuits.
  • Analog circuit migration typically includes circuit optimization of circuit-level integrated circuit device parameter values and physical optimization of device position and wiring at the graphics level.
  • the first method of circuit optimization is that the designer generally adjusts the device parameter values according to his own design experience, and then performs circuit simulation to check whether the design meets the requirements. Parameter adjustment, circuit simulation, and design checks are repeated until the circuit performance reaches the circuit performance of the source circuit.
  • the disadvantage is that the efficiency of the adjustment process is heavily dependent on the design experience of the integrated circuit designer and the need to accurately understand the effects of device parameters on circuit performance. As the scale and complexity of analog integrated circuits increase, designers are less able to control the accuracy of circuit performance as the device parameters change, so the design efficiency of relying on this design approach is greatly reduced.
  • the second method of circuit optimization is based on device parameter scanning and simulation of the circuit simulator, and then selecting appropriate device parameter values based on the simulation results.
  • the second method is usually supplemented by the former method.
  • the disadvantage is that the number of parameters to be scanned is limited, and the parameters to be scanned need to be manually determined. It is necessary to manually determine the order in which the parameters are scanned, and the parameter values need to be selected according to the simulation values. As analog integrated circuits increase in size and complexity, it can be difficult for a designer to manually determine scan parameters, determine scan order, and select parameter values.
  • the third method of circuit optimization is to randomly adjust the parameter values, perform circuit simulation or symbol analysis to determine the circuit performance, and control the optimization process by optimizing control algorithms such as simulated annealing, genetic algorithm, and micro-particle group algorithm. Optimize device parameter values.
  • control algorithms such as simulated annealing, genetic algorithm, and micro-particle group algorithm.
  • Optimize device parameter values The disadvantage is that the calculation complexity is large and it is not suitable for the rule. Circuit optimization design of analog integrated circuits with large mode and high complexity.
  • the common disadvantage is that the computational complexity is large, and it is not suitable for the circuit optimization design of the large-scale and high-complexity analog integrated circuit.
  • An object of the present invention is to provide a highly efficient circuit optimization method and circuit optimization apparatus for analog circuit migration.
  • a circuit optimization method for analog circuit migration comprising: dividing the source circuit into at least one DC path Determining the order of the at least one DC path; and optimizing the DC path of the target circuit one by one in the stated order.
  • a circuit optimization apparatus for analog circuit migration for reusing a source circuit for a target circuit
  • the circuit optimization apparatus comprising: a circuit simulation unit for performing a source Circuit simulation and target circuit simulation; circuit simulation result analysis unit, connected with the circuit simulation unit, for calculating the node signal of the source circuit and the target circuit by using the simulation results of the source circuit and the target circuit; circuit connection relationship analysis unit, and circuit simulation
  • the analysis unit is connected to analyze the circuit connection relationship of the source circuit to determine the DC path in the source circuit;
  • the circuit adjustment order determining unit is connected to the circuit connection relationship analyzing unit for analyzing the signal of the DC path of the source circuit Arrival order, determining the order of the DC path of the source circuit according to the order of signal arrival;
  • the target circuit device parameter value setting unit is connected with the circuit simulation unit and the optimization control unit for setting the device parameter value of a DC path of the target circuit; Comparison unit And connected to the circuit simulation result analyzing unit, configured to compare the node signals of the one DC path of the target circuit and
  • the circuit optimization method and circuit optimization apparatus of the present invention divides the source circuit into at least one DC path, and uses the DC path as an essential element of circuit optimization, and performs circuit optimization on a DC path according to the determined circuit sequence.
  • the performance indexes of each node of the circuit are realized by DC path one by one, which can ensure that the external port of the circuit under the new process reaches the final target performance index.
  • the circuit optimization method and apparatus reduce the complexity of the optimization calculation, significantly reduce the number of invalid attempts in the optimization process, and improve the efficiency of circuit optimization in the analog circuit migration.
  • FIG. 1 shows a flow chart of a circuit optimization method for analog circuit migration in accordance with an embodiment of the present invention.
  • Fig. 2 is a diagram showing the analysis of circuit connection relationships in a circuit optimization method for analog circuit migration according to an embodiment of the present invention.
  • Fig. 3 is a flow chart showing the implementation of optimization control in a circuit optimization method for analog circuit migration according to an embodiment of the present invention.
  • FIG. 4 shows a schematic block diagram of a circuit optimization apparatus for analog circuit migration in accordance with an embodiment of the present invention. detailed description
  • the term “external port” refers to an input/output port between a source circuit or a target circuit as a whole and an external circuit;
  • the term “node” refers to a connection point between a source circuit or portions of a target circuit, including a device.
  • the term “signal branch” refers to the signal path from the node to the other node in the source circuit or the target circuit through the corresponding device;
  • the term “direct current path” refers to the power source to the ground.
  • the term “signal arrival sequence” refers to the sequence in which the signal reaches the different modules, DC paths, or devices in the direction of signal propagation. For example, the signal first arrives at the input and finally reaches the output.
  • the source circuit and the target circuit each include a plurality of devices connected at a plurality of nodes.
  • the source circuit and the target circuit can be respectively divided into corresponding at least one module, such as a power module, a receiving module, an amplifying module, a signal processing module, and the like.
  • Each module includes a part of the components, and each module is connected at a node between the modules, and each device is connected at a node between the modules and a node between the modules.
  • the inventors have recognized that the shortcoming of the existing circuit optimization method is that in the circuit optimization process of the analog circuit migration, the performance index of the external port of the source circuit is used as an optimization target, but the performance indexes of each node of the source circuit are neglected. .
  • it is the performance metrics of the various nodes of the source circuit that ensure that the external ports of the source circuit reach the final performance specifications. Therefore, if the performance indication of each node of the source circuit is taken as an optimization target, the computational complexity can be alleviated.
  • step S101 source circuit simulation is performed (step S101).
  • Source circuit simulation can use commercial circuit simulation tools such as Spectre from Cadence and Hspice from Synopsys.
  • Source circuit simulation includes DC analysis, AC analysis, transient analysis, and other numerical analysis of the circuit for the entire source circuit.
  • the technical methods used in these analyses are not described in detail herein, and specific reference can be made to the disclosed technical references and related technical papers.
  • the source circuit simulation result is analyzed (step S102).
  • the analysis includes the use of source circuit simulation results to calculate DC analysis signal values/distributions and functions corresponding to nodes and branches, AC analysis signal values/distributions and functions, transient analysis signal values/distributions, and functions.
  • the object or range of analysis of the source circuit simulation results is the voltage, branch current, and function calculation based on the former of all nodes of the source circuit.
  • the analysis includes DC path analysis and signal flow analysis (including feedback analysis).
  • the source circuit can be divided into a circuit module 1, a circuit module 2, a circuit module 3, a circuit module 4, a circuit module 5, a circuit module 6, ..., a circuit module Nm, as shown in Fig. 2.
  • the device is traversed in the direction of current flow in the device until it reaches any ground of the circuit.
  • the direction of current flow in the MOS transistor is from drain to source
  • the direction of current flow in the bipolar transistor is from collector to emitter
  • the direction of current flow in the resistor is from one end to the other, in the diode
  • the current flow direction is from the P terminal to the N terminal.
  • several devices capable of independently providing a complete DC current path connected between the same power supply terminal and the same ground terminal can be used as one DC path.
  • at least one DC path can be determined.
  • the circuit module 4 can be divided into a DC path 1, a DC path 2, a DC path 3, a DC path 4, a DC path 5, a DC path 6, ..., a DC path Np.
  • each DC path is treated as a whole based on the DC path analysis. That is, the circuit module has a DC path as a basic element. For each circuit module, from the input, traverse the DC path in the direction of signal propagation until the output. The sequence in which the signal in the signal propagation path reaches the DC path is marked with the signal arrival depth. For example, if the signal passing through the current DC path reaches the depth N, then the signal arrival depth of the DC path through which the signal flows is determined to be N+l.
  • the circuit adjustment order is determined (step S104).
  • the order of the circuit modules and the DC path can be determined based on the order in which the signals arrive.
  • the order of the circuit modules is the circuit module 1, the circuit module 2, the circuit module 3, the circuit module 4, the circuit module 5, the circuit module 6, ..., the circuit module Nm, wherein, for the circuit module 4, DC
  • the order of the paths is a direct current path 1, a direct current path 2, a direct current path 3, a direct current path 4, a direct current path 5, a direct current path 6, ..., and a direct current path Np.
  • step S105 the target circuit device parameter value is set (step S105). This step includes setting initial parameter values for the circuit device and setting intermediate parameter values for the circuit device during device parameter optimization.
  • Two methods can be used to set the initial parameter values of the target circuit device - a)
  • Pi is set to any random value between the lower limit value ⁇ and the upper limit value Pi H of the device parameter; or
  • the method a) is easy to implement, but due to the uncertainty of the random method, the initial value is far from the final optimization point, and the subsequent optimization iteration requires relatively many times.
  • Method b) is slightly more complicated than the former, but the new value is closer to the final optimization point, and the subsequent optimization iterations require relatively few times.
  • method b) optimization efficiency is more efficient than method a).
  • the intermediate parameter value Pi is set to any random value between the lower limit value ⁇ and the upper limit value Pi mac of the device parameter, and the relationship between the circuit performance and the target value under the current value of the parameter is ignored; or b) determining the corresponding device parameter value according to the difference between the performance evaluation value of each DC path of the target circuit and the performance value of the corresponding one DC path of the source circuit and the device parameter value affecting the direction/trend/amplitude of the circuit performance Adjust direction and adjustment range,
  • LD Pi is the i-th value before adjustment device parameters Pi.;
  • Fspec is the target value of circuit performance
  • Fmeas is the value of Pi of the ith device parameter Pi.
  • k is the influence factor of the i-th device parameter Pi on the circuit performance. When k is 0, the value of Pi is unchanged.
  • an optimal Pi may be determined in a linear programming manner for the plurality of circuit performance indicators described above, as shown in the following equation:
  • Fsp eCj is the target value of the jth circuit performance indicator
  • Fcalcj is the calculated value of the jth circuit performance index in the i-th device parameter Pi; is the performance parameter of the jth circuit performance index, the i-th device parameter Pi on the circuit performance, when kj is 0, Pi The value is unchanged.
  • the method a) is easy to implement, but due to the uncertainty of the random method, the change of the parameter value may be inconsistent with the direction that needs to be changed, resulting in an invalid attempt. Even if the change of the parameter value is consistent with the direction that needs to be changed in the direction, it is farther away from the final optimization point in the amplitude, and the number of subsequent optimization iterations is relatively more.
  • the method b) is slightly more complicated than the former, but the new value is consistent with the final optimization point in the direction, and gradually approaches the final optimization point in the amplitude change, and the number of attempts to reach the final optimization point is relatively small. Thus, method b) optimization efficiency is more efficient than method a).
  • step S106 the target circuit simulation is performed (step S106) and the target circuit simulation result is analyzed (step S107).
  • the target circuit simulation performed in step S106 can use a similar circuit simulation tool as the source circuit simulation performed in step S101, and a similar analysis is performed, so a detailed description is omitted here.
  • the object and range of the target circuit simulation are different from the source circuit simulation.
  • the DC path is used as an essential element of circuit optimization, and therefore the object of the target circuit simulation is a DC path of the target circuit.
  • Circuit optimization is performed on a DC-by-DC path in accordance with the circuit sequence determined in step S104.
  • the DC path of the first target circuit simulation is the first DC path of the first circuit module
  • the second circuit simulation is performed by the second DC path of the first circuit module
  • the range of target circuit simulation is the node voltage, the branch current, and the function calculation based on the former between the current DC path of the target circuit and all previous DC paths.
  • the corresponding node signals between the source circuit and the target circuit are compared (step S108).
  • the DC path is used as an essential element of circuit optimization, and therefore the comparison step includes calculation of corresponding nodes, branches, and functions between the current DC path of the target circuit and the corresponding DC path of the source circuit. Information is compared. Then, it is judged that the target circuit performance satisfies the design requirement (step S109). If the target circuit performance satisfies the design requirements, the circuit optimization is ended (step S110).
  • step S105 if the target circuit performance does not meet the design requirements, then go to step S105 and re-execute the operations of steps S105-S109, that is, determine the new parameter value of the target circuit device and/or select the next DC path of the target circuit as a new one. Simulation object.
  • Fig. 3 is a flow chart showing the implementation of optimization control in a circuit optimization method for analog circuit migration according to an embodiment of the present invention.
  • the optimization control condition is set in the above step S109, and the main steps include:
  • step S10901 it is checked whether the overall optimization result of the target circuit satisfies the design requirements. If yes, go to step S110 to end the circuit optimization. If not, go to step S10902 to perform further processing.
  • step S10902 it is checked whether the current DC path of the target circuit satisfies the design requirements. If yes, go to step S10903 to select the next DC path of the target circuit as a new simulation object, and further go to step S105 to re-execute the operations of steps S105-S109, that is, determine the target for the next DC path of the target circuit. The initial parameter value of the circuit device. If no, go to step S10904 to perform further processing.
  • step S10904 it is checked whether the number of optimized iterations of the current DC path of the target circuit at a certain simulated annealing temperature or under generation reaches a limit value. If yes, go to step S10905 to change the simulated annealing temperature and/or genetic generation, and further go to step S105 to re-execute the operations of steps S105-S109, that is, for the current DC path of the target circuit, at the new simulated annealing temperature. And/or genetic generation to optimize target circuit device parameter values. If not, the process goes to step S105, and the operations of steps S105-S109 are re-executed, i.e., the new parameter values of the target circuit device are determined for the current DC path of the target circuit.
  • circuit sequence is determined by analysis using the source circuit when the target circuit is circuit-optimized one by one.
  • circuit optimization for the target circuit is performed on a circuit-by-circuit basis.
  • circuit optimization method for analog circuit migration in accordance with the present invention is described above, dividing the source circuit and the target circuit into corresponding circuit modules and corresponding DC paths within each circuit module.
  • the entire circuit can be divided as a DC path as a whole without dividing the circuit into circuit modules. For example, when the circuit scale is small or the feedback loop is complex, it is more efficient to optimize the entire circuit as a whole analysis.
  • the circuit optimization device comprises: a circuit simulation unit U101, a circuit simulation result analysis unit U102, a circuit connection relationship analysis unit U103, a circuit adjustment order determining unit U104, and a target circuit device parameter value setting unit.
  • U105, signal comparison unit U106, and optimization control unit U107 Each unit of the circuit optimization device can be implemented as one of hardware, software, and firmware, or a combination thereof.
  • the circuit simulation unit U101 performs DC analysis, AC analysis, transient analysis, and other numerical analysis of the circuit for each of the source circuit and the target circuit.
  • the circuit simulation result analysis unit U102 is connected to the circuit simulation unit U101.
  • the circuit simulation result analysis unit U102 uses the simulation results of the source circuit and the target circuit to calculate the DC analysis signal value/distribution and function corresponding to the node and the branch, the AC analysis signal value/distribution and function, the transient analysis signal value/distribution and the function.
  • the same circuit simulation unit U101 and circuit simulation result analysis unit U102 are used for the simulation and simulation result analysis of the source circuit and the target circuit.
  • the object and range of the target circuit simulation are different from the source circuit simulation.
  • the object or range of analysis of the source circuit simulation results is the voltage of all nodes of the source circuit, the branch current, and the function calculation based on the former.
  • the DC path is used as an essential element of circuit optimization, so the object of the target circuit simulation is a DC path of the target circuit, and the circuit is optimized one by one according to the determined circuit adjustment sequence.
  • the DC path of the first target circuit simulation is the first DC path of the first circuit module
  • the second circuit simulation is performed by the second DC path of the first circuit module, and so on.
  • the range of target circuit simulation is the node voltage, the branch current, and the function calculation based on the former between the current DC path of the target circuit and all previous DC paths.
  • the circuit connection relationship analyzing unit U103 is connected to the circuit simulation result analyzing unit U102.
  • the circuit connection relationship analyzing unit U103 analyzes the circuit connection relationship of the source circuit, wherein from the power supply terminal, the device is traversed according to the flow direction of the current in the device until any ground terminal of the circuit to determine at least one DC path.
  • the circuit adjustment order determining unit U104 is connected to the circuit connection relationship analyzing unit U103.
  • the circuit adjustment order determining unit U104 analyzes the signal arrival order of the DC path of the source circuit, wherein the DC path is traversed from the input end in the signal propagation direction until the output end, to obtain the signal arrival order of each DC path, and then according to the signal arrival order Determine the order of the circuit modules and DC paths.
  • the target circuit device parameter value setting unit U105 is connected to the circuit simulation unit U101 and the optimization control unit U107.
  • the target circuit device parameter value setting unit U105 supplies the circuit simulation unit U101 with the initial parameter value of the target circuit device, and in the device parameter optimization process, provides the middle of the target circuit device to the circuit simulation unit U101 according to the control signal of the optimization control unit U107. Parameter value.
  • the signal comparison unit U106 is connected to the circuit simulation result analysis unit U102.
  • the signal comparison unit U106 compares information such as the corresponding node, branch and function calculation results between the current DC path of the target circuit and the corresponding DC path of the source circuit.
  • the optimization control unit U107 is connected to the signal comparison unit U106 and the target circuit device parameter value setting unit U105.
  • the optimization control unit U107 supplies a control signal to the target circuit device parameter value setting unit U105 according to the comparison result of the signal comparison unit U106, or causes the target circuit device parameter value setting unit U105 to set the device of the current DC path of the target circuit in the middle of the optimization process.
  • the parameter value is used for a new circuit optimization attempt, or the target circuit device parameter value setting unit U105 sets the device initial parameter value of the next DC path of the target circuit in the optimization process, and optimizes the circuit by DC path according to the determined circuit adjustment sequence. .
  • the optimization control unit U107 changes the simulated annealing temperature and/or the genetic generation to perform a new circuit optimization attempt when the simulated annealing temperature and/or the generation of the number of optimization attempts causing the inefficiency exceeds the limit value.
  • the optimization control unit U107 ends the circuit optimization process when the circuit optimization of all the DC paths in the target circuit is completed (ie, the target circuit performance satisfies the overall design requirements).
  • the above circuit optimization method and circuit optimization apparatus for analog circuit migration use the DC path as an essential element of circuit optimization, which reduces the complexity of the optimization calculation and significantly reduces the number of invalid attempts in the optimization process.
  • the target circuit has the same adjustment object and range as the source circuit, that is, includes the voltage of all the nodes of the target circuit, the branch current, and the function calculation based on the former.
  • the source circuit consists of 50 devices, and there are 8 cases for each device's exploration space.
  • the selection space of the whole circuit is 8 5 ⁇ , and the hit probability per iteration in the optimization process is 1/8 5 °.
  • the device optimization parameter adjustment of the target circuit is performed simultaneously for all devices, and the actual optimization attempt time T a chorus of the target circuit can be expressed as
  • DC path analysis and signal flow analysis are used to determine the device composition of each DC path and the sequence between the DC paths in the optimization process, and circuit optimization is performed one by one according to the determined circuit adjustment sequence. .
  • the source circuit includes 50 devices, and there are eight cases for each device selection space. Further, it is assumed that the source circuit can be divided into 10 DC paths, and there are 5 devices on each DC path. The selection space for each DC path is 8 5 , and the hit probability for each iteration in the optimization process is 1/8 5 .
  • the actual optimization attempt time T all of the target circuit can be expressed as

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Abstract

本申请公开了一种用于模拟电路移植的电路优化方法和装置,该模拟电路移植用于将源电路重用于目标电路,该电路优化方法包括:将源电路划分成至少一个直流通路;确定所述至少一个直流通路的顺序;以及按照所述顺序逐个优化目标电路的直流通路。该电路优化方法和装置提髙了模拟电路移植中电路优化的效率。

Description

用于模拟电路移植的电路优化方法和装置 技术领域
本发明涉及集成电路设计自动化领域, 更具体地, 涉及用于模拟电路移植的电路 优化方法和装置。 背景技术
数字集成电路设计的高度自动化使得数字集成电路的设计周期大大缩短。与此相 比,模拟集成电路设计的高度手工化使得模拟集成电路的设计周期一般两三倍于数字 集成电路的设计周期。 因此, 混合信号集成电路的设计周期受制于模拟集成电路的设 计周期。 如果提高模拟集成电路设计的自动化程度, 就可以缩短模拟集成电路的设计 周期, 并且可以明显缩短混合信号集成电路的设计周期, 降低其设计成本, 提高产品 竞争力。
在模拟集成电路设计中, 模拟电路移植是一种常见的设计方法, 用于将源电路重 用于目标电路。模拟电路移植一般包括电路级的集成电路器件参数值的电路优化和版 图级的器件位置和连线的物理优化。
在模拟电路移植中, 电路优化的第一种方法是一般是设计人员根据自己的设计经 验调整器件参数值,然后进行电路仿真,检查设计是否符合要求。不断重复参数调整、 电路仿真和设计检査, 直到电路性能达到源电路的电路性能。 其缺点是, 调整过程的 效率严重依赖于集成电路设计人员的设计经验和对器件参数对电路性能的影响必须 有准确的理解。 随着模拟集成电路规模和复杂度的提高, 设计人员对电路性能随器件 参数的变化地准确性的掌控降低, 因此依赖这种设计方法的设计效率会大为降低。
在模拟电路移植中, 电路优化的第二种方法是基于电路仿真器的器件参数扫描、 仿真, 进而根据仿真结果选择合适的器件参数值。 第二种方法通常作为前一种方法的 补充。 其缺点是, 扫描的参数数量有限, 需要人工确定被扫描的参数, 需要人工确定 参数被扫描的先后顺序, 需要根据仿真值选择参数值。 随着模拟集成电路规模和复杂 度的提高, 设计人员手工确定扫描参数、 确定扫描顺序、 选择参数值会变得很困难。
在模拟电路移植中, 电路优化的第三方法是随机调整参数值, 进行电路仿真或符 号分析确定电路性能, 整体通过优化控制算法, 如模拟退火、 遗传算法、 微粒子群算 法等, 控制优化过程, 实现器件参数值的优化。 其缺点是, 计算复杂度大, 不适合规 模大和复杂度高的模拟集成电路的电路优化设计。
无论第一种方法、 第二种方法、 还是第三种方法, 其共同缺点是计算复杂度大, 不适合规模大和复杂度高的模拟集成电路的电路优化设计。 发明内容
本发明的目的在于提供一种高效率的用于模拟电路移植的电路优化方法和电路 优化装置。
根据本发明的一方面, 提供一种用于模拟电路移植的电路优化方法, 该模拟电路 移植用于将源电路重用于目标电路, 所述电路优化方法包括: 将源电路划分成至少一 个直流通路; 确定所述至少一个直流通路的顺序; 以及按照所述顺序逐个优化目标电 路的直流通路。
根据本发明的另一方面, 提供一种用于模拟电路移植的电路优化装置, 该模拟电 路移植用于将源电路重用于目标电路, 所述电路优化装置包括: 电路仿真单元, 用于 进行源电路仿真和目标电路仿真; 电路仿真结果分析单元, 与电路仿真单元相连接, 用于利用源电路和目标电路的仿真结果计算源电路和目标电路的节点信号; 电路连接 关系分析单元, 与电路仿真结果分析单元相连接, 用于分析源电路的电路连接关系, 以确定源电路中的直流通路; 电路调整顺序确定单元, 与电路连接关系分析单元相连 接, 用于分析源电路的直流通路的信号到达顺序, 根据信号到达顺序确定源电路的直 流通路的顺序; 目标电路器件参数值设置单元, 与电路仿真单元和优化控制单元相连 接, 用于设置目标电路的一个直流通路的器件参数值; 信号比较单元, 与电路仿真结 果分析单元相连接,用于比较目标电路的所述一个直流通路和源电路的相应的一个直 流通路的节点信号; 以及优化控制单元, 与信号比较单元和目标电路器件参数值设置 单元相连接, 用于根据信号比较单元的比较结果, 向目标电路器件参数值设置单元提 供控制信号, 从而按照所述顺序逐个优化目标电路的直流通路。
本发明的电路优化方法和电路优化装置将源电路划分成至少一个直流通路, 以直 流通路作为电路优化的基本要素, 按照确定的电路顺序逐个直流通路进行电路优化。
在模拟电路移植的电路优化设计时, 逐个直流通路实现电路各节点的性能指标, 可以保证新工艺下电路的外部端口达到最终的目标性能指标。 而且, 该电路优化方法 和装置降低了优化计算的复杂度, 显著减少优化过程的无效尝试次数, 提高了模拟电 路移植中电路优化的效率。 附图说明
图 1示出了根据本发明实施例的用于模拟电路移植的电路优化方法的流程图。 图 2示出了在根据本发明实施例的用于模拟电路移植的电路优化方法中进行电路 连接关系分析的示意图。
图 3示出了在根据本发明实施例的用于模拟电路移植的电路优化方法中实现优化 控制的流程图。
图 4示出了根据本发明实施例的用于模拟电路移植的电路优化装置的示意框图。 具体实施方式
在本申请中, 术语 "外部端口"指源电路或目标电路作为整体与外部电路之间的 输入 /输出端口; 术语 "节点"指源电路或目标电路的各个部分之间的连接点, 包括 器件之间、 模块之间的连接点; 术语 "信号支路"指源电路或目标电路中从一个节点 到另一个节点之间经过相应的器件的信号路径; 术语 "直流通路"指从电源到地之间 经过相应的器件的直流路径; 术语 "信号到达顺序"指信号在信号传播方向上到达不 同模块、 直流通路或器件的先后顺序, 例如信号最先到达输入端, 最后到达输出端。
通常, 源电路和目标电路各自包括在多个节点处相连的多个器件。 根据不同电路 部分实现的相对独立的功能,可以将源电路和目标电路分别划分成相对应的至少一个 模块, 如电源模块、 接收模块、 放大模块、 信号处理模块等。 每个模块包括一部分器 件, 并且各个模块在模块之间的节点处相连接, 各个器件在模块内的节点和模块之间 的节点处相连接。
本发明人认识到现有的电路优化方法存在的缺点原因在于在模拟电路移植的电 路优化过程中, 使用源电路的外部端口的性能指标作为优化目标, 却忽略了源电路的 各节点的性能指标。然而, 正是源电路的各节点的性能指标确保了源电路的外部端口 的达到了最终的性能指标。 因此, 如果以源电路的各节点的性能指示作为优化目标, 则可以减轻计算复杂度。
为了使本发明的目的、 技术方案及优点更加清楚明白, 以下结合附图及实施例, 对本发明进行进一步详细说明。应当理解, 此处所描述的具体实施例仅用以解释本发 明, 并不用于限定本发明。
图 1示出了根据本发明实施例的用于模拟电路移植的电路优化方法的流程图。 首先, 执行源电路仿真 (步骤 S101 )。 源电路仿真可以釆用商业化的电路仿真工 具, 如 Cadence公司的 Spectre和 Synopsys公司的 Hspice。
源电路仿真包括对整个源电路进行直流分析、 交流分析、 瞬态分析和电路的其他 数值分析。这些分析所釆用的技术方法在本文中不再详述, 具体可参考公开的技术参 考书和相关技术论文。
然后, 分析源电路仿真结果 (步骤 S102)。 该分析包括利用源电路仿真结果计算 节点和支路对应的直流分析信号值 /分布及函数、 交流分析信号值 /分布及函数、 瞬态 分析信号值 /分布及函数。 对源电路仿真结果进行分析的对象或范围是源电路的全部 节点的电压、 支路电流、 以及基于前者的函数计算。
然后, 分析电路连接关系 (步骤 S103)。 该分析包括直流通路分析和信号流分析 (含反馈分析)。
在分析电路连接关系时, 可以将源电路划分为电路模块 1、 电路模块 2、 电路模 块 3、 电路模块 4、 电路模块 5、 电路模块 6、 ……、 电路模块 Nm, 如图 2所示。
在直流通路分析中, 对于每个电路模块, 从任一电源端开始, 按照电流在器件内 的流动方向遍历器件, 直到电路的任一接地端。 例如, 在 M0S晶体管中的电流流动方 向是从漏到源, 在双极晶体管中的电流流动方向是从集电极到发射极, 在电阻中的电 流流动方向是从一端到另一端, 在二极管中的电流流动方向是从 P端到 N端。 结果, 可以将连接在同一个电源端和同一个接地端之间的能够独立提供完整直流电流路径 的几个器件作为一个直流通路。 对于每个电路模块, 可以确定至少一个直流通路。 例 如, 在图 2中, 电路模块 4可以划分成直流通路 1、 直流通路 2、 直流通路 3、 直流通 路 4、 直流通路 5、 直流通路 6、 ……、 直流通路 Np。
在信号流分析中,在直流通路分析的基础上,将每个直流通路作为一个整体处理。 也即, 电路模块以直流通路为基本元素。 对于每个电路模块, 从输入端开始, 按信号 传播方向遍历直流通路, 直到输出端。 信号传播路径中信号到达直流通路的先后顺序 以信号到达深度进行标记,例如,若赋予信号流经当前直流通路的信号到达深度为 N, 那么确定该信号后续流经的直流通路的信号到达深度为 N+l。
然后, 确定电路调整顺序 (步骤 S104)。 根据信号到达顺序, 可以确定电路模块 和直流通路的顺序。
例如, 在图 2中, 电路模块的顺序是电路模块 1、 电路模块 2、 电路模块 3、 电路 模块 4、 电路模块 5、 电路模块 6、 ……、 电路模块 Nm, 其中, 对于电路模块 4, 直流 通路的顺序是直流通路 1、 直流通路 2、 直流通路 3、 直流通路 4、 直流通路 5、 直流 通路 6、 ……、 直流通路 Np。
然后, 对于每一个直流通路, 设置目标电路器件参数值 (步骤 S105)。 该步骤包 括设置电路器件的初始参数值和在器件参数优化过程中设置电路器件的中间参数值。
在设置目标电路器件的初始参数值时可釆用两种方法- a)采用随机方法确定目标电路器件的初始参数值, Pi = rand[Pi, Pi„] , 即目标 电路器件的初始参数值 Pi设置为器件参数的下限值 Ρΰ和上限值 PiH之间任一随机值; 或
b)根据源电路器件之间比例关系以及新旧工艺特征尺寸之间的比例关系确定目 标电路器件的初始参数值。
在上述两种方法中, 方法 a) 易于实现, 但由于随机方法的不确定性导致初始值 距离最终的优化点较远, 后续优化迭代需要的次数相对较多。 方法 b) 较前者实现略 显复杂,但新值产生更接近最终的优化点,后续优化迭代需要的次数相对较少。因而, 方法 b) 优化效率比方法 a) 的优化效率更高。
在器件参数优化过程中设置目标电路器件的中间参数值可采用两种方法: a) 采用随机方法确定目标电路器件的中间参数值, Pi = rand [PiL, Pi„] , 即确 定目标电路器件的中间参数值 Pi设置为器件参数的下限值 Ρΰ和上限值 Pi„之间任一 随机值, 而忽略了与参数当前取值下的电路性能和目标值的差距之间的关系; 或 b ) 根据目标电路的每一个直流通路的性能评估值与源电路的相应的一个直流通 路的性能值之间的差异幅度以及器件参数值对电路性能影响方向 /趋势 /幅度确定对 应器件参数值的调整方向和调整幅度,
Pi,„ = Pioid + (fspec - fmeas) *k (1)
其中,
Pi„。》.是第 i个器件参数 Pi调整后的值, 如果 fspec = fmeas, 则 Pi取值不变; Pi。ld是第 i个器件参数 Pi调整前的值;
fspec是电路性能的目标值;
fmeas是第 i个器件参数 Pi的值为 Pi。ld时的电路性能的实际值;
k是第 i个器件参数 Pi对电路性能影响因子, k为 0时, Pi取值不变。
如果参数 Pi影响多个电路性能指标, 则仍然可以针对一个主要电路性能指标确 定目标电路器件的中间参数值。 替代地, 根据设计要求, 可以针对上述多个电路性能指标以线性规划的方式确定 最优的 Pi,, 如下式所示:
min (∑ (fspecj - fcalcj) 2) (2)
其中,
fcalcj = fmeas + kj * (Pinew― Pi。ld) (3)
其中,
fspeCj是第 j个电路性能指标的目标值;
fcalcj 是在第 i个器件参数 Pi的值为 寸第 j个电路性能指标的计算值; 是针对第 j个电路性能指标, 第 i个器件参数 Pi对电路性能影响因子, kj为 0 时, Pi取值不变。
在上述两种方法中, 方法 a) 易于实现, 但由于随机方法的不确定性, 参数值的 改变在方向上与需要改变的方向可能不一致, 从而导致无效尝试。 即使参数值的改变 在方向上与需要改变的方向一致, 但在幅度上距离最终的优化点较远, 后续优化迭代 需要的次数相对较多。 方法 b ) 较前者实现略显复杂, 但新值产生在方向上与最终的 优化点一致, 而且在幅度改变上逐步趋近于最终的优化点, 达到最终的优化点的尝试 次数相对较少。 因而, 方法 b ) 优化效率比方法 a) 的优化效率更高。
然后, 执行目标电路仿真 (步骤 S106) 和分析目标电路仿真结果 (步骤 S107)。 在步骤 S106中执行的目标电路仿真可以与在步骤 S101中执行的源电路仿真使用类似 的电路仿真工具, 并进行类似的分析, 故在此省略详细的描述。
然而, 目标电路仿真的对象和范围与源电路仿真不同。 如上所述, 在本发明中以 直流通路作为电路优化的基本要素, 因此目标电路仿真的对象是目标电路的一个直流 通路。 根据在步骤 S104中确定的电路顺序逐个直流通路进行电路优化。 例如, 第一 次目标电路仿真的直流通路是第一电路模块的第一直流通路,第二次电路仿真的对象 是第一电路模块的第二直流通路, 依此类推。 而且, 目标电路仿真的范围是目标电路 的当前直流通路与之前的所有直流通路之间的节点电压、支路电流、 以及基于前者的 函数计算。
然后, 对源电路、 目标电路之间对应的节点信号进行比较 (步骤 S108 )。 如上所 述, 在本发明中以直流通路作为电路优化的基本要素, 因此该比较步骤包括对目标电 路的当前直流通路和源电路的相应直流通路之间的相应节点、支路和函数计算结果等 信息进行比较。 然后, 判断目标电路性能满足设计要求 (步骤 S109)。 如果目标电路性能满足设 计要求, 则结束电路优化 (步骤 S110)。 相反, 如果目标电路性能未满足设计要求, 则转至步骤 S105 ,重新执行步骤 S105-S109的操作, 即确定目标电路器件的新的参数 值和 /或选择目标电路的下一个直流通路作为新的仿真对象。
图 3示出了在根据本发明实施例的用于模拟电路移植的电路优化方法中实现优化 控制的流程图。在本发明的优选实施例中, 在上述的步骤 S109中设置优化控制条件, 主要步骤包括:
在步骤 S10901 中, 检查目标电路的整体优化结果是否满足设计要求。 如果是, 则转至步骤 S110以结束电路优化。如果否,则转至步骤 S10902以执行进一步的处理。
在步骤 S10902中, 检査目标电路的当前直流通路是否满足设计要求。 如果是, 则转至步骤 S10903 以选择目标电路的下一个直流通路作为新的仿真对象, 进一步地 转至步骤 S105 ,重新执行步骤 S105-S109的操作, 即针对目标电路的下一个直流通路 确定目标电路器件的初始参数值。如果否, 则转至步骤 S10904以执行进一步的处理。
在步骤 S10904中, 检查目标电路的当前直流通路在一定模拟退火温度下或遗传 代 (generation ) 下的优化迭代次数是否达到极限值。 如果是, 则转至步骤 S10905 以改变模拟退火温度和 /或遗传代,进一步地转至步骤 S105,重新执行步骤 S105-S109 的操作, 即针对目标电路的当前直流通路, 在新的模拟退火温度和 /或遗传代下优化 目标电路器件参数值。 如果否, 则转至步骤 S105, 重新执行步骤 S105-S109的操作, 即针对目标电路的当前直流通路确定目标电路器件的新的参数值。
应当注意, 在对目标电路逐个直流通路进行电路优化时, 按照利用源电路的分析 而确定的电路顺序。在从一个电路模块的最后一个直流通路至下一个电路模块的第一 个直流通路时, 对目标电路的电路优化是逐个电路模块进行的。
在上文中描述了根据本发明的用于模拟电路移植的电路优化方法的一个实施例, 将源电路和目标电路划分成对应的电路模块以及位于每个电路模块内的相对应的直 流通路。 然而, 在替代的实施例中, 可以将整个电路作为整体划分成直流通路, 而不 将电路划分成电路模块。 例如, 在电路规模小或反馈回路复杂时, 将整个电路作为整 体分析的优化效率更高。
图 4示出了根据本发明实施例的用于模拟电路移植的电路优化装置的示意框图。 该电路优化装置包括: 电路仿真单元 U101、 电路仿真结果分析单元 U102、 电路连接 关系分析单元 U103、 电路调整顺序确定单元 U104、 目标电路器件参数值设置单元 U105、 信号比较单元 U106、 以及优化控制单元 U107。 该电路优化装置的每一个单元 可以实现为硬件、 软件和固件之一或它们的组合。
电路仿真单元 U101对源电路和目标电路中的每一个进行直流分析、 交流分析、 瞬态分析和电路的其他数值分析。
电路仿真结果分析单元 U102与电路仿真单元 U101相连接。电路仿真结果分析单 元 U102利用源电路和目标电路的仿真结果计算节点和支路对应的直流分析信号值 /分 布及函数、 交流分析信号值 /分布及函数、 瞬态分析信号值 /分布及函数。
在该实例中,对源电路和目标电路的仿真和仿真结果分析使用相同的电路仿真单 元 U101和电路仿真结果分析单元 U102。 然而, 目标电路仿真的对象和范围与源电路 仿真不同。对源电路仿真结果进行分析的对象或范围是源电路的全部节点的电压、支 路电流、以及基于前者的函数计算。在本发明中以直流通路作为电路优化的基本要素, 因此目标电路仿真的对象是目标电路的一个直流通路,并且按照确定的电路调整顺序 逐个直流通路进行电路优化。例如, 第一次目标电路仿真的直流通路是第一电路模块 的第一直流通路,第二次电路仿真的对象是第一电路模块的第二直流通路,依此类推。 而且, 目标电路仿真的范围是目标电路的当前直流通路与之前的所有直流通路之间的 节点电压、 支路电流、 以及基于前者的函数计算。
电路连接关系分析单元 U103与电路仿真结果分析单元 U102相连接。电路连接关 系分析单元 U103分析源电路的电路连接关系, 其中从电源端开始, 按照电流在器件 内的流动方向遍历器件, 直到电路的任一接地端, 以确定至少一个直流通路。
电路调整顺序确定单元 U104与电路连接关系分析单元 U103相连接。电路调整顺 序确定单元 U104分析源电路的直流通路的信号到达顺序, 其中从输入端开始按信号 传播方向遍历直流通路, 直到输出端, 以获得每个直流通路的信号到达顺序, 然后根 据信号到达顺序确定电路模块和直流通路的顺序。
目标电路器件参数值设置单元 U105与电路仿真单元 U101和优化控制单元 U107 相连接。 目标电路器件参数值设置单元 U105向电路仿真单元 U101提供目标电路器件 的初始参数值, 以及在器件参数优化过程中, 根据优化控制单元 U107的控制信号, 向电路仿真单元 U101提供目标电路器件的中间参数值。
信号比较单元 U106与电路仿真结果分析单元 U102相连接。 信号比较单元 U106 对目标电路的当前直流通路和源电路的相应直流通路之间的相应节点、支路和函数计 算结果等信息进行比较。 优化控制单元 U107与信号比较单元 U106和目标电路器件参数值设置单元 U105 相连接。优化控制单元 U107根据信号比较单元 U106的比较结果, 向目标电路器件参 数值设置单元 U105提供控制信号,或者使得目标电路器件参数值设置单元 U105在优 化过程中设置目标电路的当前直流通路的器件中间参数值以进行新的电路优化尝试, 或者使得目标电路器件参数值设置单元 U105在优化过程中设置目标电路的下一个直 流通路的器件初始参数值, 按照确定的电路调整顺序逐个直流通路进行电路优化。在 模拟退火温度和 /或遗传代导致无效的优化尝试次数超过极限值时, 优化控制单元 U107改变模拟退火温度下和 /或遗传代, 进行新的电路优化尝试。 在完成目标电路中 的全部直流通路的电路优化(即目标电路性能满足整体设计要求) 时, 优化控制单元 U107结束电路优化过程。
上述用于模拟电路移植的电路优化方法和电路优化装置以直流通路作为电路优 化的基本要素, 降低了优化计算的复杂度, 显著减少优化过程的无效尝试次数。
在现有技术中, 目标电路的调整对象和范围与源电路相同, 即包括目标电路的全 部节点的电压、 支路电流、 以及基于前者的函数计算。
例如, 假定源电路包括 50个器件, 每个器件的选择空间 (exploration space ) 有 8种情形。 整个电路的选择空间是 8, 优化过程中每次迭代的命中概率是 1/85°。 针对所有器件同时进行目标电路的器件参数调整, 目标电路的实际优化尝试时间 Ta„ 可以表示为
L = T, X 85° (4)
其中, Τ,表示每次优化尝试的时间。
在本发明的电路优化方法中,采用了直流通路分析和信号流分析确定每个直流通 路的器件组成以及优化过程中直流通路之间的先后顺序,按照确定的电路调整顺序逐 个直流通路进行电路优化。
仍然假定源电路包括 50个器件, 每个器件的选择空间有 8种情形。 进一步地, 假定源电路可以划分成 10个直流通路, 每个直流通路上有 5个器件。 每一个直流通 路的选择空间是 85, 优化过程中每次迭代的命中概率是 1/85
目标电路的实际优化尝试时间 Tall可以表示为
Tall - TparL, i
= 10 X T, X 85 (5)
其中, Τ , ι表示第 i个直流通路的实际优化时间(i=l, …, 10 ), 表示每次优 化尝试的时间。
对比上述公式 (4) 和 (5 ), 可以看到本发明的电路优化方法比现有技术的电路 优化方法的电路优化速度快得多。 随着电路规模的加大, 电路优化速度的效果更加明 显。
以上所述仅为本发明的较佳实施例而已, 并不用以限制本发明, 凡在本发明的精 神和原则之内所作的任何修改、等同替换和改进等, 均应包含在本发明的保护范围之 内。

Claims

1、 一种用于模拟电路移植的电路优化方法, 所述模拟电路移植用于将源电路重 用于目标电路, 所述电路优化方法包括:
将源电路划分成至少一个直流通路;
确定所述至少一个直流通路的顺序; 以及
按照所述顺序逐个优化目标电路的直流通路。
2、 根据权利要求 1所述的电权路优化方法, 其中将源电路划分成至少一个直流通 路的步骤包括:
针对源电路, 从电源端开始, 按照电流在器件内的流动方向遍历器件, 直到接地 端,其中将连接在同一个电源端和同一个接地端之间的能够独立提供完整直流电流路 径的器件作为一个直流通路, 以获得所述至少一个求直流通路。
3、 根据权利要求 1所述的电路优化方法, 其中确定所述至少一个直流通路的顺 序的步骤包括:
针对源电路, 从输入端开始, 按信号传播方向遍历所述至少一个直流通路, 直到 输出端, 以获得所述至少一个直流通路中的直流通路的信号到达顺序; 以及
根据信号到达顺序确定所述至少一个直流通路的顺序。
4、 根据权利要求 1所述的电路优化方法, 其中按照所述顺序逐个优化目标电路 的直流通路的步骤包括:
设置目标电路的每一个直流通路的器件参数值,使得目标电路的每一个直流通路 和源电路的相应的一个直流通路的节点信号满足设计要求。
5、 根据权利要求 4所述的电路优化方法, 其中按照所述顺序逐个优化目标电路 的直流通路的步骤包括:
a) 按照所述顺序, 选择目标电路的一个直流通路;
b) 设置目标电路的所述一个直流通路中的器件参数值;
c) 对目标电路的所述一个直流通路与在所述顺序中位于所述一个直流通路之前 的所有直流通路进行目标电路仿真;
d) 分析目标电路仿真结果, 以获得目标电路的所述一个直流通路的节点信号; e ) 比较目标电路的所述一个直流通路和源电路的相应的一个直流通路的节点信 号; 以及 f ) 根据优化控制条件, 重复步骤 a) ~e), 使得目标电路的所有直流通路满足设 计要求。
6、 根据权利要求 5所述的电路优化方法, 其中所述根据优化控制条件, 重复步 骤 a) ~e ) 的步骤包括:
如果目标电路的所述一个直流通路未满足设计要求, 则重复步骤 a)〜e), 其中选 择新的器件参数值, 以重新优化目标电路的所述一个直流通路;
如果目标电路的所述一个直流通路己满足设计要求, 则重复步骤 a) ~e), 其中选 择目标电路的下一个直流通路进行优化; 以及
如果目标电路的所有直流通路满足设计要求, 则结束电路优化过程。
7、 根据权利要求 6所述的电路优化方法, 其中所述根据优化控制条件, 重复步 骤 a) 〜e ) 的步骤还包括:
如果模拟退火温度和 /或遗传代导致无效的优化尝试次数超过极限值, 则重复步 骤 a) ), 其中改变模拟退火温度下和 /或遗传代, 以进行新的电路优化尝试。
8、 根据权利要求 5所述的电路优化方法, 其中设置目标电路的所述一个直流通 路中的器件参数值的步骤包括:
在目标电路的所述一个直流通路中, 在器件参数优化开始时, 设置目标电路的所 述一个直流通路中的器件的初始参数值; 以及
在目标电路的所述一个直流通路中, 在器件参数优化过程中, 设置目标电路的所 述一个直流通路中的器件的中间参数值。
9、 根据权利要求 8所述的电路优化方法, 其中设置目标电路的所述一个直流通 路中的器件的初始参数值的步骤包括- 采用随机方法确定目标电路器件的初始参数值; 或
根据源电路器件之间比例关系以及新旧工艺特征尺寸之间的比例关系确定目标 电路器件的初始参数值。
10、 根据权利要求 8所述的电路优化方法, 其中设置目标电路的所述一个直流通 路中的器件的中间参数值的步骤包括:
采用随机方法确定目标电路器件的中间参数值; 或
根据目标电路的所述一个直流通路的性能评估值与源电路的对应的直流通路的 性能值之间的差异幅度以及器件参数值对电路性能影响方向 /趋势 /幅度确定对应器 件参数值的调整方向和调整幅度。
11、 根据权利要求 10所述的电路优化方法, 其中设置目标电路的所述一个直流 通路中的器件的中间参数值的步骤包括:
对于多个电路性能指标以线性规划的方式确定最优的器件参数值。
12、 根据权利要求 1所述的电路优化方法, 其中将源电路划分成至少一个直流通 路的步骤包括:
将源电路划分成至少一个电路模块; 以及
将所述至少一个电路模块中的每一个划分成至少一个直流通路。
13、 一种用于模拟电路移植的电路优化装置, 所述模拟电路移植用于将源电路重 用于目标电路, 所述电路优化装置包括- 电路仿真单元, 用于进行源电路仿真和目标电路仿真;
电路仿真结果分析单元, 与电路仿真单元相连接, 用于根据源电路仿真和目标电 路仿真的结果计算源电路和目标电路的节点信号;
电路连接关系分析单元, 与电路仿真结果分析单元相连接, 用于分析源电路的电 路连接关系, 以确定源电路的直流通路;
电路调整顺序确定单元, 与电路连接关系分析单元相连接, 用于分析源电路的直 流通路的信号到达顺序, 根据信号到达顺序确定源电路的直流通路的顺序;
目标电路器件参数值设置单元, 与电路仿真单元和优化控制单元相连接, 用于设 置目标电路的一个直流通路的器件参数值;
信号比较单元, 与电路仿真结果分析单元相连接, 用于比较目标电路的所述一个 直流通路和源电路的相应的一个直流通路的节点信号; 以及
优化控制单元, 与信号比较单元和目标电路器件参数值设置单元相连接, 用于根 据信号比较单元的比较结果, 向目标电路器件参数值设置单元提供控制信号, 从而按 照所述顺序逐个优化目标电路的直流通路。
14、 根据权利要求 13所述的电路优化装置, 其中优化控制单元配置成- 如果目标电路的所述一个直流通路未满足设计要求, 则选择新的器件参数值, 以 重新优化目标电路的所述一个直流通路;
如果目标电路的所述一个直流通路巳满足设计要求,则选择目标电路的下一个直 流通路进行优化; 以及
如果目标电路的所有直流通路满足设计要求时, 则结束电路优化过程。
15、 根据权利要求 14所述的电路优化装置, 其中优化控制单元还配置成: 如果模拟退火温度和 /或遗传代导致无效的优化尝试次数超过极限值, 则改变模 拟退火温度下和 /或遗传代, 以进行新的电路优化尝试。
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Publication number Priority date Publication date Assignee Title
US9030173B2 (en) 2006-07-18 2015-05-12 Global Energy Innovations, Inc. Identifying and amerliorating a deteriorating condition for battery networks in-situ
US8710847B2 (en) 2010-10-28 2014-04-29 Donald Marvin Self-correcting amplifier system
US8738310B2 (en) 2010-12-08 2014-05-27 Paul Swanton Automatic determination of baselines for battery testing
CN103530484B (zh) * 2013-11-04 2016-05-04 中国科学院微电子研究所 一种集成电路的器件参数优化方法
CN116029251B (zh) * 2023-03-23 2023-07-07 青岛青软晶尊微电子科技有限公司 基于电路性能均衡化的电路布线优化方法及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1510733A (zh) * 2002-12-24 2004-07-07 北京艾克赛利微电子技术有限公司 面向工艺移植的晶体管级集成电路优化方法
CN102024067A (zh) * 2009-09-09 2011-04-20 中国科学院微电子研究所 一种模拟电路工艺移植的方法
CN102508977A (zh) * 2011-11-15 2012-06-20 中国科学院微电子研究所 用于模拟电路移植的电路优化方法和装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267324A (ja) 2000-03-22 2001-09-28 Hitachi Ltd 配線修正方法
US7336104B2 (en) 2004-06-28 2008-02-26 Technion Research & Development Foundation Ltd. Multiple-output transistor logic circuit
US7409651B2 (en) * 2005-08-05 2008-08-05 International Business Machines Corporation Automated migration of analog and mixed-signal VLSI design
WO2007038984A1 (en) * 2005-09-29 2007-04-12 Mentor Graphics Corp. Analog design retargeting
US8516410B2 (en) * 2008-12-30 2013-08-20 International Business Machines Corporation Method of migrating electronic devices operating in current mode to a target technology

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1510733A (zh) * 2002-12-24 2004-07-07 北京艾克赛利微电子技术有限公司 面向工艺移植的晶体管级集成电路优化方法
CN102024067A (zh) * 2009-09-09 2011-04-20 中国科学院微电子研究所 一种模拟电路工艺移植的方法
CN102508977A (zh) * 2011-11-15 2012-06-20 中国科学院微电子研究所 用于模拟电路移植的电路优化方法和装置

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