WO2013063991A1 - Amoled驱动补偿电路、方法及其显示装置 - Google Patents

Amoled驱动补偿电路、方法及其显示装置 Download PDF

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Publication number
WO2013063991A1
WO2013063991A1 PCT/CN2012/082032 CN2012082032W WO2013063991A1 WO 2013063991 A1 WO2013063991 A1 WO 2013063991A1 CN 2012082032 W CN2012082032 W CN 2012082032W WO 2013063991 A1 WO2013063991 A1 WO 2013063991A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
driving
clock signal
circuit
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Application number
PCT/CN2012/082032
Other languages
English (en)
French (fr)
Inventor
祁小敬
李天马
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/805,505 priority Critical patent/US8970644B2/en
Priority to KR1020127032551A priority patent/KR20130060232A/ko
Priority to EP12790776.4A priority patent/EP2775474B1/en
Priority to JP2014537467A priority patent/JP6037477B2/ja
Publication of WO2013063991A1 publication Critical patent/WO2013063991A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes

Definitions

  • AMOLED driving compensation circuit, method and display device thereof AMOLED driving compensation circuit, method and display device thereof
  • the present invention relates to the field of AMOLED, and in particular, to an AMOLED driving compensation circuit, a method, and a display device thereof. Background technique
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the threshold voltage may vary, which may result in inconsistent drive currents when inputting the same gray scale voltage, thereby making the brightness of the driven AMOLED different.
  • the main method to solve this problem is to add a compensation circuit to eliminate the influence of the threshold voltage, thereby achieving a uniform driving current and improving the brightness uniformity of the panel.
  • the existing AMOLED compensation circuit often requires 5 to 6 thin film transistors to be disposed in the same pixel region, so that the aperture ratio is lowered.
  • Embodiments of the present invention provide an AMOLED driving compensation circuit, method, and display device thereof, which are capable of increasing an aperture ratio.
  • an AMOLED driving compensation circuit including: a plurality of driving circuits disposed in a plurality of pixel regions for driving a plurality of AMOLEDs, wherein an AMOLED and a corresponding one are disposed in each pixel region Drive circuit, and a drive circuit for driving a corresponding AMOLED;
  • An external compensation circuit disposed outside the pixel region is provided for eliminating the influence of the threshold voltage of the driving thin film transistor on the driving current through the driving thin film transistor in the plurality of driving circuits disposed in the plurality of pixel regions.
  • each of the plurality of driving circuits disposed in the plurality of pixel regions includes: a first thin film transistor, a driving capacitor, and a driving thin film transistor;
  • the first thin film transistor has a source connected to the data line; a driving capacitor having a first end connected to a drain of the first thin film transistor; a driving thin film transistor having a gate connected to a drain of the first thin film transistor; wherein, the AMOLED corresponding to the driving circuit The input end is connected to the working voltage output end, and the output end of the AMOLED corresponding to the driving circuit is connected to the drain of the driving thin film transistor; the first thin film transistor and the driving thin film transistor are n-channel thin film transistors;
  • the external compensation circuit disposed outside the pixel region includes: a second thin film transistor, a third thin film transistor, a compensation capacitor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, and a seventh thin film Transistor
  • the second thin film transistor has a source grounded, a gate connected to the second clock signal output end, and a drain connected to the second end of the driving capacitor;
  • the third thin film transistor has a source connected to a drain of the second thin film transistor and a gate connected to the second clock signal output end;
  • the compensation capacitor has a first end connected to a drain of the third thin film transistor
  • the fourth thin film transistor has a source connected to the second end of the compensation capacitor, a gate connected to the second clock signal output end, and a drain connected to the source of the driving thin film transistor;
  • the fifth thin film transistor has a source grounded, a gate connected to the first clock signal output end, and a drain connected to a source of the fourth thin film transistor;
  • the sixth thin film transistor has a source connected to the reference voltage output terminal, a gate connected to the first clock signal output end, and a drain connected to the drain of the second thin film transistor;
  • a seventh thin film transistor having a source connected to the reference voltage output terminal, a gate connected to the first clock signal output terminal, and a drain connected to the gate of the driving thin film transistor;
  • a gate of the first thin film transistor is connected to the second clock signal output end
  • the second thin film transistor, the sixth thin film transistor, and the seventh thin film transistor are n-channel thin film transistors
  • the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor are p-channel thin film transistors.
  • the first clock signal at the first clock signal output end and the second clock signal at the second clock signal output end both include a first phase, a second phase, and a third phase; In one stage, the first clock signal output end is at a high level, and the second clock signal output end is at a low level;
  • the first clock signal output terminal is at a low level, and the second clock signal is input.
  • the output is high;
  • the first clock signal output terminal is at a low level
  • the second clock signal output terminal is at a low level
  • the third thin film transistor, the fourth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor in the external compensation circuit are turned on, and the first thin film transistor in each driving circuit and The second thin film transistor and the fifth thin film transistor in the external compensation circuit are turned off, such that the voltage difference on the compensation capacitor is a threshold voltage of the driving thin film transistor; in the second stage, the third in the external compensation circuit The thin film transistor, the fourth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor are turned off, and the first thin film transistor in each of the driving circuits and the second thin film transistor and the fifth thin film transistor in the external compensation circuit are turned on,
  • the voltage difference across the drive capacitor in each drive circuit is the gray scale voltage input to the data line corresponding to the drive circuit;
  • the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor in the external compensation circuit are turned on, the first thin film transistor in each driving circuit, and the second thin film in the external compensation circuit
  • the transistor, the sixth thin film transistor, and the seventh thin film transistor are turned off, such that a gate voltage of the driving thin film transistor in the driving circuit jumps to a threshold voltage of the driving thin film transistor and a gray scale input of a data line corresponding to the driving circuit The sum of the voltages.
  • an AMOLED driving compensation method including: a first stage, storing a threshold voltage of a driving thin film transistor of a plurality of driving circuits disposed in a plurality of pixel regions;
  • the gate voltage of the driving thin film transistor of each of the plurality of driving circuits disposed in the plurality of pixel regions jumps to a sum of the threshold voltage and a gray scale voltage of the driving circuit .
  • the threshold voltage of the driving thin film transistor storing the plurality of driving circuits disposed in the plurality of pixel regions is:
  • the first clock signal output terminal is at a high level
  • the second clock signal output terminal is at a low level
  • the third thin film transistor, the fourth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor in the compensation circuit are turned on, each The first thin film transistor in the driving circuit and the second thin film transistor and the fifth thin film transistor in the compensation circuit are turned off, and the voltage difference on the compensation capacitor is set in the plurality of pixel regions a threshold voltage of a driving thin film transistor of a plurality of driving circuits in the domain;
  • the gray scale voltage of each of the plurality of driving circuits disposed in the plurality of pixel regions is stored as:
  • the first clock signal output terminal is at a low level
  • the second clock signal output terminal is at a high level
  • the third thin film transistor, the fourth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor in the compensation circuit are turned off, each driving The first thin film transistor in the circuit and the second thin film transistor and the fifth thin film transistor in the compensation circuit are turned on, and a voltage difference on a driving capacitor in each driving circuit is a gray scale voltage input to a data line corresponding to the driving circuit ;
  • the gate voltage of the driving thin film transistor in each of the plurality of driving circuits disposed in the plurality of pixel regions jumps to the threshold voltage and the gray scale of the driving circuit
  • the sum of the voltages is:
  • the first clock signal output terminal is at a low level
  • the second clock signal output terminal is at a low level
  • the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor in the compensation circuit are turned on, and the first in each driving circuit a thin film transistor and a second thin film transistor, a sixth thin film transistor, and a seventh thin film transistor in the compensation circuit are turned off, the driving thin film transistor in each of the plurality of driving circuits disposed in the plurality of pixel regions
  • the gate voltage jumps to the sum of the threshold voltage and the gray scale voltage of the drive circuit.
  • a display device comprising the AMOLED drive compensation circuit described above.
  • the AMOLED driving compensation circuit and the method thereof are provided.
  • the external compensation circuit is disposed outside the pixel region, and can simultaneously compensate the threshold voltage of the driving thin film transistors of the plurality of driving circuits in the pixel region, and is only used in the pixel region.
  • the driving circuit of the AMOLED is driven to increase the aperture ratio.
  • FIG. 1 is a circuit diagram of an AMOLED driving compensation circuit according to an embodiment of the present invention
  • FIG. 2 is a timing diagram of a clock signal of the circuit of FIG.
  • Figure 3 is an equivalent circuit diagram of the circuit of Figure 1 in the first stage
  • Figure 4 is an equivalent circuit diagram of the circuit of Figure 1 in the second stage
  • Figure 5 is an equivalent circuit diagram of the circuit of Figure 1 in the third stage
  • FIG. 6 is a circuit diagram of another AMOLED driving compensation circuit according to an embodiment of the present invention
  • FIG. 7 is a flowchart of an AMOLED driving compensation method according to an embodiment of the present invention. detailed description
  • An embodiment of the present invention provides an AMOLED driving compensation circuit, including:
  • a plurality of driving circuits disposed in the plurality of pixel regions for driving a plurality of AMOLEDs, wherein an AMOLED and a corresponding driving circuit are disposed in one pixel region, and a driving circuit is used to drive a corresponding AMOLED;
  • Each of the driving circuits such as a conventional 2T1C (two thin film transistor and one capacitor) circuit, includes a first thin film transistor, a driving thin film transistor, and a driving capacitor, and drives the AMOLED to emit light by driving a driving current of the thin film transistor.
  • a conventional 2T1C (two thin film transistor and one capacitor) circuit includes a first thin film transistor, a driving thin film transistor, and a driving capacitor, and drives the AMOLED to emit light by driving a driving current of the thin film transistor.
  • An external compensation circuit disposed outside the pixel region for eliminating the influence of the threshold voltage of the driving thin film transistor in the plurality of driving circuits disposed in the pixel region on the driving current through the driving thin film transistor, so that the driving thin film transistor is driven
  • the drive current is independent of the threshold voltage of the driving thin film transistor, thereby improving the uniformity of the driving current.
  • the AMOLED driving compensation circuit in addition to the driving circuit, a compensating circuit composed of 5 to 6 thin film transistors is required in each pixel region, and the AMOLED driving compensation circuit provided by the embodiment of the present invention has an external compensation circuit disposed outside the pixel region.
  • the threshold voltage of the driving thin film transistor of the plurality of driving circuits in the pixel region can be simultaneously compensated, and only the driving circuit for driving the AMOLED is provided in the pixel region, so that the aperture ratio can be increased.
  • one row of pixel regions includes N pixel regions Pixel-1,
  • Pixel— 2 Pixel—N where N is a natural number greater than 1, with an AMOLED and a corresponding driver circuit set in each pixel region.
  • the driving circuit includes: a first thin film transistor T1, a driving capacitor Cst, and a driving thin film transistor T8; wherein the first thin film transistor T1 has a source connected to the data line;
  • the first capacitor is connected to the drain of the first thin film transistor T1, and the gate of the thin film transistor T8 is connected to the drain of the first thin film transistor T1.
  • the anode of the AMOLED is connected to the working voltage output terminal, specifically the voltage source VDD, and the cathode of the AMOLED is connected to the drain of the driving thin film transistor T8 of the driving circuit disposed in the pixel region.
  • the first thin film transistor and the driving thin film transistor are n-channel thin film transistors.
  • the sources of the N first thin film transistors T1 in the N pixel regions are respectively connected to N data lines Data1, Data2 DataN.
  • the external compensation circuit disposed outside the pixel region includes: a second thin film transistor T2, a third thin film transistor T3, a compensation capacitor Cth, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor. ⁇ 7; wherein the second thin film transistor ⁇ 2 has a source grounded, a gate connected to the second clock signal output terminal C1, a drain connected to the second end of the driving capacitor Cst, and a third thin film transistor T3 whose source is connected to the second The drain of the thin film transistor T2 has a gate connected to the second clock signal output terminal C1; the compensation capacitor Cth has a first end connected to the drain of the third thin film transistor T3; and a fourth thin film transistor T4 whose source is connected to the compensation capacitor Cth The second terminal has a gate connected to the second clock signal output terminal C1, a drain connected to the source of the driving thin film transistor T8, and a fifth thin film transistor T5 whose source is grounded and whose gate is connected to the
  • the drain thereof is connected to the source of the fourth thin film transistor T4;
  • the sixth thin film transistor T6 has a source connected to the reference voltage output terminal VREF, and the gate thereof The pole is connected to the first clock signal output terminal G1, and the drain thereof is connected to the drain of the second thin film transistor T2;
  • the seventh thin film transistor T7 has a source connected to the reference voltage output terminal VREF and a gate connected to the first clock signal output terminal G1 The drain is connected to the gate of the driving thin film transistor T8; the gate of the first thin film transistor T1 is connected to the second clock signal output terminal C1.
  • the second thin film transistor T2, the sixth thin film transistor ⁇ 6, and the seventh thin film transistor ⁇ 7 are! !
  • the channel thin film transistor; the third thin film transistor ⁇ 3, the fourth thin film transistor ⁇ 4, and the fifth thin film transistor ⁇ 5 are p-channel thin film transistors.
  • the first clock signal gl at the first clock signal output terminal G1 and the second clock signal cl at the second clock signal output terminal C1 each include a first phase HI, a second phase H2 and The third stage H3; in the first stage HI, the first clock signal output terminal G1 is at a high level, the second clock signal output terminal C1 is at a low level; in the second phase H2, the first clock signal output terminal G1 is at a low level Level, the second clock signal output terminal C1 is at a high level; in the third phase H3, the first clock signal output terminal G1 is at a low level, and the second clock signal output terminal C1 is at a low level.
  • the first terminal of the compensation capacitor Cth connected to the third thin film transistor T3 is the first node A: the compensation capacitor Cth
  • the second end connected to the fourth thin film transistor is a second node B; the first end of the driving capacitor Cst connected to the first thin film transistor T1 is a third node C, and the second end of the driving capacitor Cst is connected to the second thin film transistor T2 Is the fourth node 0.
  • the first stage HI is a pre-charging stage. At this time, the first clock signal output terminal G1 is at a high level, the second clock signal output terminal C1 is at a low level, and the third thin film transistor T3 and the fourth thin film transistor in the compensation circuit are ⁇ 4, the sixth thin film transistor ⁇ 6 and the seventh thin film transistor ⁇ 7 are turned on, and the first thin film transistor T1 in each driving circuit and the second thin film transistor ⁇ 2 and the fifth thin film transistor ⁇ 5 in the compensation circuit are turned off, and the circuit is equivalent at this time. For the circuit shown in FIG.
  • the reference voltage output terminal VREF charges the compensation capacitor Cth such that the voltage of the first node A is the reference voltage Vref on the reference voltage output terminal VREF, and the voltage of the second node B is the reference voltage Vref and
  • the difference between the threshold voltage Vth of the driving thin film transistor T8 is Vref-Vth, that is, the voltage difference across the compensation capacitor Cth is the threshold voltage Vth of the driving thin film transistor T8.
  • the driving film in the pixel region of the above-mentioned row Transistor T8 needs to be fabricated in the same process to ensure that the threshold voltage of each of the driving thin film transistors T8 in the row is the same. Vth.
  • the second stage H2 is a gray scale voltage input stage.
  • the first clock signal output terminal G1 is at a low level
  • the second clock signal output terminal C1 is at a high level
  • the third thin film transistor T3 and the fourth in the compensation circuit are The thin film transistor ⁇ 4 , the sixth thin film transistor ⁇ 6, and the seventh thin film transistor ⁇ 7 are turned off, and the first thin film transistor T1 in each driving circuit and the second thin film transistor ⁇ 2 and the fifth thin film transistor ⁇ 5 in the compensation circuit are turned on, at this time, the circuit Equivalent to the circuit shown in FIG.
  • the following description is based on the operation principle of the driving circuit in one pixel region Pixel-1, and the data line Data1 charges the driving capacitor Cst so that the voltage of the third node C is the data line.
  • the gray scale voltage Vdata1 input by Datal and the voltage of the fourth node D are zero, that is, the voltage difference on the driving capacitor Cst is the gray scale voltage Vdata1 input by the data line Data1.
  • the third phase H3 is an illumination phase.
  • the first clock signal output terminal G1 is at a low level
  • the second clock signal output terminal C1 is at a low level
  • the third thin film transistor T3 and the fourth thin film transistor ⁇ 4 in the compensation circuit are
  • the fifth thin film transistor ⁇ 5 is turned on
  • the first thin film transistor T1 in each driving circuit and the second thin film transistor ⁇ 2 the sixth thin film transistor ⁇ 6, and the seventh thin film transistor ⁇ 7 in the compensation circuit are turned off, and the circuit is equivalent to As shown in the circuit of FIG. 5, the second node is grounded and the voltage is zero.
  • the voltage difference stored in the compensation capacitor Cth is the threshold voltage Vth of the driving thin film transistor T8 in the first stage HI
  • the voltage of the first node A, that is, the fourth node D is the threshold voltage Vth of the driving thin film transistor T8, due to the pixel in the second stage H2
  • the voltage difference on the driving capacitor Cst is the gray-scale voltage Vdata1 input by the data line Data1.
  • the driving current I and the threshold voltage of the thin film transistor T8 are driven.
  • the above reference voltage output terminal can also be the power supply terminal VDD.
  • the first stage HI and the second stage H2 are shorter in time, and the third stage H3 is longer for the panel to emit light.
  • the expression of the driving current in the prior art usually includes the power supply voltage Vdd of the power supply terminal VDD. Due to the problem of the voltage drop (IR Drop), the variation of the power supply voltage Vdd further affects the actual effect of the panel, and is driven in the embodiment of the present invention.
  • the expression of the current does not include the supply voltage Vdd of the power supply terminal VDD, thereby further improving the IR Dro problem.
  • the working principle of the driving circuit in each pixel region of a row is the same as that of the driving circuit in the pixel region Pixel-1 described above, and will not be described herein.
  • the voltage difference on the driving capacitor Cst is the gray scale voltage Vdatai input from the data line Datai.
  • the voltage of the third node C jumps to the threshold voltage Vth of the driving thin film transistor T8 and the data line Datai.
  • an external compensation circuit corresponding to the multi-line pixel region may be separately configured to constitute an AMOLED driving compensation circuit, which includes: m a clock signal output terminal Gl, G2 Gm; m number The two clock signal output terminals C1, C2, and Cm, where m is a natural number greater than one, and the connection relationship and working principle of the AMOLED driving compensation circuit are the same as those in the foregoing embodiment, and details are not described herein again.
  • the AMOLED driving compensation circuit provided by the embodiment of the invention enables the external compensation circuit disposed outside the pixel region to simultaneously compensate the threshold voltage of the driving thin film transistors of the plurality of driving circuits in one pixel region, and only the pixel region is used for driving the AMOLED.
  • the drive circuit is such that the aperture ratio can be increased.
  • the embodiment of the present invention further provides an AMOLED driving compensation method.
  • the method is applied to the AMOLED driving compensation circuit provided in the foregoing embodiment. As shown in FIG. 7, the method includes:
  • Step 101 In a first stage, storing a threshold voltage of a driving thin film transistor of a plurality of driving circuits disposed in a plurality of pixel regions;
  • Step 102 In a second stage, storing a grayscale voltage of each of the plurality of driving circuits disposed in the plurality of pixel regions;
  • Step 103 in the third stage, setting a gate voltage of the driving thin film transistor in each of the plurality of driving circuits in the plurality of pixel regions to a threshold voltage and a grayscale voltage of the driving circuit with.
  • the threshold voltage of the driving thin film transistors of the plurality of driving circuits in the pixel region is simultaneously compensated by the external compensation circuit disposed outside the pixel region, only the driving region in the pixel region is used for driving.
  • the drive circuit of AMOLED can increase the aperture ratio.
  • the threshold voltage of the driving thin film transistor storing a plurality of driving circuits disposed in a plurality of pixel regions is specifically:
  • the first clock signal output terminal is at a high level
  • the second clock signal output terminal is at a low level
  • the third thin film transistor, the fourth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor in the compensation circuit are turned on, each The first thin film transistor in the driving circuit and the second thin film transistor and the fifth thin film transistor in the compensation circuit are turned off, and the voltage difference on the compensation capacitor is a threshold voltage of the driving thin film transistor of the plurality of driving circuits disposed in the pixel region;
  • the first clock signal output terminal is at a low level
  • the second clock signal output terminal is at a high level
  • the third thin film transistor, the fourth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor in the compensation circuit are turned off, each driving a first thin film transistor in the circuit and a second thin film crystal in the compensation circuit
  • the body tube and the fifth thin film transistor are turned on, and a voltage difference on a driving capacitor in each driving circuit is a gray scale voltage input to a data line corresponding to the driving circuit;
  • the gate voltage of the driving thin film transistor in each of the plurality of driving circuits disposed in the plurality of pixel regions is converted to a sum of a threshold voltage and a grayscale voltage of the driving circuit, specifically:
  • the first clock signal output terminal is at a low level
  • the second clock signal output terminal is at a low level
  • the third thin film transistor, the fourth thin film transistor, and the fifth thin film transistor in the compensation circuit are turned on, and the first in each driving circuit a thin film transistor and a second thin film transistor, a sixth thin film transistor, and a seventh thin film transistor in the compensation circuit are turned off, the driving thin film transistor in each of the plurality of driving circuits disposed in the plurality of pixel regions
  • the gate voltage jumps to the sum of the threshold voltage and the gray scale voltage of the drive circuit.
  • the external compensation circuit disposed outside the pixel region simultaneously compensates for the threshold voltage of the driving thin film transistors of the plurality of driving circuits in the pixel region, and only the driving circuit for driving the AMOLED is provided in the pixel region, thereby increasing the aperture ratio.
  • the embodiment of the present invention further provides a display device including the above-mentioned AMOLED driving compensation electric external circuit provided outside the pixel region and simultaneously compensating for the threshold voltage of the driving thin film transistor of the plurality of driving circuits in the pixel region, in the pixel region Only the driving circuit for driving the AMOLED can increase the aperture ratio.

Abstract

一种AMOLED驱动补偿电路、方法及其显示装置，涉及AMOLED领域，能够增加开口率。该驱动补偿电路包括：设置在像素区域内的数个驱动电路，用于驱动数个AMOLED；设置在像素区域之外的外部补偿电路，用于消除设置在像素区域内的数个驱动电路中驱动薄膜晶体管的阈值电压对通过驱动薄膜晶体管的驱动电流的影响。该驱动补偿方法包括：第一阶段，存储设置在像素区域内的数个驱动电路的驱动薄膜晶体管的阈值电压；第二阶段，存储设置在像素区域内的数个驱动电路的灰阶电压；第三阶段，设置在像素区域内的数个驱动电路的驱动薄膜晶体管的栅极电压跳变为阈值电压与灰阶电压的和。该显示装置包括上述AMOLED驱动补偿电路。

Description

AMOLED驱动补偿电路、 方法及其显示装置 技术领域
本发明涉及 AMOLED领域，尤其涉及一种 AMOLED驱动补偿电路、方 法及其显示装置。 背景技术
有源矩阵有机发光二极体面板 ( Active Matrix Organic Light Emitting Diode, AMOLED ) 能够发光是由驱动电路中的驱动薄膜晶体管产生的驱动 电流所驱动的， 但是， 随着时间的变化， 驱动薄膜晶体管的阔值电压可能会 变化， 因而会造成输入相同的灰阶电压时， 产生的驱动电流不一致， 从而使 所驱动的 AMOLED 的亮度不同。 目前， 解决这一问题的主要方法是加入补 偿电路， 消除阔值电压的影响， 从而达到一致的驱动电流， 改善面板的亮度 均匀性。
在实现本发明的过程中， 发明人发现现有技术中至少存在如下问题： 现有的 AMOLED补偿电路往往需要 5到 6个薄膜晶体管设置在同一个 像素区域内， 所以会降低开口率。 发明内容
本发明的实施例提供一种 AMOLED驱动补偿电路、方法及其显示装置， 能够增加开口率。
根据本发明实施例， 提供了一种 AMOLED驱动补偿电路， 包括： 设置在数个像素区域内的数个驱动电路，用于驱动数个 AMOLED,其中 在每个像素区域内设置一个 AMOLED和一个对应的驱动电路， 并且一个驱 动电路用于驱动一个对应的 AMOLED;
设置在像素区域之外的外部补偿电路， 用于消除所述设置在数个像素区 域内的数个驱动电路中驱动薄膜晶体管的阔值电压对通过所述驱动薄膜晶体 管的驱动电流的影响。
在一个示例中， 所述设置在数个像素区域内的数个驱动电路中的每个驱 动电路包括： 第一薄膜晶体管、 驱动电容、 以及驱动薄膜晶体管；
所述第一薄膜晶体管， 其源极连接数据线； 所述驱动电容， 其第一端连接所述第一薄膜晶体管的漏极； 所述驱动薄膜晶体管， 其栅极连接所述第一薄膜晶体管的漏极； 其中， 与该驱动电路对应的 AMOLED的输入端连接工作电压输出端 , 与该驱动电路对应的 AMOLED的输出端连接所述驱动薄膜晶体管的漏极； 所述第一薄膜晶体管和驱动薄膜晶体管为 n沟道薄膜晶体管；
在一个示例中， 所述设置在像素区域之外的外部补偿电路包括： 第二薄 膜晶体管、 第三薄膜晶体管、 补偿电容、 第四薄膜晶体管、 第五薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管；
所述第二薄膜晶体管， 其源极接地， 其栅极连接第二时钟信号输出端， 其漏极连接所述驱动电容的第二端；
所述第三薄膜晶体管， 其源极连接所述第二薄膜晶体管的漏极， 其栅极 连接所述第二时钟信号输出端；
所述补偿电容， 其第一端连接所述第三薄膜晶体管的漏极；
所述第四薄膜晶体管， 其源极连接所述补偿电容的第二端， 其栅极连接 所述第二时钟信号输出端， 其漏极连接所述驱动薄膜晶体管的源极；
所述第五薄膜晶体管， 其源极接地， 其栅极连接所述第一时钟信号输出 端， 其漏极连接所述第四薄膜晶体管的源极；
所述第六薄膜晶体管， 其源极连接参考电压输出端， 其栅极连接第一时 钟信号输出端 , 其漏极连接所述第二薄膜晶体管的漏极；
第七薄膜晶体管， 其源极连接参考电压输出端， 其栅极连接第一时钟信 号输出端， 其漏极连接所述驱动薄膜晶体管的栅极； 以及
所述第一薄膜晶体管的栅极连接所述第二时钟信号输出端，
其中， 所述第二薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管为 n 沟道薄膜晶体管；
所述第三薄膜晶体管、 第四薄膜晶体管以及第五薄膜晶体管为 p沟道薄 膜晶体管。
在一个示例中， 所述第一时钟信号输出端处的第一时钟信号与所述第二 时钟信号输出端处的第二时钟信号均包括第一阶段、 第二阶段与第三阶段； 在第一阶段， 所述第一时钟信号输出端为高电平， 所述第二时钟信号输 出端为低电平；
在第二阶段， 所述第一时钟信号输出端为低电平， 所述第二时钟信号输 出端为高电平；
在第三阶段， 所述第一时钟信号输出端为低电平， 所述第二时钟信号输 出端为低电平。
在一个示例中， 在第一阶段， 所述外部补偿电路中的第三薄膜晶体管、 第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管导通， 每个驱动电路 中的第一薄膜晶体管以及所述外部补偿电路中的第二薄膜晶体管和第五薄膜 晶体管截止， 使得所述补偿电容上的电压差为驱动薄膜晶体管的阔值电压； 在第二阶段， 所述外部补偿电路中的第三薄膜晶体管、第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管截止， 每个驱动电路中的第一薄膜晶体 管以及所述外部补偿电路中的第二薄膜晶体管和第五薄膜晶体管导通， 使得 每个驱动电路中的驱动电容上的电压差为与该驱动电路对应的数据线输入的 灰阶电压； 以及
在第三阶段， 所述外部补偿电路中的第三薄膜晶体管、 第四薄膜晶体管 以及第五薄膜晶体管导通， 每个驱动电路中的第一薄膜晶体管以及所述外部 补偿电路中的第二薄膜晶体管、 第六薄膜晶体管和第七薄膜晶体管截止， 使 得该驱动电路中的驱动薄膜晶体管的栅极电压跳变为该驱动薄膜晶体管的阔 值电压和与该驱动电路对应的数据线输入的灰阶电压的和。
根据本发明实施例， 还提供了一种 AMOLED驱动补偿方法， 包括： 第一阶段， 存储设置在数个像素区域内的数个驱动电路的驱动薄膜晶体 管的阔值电压；
第二阶段， 存储所述设置在数个像素区域内的数个驱动电路中的每个驱 动电路的灰阶电压；
第三阶段， 所述设置在数个像素区域内的数个驱动电路中的每个驱动电 路的驱动薄膜晶体管的栅极电压跳变为所述阔值电压与该驱动电路的灰阶电 压的和。
在一个示例中， 所述第一阶段， 存储设置在数个像素区域内的数个驱动 电路的驱动薄膜晶体管的阔值电压为：
第一时钟信号输出端为高电平， 第二时钟信号输出端为低电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶 体管导通， 每个驱动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶 体管和第五薄膜晶体管截止， 补偿电容上的电压差为所述设置在数个像素区 域内的数个驱动电路的驱动薄膜晶体管的阔值电压；
所述第二阶段， 存储所述设置在数个像素区域内的数个驱动电路中的每 个驱动电路的灰阶电压为：
第一时钟信号输出端为低电平， 第二时钟信号输出端为高电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶 体管截止， 每个驱动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶 体管和第五薄膜晶体管导通， 每个驱动电路中的驱动电容上的电压差为与该 驱动电路对应的数据线输入的灰阶电压；
所述第三阶段， 所述设置在数个像素区域内的数个驱动电路中的每个驱 动电路中的驱动薄膜晶体管的栅极电压跳变为所述阔值电压与该驱动电路的 灰阶电压的和为：
第一时钟信号输出端为低电平， 第二时钟信号输出端为低电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管以及第五薄膜晶体管导通， 每个驱 动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶体管、 第六薄膜晶 体管和第七薄膜晶体管截止， 所述设置在数个像素区域内的数个驱动电路中 的每个驱动电路中的驱动薄膜晶体管的栅极电压跳变为所述阔值电压与该驱 动电路的灰阶电压的和。
一种显示装置， 包括上述的 AMOLED驱动补偿电路。
本发明实施例提供的 AMOLED驱动补偿电路及其方法， 由于外部补偿 电路设置在像素区域之外， 能够同时补偿像素区域内的数个驱动电路的驱动 薄膜晶体管的阔值电压， 像素区域内只有用于驱动 AMOLED 的驱动电路， 从而能够增加开口率。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1为本发明实施例提供的一种 AMOLED驱动补偿电路的电路图； 图 2为图 1中电路的时钟信号的时序图；
图 3为图 1中电路在第一阶段的等效电路图； 图 4为图 1中电路在第二阶段的等效电路图；
图 5为图 1中电路在第三阶段的等效电路图；
图 6为本发明实施例提供的另一种 AMOLED驱动补偿电路的电路图； 图 7为本发明实施例提供的一种 AMOLED驱动补偿方法的流程图。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供一种 AMOLED驱动补偿电路， 包括：
设置在数个像素区域内的数个驱动电路，用于驱动数个 AMOLED,其中 在一个像素区域内设置一个 AMOLED和一个对应的驱动电路， 并且一个驱 动电路用于驱动一个对应的 AMOLED;
每个驱动电路如传统的 2T1C (二薄膜晶体管与一电容）电路， 包括第一 薄膜晶体管、 驱动薄膜晶体管以及驱动电容， 通过驱动薄膜晶体管的驱动电 流驱动 AMOLED发光。
设置在像素区域之外的外部补偿电路， 用于消除设置在像素区域内的数 个驱动电路中驱动薄膜晶体管的阔值电压对通过所述驱动薄膜晶体管的驱动 电流的影响， 使得通过驱动薄膜晶体管的驱动电流与驱动薄膜晶体管的阔值 电压无关， 从而提高了驱动电流的一致性。
现有技术在每一个像素区域内除了驱动电路， 还需要设置 5到 6个薄膜 晶体管组成的补偿电路， 而本发明实施例提供的 AMOLED驱动补偿电路， 由于外部补偿电路设置在像素区域之外， 能够同时补偿像素区域内的数个驱 动电路的驱动薄膜晶体管的阔值电压， 像素区域内只有用于驱动 AMOLED 的驱动电路， 从而能够增加开口率。
具体地， 如图 1 所示， 一行像素区域包括 N 个像素区域 Pixel— 1、
Pixel— 2 Pixel— N, 其中 N为大于 1的自然数， 在每个像素区域内分别设 置一个 AMOLED和一个对应的驱动电路。
在每个像素区域中， 驱动电路包括： 第一薄膜晶体管 Tl、 驱动电容 Cst、 以及驱动薄膜晶体管 T8; 其中第一薄膜晶体管 T1 , 其源极连接数据线； 驱 动电容 Cst, 其第一端连接第一薄膜晶体管 Tl的漏极； 驱动薄膜晶体管 T8, 其栅极连接第一薄膜晶体管 T1 的漏极。 此外， 在该像素区域中， AMOLED 的阳极连接工作电压输出端， 具体为电压源 VDD, AMOLED的阴极连接设 置在该像素区域中的驱动电路的驱动薄膜晶体管 T8的漏极。第一薄膜晶体管 和驱动薄膜晶体管为 n沟道薄膜晶体管。
此外， N个像素区域内的 N个第一薄膜晶体管 T1的源极分别连接 N条 数据线 Datal、 Data2 DataN。
设置在像素区域之外的外部补偿电路包括： 第二薄膜晶体管 T2、 第三薄 膜晶体管 Τ3、 补偿电容 Cth、 第四薄膜晶体管 T4、 第五薄膜晶体管 Τ5、 第 六薄膜晶体管 Τ6以及第七薄膜晶体管 Τ7; 其中第二薄膜晶体管 Τ2, 其源极 接地， 其栅极连接第二时钟信号输出端 C1 , 其漏极连接驱动电容 Cst的第二 端； 第三薄膜晶体管 T3 , 其源极连接第二薄膜晶体管 T2的漏极， 其栅极连 接第二时钟信号输出端 C1 ; 补偿电容 Cth, 其第一端连接第三薄膜晶体管 T3 的漏极； 第四薄膜晶体管 T4, 其源极连接补偿电容 Cth的第二端， 其栅极连 接第二时钟信号输出端 C1 , 其漏极连接驱动薄膜晶体管 T8的源极； 第五薄 膜晶体管 T5, 其源极接地， 其栅极连接第一时钟信号输出端 G1 , 其漏极连 接第四薄膜晶体管 T4的源极； 第六薄膜晶体管 T6, 其源极连接参考电压输 出端 VREF, 其栅极连接第一时钟信号输出端 G1 , 其漏极连接第二薄膜晶体 管 T2的漏极； 第七薄膜晶体管 T7, 其源极连接参考电压输出端 VREF, 其 栅极连接第一时钟信号输出端 G1 , 其漏极连接驱动薄膜晶体管 T8的栅极； 第一薄膜晶体管 T1的栅极连接第二时钟信号输出端 C1。第二薄膜晶体管 T2、 第六薄膜晶体管 Τ6以及第七薄膜晶体管 Τ7为！！沟道薄膜晶体管； 第三薄膜 晶体管 Τ3、第四薄膜晶体管 Τ4以及第五薄膜晶体管 Τ5为 ρ沟道薄膜晶体管。
进一步地， 如图 2所示， 第一时钟信号输出端 G1处的第一时钟信号 gl 与第二时钟信号输出端 C1处的第二时钟信号 cl均包括第一阶段 HI、第二阶 段 H2与第三阶段 H3; 在第一阶段 HI , 第一时钟信号输出端 Gl为高电平， 第二时钟信号输出端 C1为低电平； 在第二阶段 H2, 第一时钟信号输出端 G1 为低电平， 第二时钟信号输出端 C1为高电平； 在第三阶段 H3 , 第一时钟信 号输出端 G1为低电平， 第二时钟信号输出端 C1为低电平。
以下通过一行像素的充电过程详细描述本方案， 如图 1所示， 定义： 补 偿电容 Cth与第三薄膜晶体管 T3连接的第一端为第一节点 A: 补偿电容 Cth 与第四薄膜晶体管连接的第二端为第二节点 B; 驱动电容 Cst与第一薄膜晶 体管 T1连接的第一端为第三节点 C, 驱动电容 Cst与第二薄膜晶体管 T2连 接的第二端为第四节点0。
第一阶段 HI为预充电阶段， 此时， 第一时钟信号输出端 G1为高电平， 第二时钟信号输出端 C1为低电平， 补偿电路中的第三薄膜晶体管 T3、 第四 薄膜晶体管 Τ4、 第六薄膜晶体管 Τ6以及第七薄膜晶体管 Τ7导通，每个驱动 电路中的第一薄膜晶体管 T1以及补偿电路中的第二薄膜晶体管 Τ2和第五薄 膜晶体管 Τ5截止，此时电路等效为如图 3所示的电路，参考电压输出端 VREF 对补偿电容 Cth充电， 使得第一节点 A的电压为参考电压输出端 VREF上的 参考电压 Vref, 第二节点 B的电压为参考电压 Vref与驱动薄膜晶体管 T8的 阔值电压 Vth的差， 为 Vref-Vth, 也就是补偿电容 Cth上的电压差为驱动薄 膜晶体管 T8的阔值电压 Vth, 需要说明的是， 上述一行像素区域内的驱动薄 膜晶体管 T8需要釆用相同的工艺制作，以保证此行中的每个驱动薄膜晶体管 T8的阔值电压相同， 都为 Vth。
第二阶段 H2为灰阶电压输入阶段， 此时， 第一时钟信号输出端 G1为低 电平， 第二时钟信号输出端 C1为高电平， 补偿电路中的第三薄膜晶体管 T3、 第四薄膜晶体管 Τ4、第六薄膜晶体管 Τ6以及第七薄膜晶体管 Τ7截止，每个 驱动电路中的第一薄膜晶体管 T1以及补偿电路中的第二薄膜晶体管 Τ2和第 五薄膜晶体管 Τ5导通， 此时电路等效为如图 4所示的电路， 以下以一个像素 区域 Pixel— 1内驱动电路的工作原理为例说明本方案，数据线 Datal对驱动电 容 Cst充电，使得第三节点 C的电压为数据线 Datal输入的灰阶电压 Vdatal , 第四节点 D的电压为零， 也就是驱动电容 Cst上的电压差为数据线 Datal输 入的灰阶电压 Vdatal。
第三阶段 H3为发光阶段， 此时， 第一时钟信号输出端 G1为低电平， 第 二时钟信号输出端 C1为低电平， 补偿电路中的第三薄膜晶体管 T3、 第四薄 膜晶体管 Τ4以及第五薄膜晶体管 Τ5导通， 每个驱动电路中的第一薄膜晶体 管 T1以及补偿电路中的第二薄膜晶体管 Τ2、第六薄膜晶体管 Τ6和第七薄膜 晶体管 Τ7截止， 此时电路等效为如图 5所示的电路， 第二节点 Β接地， 电 压为零， 由于在第一阶段 HI , 补偿电容 Cth上存储的电压差为驱动薄膜晶体 管 T8的阔值电压 Vth, 因此在第三阶段 H3 , 第一节点 A,也就是第四节点 D 的电压为驱动薄膜晶体管 T8的阔值电压 Vth, 由于在第二阶段 H2, 以像素 区域 Pixel— 1内驱动电路为例， 驱动电容 Cst上的电压差为数据线 Datal输入 的灰阶电压 Vdatal , 因此在第三阶段 H3 , 仍以像素区域 Pixel— 1内驱动电路 为例， 第三节点 C的电压跳变为驱动薄膜晶体管 T8的阔值电压 Vth与数据 线 Datal输入的灰阶电压 Vdatal 的和， 为 Vth+ Vdatal , 即驱动薄膜晶体管 T8的栅极电压 Vgs=Vth+Vdatal , 通过驱动薄膜晶体管 T8的驱动电流为： I = k(Vgs - Vth)2 = k(datal + Vth - Vth)2 = k(Vdatal)2 ,
其中 k= effxCoxx ( W/L ) 12, eff表示驱动薄膜晶体管 T8的载流子有 效迁移率， Cox表示驱动薄膜晶体管 T8的栅绝缘层介电常数， W/L表示驱动 薄膜晶体管 T8的沟道宽长比。
通过上述表达式， 通过驱动薄膜晶体管 T8的驱动电流 I与其阔值电压
Vth无关， 消除了驱动薄膜晶体管 T8的阔值电压 Vth对通过所述驱动薄膜晶 体管 T8的驱动电流 I的影响。
上述参考电压输出端也可以为电源端 VDD。 上述第一阶段 HI与第二阶 段 H2时间较短， 而第三阶段 H3较长用于使面板发光显示。
现有技术中驱动电流的表达式中通常包含电源端 VDD的电源电压 Vdd, 由于电压降（IR Drop )的问题， 电源电压 Vdd的变化会进一步影响面板的现 实效果，而本发明实施例中驱动电流的表达式中不含电源端 VDD的电源电压 Vdd, 从而进一步改善 IR Dro 的问题。
一行中每个像素区域内驱动电路的工作原理都与上述一个像素区域 Pixel— 1内驱动电路的工作原理相同， 在此不再赘述。
简言之， 对于 N个像素区域 Pixel— 1、 Pixel— 2 Pixel— N中的第 i个 像素区域 Pixel— i ( i为大于 1且小于等于 N的自然数） 内的驱动电路而言， 在第二阶段 H2, 驱动电容 Cst上的电压差为数据线 Datai输入的灰阶电压 Vdatai, 在第三阶段 H3 , 第三节点 C的电压跳变为驱动薄膜晶体管 T8的阔 值电压 Vth与数据线 Datai输入的灰阶电压 Vdatai的和， 为 Vth+Vdatai, 即 驱动薄膜晶体管 T8的栅极电压 Vgs= Vth+Vdatai, 通过驱动薄膜晶体管 T8的 驱动电流为：
I = k(Vgs - Vth)2 = k(datai + Vth - Vth)2 = k(Vdatai)2。
以上仅以一行像素的充电过程详细描述了本方案， 如图 6所示， 还可以 在多行像素区域之外分别设置与之对应的外部补偿电路构成 AMOLED驱动 补偿电路， 其中包括： m个第一时钟信号输出端 Gl、 G2 Gm; m个第 二时钟信号输出端 Cl、 C2 Cm, 其中 m为大于一的自然数， AMOLED 驱动补偿电路的连接关系与工作原理与上述实施例相同， 在此不再赘述。
本发明实施例提供的 AMOLED驱动补偿电路， 使得设置在像素区域之 外的外部补偿电路同时补偿一行像素区域内数个驱动电路的驱动薄膜晶体管 的阔值电压， 像素区域内只有用于驱动 AMOLED 的驱动电路， 从而能够增 加开口率。
本发明实施例还提供一种 AMOLED驱动补偿方法， 该方法应用于上述 实施例提供的 AMOLED驱动补偿电路， 如图 7所示， 包括：
步骤 101、 在第一阶段， 存储设置在数个像素区域内的数个驱动电路的 驱动薄膜晶体管的阔值电压；
步骤 102、 在第二阶段， 存储所述设置在数个像素区域内的数个驱动电 路中的每个驱动电路的灰阶电压；
步骤 103、 在第三阶段， 设置在数个像素区域内的数个驱动电路中的每 个驱动电路中的驱动薄膜晶体管的栅极电压跳变为阔值电压与该驱动电路的 灰阶电压的和。
而本发明实施例提供的 AMOLED驱动补偿方法， 由于通过设置在像素 区域之外的外部补偿电路同时补偿像素区域内的数个驱动电路的驱动薄膜晶 体管的阔值电压， 像素区域内只有用于驱动 AMOLED 的驱动电路， 从而能 够增加开口率。
在第一阶段， 存储设置在数个像素区域内的数个驱动电路的驱动薄膜晶 体管的阔值电压具体为：
第一时钟信号输出端为高电平， 第二时钟信号输出端为低电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶 体管导通， 每个驱动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶 体管和第五薄膜晶体管截止， 补偿电容上的电压差为设置在像素区域内的数 个驱动电路的驱动薄膜晶体管的阔值电压；
在第二阶段， 存储所述设置在数个像素区域内的数个驱动电路中的每个 驱动电路的灰阶电压具体为：
第一时钟信号输出端为低电平， 第二时钟信号输出端为高电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶 体管截止， 每个驱动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶 体管以及第五薄膜晶体管导通， 每个驱动电路中的驱动电容上的电压差为与 该驱动电路对应的数据线输入的灰阶电压；
第三阶段， 设置在数个像素区域内的数个驱动电路中的每个驱动电路中 的驱动薄膜晶体管的栅极电压跳变为阔值电压与该驱动电路的灰阶电压的和 具体为：
第一时钟信号输出端为低电平， 第二时钟信号输出端为低电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管以及第五薄膜晶体管导通， 每个驱 动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶体管、 第六薄膜晶 体管和第七薄膜晶体管截止， 所述设置在数个像素区域内的数个驱动电路中 的每个驱动电路中的驱动薄膜晶体管的栅极电压跳变为所述阔值电压与该驱 动电路的灰阶电压的和。
本发明实施例提供的 AMOLED驱动补偿方法具体的工作原理与上述实 施例相同， 在此不再赘述。
设置在像素区域之外的外部补偿电路同时补偿像素区域内的数个驱动电 路的驱动薄膜晶体管的阔值电压， 像素区域内只有用于驱动 AMOLED 的驱 动电路， 从而能够增加开口率。
本发明实施例还提供一种显示装置， 包括上述的 AMOLED驱动补偿电 设置在像素区域之外的外部补偿电路同时补偿像素区域内的数个驱动电 路的驱动薄膜晶体管的阔值电压， 像素区域内只有用于驱动 AMOLED 的驱 动电路， 从而能够增加开口率。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种 AMOLED驱动补偿电路， 其特征在于， 包括：
设置在数个像素区域内的数个驱动电路，用于驱动数个 AMOLED,其中 在每个像素区域内设置一个 AMOLED和一个对应的驱动电路， 并且一个驱 动电路用于驱动一个对应的 AMOLED;
设置在像素区域之外的外部补偿电路， 用于消除所述设置在数个像素区 域内的数个驱动电路中驱动薄膜晶体管的阔值电压对通过所述驱动薄膜晶体 管的驱动电流的影响。
2、 根据权利要求 1所述的 AMOLED驱动补偿电路， 其特征在于， 所述设置在数个像素区域内的数个驱动电路中的每个驱动电路包括： 第 一薄膜晶体管、 驱动电容、 以及驱动薄膜晶体管；
所述第一薄膜晶体管， 其源极连接数据线；
所述驱动电容， 其第一端连接所述第一薄膜晶体管的漏极； 以及 所述驱动薄膜晶体管， 其栅极连接所述第一薄膜晶体管的漏极， 其中， 与该驱动电路对应的 AMOLED的输入端连接工作电压输出端 , 并且与该驱动电路对应的 AMOLED 的输出端连接所述驱动薄膜晶体管的漏 极；
所述第一薄膜晶体管和驱动薄膜晶体管为 n沟道薄膜晶体管。
3、 根据权利要求 1或 2所述的 AMOLED驱动补偿电路， 其特征在于， 所述设置在像素区域之外的外部补偿电路包括：
第二薄膜晶体管、 第三薄膜晶体管、 补偿电容、 第四薄膜晶体管、 第五 薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管；
所述第二薄膜晶体管， 其源极接地， 其栅极连接第二时钟信号输出端， 其漏极连接所述驱动电容的第二端；
所述第三薄膜晶体管， 其源极连接所述第二薄膜晶体管的漏极， 其栅极 连接所述第二时钟信号输出端；
所述补偿电容， 其第一端连接所述第三薄膜晶体管的漏极；
所述第四薄膜晶体管， 其源极连接所述补偿电容的第二端， 其栅极连接 所述第二时钟信号输出端， 其漏极连接所述驱动薄膜晶体管的源极；
所述第五薄膜晶体管， 其源极接地， 其栅极连接所述第一时钟信号输出 端， 其漏极连接所述第四薄膜晶体管的源极；
所述第六薄膜晶体管， 其源极连接参考电压输出端， 其栅极连接第一时 钟信号输出端 , 其漏极连接所述第二薄膜晶体管的漏极；
第七薄膜晶体管， 其源极连接参考电压输出端， 其栅极连接第一时钟信 号输出端， 其漏极连接所述驱动薄膜晶体管的栅极； 以及
所述第一薄膜晶体管的栅极连接所述第二时钟信号输出端，
其中， 所述第二薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管为 n 沟道薄膜晶体管；
所述第三薄膜晶体管、 第四薄膜晶体管以及第五薄膜晶体管为 p沟道薄 膜晶体管。
4、 根据权利要求 3所述的 AMOLED驱动补偿电路， 其特征在于， 所述第一时钟信号输出端处的第一时钟信号与所述第二时钟信号输出端 处的第二时钟信号均包括第一阶段、 第二阶段与第三阶段；
在第一阶段， 所述第一时钟信号输出端为高电平， 所述第二时钟信号输 出端为低电平；
在第二阶段， 所述第一时钟信号输出端为低电平， 所述第二时钟信号输 出端为高电平；
在第三阶段， 所述第一时钟信号输出端为低电平， 所述第二时钟信号输 出端为低电平。
5、 根据权利要求 4所述的 AMOLED驱动补偿电路， 其特征在于， 在第一阶段， 所述外部补偿电路中的第三薄膜晶体管、第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管导通， 每个驱动电路中的第一薄膜晶体 管以及所述外部补偿电路中的第二薄膜晶体管和第五薄膜晶体管截止， 使得 所述补偿电容上的电压差为驱动薄膜晶体管的阔值电压；
在第二阶段， 所述外部补偿电路中的第三薄膜晶体管、第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶体管截止， 每个驱动电路中的第一薄膜晶体 管以及所述外部补偿电路中的第二薄膜晶体管和第五薄膜晶体管导通， 使得 每个驱动电路中的驱动电容上的电压差为与该驱动电路对应的数据线输入的 灰阶电压； 以及
在第三阶段， 所述外部补偿电路中的第三薄膜晶体管、 第四薄膜晶体管 以及第五薄膜晶体管导通， 每个驱动电路中的第一薄膜晶体管以及所述外部 补偿电路中的第二薄膜晶体管、 第六薄膜晶体管和第七薄膜晶体管截止， 使 得该驱动电路中的驱动薄膜晶体管的栅极电压跳变为该驱动薄膜晶体管的阔 值电压和与该驱动电路对应的数据线输入的灰阶电压的和。
6、 一种 AMOLED驱动补偿方法， 其特征在于， 包括：
第一阶段， 存储设置在数个像素区域内的数个驱动电路的驱动薄膜晶体 管的阔值电压；
第二阶段， 存储所述设置在数个像素区域内的数个驱动电路中的每个驱 动电路的灰阶电压；
第三阶段， 所述设置在数个像素区域内的数个驱动电路中的每个驱动电 路的驱动薄膜晶体管的栅极电压跳变为所述阔值电压与该驱动电路的灰阶电 压的和。
7、 根据权利要求 6所述的 AMOLED驱动补偿方法， 其特征在于， 所述第一阶段， 存储设置在数个像素区域内的数个驱动电路的驱动薄膜 晶体管的阔值电压为：
第一时钟信号输出端为高电平， 第二时钟信号输出端为低电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶 体管导通， 每个驱动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶 体管和第五薄膜晶体管截止， 补偿电容上的电压差为所述设置在数个像素区 域内的数个驱动电路的驱动薄膜晶体管的阔值电压；
所述第二阶段， 存储所述设置在数个像素区域内的数个驱动电路中的每 个驱动电路的灰阶电压为：
第一时钟信号输出端为低电平， 第二时钟信号输出端为高电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管、 第六薄膜晶体管以及第七薄膜晶 体管截止， 每个驱动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶 体管和第五薄膜晶体管导通， 每个驱动电路中的驱动电容上的电压差为与该 驱动电路对应的数据线输入的灰阶电压；
所述第三阶段， 所述设置在数个像素区域内的数个驱动电路中的每个驱 动电路中的驱动薄膜晶体管的栅极电压跳变为所述阔值电压与该驱动电路的 灰阶电压的和为：
第一时钟信号输出端为低电平， 第二时钟信号输出端为低电平， 补偿电 路中的第三薄膜晶体管、 第四薄膜晶体管以及第五薄膜晶体管导通， 每个驱 动电路中的第一薄膜晶体管以及补偿电路中的第二薄膜晶体管、 第六薄膜晶 体管和第七薄膜晶体管截止， 所述设置在数个像素区域内的数个驱动电路中 的每个驱动电路中的驱动薄膜晶体管的栅极电压跳变为所述阔值电压与该驱 动电路的灰阶电压的和。
8、 一种显示装置， 其特征在于， 包括如权利要求 1至 5中任一项所述的 AMOLED驱动补偿电路。
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