WO2013062128A1 - Circuit à capteur capacitif, et appareil électrique - Google Patents

Circuit à capteur capacitif, et appareil électrique Download PDF

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Publication number
WO2013062128A1
WO2013062128A1 PCT/JP2012/077893 JP2012077893W WO2013062128A1 WO 2013062128 A1 WO2013062128 A1 WO 2013062128A1 JP 2012077893 W JP2012077893 W JP 2012077893W WO 2013062128 A1 WO2013062128 A1 WO 2013062128A1
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Prior art keywords
capacitance
voltage
circuit
drive
sense
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PCT/JP2012/077893
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English (en)
Japanese (ja)
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飯塚　邦彦
濱口　睦
明 長尾
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シャープ株式会社
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Publication of WO2013062128A1 publication Critical patent/WO2013062128A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Definitions

  • a device for detecting capacitance values distributed in a matrix for example, capacitance detection for detecting the distribution of capacitance values of a capacitance matrix formed between M drive lines and L sense lines
  • An apparatus is disclosed in US Pat.
  • the capacitance detection device reduces the capacitance value of the touched capacitance, and thus detects a change in the capacitance value and detects a touch of the finger or the pen.
  • the sense amplifier 2 has an operational amplifier 10.
  • the non-inverted input terminal of the operational amplifier 10 is connected to the sense line SL, and the inverted input terminal is connected to the reference voltage Vr.
  • an integration capacitance Cf and a switch SWR connected to the non-inversion input terminal of the operational amplifier 10 and the output of the operational amplifier 10 are provided in parallel with each other.
  • the output voltage Vout (t) of the sense amplifier 2 at time t when the drive lines DL1 to DL4 are driven by the drive voltages Vin1, Vin2, Vin3 and Vin4 is expressed by the following equation (1).
  • the absolute value of the product of the noise voltage difference ⁇ Vn (t) ⁇ Vn (t0) ⁇ and the sense line parasitic capacitance Cp is ⁇ Vin1 ⁇ C1 + Vin2 ⁇ C2 + Vin3 ⁇ C3 + Vin4 ⁇ C4 ⁇ If the output voltage Vout (t) is used to estimate the electrostatic capacitances C1, C2, C3 and C4, an error occurs if the absolute value is not sufficiently small.
  • the process of resetting the electrostatic capacitances C1 to C4 and recharging the electrostatic capacitances C1 to C4 with the drive voltages Vin1 to Vin4 and reading the charges of the electrostatic capacitances C1 to C4 by the sense amplifier 2 is the drive line DL1.
  • ⁇ DL4 in order to change the voltage of the sense line SL, it takes a time determined by the time constant of those lines before the voltage change converges, and within the limited time required for the estimation of the capacitance value There is a problem that the number of times of averaging that can be performed is insufficient.
  • An object of the present invention is to provide a capacitance detection circuit and an electronic device capable of resetting a capacitance, recharging with a drive voltage, and shortening a processing time for reading by a sense amplifier.
  • the capacitance detection circuit estimates the capacitance value of one or more capacitances, one end of which is connected to one or more drive lines crossing the sense line and the other end of which is connected to the sense line.
  • a drive circuit for applying a predetermined voltage to the drive line, and the charge accumulated in the capacitance by the application of the voltage through the sense line
  • a sense amplifier to be read out an AD converter which samples the output of the sense amplifier a plurality of times while the drive circuit applies the voltage to the drive line, and converts it to a digital value for each sampling, and the AD conversion
  • a digital arithmetic circuit for averaging a plurality of digital values converted by the digital signal processor.
  • Another capacitance detection circuit is a capacitance value of one or more capacitances having one end connected to one or more drive lines crossing the sense line and the other end connected to the sense line.
  • a capacitance detection circuit for acquiring data for estimating the capacitance, the drive circuit applying a predetermined voltage to the drive line, the charge accumulated in the capacitance by the application of the voltage, the sense circuit
  • a sense amplifier for reading out through a line, a sampling capacitance circuit which samples the output of the sense amplifier a plurality of times while the drive circuit applies the voltage to the drive line, and the sense sampled by the sampling capacitance circuit
  • an analog operation circuit that averages a plurality of outputs of the amplifier.
  • a sense amplifier for reading out the charge accumulated in the electrostatic capacitance through the sense line by applying the second voltage after reading out the electric charge accumulated in the electrostatic capacitance through the sense line; and the drive circuit While applying the first voltage to the line, the output of the sense amplifier is sampled a plurality of times, converted to a first digital value for each sampling, and An AD converter that samples the output of the sense amplifier a plurality of times while the second voltage is applied, and converts the output into a second digital value for each sampling, and a plurality of second converters converted by the AD converter
  • a digital operation circuit for estimating the capacitance value of the capacitance by obtaining a difference between a first detection voltage obtained by averaging one digital value and a second detection voltage obtained by averaging the plurality of second digital values; It is characterized by having.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • Estimating capacitance values of one capacitance and one or more second capacitances having one end connected to the drive line crossing the second sense line and the other end connected to the second sense line
  • a drive circuit for applying a predetermined voltage to the drive line, and the charge accumulated in the first and second capacitances by the application of the voltage.
  • a sense amplifier for reading out through the first and second sense lines, and the differential output of the sense amplifier is sampled a plurality of times while the drive circuit applies the voltage to the drive line.
  • An AD converter for converting the digital value, characterized in that said a digital arithmetic circuit for averaging the converted plurality of digital values by an AD converter.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • Estimating capacitance values of one capacitance and one or more second capacitances having one end connected to the drive line crossing the second sense line and the other end connected to the second sense line
  • a drive circuit for applying a predetermined voltage to the drive line, and the charge accumulated in the first and second capacitances by the application of the voltage.
  • a sense amplifier for reading out through the first and second sense lines, and a sump for sampling a differential output of the sense amplifier a plurality of times while the drive circuit applies the voltage to the drive line.
  • ring capacitor circuit characterized in that a plurality of differential outputs of the sense amplifiers sampled by the sampling capacitor circuit having an analog arithmetic circuit for averaging.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • Estimating capacitance values of one capacitance and one or more second capacitances having one end connected to the drive line crossing the second sense line and the other end connected to the second sense line
  • a capacitance detection circuit for acquiring data for driving the drive line, the drive circuit applying a predetermined first voltage and a second voltage to the drive line in this order, and the application of the first voltage to the drive line.
  • the charge stored in the second capacitance is read out through the first and second sense lines, respectively, and then the charge stored in the first and second capacitances is applied by the application of the second voltage.
  • a sense amplifier for reading out the signal and the differential output of the sense amplifier while the drive circuit is applying the first voltage to the drive line, and sampling the output of the sense amplifier a plurality of times and converting it into a first digital value for each sampling After that, while the drive circuit is applying the second voltage, an AD converter which samples the differential output of the sense amplifier a plurality of times and converts it into a second digital value for each sampling, and the AD converter Calculating a difference between a first detection voltage obtained by averaging a plurality of first digital values converted by the second detection voltage and a second detection voltage obtained by averaging the plurality of second digital values. And a digital operation circuit for estimating.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • Estimating capacitance values of one capacitance and one or more second capacitances having one end connected to the drive line crossing the second sense line and the other end connected to the second sense line
  • a capacitance detection circuit for acquiring data for driving the drive line, the drive circuit applying a predetermined first voltage and a second voltage to the drive line in this order, and the application of the first voltage to the drive line.
  • the charge stored in the second capacitance is read out through the first and second sense lines, respectively, and then the charge stored in the first and second capacitances is applied by the application of the second voltage.
  • the drive circuit After the first differential output of the sense amplifier is sampled multiple times while the drive circuit applies the first voltage to the drive line, the drive circuit performs the second operation.
  • a sampling capacitor circuit that samples the second differential output of the sense amplifier a plurality of times while applying a voltage, and averaging a plurality of first differential outputs of the sense amplifier sampled by the sampling capacitor circuit.
  • the capacitance value of the capacitance is estimated by calculating the difference between the first detected voltage and the second detected voltage obtained by averaging the plurality of second differential outputs of the sense amplifier sampled by the sampling capacitance circuit. And an analog operation circuit.
  • An electronic device comprises the capacitance detection circuit according to the present invention, wherein the sense line, the drive line, and the capacitance form a touch panel, and are superimposed on the touch panel, or the touch panel And a display panel having a built-in display.
  • the electrostatic capacitance detection circuit samples the output of the sense amplifier a plurality of times while the drive circuit applies the voltage to the drive line, and converts the output into a digital value for each sampling. Therefore, the processing time can be shortened compared to the configuration in which the process of resetting the capacitance, providing the drive voltage, and reading out by the sense amplifier is repeated.
  • FIG. 1 is a circuit diagram showing a configuration of a capacitance detection circuit according to a first embodiment.
  • 5 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit according to Embodiment 1.
  • FIG. 7 is a circuit diagram showing a configuration of a capacitance detection circuit according to a second embodiment.
  • FIG. 16 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit according to Embodiment 2.
  • FIG. 13 is a circuit diagram showing a configuration of a capacitance detection circuit according to a third embodiment.
  • FIG. 16 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit according to Embodiment 3.
  • FIG. 16 is a circuit diagram showing a configuration of a capacitance detection circuit according to a fourth embodiment.
  • FIG. 16 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit according to Fourth Embodiment.
  • FIG. 18 is a block diagram showing a configuration of a mobile phone according to Embodiment 5. It is a circuit diagram which shows the structure of the conventional electrostatic capacitance detection circuit.
  • FIG. 1 is a circuit diagram showing a configuration of a capacitance detection circuit 1 according to a first embodiment.
  • the electrostatic capacitance detection circuit 1 has one end connected to the drive lines DL1 to DL4 crossing the sense line SL and the other end to estimate capacitance values of the electrostatic capacitances C1 to C4 connected to the sense line SL. Get data
  • the electrostatic capacitance detection circuit 1 includes a drive circuit 8.
  • the drive circuit 8 applies voltages Vin1 to Vin4 to the drive lines DL1 to DL4.
  • Sense line parasitic capacitance Cp is present in sense line SL.
  • Noise NZ is externally applied to the sense line parasitic capacitance Cp.
  • the electrostatic capacitance detection circuit 1 is provided with a sense amplifier 2.
  • the sense amplifier 2 reads the charges accumulated in the capacitances C1 to C4 by application of the voltages Vin1 to Vin4 through the sense line SL.
  • the sense amplifier 2 has an operational amplifier 10.
  • the non-inverted input terminal of the operational amplifier 10 is connected to the sense line SL, and the inverted input terminal is connected to the reference voltage Vr.
  • an integration capacitance Cf and a switch SWR connected to the non-inversion input terminal of the operational amplifier 10 and the output of the operational amplifier 10 are provided in parallel with each other.
  • the sense amplifier 2 is integrated and has an input terminal 9 connected to the sense line SL.
  • the capacitance detection circuit 1 includes an AD converter 3. While the drive circuit 8 applies the voltages Vin1 to Vin4 to the drive lines DL1 to DL4, the AD converter 3 repeatedly samples the output of the sense amplifier 2 a plurality of times, and converts the output into digital values for each sampling.
  • the pseudo random number generation circuit 7 is connected to the AD converter 3. The pseudo random number generation circuit 7 generates a random number within a predetermined range and supplies it to the AD converter 3 in order to control the sampling period of the AD converter 3.
  • the electrostatic capacitance detection circuit 1 is provided with a digital arithmetic circuit 4.
  • the digital arithmetic circuit 4 averages a plurality of digital values converted by the AD converter 3.
  • the voltages Vin1, Vin2, Vin3 and Vin4 are applied to the terminals of the capacitances C1, C2, C3 and C4 not connected to the sense line SL through the drive lines DL1 to DL4, and the sense amplifier 2 at that time is
  • the output voltage is repeatedly read a plurality of times by the AD converter 3 to obtain data for estimating the values of the capacitors C1, C2, C3 and C4.
  • the number of repetitions of readout by the AD converter 3 can actually take various values from several times to 1000 or more times depending on the driving method, the situation of external noise, and required S / N. Choose the appropriate number of repetitions that can achieve the signal-to-noise ratio needed to detect the touch position of a finger or pen and can be completed within the time allowed for one touch position detection.
  • Vout (t) - ⁇ Vd ⁇ C1 + (Vn (t)-Vn (t0)) ⁇ Cp ⁇ / Cf + Vr formula (1)
  • the value of the capacitance C1 can be estimated by accepting an error determined by noise such as Vn (t) ⁇ Vn (t0). Assuming that the rms (root mean square) value of the noise voltage Vn is Vn_rms, the rms value of Vn (t) ⁇ Vn (t0) is 2Vn_rms.
  • the output voltage after the output converges is AD converter 3 at time t11, t12,.
  • the term of noise included in the addition average value, (Vn (t11) + Vn (t12) +... + Vn (t1n) / n is the noise voltage between samples Vn (t11), Vn (t12),. If there is no correlation in t1n), the noise rms value becomes 1 / sqrt (n) of the rms value of the noise voltage Vn at rms value, so the noise rms value that was 2Vn_rms at Vout (t) If it is larger, it can be reduced to Vn_rms.
  • the noise voltage Vn affecting the sense line SL through the parasitic capacitance Cp has a random change depending on the display screen of the liquid crystal display, and it is expected that the correlation between samples is small.
  • periodic sampling takes between samples
  • the correlation of Even in such a case in order to reduce the amount of noise effectively by averaging, it is recommended that the pseudo random number generation circuit 7 make the sampling time non-periodic.
  • the sampling for obtaining the outputs Vout (t1), Vout (t2), Vout (t3), and Vout (t4) is repeated a plurality of times by the AD converter 3 to obtain digital values. Converting and calculating the addition average Vout_ave1, Vout_ave2, Vout_ave3 and Vout_ave4 of the digital values by the digital operation circuit 4, the output Vout in the equation (6), the equation (7), the equation (8) and the equation (9) It is possible to reduce noise by replacing (t1), Vout (t2), Vout (t3), and Vout (t4).
  • FIG. 2 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit 1A according to the first embodiment.
  • the same components as those described above are designated by the same reference numerals. Detailed descriptions of these components are omitted.
  • Capacitance detection circuit 1A shows a circuit example in the case of obtaining an addition average of a plurality of sampling voltages by an analog circuit, and in place of AD converter 3 and digital operation circuit 4, sampling capacitance circuit 5A, integrator 6A Is equipped.
  • the sampling capacitor circuit 5A has a sampling capacitor Cs.
  • the switches SW1 and SW3 are connected to one terminal of the sampling capacitor Cs, and the switches SW2 and SW4 are connected to the other terminal.
  • the switch SW1 switches the connection of one terminal of the sampling capacitor Cs between the output of the sense amplifier 2 and the reference voltage Vr.
  • the switch SW2 switches the connection of the other terminal of the sampling capacitor Cs between the reference voltage Vr and the output of the sense amplifier 2.
  • the switch SW3 turns on and off the connection between one terminal of the sampling capacitor Cs and the integrator 6A.
  • the switch SW4 turns on and off the connection between the other terminal of the sampling capacitor Cs and the integrator 6A.
  • a pseudo random number generation circuit 7A is connected to the sampling capacitance circuit 5A.
  • the pseudo random number generation circuit 7A generates a pseudo random number within a predetermined range and supplies it to the sampling capacitance circuit 5A in order to control the operation cycle of the switches SW1 to SW4.
  • the integrator 6A has an operational amplifier 11.
  • the noninverting input terminal of the operational amplifier 11 is connected to the switch SW3 of the sampling capacitor circuit 5A.
  • the inverting input terminal of the operational amplifier 11 is connected to the reference voltage Vr and the switch SW4 of the sampling capacitance circuit 5A.
  • integration capacitors Cint and switches SWR_int connected in parallel to each other and connected to the non-inversion input terminal of the operational amplifier 11 and the output of the operational amplifier 11 are provided in parallel with each other.
  • Vout_ave ⁇ Vout (t1) + Vout (t2) +... + Vout (tn) ⁇ Cs / Cint, Is obtained.
  • FIG. 3 is a circuit diagram showing a configuration of a capacitance detection circuit 1B according to a second embodiment.
  • the same components as those described above are designated by the same reference numerals. Detailed descriptions of these components are omitted.
  • the electrostatic capacitance detection circuit 1B includes a drive circuit 8B, a sense amplifier 2B, an AD converter 3B, and a digital arithmetic circuit 4B.
  • Vout (t1) -(Vin11.C1 + Vin21.C2 + Vin31.C3 + Vin41.C4) / Cf- (Vn (t1) -Vn (t01)).
  • Voff is an input offset voltage of the sense amplifier 2B.
  • the noise term Vn (t2) ⁇ Vn (t1) included in Vout_cds is canceled if the noise at time t1 and time t2 is correlated.
  • the noise of the sense amplifier 2B is also canceled at time t1 and time t2 at portions having correlation. In particular, noise having no time variation such as the input offset of the sense amplifier 2B is completely canceled.
  • the variation of the input offset voltage of each sense amplifier 2B becomes a problem, so it is desirable to use correlated double sampling.
  • Vout_ave1 ⁇ (Vin11 ⁇ C1 + Vin21 ⁇ C2 + Vin31 ⁇ C3 + Vin41 ⁇ C4) / Cf ⁇ (Vn (t1) _ave ⁇ Vn (t01)) ⁇ Cp / Cf + Vr + Voff Formula (12), It becomes.
  • Vn (t1) _ave represents the average of noise Vn (t) when sampled a plurality of times in the state where the first applied voltage is applied.
  • Vout_ave2 -(Vin12.C1 + Vin22.C2 + Vin32.C3 + Vin42.C4) / Cf- (Vn (t2) _ave-Vn (t01)).
  • Vn (t2) _ave represents the average of noise Vn (t) when sampled a plurality of times with the second applied voltage applied.
  • Vn (t1) _ave and Vn (t2) _ave are expected to be smaller than Vn (t1) and Vn (t2) if the correlation between samples is small. Even in this case, it is recommended to randomize the sampling time by the pseudo random number generation circuit 7 in order to reduce the amount of noise effectively by averaging.
  • capacitance detection circuit 1C single end, CDS
  • FIG. 4 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit 1C according to the second embodiment.
  • the same components as those described above are designated by the same reference numerals. Detailed descriptions of these components are omitted.
  • the electrostatic capacitance detection circuit 1C includes a sampling capacitance circuit 5C and an integrator 6C instead of the AD converter 3B and the digital operation circuit 4B.
  • the output of the sense amplifier 2B in a state where the drive lines DL1 to DL4 are driven by the first drive voltage set is repeatedly sampled a plurality of times by the sampling capacitance Cs and integrated by the integration capacitance Cint by the integrator 6C. .
  • the sampling at this time is performed by connecting the switch SW1 to the output Vout of the sense amplifier 2B and connecting the switch SW2 to the reference voltage Vr.
  • the output of the sense amplifier 2B in a state in which the drive lines DL1 to DL4 are driven by the second set of drive voltages is repeatedly sampled a plurality of times by the sampling capacitor Cs.
  • the switch SW2 is connected to the output Vout.
  • the output of the integrator 6C is expressed as follows, and the addition average of the output of the sense amplifier 2B when the first drive voltage is applied and the output of the sense amplifier 2B when the second drive voltage is applied The difference from the arithmetic mean is obtained.
  • FIG. 5 is a circuit diagram showing a configuration of a capacitance detection circuit 1D according to a third embodiment.
  • the same components as those described above are designated by the same reference numerals. Detailed descriptions of these components are omitted.
  • Capacitance detection circuit 1D has one end connected to drive lines DL1 to DL4 intersecting sense lines SLA and SLB, and the other ends connected to sense lines SLA and SLB, respectively. Obtain data to estimate C4B capacity value.
  • the electrostatic capacitance detection circuit 1D includes a drive circuit 8.
  • the drive circuit 8 applies voltages Vin1 to Vin4 to the drive lines DL1 to DL4.
  • Sense line parasitic capacitances CpA and CpB exist in the sense lines SLA and SLB, respectively.
  • Noise NZA ⁇ NZB is externally applied to the sense line parasitic capacitances CpA ⁇ CpB, respectively.
  • the electrostatic capacitance detection circuit 1D is provided with a sense amplifier 2D.
  • the sense amplifier 2D reads the difference between the charges accumulated in the capacitances C1A to C4A and the charges accumulated in the capacitances C1B to C4B by the application of the voltages Vin1 to Vin4 through the sense lines SLA and SLB.
  • the sense amplifier 2D has a differential operational amplifier 11D.
  • the noninverting input terminal of the differential operational amplifier 11D is connected to the sense line SLB, and the inverting input terminal is connected to the sense line SLA.
  • an integration capacitance CfB and a switch SWRB connected to the non-inversion input terminal of the differential operational amplifier 11D and one output of the differential operational amplifier 11D are provided in parallel with each other.
  • An integration capacitance CfA and a switch SWRA connected to the input terminal and the other output of the differential operational amplifier 11D are provided in parallel with each other.
  • the electrostatic capacitance detection circuit 1D includes an AD converter 3D. While the drive circuit 8 applies the voltages Vin1 to Vin4 to the drive lines DL1 to DL4, the AD converter 3D repeatedly samples the pair of outputs of the sense amplifier 2D a plurality of times, and converts the outputs into digital values for each sampling. Do.
  • the pseudo random number generation circuit 7 is connected to the AD converter 3D. The pseudo random number generation circuit 7 generates a random number within a predetermined range and supplies it to the AD converter 3D in order to control the sampling period of the AD converter 3D.
  • the electrostatic capacitance detection circuit 1D is provided with a digital arithmetic circuit 4D.
  • the digital arithmetic circuit 4D averages a plurality of digital values converted by the AD converter 3D.
  • FIG. 5 shows capacitance differences C1A-C1B, C2A of capacitance pairs (C1A, C1B), (C2A, C2B), (C3A, C3B), (C4A, C4B) connected to the sense line SLA and the sense line SLB.
  • the circuit example in the case of estimating -C2B, C3A-C3B, C4A-C4B is shown.
  • Vn (t) ⁇ Cp ⁇ Vn ′ (t) ⁇ Cp 'Is reduced to 1 / sqrt (n) to improve the signal to noise ratio. Also in this case, it is recommended to randomize the sampling time in order to reduce the amount of noise effectively by averaging.
  • FIG. 6 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit 1E according to the third embodiment.
  • the same components as those described above are designated by the same reference numerals. Detailed descriptions of these components are omitted.
  • the electrostatic capacitance detection circuit 1E includes a sampling capacitance circuit 5E and an integrator 6E instead of the AD converter 3D and the digital operation circuit 4D.
  • the sampling capacitance circuit 5E has sampling capacitances CsA and CsB.
  • One terminal of the sampling capacitor CsA is connected to a switch SW4 that switches the connection between the switch SW2 and the reference voltage Vc.
  • the switch SW2 connects the switch SW4 to one of the one output and the other output of the operational amplifier 11D.
  • the other terminal of the sampling capacitor CsA is connected to a switch SW6 that switches connection to either the reference voltage Vc or the integrator 6E.
  • One terminal of the sampling capacitor CsB is connected to a switch SW3 that switches the connection between the switch SW1 and the reference voltage Vc.
  • the switch SW1 connects the switch SW3 to one of the one output and the other output of the operational amplifier 11D.
  • the other terminal of the sampling capacitor CsB is connected to a switch SW5 that switches connection to either the reference voltage Vc or the integrator 6E.
  • the integrator 6E has an operational amplifier 11E.
  • the non-inverting input terminal of the operational amplifier 11E is connected to the switch SW5 of the sampling capacitance circuit 5E.
  • the inverting input terminal of the operational amplifier 11E is connected to the switch SW6 of the sampling capacitance circuit 5E.
  • the integration capacitance CintB and the switch SWR_intB connected to the non-inversion input terminal of the operational amplifier 11E and one output of the operational amplifier 11 and arranged in parallel with each other, the inverting input terminal of the operational amplifier 11E and the other of the operational amplifier 11 Integral capacitors CintA and switches SWR_intA which are connected to the output and arranged in parallel with each other are provided.
  • FIG. 6 shows an example of a circuit that performs an operation of obtaining an addition average without using the AD converter 3D.
  • the differential output of the sense amplifier 2D is repeatedly sampled a plurality of times by the sampling capacitance pair CsA ⁇ CsB, and integration is performed by the integrator 6E to obtain an averaged voltage as an output.
  • FIG. 7 is a circuit diagram showing a configuration of a capacitance detection circuit 1F according to a fourth embodiment.
  • the same components as those described above are designated by the same reference numerals. Detailed descriptions of these components are omitted.
  • the electrostatic capacitance detection circuit 1F includes an AD converter 3F and a digital arithmetic circuit 4F instead of the AD converter 3D and the digital arithmetic circuit 4D.
  • FIG. 7 shows capacitance differences C1A-C1B, C2A of capacitance pairs (C1A, C1B), (C2A, C2B), (C3A, C3B), (C4A, C4B) connected to the sense line SLA and the sense line SLB.
  • the circuit example in the case of estimating -C2B, C3A-C3B, and C4A-C4B is shown.
  • Vn (t2) _ave is the average of noise Vn (t) when sampling is repeated multiple times with the second drive voltage applied
  • Vn '(t2) _ave is the second drive voltage added. It represents the average of noises Vn '(t) when sampled a plurality of times in a state of.
  • Dout_2-Dout_1 - ⁇ (Vin12-Vin11) (C1A-C1B) + (Vin22-Vin21) ⁇ (C2A-C2B) + (Vin32-Vin31) (C3A-C3B) + (Vin42-Vin41) (C4A-C4B) ⁇ + (Vn (t2) _ave-Vn (t1) _ave) CpA-(Vn '(t2) _ave-Vn' (t1) _ave) CpB / CfA, It becomes. Therefore, it can be expected that noise is effectively reduced by correlated double sampling and averaging.
  • FIG. 8 is a circuit diagram showing a configuration of another electrostatic capacitance detection circuit 1G according to the fourth embodiment.
  • the electrostatic capacitance detection circuit 1G includes a sampling capacitance circuit 5G and an integrator 6G instead of the AD converter 3F and the digital operation circuit 4F.
  • FIG. 8 shows a circuit example in the case where arithmetic processing relating to averaging and correlation double sampling is performed by an analog circuit without using an AD converter.
  • the differential output of the sense amplifier 2D is repeatedly sampled a plurality of times by the sampling capacitance pair CsA ⁇ CsB, and integration is performed by the integrator 6G to obtain an averaged voltage as an output.
  • FIG. 9 is a block diagram showing the configuration of a mobile telephone 60 according to the fifth embodiment.
  • the mobile phone 60 includes a CPU 65, a RAM 73, a ROM 72, a camera 66, a microphone 67, a speaker 68, an operation key 69, a display panel 70, a display control circuit 71, and a touch panel system 61. .
  • Each component is connected to each other by a data bus.
  • the CPU 65 controls the operation of the mobile phone 70.
  • the CPU 65 executes, for example, a program stored in the ROM 72.
  • Operation key 69 receives an input of an instruction from the user of mobile phone 60.
  • the RAM 73 volatileally stores data generated by execution of a program by the CPU 65 or data input through the operation key 69.
  • the ROM 72 stores data in a non-volatile manner.
  • the ROM 72 is a ROM that can be written and erased, such as an erasable programmable read-only memory (EPROM) and a flash memory.
  • EPROM erasable programmable read-only memory
  • the mobile phone 60 may be configured to include an interface (IF) for connecting to another electronic device by wire.
  • IF interface
  • the camera 66 captures a subject in response to the user's operation of the operation key 69.
  • the image data of the photographed subject is stored in the RAM 73 or an external memory (for example, a memory card).
  • the microphone 67 receives an input of the user's voice.
  • the mobile phone 60 digitizes the input voice (analog data). Then, the mobile phone 60 sends the digitized voice to the communication partner (for example, another mobile phone).
  • the speaker 68 outputs a sound based on, for example, music data stored in the RAM 73.
  • the touch panel system 61 includes the touch panel 62, a capacitance detection circuit 1 that detects capacitance or a capacitance difference, and a touch position detection circuit 64.
  • the CPU 65 controls the operation of the touch panel system 61.
  • the CPU 65 executes, for example, a program stored in the ROM 72.
  • the RAM 73 stores data generated by the execution of the program by the CPU 65 in a volatile manner.
  • the ROM 72 stores data in a non-volatile manner.
  • the display panel 70 causes the display control circuit 71 to display the images stored in the ROM 72 and the RAM 73.
  • the display panel 70 is superimposed on the touch panel 62 or incorporates the touch panel 62.
  • the capacitance detection circuit estimates the capacitance value of one or more capacitances, one end of which is connected to one or more drive lines crossing the sense line and the other end of which is connected to the sense line.
  • a drive circuit for applying a predetermined voltage to the drive line, and the charge accumulated in the capacitance by the application of the voltage through the sense line A sense amplifier to be read out, an AD converter which samples the output of the sense amplifier a plurality of times while the drive circuit applies the voltage to the drive line, and converts it to a digital value for each sampling, and the AD conversion
  • a digital arithmetic circuit for averaging a plurality of digital values converted by the digital signal processor.
  • Another capacitance detection circuit is a capacitance value of one or more capacitances having one end connected to one or more drive lines crossing the sense line and the other end connected to the sense line.
  • a capacitance detection circuit for acquiring data for estimating the capacitance, the drive circuit applying a predetermined voltage to the drive line, the charge accumulated in the capacitance by the application of the voltage, the sense circuit
  • a sense amplifier for reading out through a line, a sampling capacitance circuit which samples the output of the sense amplifier a plurality of times while the drive circuit applies the voltage to the drive line, and the sense sampled by the sampling capacitance circuit
  • an analog operation circuit that averages a plurality of outputs of the amplifier.
  • a sense amplifier for reading out the charge accumulated in the electrostatic capacitance through the sense line by applying the second voltage after reading out the electric charge accumulated in the electrostatic capacitance through the sense line; and the drive circuit While applying the first voltage to the line, the output of the sense amplifier is sampled a plurality of times, converted to a first digital value for each sampling, and An AD converter that samples the output of the sense amplifier a plurality of times while the second voltage is applied, and converts the output into a second digital value for each sampling, and a plurality of second converters converted by the AD converter
  • a digital operation circuit for estimating the capacitance value of the capacitance by obtaining a difference between a first detection voltage obtained by averaging one digital value and a second detection voltage obtained by averaging the plurality of second digital values; It is characterized by having.
  • noise components mixed in via the sense line parasitic capacitance Cp at the moment of sampling the first detection voltage are averaged, and at the moment of sampling the second detection voltage via the sense line parasitic capacitance Cp. Since the mixed noise component is also averaged, the noise component included in the difference between the first detection voltage and the second detection voltage is reduced, and the signal-to-noise ratio can be improved.
  • the output of the sense amplifier is sampled a plurality of times while the drive circuit applies the first voltage to the drive line, and the drive circuit converts the output into a first digital value for each sampling, and then the drive circuit performs the sampling.
  • the output of the sense amplifier is sampled a plurality of times and converted into a second digital value every sampling, so that the drive terminal is a first drive voltage or a set of voltages, and
  • the processing time can be shorter than in the configuration in which driving with the drive voltage or the set of voltages is repeated a plurality of times.
  • a sense amplifier for reading out the charge accumulated in the electrostatic capacitance through the sense line by applying the second voltage after reading out the electric charge accumulated in the electrostatic capacitance through the sense line; and the drive circuit Generating a plurality of first sampling values obtained by sampling the output of the sense amplifier a plurality of times while applying the first voltage to the line;
  • a sampling capacitor circuit for generating a plurality of second sampling values obtained by sampling the output of the sense amplifier a plurality of times while applying the second voltage to the brine; and a plurality of first sampling circuits sampled by the sampling capacitor circuit
  • the capacitance value of the capacitance is estimated by calculating the difference between the first detection voltage obtained by averaging the sampling values and the second detection voltage obtained by averaging the plurality of second sampling values sampled by the sampling capacitance circuit. And an analog operation circuit.
  • noise components mixed in via the sense line parasitic capacitance Cp at the moment of sampling the first detection voltage are averaged, and at the moment of sampling the second detection voltage via the sense line parasitic capacitance Cp. Since the mixed noise component is also averaged, the noise component included in the difference between the first detection voltage and the second detection voltage is reduced, and the signal-to-noise ratio can be improved. Then, while the drive circuit applies the first voltage to the drive line, a plurality of first sampling values are generated by sampling the output of the sense amplifier a plurality of times, and the drive circuit generates the first drive voltage to the drive line.
  • the drive terminal includes a first driving voltage or a set of voltages, and a second driving voltage. Processing time can be shortened compared with the structure which repeats driving by the drive voltage or the group of voltage in multiple times. Further, since averaging is performed by the analog circuit without AD conversion, it is possible to eliminate the mixing of quantization noise.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • a drive circuit for applying a predetermined voltage to the drive line, and a difference between charges accumulated in the first and second capacitors by the application of the voltage.
  • a sense amplifier for reading out the first and second sense lines, and sampling a differential output of the sense amplifier multiple times while the drive circuit applies the voltage to the drive line;
  • the AD converter for converting the digital value, that a digital arithmetic circuit for averaging the converted plurality of digital values by the AD converter for each.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • a drive circuit for applying a predetermined voltage to the drive line, and a difference between charges accumulated in the first and second capacitors by the application of the voltage.
  • a sense amplifier for reading out the signal through the first and second sense lines, and a sensor for sampling a differential output of the sense amplifier a plurality of times while the drive circuit applies the voltage to the drive line.
  • pulling capacitor circuit characterized in that a plurality of differential outputs of the sense amplifiers sampled by the sampling capacitor circuit having an analog arithmetic circuit for averaging.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • the difference between the charges accumulated in the two capacitances is read out through the first and second sense lines, respectively, and then the difference between the charges accumulated in the first and second capacitances by the application of the second voltage is calculated.
  • Each of the first and second The differential output of the sense amplifier is sampled multiple times while the drive circuit applies the first voltage to the drive line, and the first digital value is converted every sampling After that, while the drive circuit is applying the second voltage, an AD converter which samples the differential output of the sense amplifier a plurality of times and converts it into a second digital value for each sampling, and the AD converter Calculating a difference between a first detection voltage obtained by averaging a plurality of first digital values converted by the second detection method and a second detection voltage obtained by averaging the plurality of second digital values. And a digital arithmetic circuit for estimating a capacitance difference of the second capacitance.
  • This feature averages noise components mixed via sense line parasitic capacitances CpA and CpB at the moment of sampling the first detection voltage, and sense line parasitic capacitance CpA and the moment of sampling the second detection voltage. Since the noise component mixed via CpB is also averaged, the noise component included in the difference between the first detection voltage and the second detection voltage is reduced, and the signal-to-noise ratio can be improved.
  • the differential output of the sense amplifier is sampled a plurality of times and converted into a first digital value for each sampling, and then the drive circuit While the second voltage is applied, the differential output of the sense amplifier is sampled a plurality of times and converted into a second digital value every sampling, so that the drive terminal is a first drive voltage pair or voltage pair.
  • the processing time can be shorter than in the configuration in which driving with the second set of driving voltage pairs or voltage pairs is repeated a plurality of times.
  • one or more first capacitance lines each having one end connected to one or more drive lines intersecting the first sense line and the other end connected to the first sense line
  • the difference between the charges accumulated in the two capacitances is read out through the first and second sense lines, respectively, and then the difference between the charges accumulated in the first and second capacitances by the application of the second voltage is calculated.
  • the A sampling capacitor circuit that samples the second differential output of the sense amplifier a plurality of times while applying a voltage, and averaging a plurality of first differential outputs of the sense amplifier sampled by the sampling capacitor circuit.
  • the first capacitance and the first capacitance may be calculated by determining a difference between the first detection voltage and a second detection voltage obtained by averaging a plurality of second differential outputs of the sense amplifier sampled by the sampling capacitance circuit. And (ii) an analog operation circuit for estimating a capacitance difference between the two capacitances.
  • the first differential output of the sense amplifier is sampled a plurality of times while the drive circuit applies the first voltage to the drive line, and then the drive circuit applies the second voltage.
  • the drive terminal is driven by the first drive voltage pair or the set of voltage pairs and the second drive voltage pair or the set of voltage pairs Processing time can be shortened compared with the structure which repeats several times. Further, since the averaging is performed without the A / D conversion, the mixing of quantization noise can be eliminated.
  • the AD converter preferably samples the output or the differential output of the sense amplifier at non-periodic sampling timing, and the sampling capacitance circuit is non-periodic It is preferable to sample the output or differential output of the sense amplifier according to sampling timing.
  • the sense amplifier is integrated, and has an input terminal connected to the sense line or the first sense line and the second sense line. .
  • An electronic device includes the capacitance detection circuit according to the present invention, and the sense line, the drive line, and the capacitance, or the first capacitance and the second capacitance.
  • the display device is characterized in that it comprises a touch panel, and further includes a display panel which is superimposed on the touch panel or which incorporates the touch panel.
  • the output of the sense amplifier is sampled a plurality of times and converted to a digital value for each sampling, so that the capacitance is reset to drive voltage. It is possible to obtain an electronic device in which the processing time for electrostatic capacitance detection is reduced as compared with the configuration in which the processing of repeating the processing of reading by the sense amplifier is given.
  • data is acquired to estimate the capacitance value of one or more capacitances, one end of which is connected to one or more drive lines crossing the sense line and the other end connected to the sense line.
  • the present invention can be used for a capacitance detection circuit and an electronic device provided with the same.
  • Capacitance detection circuit 2 Sense amplifier 3 AD converter 4 Digital operation circuit 5A Sampling capacity circuit 6A Integrator (analog operation circuit) 7 pseudo random number generation circuit 9 input terminal 10 operational amplifier 11 operational amplifier

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente invention concerne un circuit à capteur capacitif (1) permettant de réduire le temps de traitement requis pour la remise à zéro et la recharge des capacités et l'utilisation d'un amplificateur de détection (2) pour la lecture de la capacité. Le circuit est équipé : d'un amplificateur de détection (2) qui assure la lecture de la charge accumulée par les capacités (C1-C4) par l'application d'une tension ; un convertisseur analogique-numérique (3) qui effectue un échantillonnage d'une pluralité d'instants sur la sortie depuis l'amplificateur de détection (2) tandis qu'un circuit de commande (8) applique la tension, et convertit la sortie en valeurs numériques ; et un circuit arithmétique numérique (4) qui calcule la moyenne de la pluralité de valeurs numériques converties.
PCT/JP2012/077893 2011-10-27 2012-10-29 Circuit à capteur capacitif, et appareil électrique WO2013062128A1 (fr)

Applications Claiming Priority (2)

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JP2011236525A JP5290381B2 (ja) 2011-10-27 2011-10-27 静電容量検出回路及び電子機器
JP2011-236525 2011-10-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3026533A1 (fr) * 2014-11-21 2016-06-01 LG Display Co., Ltd. Système de détection tactile

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150042366A (ko) * 2013-10-10 2015-04-21 삼성전자주식회사 터치 스크린 센서 집적 회로, 이의 동작 방법, 및 이를 포함하는 시스템

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH09292950A (ja) * 1996-04-24 1997-11-11 Sharp Corp 座標入力装置
JP2009079972A (ja) * 2007-09-26 2009-04-16 Osaki Electric Co Ltd 電力測定方法および電力測定装置
JP2010039602A (ja) * 2008-08-01 2010-02-18 Sony Corp タッチパネルおよびその動作方法ならびに電子機器およびその動作方法
JP2011175452A (ja) * 2010-02-24 2011-09-08 Renesas Sp Drivers Inc タッチセンサ装置

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH09292950A (ja) * 1996-04-24 1997-11-11 Sharp Corp 座標入力装置
JP2009079972A (ja) * 2007-09-26 2009-04-16 Osaki Electric Co Ltd 電力測定方法および電力測定装置
JP2010039602A (ja) * 2008-08-01 2010-02-18 Sony Corp タッチパネルおよびその動作方法ならびに電子機器およびその動作方法
JP2011175452A (ja) * 2010-02-24 2011-09-08 Renesas Sp Drivers Inc タッチセンサ装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3026533A1 (fr) * 2014-11-21 2016-06-01 LG Display Co., Ltd. Système de détection tactile
CN105630261A (zh) * 2014-11-21 2016-06-01 乐金显示有限公司 积分器及使用积分器的触摸感测系统
US9524054B2 (en) 2014-11-21 2016-12-20 Lg Display Co., Ltd. Integrator and touch sensing system using the same

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JP5290381B2 (ja) 2013-09-18

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