WO2013051343A1 - Dispositif à semi-conducteurs en carbure de silicium et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs en carbure de silicium et son procédé de fabrication Download PDF

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Publication number
WO2013051343A1
WO2013051343A1 PCT/JP2012/070739 JP2012070739W WO2013051343A1 WO 2013051343 A1 WO2013051343 A1 WO 2013051343A1 JP 2012070739 W JP2012070739 W JP 2012070739W WO 2013051343 A1 WO2013051343 A1 WO 2013051343A1
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silicon carbide
layer
region
thickness direction
semiconductor device
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PCT/JP2012/070739
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English (en)
Japanese (ja)
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林　秀樹
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住友電気工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more specifically to a silicon carbide semiconductor device which is a lateral junction field effect transistor and a manufacturing method thereof.
  • RESURF-JFET Reduced SURface Field-Junction Field Effect Transistor: surface field relaxation junction field effect transistor
  • SiC silicon carbide
  • JFET Joint Field Effect Transistor
  • a current flows in a direction along the surface of the wafer. For this reason, it is difficult to ensure a large cross-sectional area of the current path, and the characteristic on-resistance increases.
  • the characteristic on-resistance is usually composed of a gate-source resistance, a gate-drain resistance, a channel resistance, a source ohmic resistance, and a drain ohmic resistance.
  • the characteristic on-resistance is usually composed of a gate-source resistance, a gate-drain resistance, a channel resistance, a source ohmic resistance, and a drain ohmic resistance.
  • about 75% of the characteristic on-resistance is the sum of the first three resistances (that is, the gate-source resistance, the gate-drain resistance, and the channel resistance) (hereinafter referred to as the resistance of the channel portion near the gate region) This is due to Therefore, in order to reduce the characteristic on-resistance, it is important to reduce the resistance of the channel portions near these gate regions.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to lower the characteristic on-resistance than before by reducing the resistance of the channel portion in the vicinity of the gate region.
  • An object is to provide a silicon carbide semiconductor device and a method of manufacturing the same.
  • a silicon carbide semiconductor device includes a substrate, a silicon carbide layer provided on the substrate and having a main surface and a thickness direction intersecting the main surface.
  • the silicon carbide layer includes a channel layer having the first conductivity type, a source region having the first conductivity type and extending from the main surface into the channel layer along the thickness direction, and the first conductivity type A drain region extending from the main surface along the thickness direction into the channel layer and sandwiching the channel layer between the source region in the opposite direction intersecting the thickness direction, and the first conductive layer A gate region having a second conductivity type different from the type and extending between the source region and the drain region so as to protrude from the main surface into the channel layer along the thickness direction.
  • the dimension along the facing direction of the gate region decreases as the distance from the main surface increases.
  • the dimension of the gate region decreases as the distance from the main surface increases. Therefore, the resistance of the channel portion in the vicinity of the gate region is reduced, so that the characteristic on-resistance can be lowered.
  • the first conductivity type is preferably n-type.
  • the conductivity type of the channel layer becomes n-type. Therefore, electrons having a higher mobility than holes can be used as main carriers flowing in the channel layer. Therefore, the characteristic on-resistance is further reduced.
  • the length of the gate region in the opposing direction passing through the main surface is A, and in the channel layer of the gate region in the thickness direction
  • the ratio B / A is less than 0.9, where B is the length of the gate region in the opposite direction passing through the middle position of the protruding portion.
  • the gate region has a V-shaped portion protruding into the channel layer in the thickness direction in a cross-sectional view including the thickness direction and the facing direction.
  • the gate region is constituted by at least a part of an epitaxial layer having the second conductivity type.
  • the gate region is formed by ion implantation
  • the impurity profile around the boundary between the gate region and the channel layer also varies due to variations in ion implantation. For this reason, the characteristic on-resistance and threshold voltage vary for each silicon carbide semiconductor device.
  • the gate region is formed of an epitaxial layer as described above, since it is not necessary to use ion implantation, variations in characteristic on-resistance and threshold voltage for each silicon carbide semiconductor device can be suppressed.
  • the epitaxial layer is connected between the source region and the drain region along the facing direction on the channel layer.
  • the RESURF structure is provided on the channel layer by the epitaxial layer, the breakdown voltage is higher than that in the case where there is no RESURF structure. Therefore, the impurity concentration of the channel layer can be made relatively high. Thereby, the characteristic on-resistance can be further reduced.
  • the method for manufacturing a silicon carbide semiconductor device includes a step of forming a silicon carbide layer having a main surface and a thickness direction intersecting the main surface on a substrate.
  • the step of forming the silicon carbide layer includes a step of forming a channel layer having the first conductivity type.
  • the manufacturing method further has a first conductivity type, has a source region extending from the main surface into the channel layer along the thickness direction, and has a first conductivity type and extends from the main surface in the thickness direction. Forming a drain region extending along the channel layer.
  • the step of forming the source region and the drain region is performed so that the source region and the drain region sandwich the channel layer in the opposing direction crossing the thickness direction.
  • the manufacturing method further includes a step of forming a recess extending so as to protrude from the main surface into the channel layer along the thickness direction between the position where the source region is formed and the position where the drain region is formed. Contains.
  • the step of forming the recess is performed such that the dimension along the facing direction of the recess becomes smaller as the distance from the main surface increases in a cross-sectional view including the thickness direction and the facing direction.
  • the manufacturing method further includes a step of providing a gate region having a second conductivity type different from the first conductivity type in the silicon carbide layer by epitaxial growth in the recess.
  • each of “the position where the source region is formed” and “the position where the drain region is formed” may be a position where the source region and the drain region are to be formed, or has already been formed. It may be the position of the source region and the drain region. In other words, the order of the step of forming the source region and the drain region and the step of forming the recess is not limited.
  • the method for manufacturing a silicon carbide semiconductor device it is possible to manufacture a silicon carbide semiconductor device in which the dimension of the gate region decreases with increasing distance from the main surface. Therefore, the resistance of the channel portion in the vicinity of the gate region is reduced, so that a silicon carbide semiconductor device with low characteristic on-resistance can be manufactured.
  • the first conductivity type is n-type.
  • the step of forming the recesses includes a thickness A and a length of the recesses in the opposing direction passing through the main surface in a cross-sectional view including the thickness direction and the opposing direction.
  • the ratio B / A is less than 0.9, where B is the length of the recess in the opposite direction passing through the intermediate position of the recess in the direction.
  • the resistance of the channel portion in the vicinity of the gate region is further reduced, so that a silicon carbide semiconductor device having a reduced total characteristic on-resistance can be manufactured.
  • the step of forming the recess includes a V-shaped portion in which the recess protrudes into the channel layer in the thickness direction in a cross-sectional view including the thickness direction and the opposing direction. To be done.
  • the step of forming the recess includes a step of forming a mask layer having an opening on the main surface of the silicon carbide layer, and a silicon carbide layer exposed at the opening.
  • a step of performing dry etching using a process gas containing chlorine gas is included.
  • the recessed part which has a shape as mentioned above can be formed.
  • the step of providing the gate region is performed by forming an epitaxial layer including the gate region.
  • the epitaxial layer is formed on the channel layer so as to connect between the source region and the drain region along the opposing direction.
  • the RESURF structure is provided on the channel layer by the epitaxial layer, the withstand voltage becomes higher than when no RESURF layer is provided. Therefore, the impurity concentration of the channel layer can be made relatively high. Thereby, the characteristic on-resistance can be further reduced.
  • the present invention since the resistance of the channel portion in the vicinity of the gate region is reduced by having the gate region whose width decreases as the distance from the main surface increases, a silicon carbide semiconductor device having a lower characteristic on-resistance than the conventional one can be obtained. Can do.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1.
  • FIG. 8 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device shown in FIG. 1. It is a cross-sectional schematic diagram which shows the modification of Embodiment 1 of the silicon carbide semiconductor device according to this invention.
  • FIG. 2 is a schematic diagram for explaining carrier flows in each of the silicon carbide semiconductor device shown in FIG. 1 and a conventional silicon carbide semiconductor device. It is a cross-sectional schematic diagram which shows Embodiment 2 of the silicon carbide semiconductor device according to this invention.
  • the silicon carbide semiconductor device in the present embodiment is n-type JFET 10.
  • JFET 10 mainly includes substrate 11 and silicon carbide layer 4.
  • Substrate 11 is made of silicon carbide and has an n-type (first conductivity type).
  • Silicon carbide layer 4 is provided on substrate 11 and has a main surface 13A and a thickness direction (vertical direction in the drawing) intersecting each of main surfaces 13A.
  • the silicon carbide layer 4 includes a p-type layer 2 which is an electric field relaxation layer formed on the substrate 11, a p-type layer 12 as a breakdown voltage holding layer formed on the p-type layer 2, and a p-type layer 12.
  • a channel layer 13 which is an n-type layer.
  • An epitaxial layer 3 is formed on the channel layer 13.
  • the epitaxial layer 3 has a gate region 16 and a p-type layer 14.
  • the p-type layers 2, 12 and 14 are p-type (second conductivity type).
  • the thicknesses of the p-type layer 2, the p-type layer 12, the channel layer 13, and the p-type layer 14 are, for example, 0.5 ⁇ m, 10 ⁇ m, 0.3 ⁇ m, and 0.4 ⁇ m, respectively.
  • the impurity concentrations of the p-type layer 2, the p-type layer 12, the channel layer 13 and the p-type layer 14 are, for example, 5 ⁇ 10 16 , 1 ⁇ 10 16 , 2 ⁇ 10 17 and 2 ⁇ 10 17 atoms / cm, respectively. 3 .
  • the silicon carbide layer 4 further has a source region 15 and a drain region 17.
  • Each of source region 15 and drain region 17 extends from main surface 13A into channel layer 13 along the thickness direction.
  • a part of the channel layer 13 is sandwiched between the source region 15 and the drain region 17 in the opposite direction (lateral direction in the figure) intersecting the thickness direction.
  • Silicon carbide layer 4 further has a gate region 16 extending from main surface 13A into channel layer 13 along the thickness direction between source region 15 and drain region 17.
  • the dimension of the gate region 16 along the horizontal direction in the drawing decreases with increasing distance from the main surface 13A. In other words, the width of the gate region 16 becomes smaller toward the substrate 11.
  • the gate region 16 has a V-shaped portion protruding into the channel layer 13 in the thickness direction.
  • the shape of the gate region 16 may be an inverted trapezoid.
  • the inverted trapezoid means that the width of the gate region 16 decreases from the main surface 13A of the channel layer 13 toward the substrate 11 and has a finite width on the side of the gate region 16 closest to the substrate 11. is there. Further, the shape of the gate region 16 on the substrate 11 side may be rounded.
  • the length of the gate region in the opposing direction passing through the main surface 13A is A, and in the channel layer 13 of the gate region 16 in the thickness direction. It is preferable that the ratio B / A is less than 0.9, where B is the length of the gate region 16 in the facing direction passing through the intermediate position (position divided into two equal parts) of the portion extending so as to protrude into the area. More preferably, the ratio B / A is 0.5 or more and less than 0.9.
  • the gate region 16 is constituted by a part of the epitaxial layer 3 having p-type (second conductivity type).
  • the gate region 16 and the p-type layer 14 are composed of the same epitaxial layer 3.
  • the epitaxial layer 3 connects the source region 15 and the drain region 17 on the channel layer 13 along the horizontal direction in the drawing.
  • the p-type layer 12 may be formed directly on the surface 11A of the n-type substrate 11.
  • a source region 15 and a drain region 17 containing an impurity (n-type impurity) whose conductivity type is higher than that of the channel layer 13 are formed.
  • a gate region 16 containing an impurity (p-type impurity) having a higher conductivity type than the p-type layers 12 and 14 is formed so as to be sandwiched between the drain region 17 and the drain region 17. That is, the source region 15, the gate region 16, and the drain region 17 are formed so as to penetrate the p-type layer 14 and reach the channel layer 13.
  • the bottoms of the source region 15, the gate region 16, and the drain region 17 are spaced apart from the upper surface of the p-type layer 12 (the boundary between the p-type layer 12 and the channel layer 13) inside the channel layer 13. Has been placed.
  • the channel layer 13 penetrates the p-type layer 14 from the upper surface of the p-type layer 14 (the main surface opposite to the channel layer 13 side).
  • the groove portion 31 is formed so as to reach the point. That is, the bottom wall of the groove portion 31 is located inside the channel layer 13 with a distance from the interface between the p-type layer 12 and the channel layer 13. Furthermore, a potential holding region 23 containing p-type impurities at a higher concentration than p-type layer 12 and p-type layer 14 is formed so as to penetrate channel layer 13 from the bottom wall of trench 31 and reach p-type layer 12. ing.
  • the bottom of the potential holding region 23 is spaced apart from the upper surface of the n-type substrate 11 (the boundary between the n-type substrate 11 and the p-type layer 2) (more specifically, the p-type layer 2 and the p-type layer).
  • the p-type layer 12 is disposed at a distance from the boundary with the layer 12.
  • contact electrodes 19 are formed so as to be in contact with the upper surfaces of the source region 15, the gate region 16, the drain region 17, and the potential holding region 23.
  • the contact electrode 19 is made of a material that can make ohmic contact with the source region 15, the gate region 16, the drain region 17, and the potential holding region 23, for example, NiSi (nickel silicide).
  • An oxide film 18 is formed between adjacent contact electrodes 19. More specifically, the oxide film 18 as an insulating layer is formed so as to cover the entire region other than the region where the contact electrode 19 is formed on the upper surface of the p-type layer 14 and the bottom wall and side wall of the groove 31. Has been. As a result, the adjacent contact electrodes 19 are insulated from each other.
  • a source electrode 25, a gate electrode 26, and a drain electrode 27 are formed so as to be in contact with the upper surfaces of the contact electrodes 19 on the source region 15, the gate region 16, and the drain region 17, respectively.
  • the source electrode 25, the gate electrode 26 and the drain electrode 27 are electrically connected to the source region 15, the gate region 16 and the drain region 17 through the contact electrode 19, respectively.
  • the source electrode 25 is also in contact with the upper surface of the contact electrode 19 on the potential holding region 23 and is also electrically connected to the potential holding region 23 through the contact electrode 19. That is, the source electrode 25 is formed to extend from the upper surface of the contact electrode 19 on the source region 15 to the upper surface of the contact electrode 19 on the potential holding region 23.
  • the contact electrode 19 on the potential holding region 23 is held at the same potential as the contact electrode 19 on the source region 15.
  • the source electrode 25, the gate electrode 26, and the drain electrode 27 are made of a conductor such as aluminum (Al).
  • an insulating protective film 28 made of an insulator is formed so as to cover the oxide film 18 and the gate electrode 26 and to fill a region between the source electrode 25 and the drain electrode 27. ing.
  • openings 33 and 34 are formed in a region on the source region 15 and the potential holding region 23 and a region on the drain region 17, respectively.
  • the source electrode 25 and the drain electrode 27 are disposed inside the openings 33 and 34.
  • the upper surfaces of the source electrode 25 and the drain electrode 27 are located above the upper surface of the insulating protective film 28 (that is, the upper portions of the source electrode 25 and the drain electrode 27 protrude from the upper surface of the insulating protective film 28, respectively. ing).
  • the JFET 10 in this embodiment is a RESURF type JFET in which a p-type layer 14 (Resurf layer) is formed so as to be in contact with the channel layer 13. Therefore, in the off state, the depletion layer extends in the vertical direction (thickness direction) from the interface between the channel layer 13 and the p-type layer 14. As a result, the electric field distribution in the drift region becomes uniform, the electric field concentration near the gate region 16 is relaxed, and the breakdown voltage is improved.
  • JFET 10 which is the silicon carbide semiconductor device in the first embodiment will be described.
  • a substrate preparation step is performed as a step (S10).
  • an n-type substrate 11 is used.
  • silicon carbide layer 4 is formed as a step (S20). Specifically, on one surface of n-type substrate 11, p-type layer 2, p-type layer 12, and channel layer 13 made of SiC, for example, are formed sequentially by vapor phase epitaxial growth.
  • vapor phase epitaxial growth for example, silane (SiH 4 ) gas and propane (C 3 H 8 ) gas can be used as a material gas, and hydrogen (H 2 ) gas can be used as a carrier gas.
  • a p-type impurity source for forming a p-type layer for example, diborane (B 2 H 6 ) or trimethylaluminum (TMA) is used, and as an n-type impurity for forming an n-type layer, for example, nitrogen ( N 2 ) can be employed.
  • B 2 H 6 diborane
  • TMA trimethylaluminum
  • N 2 nitrogen
  • a recessed part formation process is implemented as process (S30).
  • process (S30) referring to FIG. 4, first, mask 5 having an opening is formed on main surface 13A of channel layer 13 at a position where gate region 16 (FIG. 1) is to be formed.
  • the mask 5 for example, an SiO 2 film can be adopted.
  • recess 16 ⁇ / b> C is formed in channel layer 13 by dry etching using mask 5. Dry etching can be performed using, for example, chlorine gas or a mixed gas of chlorine gas and oxygen gas.
  • Recess 16C is formed to extend from main surface 13A into channel layer 13 along the thickness direction. The recess 16C is formed between the position where the source region 15 (FIG. 1) is formed and the position where the drain region 17 (FIG. 1) is formed.
  • the dimension along the horizontal direction in the drawing of the recess 16C is performed so as to decrease as the distance from the main surface 13A increases.
  • the shape of the recess 16C is V-shaped in the present embodiment.
  • the mask 5 is removed (FIG. 6).
  • an inverted trapezoidal recess 16C is formed instead of the V-shaped recess 16C.
  • the length of the recess 16C in the lateral direction in the figure passing through the main surface 13A is A
  • the length of the recess 16C in the lateral direction in the figure passing through the intermediate position of the recess 16C in the thickness direction is B
  • the ratio B / A is preferably less than 0.9. More preferably, the ratio B / A is 0.5 or more and less than 0.9.
  • an epitaxial layer forming step is performed as a step (S40).
  • p type epitaxial layer 3 is formed with reference to FIG.
  • the p-type epitaxial layer 3 grows so as to cover the inner surface of the recess 16 ⁇ / b> C and the main surface 13 ⁇ / b> A of the channel layer 13.
  • gate region 16 embedded in recess 16C and p-type layer 14 covering main surface 13A are formed.
  • the upper surface 14A of the epitaxial layer 3 may have a recess at a position corresponding to the recess 16C.
  • a groove part formation process is implemented as process (S50). Specifically, as shown in FIG. 8, the groove 31 is formed so as to penetrate from the upper surface 14 ⁇ / b> A of the p-type layer 14 to the channel layer 13 through the p-type layer 14. Formation of the groove 31 can be performed, for example, by forming a mask layer having an opening at a position where the desired groove 31 is formed on the upper surface of the p-type layer 14 and then performing dry etching using, for example, SF 6 gas.
  • a first ion implantation step is performed.
  • a potential holding region that is a region containing a high concentration p-type impurity is formed.
  • a resist is applied on the upper surface of p-type layer 14 and the inner wall of groove portion 31, and then exposure and development are carried out to maintain desired gate region 16 and potential holding.
  • a resist film (not shown) having an opening in a region corresponding to the planar shape of region 23 is formed.
  • p-type impurities such as Al (aluminum) and B (boron) are introduced into the channel layer 13 and the p-type layer 12 by ion implantation. Thereby, the potential holding region 23 is formed.
  • a second ion implantation step is performed.
  • a source region 15 and a drain region 17 that are regions containing high-concentration n-type impurities are formed.
  • a resist film (not shown) having openings in regions corresponding to the planar shape of desired source region 15 and drain region 17 in the same procedure as in step (S60). ) Is formed.
  • n-type impurities such as P (phosphorus) and N (nitrogen) are introduced into the p-type layer 14 and the channel layer 13 by ion implantation. Thereby, the source region 15 and the drain region 17 are formed.
  • the source region 15 and the drain region 17 are formed in contact with the epitaxial layer 3.
  • the epitaxial layer 3 is formed on the channel layer 13 so as to connect between the source region 15 and the drain region 17 along the horizontal direction in the drawing.
  • an activation annealing step is performed as a step (S80).
  • the p-type layer 14, the channel layer 13 and the p-type layer 12 on which ion implantation is performed in the step (S60) and the step (S70) are performed.
  • activation annealing which is a heat treatment for activating the impurities introduced by the ion implantation, is performed.
  • the activation annealing can be performed, for example, by performing a heat treatment that is held at a temperature of about 1700 ° C. for about 30 minutes in an argon gas atmosphere.
  • an oxide film forming step is performed.
  • steps (S10) to (S80) are performed, and p-type layer 14, channel layer 13, p-type layer 12 and p-type including a desired ion implantation layer are implemented.
  • the n-type substrate 11 on which the mold layer 2 is formed is thermally oxidized.
  • an oxide film 18 made of silicon dioxide (SiO 2 ) is formed so as to cover the upper surface 14A of the p-type layer 14 and the inner wall of the groove 31.
  • a contact electrode forming step is performed as a step (S100).
  • contact electrode 19 made of, for example, NiSi is formed so as to be in contact with the upper surfaces of source region 15, gate region 16, drain region 17, and potential holding region 23.
  • a resist film (not shown) having an opening in a region corresponding to the planar shape of the desired contact electrode 19 is formed by the same procedure as in the step (S60).
  • oxide film 18 on source region 15, gate region 16, drain region 17, and potential holding region 23 is removed by, for example, RIE (Reactive Ion Etching). .
  • Ni nickel
  • the nickel layer on the resist film is removed (lifted off), and the nickel is formed on the source region 15, the gate region 16, the drain region 17 and the potential holding region 23 exposed from the oxide film 18.
  • the layer remains.
  • the nickel layer is silicided by performing a heat treatment to be heated to a predetermined temperature (for example, 950 ° C.) in a temperature range of, for example, 900 ° to 1000 ° C.
  • a contact electrode 19 which is an ohmic electrode made of NiSi capable of making ohmic contact with the source region 15, the gate region 16, the drain region 17, and the potential holding region 23 is formed.
  • an electrode formation process is implemented as a process (S110).
  • this step first, referring to FIG. 13, gate electrode 26 that contacts the upper surface of contact electrode 19 on gate region 16 is formed. For example, after forming a resist film (not shown) having an opening in a desired region where the gate electrode 26 is to be formed and depositing Al, Al on the resist film is removed together with the resist film (lift-off).
  • an insulating protective film 28 made of an insulator such as SiO 2 is formed so as to cover gate electrode 26, contact electrode 19 and oxide film 18. Specifically, for example, by CVD (Chemical Vapor Deposition), contact electrode 19 disposed on gate electrode 26, source region 15, drain region 17, and potential holding region 23, and oxide film, respectively.
  • An insulating protective film 28 (see FIG. 14) made of a SiO 2 film covering 18 is formed.
  • source electrode 25 that contacts the upper surface of contact electrode 19 on source region 15 and potential holding region 23, and drain that contacts the upper surface of contact electrode 19 on drain region 17. Electrode 27 is formed.
  • openings 33 and 34 are formed in the insulating protective film 28 in regions located on the source region 15, the drain region 17, and the potential holding region 23 by using a photolithography method.
  • a method of forming the openings 33 and 34 for example, a resist film (not shown) having an opening similar to the planar shape of the openings 33 and 34 is formed on the main surface of the insulating protective film 28, and this resist film As a mask, a part of the insulating protective film 28 is removed by etching or the like. In this way, the openings 33 and 34 are formed in the insulating protective film 28 as shown in FIG.
  • the resist film (not shown) is removed by any conventionally known method.
  • the source electrode 25 and the drain electrode 27 are formed.
  • a resist film (not shown) having openings in desired regions (regions where the openings 33 and 34 are formed) where the source electrode 25 and the drain electrode 27 are to be formed, and depositing Al, Al on the resist film is removed together with the resist film (lift-off).
  • the resist film used for forming the source electrode 25 and the drain electrode 27 may be used as the resist film used for forming the source electrode 25 and the drain electrode 27, the resist film used for forming the openings 33 and 34 may be used. That is, after forming the openings 33 and 34 by etching using the resist film as a mask as described above, the conductor film constituting the electrode such as Al is formed as described above without removing the resist film. Then, the source electrode 25 and the drain electrode 27 may be formed inside the openings 33 and 34 by lift-off.
  • the JFET 10 in the present embodiment is completed through the above steps. Next, the effect of this Embodiment is demonstrated.
  • the gate region 16 has a tapered shape in which the dimension in the facing direction (lateral direction in the drawing) becomes smaller as the distance from the main surface 13A increases. Therefore, the total characteristic on-resistance is reduced by reducing the resistance of the channel portion in the vicinity of the gate region 16.
  • the reason why the characteristic on-resistance of the JFET 10 of the present embodiment is smaller than that of the conventional JFET will be schematically described with reference to FIG. If the cross-sectional shape of the gate region 16 is a rectangle as indicated by a broken line, the carrier path is limited to the portion indicated by the arrow b. On the other hand, in the case of the JFET 10 of the present embodiment, the gate region 16 has the tapered shape as described above, so that the carrier can flow in the portion indicated by the arrow a in addition to the arrow b. Therefore, the JFET 10 of the present embodiment can reduce the characteristic on-resistance.
  • the channel layer 13 has an n-type. Therefore, electrons having a higher mobility than holes can be used as main carriers flowing in the channel layer 13. Therefore, the characteristic on-resistance is further reduced.
  • the gate region 16 has a V-shaped portion (FIG. 1)
  • the resistance of the channel portion near the gate region 16 is further reduced as compared with the case where the gate region 16 has an inverted trapezoidal shape (FIG. 15). Therefore, the total characteristic on-resistance is further reduced.
  • the gate region 16 is constituted by the epitaxial layer 3. If the gate region 16 is formed by ion implantation, the impurity profile around the boundary between the gate region 16 and the channel layer also varies due to variations in ion implantation. For this reason, the characteristic on-resistance and the threshold voltage for each JFET 10 vary. On the other hand, when the gate region 16 is formed of an epitaxial layer as in the present embodiment, it is not necessary to use ion implantation, so that variations in the characteristic on-resistance and threshold voltage for each JFET 10 can be suppressed.
  • the gate region 16 when the gate region 16 is manufactured by ion implantation, it is difficult to manufacture the deep gate region 16 because it is necessary to increase the acceleration energy of ions.
  • the gate region 16 since the gate region 16 is formed not by ion implantation but by the epitaxial layer 3, the deep gate region 16 can be easily formed. Specifically, the deep gate region 16 can be easily formed by forming the recess 16C (FIG. 6) deeply.
  • the epitaxial layer 3 connects the source region 15 and the drain region 17 on the channel layer 13. Therefore, since the RESURF structure is provided on the channel layer 13, the breakdown voltage is higher than when no RESURF structure is provided. Therefore, the impurity concentration of the channel layer 13 can be made relatively high. Thereby, the characteristic on-resistance can be further reduced.
  • JFET 20 Referring to FIG. 17, JFET 20 according to the second embodiment of the present invention has approximately the same structure as JFET 10 (FIG. 1), but p-type layer 14 (FIG. 1) is not formed on channel layer 13. The point is different from JFET10. That is, in JFET 20, source region 15, gate region 16, and drain region 17 are formed in channel layer 13, and oxide film 18 is formed on the upper surface of channel layer 13 (and the inner wall of trench 31). Yes.
  • the manufacturing method of JFET 20 is basically the same as the manufacturing method shown in FIGS. 2 to 14 (Embodiment 1). However, after the step of FIG. 7, the epitaxial layer on channel layer 13 is polished by, for example, polishing or etchback. Layer 3 is removed. Eventually, the epitaxial layer 3 remains only in the recess 16C. That is, the p-type layer 14 is not provided on the main surface 13A of the channel layer 13. Except for this point, it is almost the same as the manufacturing method of the JFET 10 shown in the first embodiment.
  • n-type and the p-type in the above-described embodiment are interchanged may be used.
  • a p-type JFET is configured instead of the n-type JFET.

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Abstract

L'invention concerne un dispositif à semi-conducteurs (10) en carbure de silicium, lequel comporte un substrat (11) ainsi qu'une couche de carbure de silicium (4) située sur le substrat (11) et possédant une surface principale (13A) et une direction d'épaisseur croisant cette surface principale (13A). La couche de carbure de silicium (4) contient une couche canal (13), une région source (15), une région drain (17), ainsi qu'une région grille (16), située entre la région source (15) et la région drain (17) et s'étendant en suivant la direction de l'épaisseur à partir de la surface principale (13A) dans la couche canal (13) de manière à faire saillie. La dimension de la région grille (16) s'amenuise au fur et à mesure qu'elle s'éloigne de la surface principale (13A) en suivant une direction opposée. Ainsi, la résistance de la partie canal voisine de la région grille (16) est réduite et on obtient un dispositif à semi-conducteurs (10) en carbure de silicium dans lequel la résistance à l'état passant spécifique est réduite par rapport à l'art antérieur.
PCT/JP2012/070739 2011-10-03 2012-08-15 Dispositif à semi-conducteurs en carbure de silicium et son procédé de fabrication WO2013051343A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102267A (ja) * 1986-10-20 1988-05-07 Fujitsu Ltd 接合型電界効果トランジスタの製造方法
JPH0478142A (ja) * 1990-07-20 1992-03-12 Nissan Motor Co Ltd 接合型電界効果トランジスタ
WO2010071084A1 (fr) * 2008-12-16 2010-06-24 住友電気工業株式会社 Dispositif semiconducteur et son procédé de fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102267A (ja) * 1986-10-20 1988-05-07 Fujitsu Ltd 接合型電界効果トランジスタの製造方法
JPH0478142A (ja) * 1990-07-20 1992-03-12 Nissan Motor Co Ltd 接合型電界効果トランジスタ
WO2010071084A1 (fr) * 2008-12-16 2010-06-24 住友電気工業株式会社 Dispositif semiconducteur et son procédé de fabrication

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