WO2013027471A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2013027471A1
WO2013027471A1 PCT/JP2012/064933 JP2012064933W WO2013027471A1 WO 2013027471 A1 WO2013027471 A1 WO 2013027471A1 JP 2012064933 W JP2012064933 W JP 2012064933W WO 2013027471 A1 WO2013027471 A1 WO 2013027471A1
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Prior art keywords
insulating film
film
type
region
drift layer
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PCT/JP2012/064933
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French (fr)
Japanese (ja)
Inventor
泰之 沖野
泰洋 嶋本
浩孝 濱村
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株式会社日立製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device formed on a substrate containing silicon carbide.
  • SiC silicon carbide
  • SiC has a dielectric breakdown electric field about 10 times larger than that of Si, so that the drift layer that maintains the withstand voltage can be made thin and highly concentrated, and the conduction loss can be reduced. For this reason, it is expected to be applied to next-generation power devices with high breakdown voltage and low loss.
  • the structure of the termination region such as junction termination extension (JTE) or field limiting ring (FLR) is used to alleviate the electric field concentration at the device end in the blocking state.
  • JTE junction termination extension
  • FLR field limiting ring
  • the blocking state here refers to a state where a high potential difference is generated between the electrodes of the power device and no current flows between the electrodes.
  • Patent Document 1 Japanese Patent Laid-Open No. 11-330496
  • a passivation film is formed of a silicon oxide film (SiO 2 film) and a high dielectric film (high-k film), and thus the passivation film is applied. It is described that the voltage is shared between the silicon oxide film and the high-k film to prevent the passivation film from being broken.
  • Patent Document 2 Japanese Patent Laid-Open No. 2002-524860
  • a voltage applied to the passivation film is formed by forming the passivation film with three layers of a silicon oxide film, a high-k film, and a silicon oxide film. Is divided by a silicon oxide film and a high-k film to prevent leakage current from flowing through the passivation film.
  • FIGS. 14 and 15 are plan views of the surface electrode of the diode and the passivation film
  • FIG. 15 is a cross-sectional view taken along line AA of FIG.
  • the n ⁇ type drift layer 2 on the n + type substrate 1 see FIG. 15
  • the p type guard ring region 3 the p type JTE region 4 and the n + formed on the upper surface of the n ⁇ type drift layer 2.
  • Only the mold field stop region 5 is shown, and a passivation film, a surface electrode, a resin film, and the like formed thereon are not shown.
  • FIG. 14 is a plan view of the surface electrode of the diode and the passivation film
  • FIG. 15 is a cross-sectional view taken along line AA of FIG.
  • the n ⁇ type drift layer 2 on the n + type substrate 1 see FIG. 15
  • the p type guard ring region 3 the p type JTE region 4
  • FIG. 15 shows only a termination region which is an end portion of the semiconductor chip in FIG. 14, and illustration of an active region in the central portion of the semiconductor chip and a diode formed in the active region is omitted.
  • FIG. 14 is a plan view, but is partially hatched to make the drawing easy to see.
  • a p-type guard ring region 3, a p-type JTE region 4 and an n + -type field stop region 5 are formed on the upper surface of the n ⁇ -type drift layer 2 formed on the n + -type substrate 1.
  • the back electrode 7 is formed on the back surface of the n + type substrate 1, and the surface electrode 8, the passivation film 11, and the floating electrode are in contact with the top surface of the n ⁇ type drift layer 2 on the n ⁇ type drift layer 2.
  • 9 is formed.
  • a floating electrode 9 is electrically connected on the n + -type field stop region 5, and a part of each of the surface electrode 8 and the floating electrode 9 is formed on the passivation film 11. As shown in FIG.
  • p-type guard ring region 3, p-type JTE region 4 and n + -type field stop region 5, n - n so as to surround the active region of the type drift layer 2 top - -type drift layer 2 top are formed in order from the center to the end.
  • a high breakdown voltage diode is formed in the active region surrounded by the p-type guard ring region 3, the illustration thereof is omitted here, and only the n ⁇ -type drift layer 2 is shown in the active region.
  • a p-type semiconductor layer or the like is formed on the upper surface of the n ⁇ -type drift layer 2 in the active region.
  • the front electrode 8 to which a voltage of 0 V is applied from the back electrode 7 to which a voltage of several kV is applied for example.
  • Electric lines of force extend toward. At this time, electric lines of force tend to concentrate on the edge portion of the surface electrode 8, but the presence of the p-type guard ring region 3 and the p-type JTE region 4 spreads the electric lines of force in the lateral direction.
  • the electric field concentration at the edge portion of 8 can be relaxed. Even in an FLR having a plurality of p-type regions for relaxing the electric field, the electric field lines can be similarly expanded in the lateral direction, so that the electric field concentration can be reduced. This makes it possible to increase the breakdown voltage of the power device.
  • the passivation film typically has a thickness of several hundreds of nanometers to several ⁇ m in order to prevent it from being broken by a high electric field, and the voltage applied to the passivation film is shared between the silicon oxide film and the high-k film. In this case, the high-k film naturally needs to have a corresponding film thickness.
  • the insulating film is composed of a silicon oxide film and a high-k film, if the high-k film is thick, the reliability of the insulating film (stabilization of the charge amount of the insulating film due to the application of electrical stress) It became clear that there was a problem that the
  • the breakdown voltage of the power device that is, the anode-cathode breakdown voltage of the diode or the source-drain breakdown voltage of the transistor fluctuates, which is a problem from the viewpoint of reliability.
  • An object of the present invention is to provide a semiconductor device having high reliability.
  • a semiconductor device includes a semiconductor substrate including silicon carbide having a first conductivity type, A drift layer formed on the semiconductor substrate, having the first conductivity type, having a lower impurity concentration than the semiconductor substrate and containing silicon carbide; A semiconductor region having a second conductivity type different from the first conductivity type formed on an upper surface in the drift layer; A passivation film formed on the drift layer; An electrode formed on the drift layer; A back electrode formed in contact with the back surface of the drift layer; Including The passivation film is A first insulating film formed in contact with the upper surface of the drift layer; A metal insulating film formed on the first insulating film; A second insulating film formed on the metal insulating film; Have The metal insulating film has a thickness in the range of 0.3 nm to 10 nm.
  • the reliability of the semiconductor device can be improved.
  • FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG.
  • FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6;
  • FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;
  • FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;
  • FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;
  • It is sectional drawing which shows the semiconductor device which is Embodiment 2 of this invention.
  • It is sectional drawing which shows the semiconductor device which is Embodiment 3 of this invention.
  • It is a top view of the semiconductor device shown as an example of a power device. It is sectional drawing in the AA of FIG.
  • FIG. 1 shows a cross-sectional view of the semiconductor device of this embodiment.
  • the semiconductor device of the present embodiment has a power device (not shown) such as a high breakdown voltage transistor formed on a semiconductor substrate made of silicon carbide (SiC).
  • a power device such as a high breakdown voltage transistor formed on a semiconductor substrate made of silicon carbide (SiC).
  • FIG. The cross section of the area
  • SiC has a higher dielectric breakdown electric field and higher breakdown voltage than Si (silicon). Since the breakdown voltage of the device is greatly affected by the thickness of the drift layer, the drift layer can be made thin and highly concentrated while securing the breakdown voltage of the device by using SiC for the substrate and the drift layer.
  • a p-type guard ring region 3, a p-type JTE region 4, and an n + -type field stop are formed on the upper surface of an n ⁇ -type drift layer 2 formed on an n + -type substrate 1 by an epitaxial growth method or the like.
  • Region 5 is formed.
  • the p-type guard ring region 3, the p-type JTE region 4 and the n + -type field stop region 5 surround the active region in the central portion of the semiconductor chip from the central portion (left side in FIG. 1) to the end portion of the semiconductor chip. They are arranged in order toward the right side of FIG.
  • the p-type guard ring region 3 is formed so as to surround the active region on the upper surface of the n ⁇ -type drift layer 2, and the p-type JTE region so as to surround the p-type guard ring region 3. 4 are formed, and n + -type field stop regions 5 are formed in an annular shape so as to surround the p-type JTE region 4.
  • p-type guard ring region 3 and the p-type JTE region 4 is in contact
  • p-type JTE region 4 and n + -type field stop region 5 is not in contact, no impurity is introduced between n - A type drift layer 2 is present.
  • the p-type guard ring region 3 and the p-type JTE region 4 are semiconductor regions formed by introducing p-type impurities (for example, Al (aluminum)) into the upper surface of the n ⁇ -type drift layer 2 made of SiC.
  • p-type impurities for example, Al (aluminum)
  • the p-type guard ring region 3 has a higher p-type impurity concentration than the p-type JTE region 4, but which of the impurity concentrations of the p-type guard ring region 3 and the p-type JTE region 4 is different. It may be high or may have the same impurity concentration.
  • the p-type guard ring region 3 and the p-type JTE region 4 have the same junction depth, and the n + -type field stop region 5 has a shallower junction depth than the p-type JTE region 4.
  • the junction depth of each semiconductor region is not limited to this.
  • the n + type field stop region 5 is a semiconductor region for preventing the electric field applied to the device from reaching the end portion of the semiconductor chip.
  • a back surface electrode 7 is formed on the back surface of the n + type substrate 1, and a surface electrode 8, a passivation film 6 and a floating electrode 9 are in contact with the top surface of the n ⁇ type drift layer 2 on the n ⁇ type drift layer 2. Is formed.
  • the back electrode 7, the front electrode 8, and the floating electrode 9 are made of, for example, Al (aluminum), and the passivation film 6 is a first silicon oxide film 6 a that is laminated in order from the upper surface of the n ⁇ -type drift layer 2.
  • the metal insulating film 6b and the second silicon oxide film 6c are used.
  • the bottom surface of the first silicon oxide film 6a is in contact with the n ⁇ type drift layer 2 made of SiC, and the film thickness of the metal insulating film 6b is not less than 0.3 nm and not more than 10 nm.
  • the film thickness of the metal insulating film 6b is assumed to be 1 nm, for example.
  • a film made of a metal compound having an insulating property is called a metal insulating film.
  • the metal insulating film 6b is an insulating film made of, for example, aluminum oxide (for example, alumina (Al 2 O 3 )).
  • a film containing an aluminum oxide containing oxygen (O) and aluminum (Al) is referred to as an aluminum oxide film.
  • the metal insulating film 6b is formed of titanium oxide.
  • the lower surface and the upper surface of the metal insulating film 6b are used here as the first silicon oxide film 6a and the second oxide film. It is covered with a silicon film 6c.
  • a floating electrode 9 is electrically connected to the upper surface of the n + -type field stop region 5, and the surface electrode 8 is a high voltage MOSFET (Metal Oxide Semiconductor Field) formed on the upper surface of the n ⁇ -type drift layer 2 in the active region. It is electrically connected to the source electrode (not shown) of Effect Transistor. A part of each of the surface electrode 8 and the floating electrode 9 is formed so as to run on the end portion of the passivation film 6.
  • the floating electrode 9 is an electrode for fixing the potential of the n + type field stop region 5.
  • the passivation film 6 is arranged so as to cover the upper surface of the end portion of the p-type guard ring region 3, the upper surface of the p-type JTE region 4, and the upper surface of the end portion of the n + -type field stop region 5. That is, the passivation film 6 is formed from a portion directly above the p-type guard ring region 3 to a portion directly above the n + -type field stop region 5 and covers the entire upper surface of the p-type JTE region 4.
  • An insulating film that covers the passivation film 6, the surface electrode 8, and the floating electrode 9 may be further provided above the passivation film 6.
  • As the material of the insulating film it is conceivable to use an insulating film such as a silicon oxide film or a resin such as polyimide.
  • the metal insulating film 6b having a negative charge is used for the passivation film 6, an effective inside of the passivation film 6 is caused by a high electric field applied to the passivation film 6. Even if the charge fluctuates, concentration of electric lines of force on the surface electrode 8 can be prevented. For this reason, it is possible to suppress withstand voltage fluctuation.
  • a semiconductor device includes a first silicon oxide film in which a passivation film on a p-type impurity region forming a termination structure of an SiC power device is in contact with SiC (n ⁇ type drift layer 2), It has a metal insulating film located above the first silicon oxide film and a second silicon oxide film located above the metal insulating film, and the thickness of the metal insulating film is not less than 0.3 nm and not more than 10 nm. It is characterized by.
  • FIG. 2 is a graph showing the relationship between the effective passivation film charge and the breakdown voltage of the device.
  • the vertical axis of the graph represents the breakdown voltage of the power device, and the breakdown voltage when the charge amount of the passivation film is 0 is defined as 1.
  • the horizontal axis of the graph indicates the amount of charge in the passivation film.
  • the breakdown voltage sharply decreases as the positive charge increases. That is, on the right side of the graph, the withstand voltage changes rapidly as the charge amount of the passivation film changes.
  • the first silicon oxide film 6a and the second silicon oxide film 6c are disposed on the lower layer and the upper layer of the metal insulating film 6b, respectively, so that a high electric field is applied to the passivation film 6. Charge injection into the metal insulating film 6b can be suppressed. Thereby, the charge fluctuation of the passivation film 6 can be suppressed.
  • the film thickness of the aluminum oxide film and the negative charge amount have a relationship as shown in the graph of FIG. 3, the vertical axis represents the absolute value of the effective negative charge amount Q F of passivation film including an aluminum oxide film, the negative charge amount when the film thickness of the aluminum oxide film is 20 nm 1 It is defined as The horizontal axis of the graph indicates the film thickness of the aluminum oxide film.
  • the thickness of the aluminum oxide film is increased from 0 nm, the negative charge amount increases rapidly.
  • the film thickness is 0.3 nm or more, the increase in the negative charge amount becomes very gradual. That is, if the film thickness of the aluminum oxide film is 0.3 nm or more, a desired negative charge can be provided in the aluminum oxide film.
  • the film thickness of the aluminum oxide film and the amount of change in the charge of the passivation film when an electrical stress is applied have a relationship as shown in the graph of FIG. became.
  • the vertical axis indicates the amount of change in the charge of the passivation film including the aluminum oxide film due to electrical stress.
  • the amount of change in the charge when the film thickness is 20 nm is defined as 1.
  • the horizontal axis of the graph indicates the film thickness of the aluminum oxide film.
  • the thickness of the aluminum oxide film is small, the amount of fluctuation in the charge is small and stable, but if the thickness exceeds 5 nm, the amount of fluctuation in the charge increases, and if it exceeds 10 nm, the aluminum oxide film is not used.
  • the charge fluctuation amount is five times or more compared to the case where the passivation film 11 is made of only SiO 2 .
  • the passivation film 11 is made of only SiO 2 .
  • the thickness of the metal insulating film is not less than 0.3 nm and not more than 10 nm. That is, if the thickness of the metal insulating film is 0.3 nm or more, a sufficient amount of charge can be provided, but if the thickness is larger than 10 nm, the amount of charge in the metal insulating film becomes unstable.
  • the thickness needs to be 10 nm or less. More preferably, the thickness of the metal insulating film is from 0.3 nm to 5 nm. Thereby, a passivation film having a more stable charge against electrical stress can be provided.
  • the thickness of the metal insulating film is not less than 0.3 nm and not more than 1 nm. More desirable. Thereby, there is no etching residue, and the metal insulating film and the silicon oxide film positioned above and below the metal insulating film can be processed continuously.
  • the thickness of the passivation film can be reduced without forming a thick high-k film. Insulation breakdown can be prevented and leakage current can be reduced, and the device can have a high breakdown voltage. Therefore, as shown in FIG. 1, it is not always necessary to form a high-k film having a high dielectric constant and a large film thickness in the passivation film 6. Although the high-k film having a large film thickness is less stable in the charge amount of the insulating film when an electrical stress is applied, in the semiconductor device shown in FIG. 1, the high-k film having a large film thickness in the passivation film 6 is used. Since the k film is not formed, it is possible to prevent the charge amount of the passivation film 6 from fluctuating.
  • the passivation film 6 is formed using a metal insulating film 6b having a film thickness of 0.3 nm or more and 10 nm or less, so that it is hardly affected by an electric field. A termination structure that can maintain a stable charge is realized. Further, since the metal insulating film 6b is made of an aluminum oxide film, the metal insulating film 6b is an insulating film having a negative charge. Therefore, as described with reference to FIG. 2, the passivation film is formed by a high electric field in the blocking state. Even if the positive charge in 6 increases, the high breakdown voltage of the passivation film 6 can be maintained.
  • the charge in the passivation film can be stabilized even when a high electric field is applied, and the amount of fluctuation in the breakdown voltage of the passivation film is reduced, resulting in a high breakdown voltage. Can be maintained stably. For this reason, the generation of leakage current that flows due to the concentration of electric lines of force on the edge portion of the surface electrode 8 is prevented, and the reliability of the insulating film (the stability of the charge amount of the insulating film due to the application of electrical stress) is improved. It is possible to prevent the withstand voltage of the transistor, that is, the anode-cathode withstand voltage of the diode or the source-drain withstand voltage of the transistor from fluctuating. Thereby, the reliability of the semiconductor device can be improved.
  • the metal insulating film 6 b having a negative fixed charge into the passivation film 6 the effective passivation film charge can be made negative. As a result, it is possible to provide a stable termination structure with little fluctuation in breakdown voltage even when a high electric field is applied to the passivation film.
  • FIG. 5 to 10 are cross-sectional views of the semiconductor device during the manufacturing process.
  • the active region is not shown, and the description of the manufacturing process of the high breakdown voltage element formed in the active region is omitted, but at the same time as the termination structure is formed, a semiconductor element is formed in the active region according to the device structure. Needless to say.
  • a base is prepared in which an n ⁇ type drift layer 2 is laminated on an n + type substrate 1 which is a SiC substrate.
  • the n ⁇ type drift layer 2 is an n type SiC film formed on the n + type substrate 1 by an epitaxial growth method.
  • the insulating film is patterned to form an ion implantation mask M1.
  • p-type impurities for example, Al (aluminum)
  • the p-type guard ring region 3 is formed with a doping concentration of about 1 ⁇ 10 18 cm ⁇ 3 to 2 ⁇ 10 20 cm ⁇ 3 and a thickness (junction depth) of about 0.5 to 2.0 ⁇ m. .
  • a patterned ion implantation mask M2 made of a silicon oxide film or the like is formed on the n ⁇ -type drift layer 2 and the p-type guard ring region 3.
  • p-type impurities for example, Al (aluminum)
  • the p-type JTE region 4 is formed with a doping concentration of about 5 ⁇ 10 16 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of about 0.5 to 2.0 ⁇ m.
  • the p-type JTE region 4 is formed adjacent to the p-type guard ring region 3.
  • n + type field stop region 5 is formed by ion implantation of an n type impurity (for example, N (nitrogen)) on the upper surface of the n ⁇ type drift layer 2 exposed from the mask M3.
  • n type impurity for example, N (nitrogen)
  • the p-type guard ring region 3, the p-type JTE region 4 and the n + -type field stop region 5 are formed in order toward the outside of the active region so as to surround the active region (not shown) on the upper surface of the n ⁇ -type drift layer 2. .
  • the p-type guard ring region 3 is formed so as to surround the active region on the upper surface of the n ⁇ -type drift layer 2
  • the p-type JTE region 4 is formed so as to surround the p-type guard ring region 3
  • p An n + type field stop region 5 is formed so as to surround the type JTE region 4.
  • the semiconductor device in the manufacturing process including the n + type substrate 1 is heat-treated at, for example, 1700 ° C. in order to activate the implanted Al (aluminum) and N (nitrogen).
  • a first silicon oxide film 6a is formed on the n ⁇ -type drift layer 2 by thermal oxidation, CVD (Chemical Vapor Deposition), or a combination of both.
  • a metal insulating film 6b and a second silicon oxide film 6c are sequentially formed on the first silicon oxide film 6a using a CVD method or the like, and the first silicon oxide film 6a, the metal insulating film 6b, and the second silicon oxide film 6c are formed.
  • a passivation film 6 is formed.
  • the first silicon oxide film 6a and the second silicon oxide film 6c are SiO 2 films, and the metal insulating film 6b is an insulating film containing aluminum oxide, and here is composed of an Al 2 O 3 film.
  • the thickness of the metal insulating film 6b is not less than 0.3 nm and not more than 10 nm.
  • a patterned mask M4 is formed on the passivation film 6, and the passivation film 6 is processed by dry etching or wet etching, so that the p-type guard ring region 3 and the n + -type field stop region 5 are processed.
  • the mask M4 is assumed to be a photoresist film formed using, for example, a photolithography technique.
  • the back surface electrode 7 is formed on the back surface that is the surface opposite to the main surface of the n + type substrate 1.
  • the back electrode 7 may be formed by sputtering Al (aluminum), for example, but may be formed by NiSi or TiSi.
  • the metal film is patterned to form a passivation film. The upper surface of the passivation film 6 is exposed. At this time, the upper surfaces of both ends of the passivation film 6 are not exposed.
  • the surface electrode 8 and the floating electrode 9 made of the metal film are formed on the inner side (active region side) and the outer side of the passivation film 6 having an annular planar shape, respectively. That is, the surface electrode 8 is formed on the active region side with respect to the passivation film 6, and the floating electrode 9 is formed on the opposite side of the active region with respect to the passivation film 6. Both the surface electrode 8 and the floating electrode 9 are formed so that a part thereof rides on the end portion of the passivation film 6.
  • the surface electrode 8 electrically connected to a part of the power device in the active region and the floating electrode 9 electrically connected to the n + type field stop region 5 are formed.
  • the termination structure shown in FIG. 10 is completed.
  • the p-type guard ring region 3 and the p-type JTE region 4 need not have the same depth.
  • the p-type JTE region 4 does not have to be a single region, and may be formed of a plurality of regions. That is, the p-type JTE region 4 may be formed of a semiconductor region having a relatively high impurity concentration and a semiconductor region having a lower impurity concentration, and the p-type JTE region 4 may have a concentration gradient.
  • the order of forming the p-type guard ring region 3, the p-type JTE region 4, and the n + -type field stop region 5 need not be as described above.
  • the semiconductor device of the present embodiment is completed by dicing the n + type substrate 1 into pieces to form a plurality of semiconductor chips.
  • An insulating film covering the entire surface of the n + type substrate 1 may be formed before dicing.
  • the semiconductor chip may be covered with a resin film made of polyimide or the like.
  • the n + -type field stop region 5 is located near the end of the semiconductor chip formed by dicing, and the p-type guard ring region 3 is closer to the center of the semiconductor chip than the n + -type field stop region 5. The area will be located.
  • aluminum oxide is exemplified as a member of the metal insulating film 6b, but the present invention is not limited to this, and may be aluminum nitride or titanium oxide. That is, since the metal insulating film 6b may be an insulating film having a negative charge, various members can be used.
  • the thickness of the metal insulating film 6b is more preferably 0.3 nm or more and 5 nm or less. As a result, a passivation film that is stable against electrical stress can be provided.
  • the thickness of the metal insulating film 6b is more preferably 0.3 nm or more and 1 nm or less. As a result, there is no etching residue, and the metal insulating film 6b and the first silicon oxide film 6a positioned above and below the metal insulating film 6b can be processed continuously.
  • FIG. 11 is a cross-sectional view showing a modification of the semiconductor device according to the present embodiment.
  • a plurality of p-type semiconductor regions 4 a are formed on the upper surface of the n ⁇ -type drift layer 2 instead of the p-type JTE region 4.
  • Each of the plurality of p-type semiconductor regions 4 a has an annular planar shape like the p-type guard ring region 3 and is disposed so as to surround the active region and the p-type guard ring region 3.
  • the n ⁇ type drift layer 2 made of SiC of the first silicon oxide film 6a is formed by oxynitriding with nitrogen monoxide or dinitrogen monoxide or annealing.
  • N nitrogen
  • reducing the trap (trap level) at the interface between the n ⁇ -type drift layer 2 and the passivation film 6 is effective for suppressing the fluctuation of the effective passivation film charge.
  • a metal insulating film having a thickness of 0.3 nm to 10 nm and having a negative charge is provided in the passivation film, as described above.
  • the charge in the passivation film can be stabilized even when a high electric field is applied. Therefore, it is possible to prevent the breakdown voltage of the power device from fluctuating, so that the reliability of the semiconductor device can be improved.
  • FIG. 12 is a cross-sectional view of the semiconductor device according to the present embodiment, and shows a structure substantially similar to the termination structure shown in FIG.
  • the first silicon oxide film 6a, the silicon nitride (SiN) film 6d, the metal insulating film 6b, the silicon nitride film 6e, and the first film in which the passivation film 6 is sequentially stacked on the substrate it differs from the first embodiment in that it has at least five layers of the silicon dioxide film 6c.
  • the passivation film 6 includes the first silicon oxide film 6a, the silicon nitride film 6d, the metal insulating film 6b, the silicon nitride film 6e, and the second silicon oxide film 6c that are sequentially stacked on the upper surface of the n ⁇ type drift layer 2.
  • the metal insulating film 6b is made of a metal oxide film such as aluminum oxide, for example.
  • the thickness of the metal insulating film 6b is 0.3 nm or more, and the sum of the thicknesses of the silicon nitride film 6d, the metal insulating film 6b, and the silicon nitride film 6e is 10 nm or less. Note that an insulating film may be further provided on the passivation film 6.
  • the reliability of the film itself is improved as compared with a laminated insulating film without a silicon nitride film. To do. Specifically, the life until dielectric breakdown and the stability of effective insulating film charge are improved.
  • the total film thickness of the silicon nitride film 6d, the metal insulating film 6b, and the silicon nitride film 6e is set to 10 nm or less, thereby stabilizing the charge in the passivation film 6 and improving the breakdown voltage of the device. It is possible to make it.
  • the semiconductor device shown in FIG. 12 can be formed by performing substantially the same steps as those described in Embodiment 1 with reference to FIGS.
  • the structure of the passivation film 6 is different from that of the first embodiment. Therefore, in the process described with reference to FIG. 9, after the first silicon oxide film 6a is formed by thermal oxidation or CVD, or a combination of both, the silicon nitride film 6d, the metal insulating film 6b, the silicon nitride film 6e, The passivation film 6 is formed by sequentially laminating the second silicon oxide film 6c using the CVD method or the like and patterning the laminated insulating film formed thereby.
  • the film thickness of the metal insulating film 6b is 0.3 nm or more, and the sum of the film thicknesses of the silicon nitride film 6d, the metal insulating film 6b, and the silicon nitride film 6e is 10 nm or less.
  • the metal insulating film is, for example, aluminum oxide.
  • the reliability of the stacked insulating film itself is improved in the stacked insulating film including the silicon oxide film, the silicon nitride film, and the metal insulating film described in this embodiment as compared with the stacked insulating film without the silicon nitride film. did it. Specifically, the life until breakdown and the stability of the effective insulating film charge were improved.
  • the present invention is not limited to this and may be aluminum nitride or titanium oxide.
  • the termination structure is JTE, but the same effect can be obtained even if the termination structure is FLR.
  • the n ⁇ type drift layer 2 made of SiC of the first silicon oxide film 6a is formed by oxynitriding with nitrogen monoxide or dinitrogen monoxide or annealing.
  • N nitrogen
  • reducing traps at the interface between the n ⁇ -type drift layer 2 and the passivation film 6 is effective for suppressing fluctuations in effective passivation film charge.
  • FIG. 13 shows a cross-sectional view including the MOSFET and termination region formed in the active region on the SiC substrate in the present embodiment.
  • the termination region on the right side of the figure has the same structure as the termination structure of the first embodiment shown in FIG.
  • the passivation film 27 includes a first silicon oxide film 27a, a metal insulating film 27b, a second silicon oxide film 27c, and an insulating film 27d that are sequentially formed on the n ⁇ type drift layer 2.
  • a high breakdown voltage MOSFET is formed in the active region shown on the left side of FIG.
  • MOSFET the n - formed via a gate insulating film 24 made of the first silicon oxide film 24a from the type drift layer 2 above are laminated in this order, a metal insulating film 24b and the second silicon oxide film 24c - -type drift layer 2 on the n Gate electrode 25, n + type source region 22 formed on the upper surface of n ⁇ type drift layer 2 on both sides of gate electrode 25, and n + type substrate 1 serving as a drain region. That is, the back electrode 7 in contact with the n + type substrate 1 is a drain electrode that supplies a potential to the drain region of the MOSFET.
  • the surface electrode 8 to the n + -type source regions 22 are electrically connected is a source electrode supplying a potential to the n + -type source region 22.
  • the gate insulating film 24 is in contact with the upper surfaces of the n ⁇ type drift layer 2 and the p type base region 21 and the n + type source region 22 formed on both sides of the n ⁇ type drift layer 2, respectively.
  • a p + -type contact region 23 is formed further outside the n + -type source region 22 formed on the upper surface of the n ⁇ -type drift layer 2 on both sides of the gate electrode 25, and is formed on the upper surface of the n ⁇ -type drift layer 2.
  • the p-type base region 21 is formed so as to cover the bottom and side surfaces of the semiconductor region formed of the n + -type source region 22 and the p + -type contact region 23.
  • the surface electrode 8 is formed in contact with the upper surfaces of the n + -type source region 22 and the p + -type contact region 23, and the p + -type contact region 23 has a role of supplying a potential to the p-type base region 21. Yes.
  • the p-type base region 21 is a p-type semiconductor region in which a MOSFET channel region is formed, and has a deeper junction depth than the n + -type source region 22 and the p + -type contact region 23.
  • the side surface of the p-type base region 21 is in contact with the side surface of the p-type guard ring region 3, and the junction depths of the p-type base region 21, the p-type guard ring region 3 and the p-type JTE region 4 are substantially the same. It shall be. However, the junction depth of these semiconductor regions can be changed as appropriate.
  • An insulating film 26 is formed immediately above the gate insulating film 24 so as to cover the surface of the gate electrode 25 and the upper surface of the end of the gate electrode 25.
  • the surface electrode 8 includes an upper surface of one end of the passivation film 27, a p-type guard ring region 3, a p-type base region 21, an n + -type source region 22, a p + -type contact region 23, and a gate insulating film 24. It is continuously formed in contact with the sidewall and the surface of the insulating film 26. That is, the gate insulating film 24 and the insulating film 26 are covered with the surface electrode 8.
  • the gate insulating film 24 is composed of a laminated film in which a first silicon oxide film 24a, a metal insulating film 24b, and a second silicon oxide film 24c are sequentially formed on a substrate containing SiC.
  • the passivation film 27 has the same structure as the gate insulating film 24, that is, has a first silicon oxide film 27a, a metal insulating film 27b, and a second silicon oxide film 27c in the film, and further on the second silicon oxide film 27c.
  • the insulating film 27d is formed on the substrate.
  • the metal insulating films 24b and 27b are made of, for example, a metal oxide film such as aluminum oxide, and their film thickness is not less than 0.3 nm and not more than 10 nm. Note that an insulating film may be further provided above the passivation film 27 in the termination region.
  • this MOSFET As an operation of this MOSFET, when a positive voltage is applied to the gate electrode 25 with a voltage applied between the back electrode (drain electrode) 7 and the front electrode (source electrode) 8, a p-type base is applied. An electron inversion layer is formed on the surface layer of the region 21. As a result, a current flows from the back electrode 7 to the surface electrode 8 through the n + type substrate 1, the n ⁇ type drift layer 2, the surface layer of the p type base region 21, and the n + type source region 22.
  • the termination structure when a voltage is applied between the back electrode 7 and the front electrode 8 and 0 V is applied to the gate electrode 25, a current flows between the back electrode 7 and the front electrode 8.
  • Electric field lines tend to concentrate on the edge portion of the surface electrode 8, but the electric field lines are laterally expanded by the p-type guard ring region 3 and the p-type JTE region 4. Can be relaxed. Since the metal film 27b having a negative charge is used for the passivation film 27, even if the effective passivation film charge fluctuates due to a high electric field applied to the passivation film 27, the passivation film 27 is applied to the surface electrode 8. Concentration of electric field lines can be prevented. For this reason, it is possible to suppress fluctuations in the breakdown voltage of the device.
  • the present invention relates to a termination structure, and the MOSFET is formed by a well-known manufacturing method, and thus the illustration of the semiconductor device during the manufacturing process is omitted. Further, the manufacturing process of the termination structure on the right side of FIG. 13 is substantially the same as in the first embodiment.
  • an n ⁇ type drift layer 2 is formed on an n + type substrate 1 made of SiC by an epitaxial growth method.
  • a p-type guard ring region 3 is formed by forming a hard mask made of a silicon oxide film or the like on the upper surface of the n ⁇ -type drift layer 2 and ion-implanting p-type impurities (for example, Al (aluminum)).
  • the p-type guard ring region 3 is formed with a doping concentration of about 1 ⁇ 10 18 cm ⁇ 3 to 2 ⁇ 10 20 cm ⁇ 3 and a thickness of about 0.5 to 2.0 ⁇ m.
  • n + -type field stop region 5 is formed by ion-implanting n-type impurities (for example, N (nitrogen)) into the upper surface of n ⁇ -type drift layer 2 in the same manner using a hard mask.
  • n-type impurities for example, N (nitrogen)
  • a p-type base region 21 is formed by ion-implanting a p-type impurity (for example, Al (aluminum)) on the upper surface of the n ⁇ -type drift layer 2.
  • the p-type base region 21 is formed with a doping concentration of about 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 and a thickness of about 0.5 to 3.0 ⁇ m.
  • a hard mask that exposes a part of the p-type base region 21 is formed on the n ⁇ -type drift layer 2, and an n + -type source region is formed by ion implantation of an n-type impurity (for example, N (nitrogen)). 22 is formed.
  • a hard mask is formed on the n ⁇ type drift layer 2 so as to cover the n + type source region 22 and expose a part of the p type base region 21, and p type impurities (for example, Al (aluminum)) are formed.
  • a p + -type contact region 23 is formed by ion implantation.
  • heat treatment is performed at 1700 ° C., for example, to activate the implanted Al (aluminum) and N (nitrogen).
  • a first insulating film made of silicon oxide is formed on the n ⁇ -type drift layer 2 by performing thermal oxidation within a process temperature range of about 1000 to 1300 ° C.
  • a second insulating film containing metal and a third insulating film made of silicon oxide are sequentially formed on the first insulating film by a CVD method or the like.
  • the polycrystalline silicon film is patterned to form a gate directly above the region between the two p-type base regions 21 in the active region.
  • the electrode 25 is formed.
  • a fourth insulating film made of, for example, silicon oxide is formed on the third insulating film so as to cover the gate electrode 25.
  • the first to fourth layers are formed using a dry etching method or a wet etching method.
  • the insulating film is patterned.
  • the first silicon oxide film 24a made of the first insulating film, the metal insulating film 24b made of the second insulating film, and the third insulating film are formed immediately above the region between the two p-type base regions 21 in the active region.
  • a gate insulating film 24 made of a laminated film in which the second silicon oxide film 24c is sequentially laminated is formed.
  • the termination region includes a first silicon oxide film 27a made of a first insulating film, a metal insulating film 27b made of a second insulating film, a second silicon oxide film 27c made of a third insulating film, and a fourth insulating film.
  • a passivation film 27 in which insulating films 27d are sequentially stacked is formed.
  • the film thickness of the metal insulating films 24b and 27b is 0.3 nm or more and 10 nm or less, and the total film thickness of the gate insulating film 24 is 30 nm or more and 100 nm or less.
  • the metal insulating films 24b and 27b are made of, for example, aluminum oxide.
  • the passivation film 27 includes the same structure as the gate insulating film 24.
  • an insulating film 26 made of the fourth insulating film is formed on the second silicon oxide film 24c.
  • the insulating film 26 is formed so as to cover the surface of the gate electrode 25, and is formed with the same width as the gate insulating film 24 immediately above the gate insulating film 24. That is, the width of the gate electrode 25 in the gate length direction is narrower than the width of the gate insulating film 24 in the same direction.
  • the gate electrode 25 is formed via the gate insulating film 24 immediately above the region between the two p-type base regions 21 in the active region.
  • a back electrode (drain electrode) 7 is formed on the back surface of the n + -type substrate 1 using a sputtering method or the like, and subsequently a metal film is formed on the entire surface of the n ⁇ -type drift layer 2.
  • the surface electrode 8 electrically connected to the n + type source region 22 and the p + type contact region 23 and the floating electrode 9 electrically connected to the n + type field stop region 5 are formed.
  • the MOSFET and termination structure shown in FIG. 13 are completed. Note that the p-type guard ring region 3 and the p-type JTE region 4 need not have the same depth.
  • the p-type JTE region 4 does not have to be a single region, and may be formed of a plurality of regions. Further, the formation order of the p-type guard ring region 3, the p-type JTE region 4, the n + -type field stop region 5, the p-type base region 21, the n + -type source region 22, and the p + -type contact region 23 is as described above. Need not be.
  • the passivation film 27 including the metal insulating film 27b having a film thickness of 0.3 nm to 10 nm is formed as shown in FIG.
  • the gate insulating film 24 is a gate insulating film of a MOSFET
  • the film thickness cannot be increased more than necessary. Therefore, the film thickness is set to 30 nm to 100 nm.
  • the insulating film 27d is provided here to increase the thickness of the insulating film 27d. Specifically, the thickness of the passivation film 27 needs to be several hundred nm to several ⁇ m.
  • the present invention is not limited to this and may be aluminum nitride or titanium oxide.
  • the termination structure is JTE, but the same effect can be obtained even if the termination structure is FLR.
  • the first silicon oxide films 24a and 27a are formed, if they are oxynitrided with nitrogen monoxide or dinitrogen monoxide or annealed, the first silicon oxide films 24a and 27a and n made of SiC are formed.
  • N nitrogen
  • the present invention is effective when applied to a manufacturing technique of a semiconductor device including a SiC substrate.

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Abstract

In this semiconductor device having a power device on a semiconductor substrate that includes a silicon carbide, a termination structure is achieved, said termination structure maintaining a stable withstand voltage even if a high electrical field is applied to a passivation film on a substrate main surface. As a means for achieving the termination structure, the passivation film on a p-type impurity region that forms the termination structure of the SiC power device has the laminated structure including a first silicon oxide film in contact with SiC, a metal insulating film on the first silicon oxide film, and a second silicon oxide film on the metal insulating film, and the thickness of the metal insulating film is 0.3-10 nm. Consequently, effective charge of the passivation film is made negative.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関し、特に、炭化ケイ素を含む基板上に形成された半導体装置に適用して有効な技術に関する。 The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device formed on a substrate containing silicon carbide.
　高耐圧を必要とし、大きな電流が流れるパワーデバイスの低損失化を目的として、従来のケイ素（Ｓｉ）に代わる新しい材料である炭化ケイ素（ＳｉＣ）を半導体基板に用いた半導体装置が研究されている。ＳｉＣは、絶縁破壊電界がＳｉに比べ約１０倍大きいため、耐圧を維持するドリフト層を薄く、且つ高濃度にすることができ、導通損失を低減できる材料である。このため次世代の高耐圧・低損失なパワーデバイスへの応用が期待されている。 Semiconductor devices using silicon carbide (SiC), a new material that replaces conventional silicon (Si), have been studied for the purpose of reducing the loss of power devices that require high withstand voltage and through which large current flows. . SiC has a dielectric breakdown electric field about 10 times larger than that of Si, so that the drift layer that maintains the withstand voltage can be made thin and highly concentrated, and the conduction loss can be reduced. For this reason, it is expected to be applied to next-generation power devices with high breakdown voltage and low loss.
　パワーデバイスではブロッキング状態においてデバイス端部への電界集中を緩和するために、ジャンクションターミネーションエクステンション（Junction Termination Extension：ＪＴＥ）またはフィールドリミティングリング（Field Limiting Ring：ＦＬＲ）などのターミネーション領域の構造（ターミネーション構造）を形成することが知られている。なお、ここでいうブロッキング状態とは、パワーデバイスの電極間に高い電位差が生じており、かつ前記電極間に電流が流れていない状態を指す。 In power devices, the structure of the termination region (termination structure) such as junction termination extension (JTE) or field limiting ring (FLR) is used to alleviate the electric field concentration at the device end in the blocking state. ) Is known to form. In addition, the blocking state here refers to a state where a high potential difference is generated between the electrodes of the power device and no current flows between the electrodes.
　特許文献１（特開平１１－３３０４９６号公報）には、パッシべーション膜を酸化シリコン膜（ＳｉＯ２膜）および高誘電体膜（ｈｉｇｈ－ｋ膜）で構成することによってパッシべーション膜にかかる電圧を酸化シリコン膜とｈｉｇｈ－ｋ膜で分担し、パッシべーション膜の破壊を防ぐことが記載されている。 In Patent Document 1 (Japanese Patent Laid-Open No. 11-330496), a passivation film is formed of a silicon oxide film (SiO 2 film) and a high dielectric film (high-k film), and thus the passivation film is applied. It is described that the voltage is shared between the silicon oxide film and the high-k film to prevent the passivation film from being broken.
　また、特許文献２（特開２００２－５２４８６０号公報）には、パッシべーション膜を酸化シリコン膜、ｈｉｇｈ－ｋ膜および酸化シリコン膜の３層で構成することにより、パッシべーション膜にかかる電圧を酸化シリコン膜とｈｉｇｈ－ｋ膜とで分担し、パッシべーション膜にリーク電流が流れることを抑制することが記載されている。 In Patent Document 2 (Japanese Patent Laid-Open No. 2002-524860), a voltage applied to the passivation film is formed by forming the passivation film with three layers of a silicon oxide film, a high-k film, and a silicon oxide film. Is divided by a silicon oxide film and a high-k film to prevent leakage current from flowing through the passivation film.
特開平１１－３３０４９６号公報Japanese Patent Laid-Open No. 11-330496 特開２００２－５２４８６０号公報JP 2002-524860 A
　基板にＳｉＣを用いたパワーデバイスのターミネーション設計においてはＪＴＥ、ＦＬＲの構造設計のみでなく、ターミネーション構造の上部に設けられたパッシべーション膜にも高電界がかかることを考慮する必要がある。 In the termination design of power devices using SiC as the substrate, it is necessary to consider that a high electric field is applied not only to the structural design of JTE and FLR but also to the passivation film provided above the termination structure.
　ここで、図１４、図１５に示すダイオードをパワーデバイスの例としてＪＴＥの動作原理を説明する。図１４はダイオードの表面電極とパッシべーション膜の平面図であり、図１５は図１４のＡ－Ａ線における断面図である。図１４では、ｎ＋型基板１（図１５参照）上のｎ－型ドリフト層２と、ｎ－型ドリフト層２上面に形成されたｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５のみを示しており、それより上部に形成されたパッシべーション膜、表面電極および樹脂膜などは図示を省略している。また、図１５では図１４の半導体チップの端部であるターミネーション領域のみを示し、半導体チップの中央部にあるアクティブ領域およびアクティブ領域に形成されたダイオードの図示は省略している。また、図１４は平面図であるが、図面を見易くするために部分的にハッチングを付している。 Here, the operation principle of JTE will be described using the diode shown in FIGS. 14 and 15 as an example of a power device. 14 is a plan view of the surface electrode of the diode and the passivation film, and FIG. 15 is a cross-sectional view taken along line AA of FIG. In FIG. 14, the n − type drift layer 2 on the n + type substrate 1 (see FIG. 15), the p type guard ring region 3, the p type JTE region 4 and the n + formed on the upper surface of the n − type drift layer 2. Only the mold field stop region 5 is shown, and a passivation film, a surface electrode, a resin film, and the like formed thereon are not shown. Further, FIG. 15 shows only a termination region which is an end portion of the semiconductor chip in FIG. 14, and illustration of an active region in the central portion of the semiconductor chip and a diode formed in the active region is omitted. FIG. 14 is a plan view, but is partially hatched to make the drawing easy to see.
　図１５に示すように、ｎ＋型基板１上に形成されたｎ－型ドリフト層２の上面には、ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５が形成され、ｎ＋型基板１の裏面には裏面電極７が形成され、ｎ－型ドリフト層２上にはｎ－型ドリフト層２の上面に接して表面電極８、パッシべーション膜１１およびフローティング電極９が形成されている。ｎ＋型フィールドストップ領域５上にはフローティング電極９が電気的に接続されており、表面電極８およびフローティング電極９のそれぞれの一部はパッシべーション膜１１上に乗り上げるように形成されている。図１４に示すように、ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５は、ｎ－型ドリフト層２上面のアクティブ領域を囲むようにｎ－型ドリフト層２上面の中心部から端部にかけて順に形成されている。また、ｐ型ガードリング領域３に囲まれたアクティブ領域には高耐圧のダイオードが形成されているがここではその図示を省略し、アクティブ領域にはｎ－型ドリフト層２のみを示している。実際には、アクティブ領域のｎ－型ドリフト層２の上面にはｐ型の半導体層などが形成されている。 As shown in FIG. 15, a p-type guard ring region 3, a p-type JTE region 4 and an n + -type field stop region 5 are formed on the upper surface of the n − -type drift layer 2 formed on the n + -type substrate 1. The back electrode 7 is formed on the back surface of the n + type substrate 1, and the surface electrode 8, the passivation film 11, and the floating electrode are in contact with the top surface of the n − type drift layer 2 on the n − type drift layer 2. 9 is formed. A floating electrode 9 is electrically connected on the n + -type field stop region 5, and a part of each of the surface electrode 8 and the floating electrode 9 is formed on the passivation film 11. As shown in FIG. 14, p-type guard ring region 3, p-type JTE region 4 and n + -type field stop region 5, n - n so as to surround the active region of the type drift layer 2 top - -type drift layer 2 top Are formed in order from the center to the end. In addition, although a high breakdown voltage diode is formed in the active region surrounded by the p-type guard ring region 3, the illustration thereof is omitted here, and only the n − -type drift layer 2 is shown in the active region. Actually, a p-type semiconductor layer or the like is formed on the upper surface of the n − -type drift layer 2 in the active region.
　図１５に示す裏面電極７と表面電極８との間に電圧が印加されたブロッキング状態においては、例えば数ｋＶの電圧が印加された裏面電極７から、例えば０Ｖの電圧が印加された表面電極８に向かって電気力線が伸びる。このとき、表面電極８のエッジ部分には電気力線が集中しやすいが、ｐ型ガードリング領域３とｐ型ＪＴＥ領域４が存在することによって電気力線が横方向に広げられるため、表面電極８のエッジ部分における電界集中を緩和できる。電界を緩和するｐ型領域を複数有するＦＬＲでも、同様に横方向に電気力線を広げられるため、電界集中を緩和できる。これによりパワーデバイスの高耐圧化が可能となる。 In the blocking state in which a voltage is applied between the back electrode 7 and the front electrode 8 shown in FIG. 15, for example, the front electrode 8 to which a voltage of 0 V is applied from the back electrode 7 to which a voltage of several kV is applied, for example. Electric lines of force extend toward. At this time, electric lines of force tend to concentrate on the edge portion of the surface electrode 8, but the presence of the p-type guard ring region 3 and the p-type JTE region 4 spreads the electric lines of force in the lateral direction. The electric field concentration at the edge portion of 8 can be relaxed. Even in an FLR having a plurality of p-type regions for relaxing the electric field, the electric field lines can be similarly expanded in the lateral direction, so that the electric field concentration can be reduced. This makes it possible to increase the breakdown voltage of the power device.
　しかし、パッシべーション膜にｈｉｇｈ－ｋ膜を用いる際には以下に説明する技術課題が存在する。パッシべーション膜は高電界により破壊されることを防ぐために通例数１００ｎｍから数μｍの膜厚を有しており、パッシべーション膜にかかる電圧を酸化シリコン膜とｈｉｇｈ－ｋ膜とで分担する場合には、当然ｈｉｇｈ－ｋ膜も相応の膜厚が必要となる。ところが、本発明者らが検討したところ、絶縁膜を酸化シリコン膜とｈｉｇｈ－ｋ膜で構成した場合、ｈｉｇｈ－ｋ膜が厚いと絶縁膜の信頼性（電気ストレス印加による絶縁膜電荷量の安定性）が悪化するという問題があることが明らかになった。 However, when a high-k film is used for the passivation film, there are technical problems described below. The passivation film typically has a thickness of several hundreds of nanometers to several μm in order to prevent it from being broken by a high electric field, and the voltage applied to the passivation film is shared between the silicon oxide film and the high-k film. In this case, the high-k film naturally needs to have a corresponding film thickness. However, as a result of studies by the present inventors, when the insulating film is composed of a silicon oxide film and a high-k film, if the high-k film is thick, the reliability of the insulating film (stabilization of the charge amount of the insulating film due to the application of electrical stress) It became clear that there was a problem that the
　さらに、ＳｉＣパワーデバイスのようにパッシべーション膜に高電界が印加される場合、パッシべーション膜の破壊、リーク電流の増加だけでなく、以下に説明する技術課題が存在する。つまり、高電界によって加速されたキャリアがパッシべーション膜に注入される問題があり、また、パッシべーション膜内の電荷が高電界によって移動することにより、実効的なパッシべーション膜電荷が経時的に変動する問題がある。また、ＳｉＣと絶縁膜の界面には多数の界面トラップが存在するため、トラップへの電荷の充放電によっても実効的なパッシべーション膜電荷が変動する。パッシべーション膜内の電荷が変動すると、ＪＴＥまたはＦＬＲなどにおける電気力線の広がり方が変化してしまう。このため、パワーデバイスの耐圧、すなわちダイオードのアノード－カソード間耐圧またはトランジスタのソース－ドレイン耐圧などが変動してしまい、信頼性の観点から問題となる。 Furthermore, when a high electric field is applied to the passivation film as in a SiC power device, there are not only the destruction of the passivation film and an increase in leakage current, but also technical problems described below. In other words, there is a problem that carriers accelerated by a high electric field are injected into the passivation film, and the charge in the passivation film is moved by the high electric field, so that the effective passivation film charge is changed over time. There is a problem that fluctuates. In addition, since there are a large number of interface traps at the interface between the SiC and the insulating film, the effective passivation film charge fluctuates also due to charge / discharge of charges in the trap. When the charge in the passivation film fluctuates, the way in which the electric lines of force spread in JTE or FLR changes. For this reason, the breakdown voltage of the power device, that is, the anode-cathode breakdown voltage of the diode or the source-drain breakdown voltage of the transistor fluctuates, which is a problem from the viewpoint of reliability.
　本発明の目的は、高い信頼性を有する半導体装置を提供することにある。 An object of the present invention is to provide a semiconductor device having high reliability.
　本発明の前記の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
　本願の一発明による半導体装置は、第１導電型を有する炭化ケイ素を含む半導体基板と、
　前記半導体基板上に形成され、前記第１導電型を有し、前記半導体基板よりも不純物濃度が低く炭化ケイ素を含むドリフト層と、
　前記ドリフト層内の上面に形成された前記第１導電型と異なる第２導電型を有する半導体領域と、
　前記ドリフト層上に形成されたパッシベーション膜と、
　前記ドリフト層上に形成された電極と、
　前記ドリフト層の裏面に接して形成された裏面電極と、
を含み、
　前記パッシベーション膜は、
　前記ドリフト層の上面に接して形成された第１絶縁膜と、
　前記第１絶縁膜上に形成された金属絶縁膜と、
　前記金属絶縁膜上に形成された第２絶縁膜と、
を有し、
　前記金属絶縁膜の膜厚は０．３ｎｍ以上１０ｎｍ以下の範囲にあるものである。 A semiconductor device according to an invention of the present application includes a semiconductor substrate including silicon carbide having a first conductivity type,
A drift layer formed on the semiconductor substrate, having the first conductivity type, having a lower impurity concentration than the semiconductor substrate and containing silicon carbide;
A semiconductor region having a second conductivity type different from the first conductivity type formed on an upper surface in the drift layer;
A passivation film formed on the drift layer;
An electrode formed on the drift layer;
A back electrode formed in contact with the back surface of the drift layer;
Including
The passivation film is
A first insulating film formed in contact with the upper surface of the drift layer;
A metal insulating film formed on the first insulating film;
A second insulating film formed on the metal insulating film;
Have
The metal insulating film has a thickness in the range of 0.3 nm to 10 nm.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　本発明によれば、半導体装置の信頼性を向上させることができる。 According to the present invention, the reliability of the semiconductor device can be improved.
本発明の実施の形態１である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. 耐圧とパッシべーション膜電荷量との関係を示すグラフである。It is a graph which shows the relationship between a proof pressure and the charge amount of a passivation film. アルミ酸化膜の膜厚と実効的なアルミ酸化膜の負電荷量との関係を示すグラフである。It is a graph which shows the relationship between the film thickness of an aluminum oxide film, and the effective negative charge amount of an aluminum oxide film. アルミ酸化膜の膜厚と電気ストレスを印加した後の絶縁膜電荷の変動量との関係を示すグラフである。It is a graph which shows the relationship between the film thickness of an aluminum oxide film, and the variation | change_quantity of the insulating film charge after applying an electrical stress. 本発明の実施の形態１である半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. 図５に続く半導体装置の製造工程中の断面図である。FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; 図６に続く半導体装置の製造工程中の断面図である。FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; 図７に続く半導体装置の製造工程中の断面図である。FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; 図８に続く半導体装置の製造工程中の断面図である。FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; 図９に続く半導体装置の製造工程中の断面図である。FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; 本発明の実施の形態１である半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which is Embodiment 1 of this invention. 本発明の実施の形態２である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is Embodiment 2 of this invention. 本発明の実施の形態３である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is Embodiment 3 of this invention. パワーデバイスの例として示す半導体装置の平面図である。It is a top view of the semiconductor device shown as an example of a power device. 図１４のＡ－Ａ線における断面図である。It is sectional drawing in the AA of FIG.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、以下の実施の形態では、特に必要なときを除き、同一または同様な部分の説明を原則として繰り返さない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
　（実施の形態１）
　図１に、本実施の形態の半導体装置の断面図を示す。本実施の形態の半導体装置は、炭化ケイ素（ＳｉＣ）からなる半導体基板に形成された高耐圧トランジスタなどのパワーデバイス（図示しない）を有しており、図１には当該半導体基板をダイシングして個片化することで形成する半導体チップの端部となる領域（ターミネーション領域）の断面を示している。ＳｉＣはＳｉ（シリコン）に比べて絶縁破壊電界が高く、耐圧が高い。デバイスの耐圧はドリフト層の厚さに大きく影響されるため、基板およびドリフト層にＳｉＣを用いることで、デバイスの耐圧を確保しつつ、ドリフト層を薄く、高濃度にする事ができる。したがって、導通損失を低減することができるが、高耐圧化が可能となった分、ドリフト層上のパッシべーション膜にも高い耐圧がかかるため、これに起因してリーク電流が発生するなどの問題もある。なお、図１に示す構造体では、図の左側に半導体チップの中心部が位置し、図の右側に半導体チップの端部が位置する。 (Embodiment 1)
FIG. 1 shows a cross-sectional view of the semiconductor device of this embodiment. The semiconductor device of the present embodiment has a power device (not shown) such as a high breakdown voltage transistor formed on a semiconductor substrate made of silicon carbide (SiC). FIG. The cross section of the area | region (termination area | region) used as the edge part of the semiconductor chip formed by dividing into pieces is shown. SiC has a higher dielectric breakdown electric field and higher breakdown voltage than Si (silicon). Since the breakdown voltage of the device is greatly affected by the thickness of the drift layer, the drift layer can be made thin and highly concentrated while securing the breakdown voltage of the device by using SiC for the substrate and the drift layer. Therefore, although conduction loss can be reduced, since the high withstand voltage is applied to the passivation film on the drift layer, a leakage current is generated due to this. There is also a problem. In the structure shown in FIG. 1, the center portion of the semiconductor chip is located on the left side of the drawing, and the end portion of the semiconductor chip is located on the right side of the drawing.
　図１に示すように、ｎ＋型基板１上にエピタキシャル成長法などにより形成されたｎ－型ドリフト層２の上面には、ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５が形成されている。ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５は、半導体チップの中央部のアクティブ領域を囲むように、前記中央部（図１の左側）から半導体チップの端部（図１の右側）に向かって順に配置されている。つまり、当該半導体チップを上方から見ると、ｎ－型ドリフト層２の上面のアクティブ領域を囲むようにｐ型ガードリング領域３が形成され、ｐ型ガードリング領域３を囲むようにｐ型ＪＴＥ領域４が形成され、ｐ型ＪＴＥ領域４を囲むようにｎ＋型フィールドストップ領域５がそれぞれ環状に形成されている。図において、ｐ型ガードリング領域３およびｐ型ＪＴＥ領域４は接しているが、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５は接しておらず、間に不純物が導入されていないｎ－型ドリフト層２が存在する。 As shown in FIG. 1, a p-type guard ring region 3, a p-type JTE region 4, and an n + -type field stop are formed on the upper surface of an n − -type drift layer 2 formed on an n + -type substrate 1 by an epitaxial growth method or the like. Region 5 is formed. The p-type guard ring region 3, the p-type JTE region 4 and the n + -type field stop region 5 surround the active region in the central portion of the semiconductor chip from the central portion (left side in FIG. 1) to the end portion of the semiconductor chip. They are arranged in order toward the right side of FIG. That is, when the semiconductor chip is viewed from above, the p-type guard ring region 3 is formed so as to surround the active region on the upper surface of the n − -type drift layer 2, and the p-type JTE region so as to surround the p-type guard ring region 3. 4 are formed, and n + -type field stop regions 5 are formed in an annular shape so as to surround the p-type JTE region 4. In the figure, although the p-type guard ring region 3 and the p-type JTE region 4 is in contact, p-type JTE region 4 and n + -type field stop region 5 is not in contact, no impurity is introduced between n - A type drift layer 2 is present.
　ｐ型ガードリング領域３およびｐ型ＪＴＥ領域４はＳｉＣからなるｎ－型ドリフト層２の上面にｐ型の不純物（例えばＡｌ（アルミニウム））を導入して形成された半導体領域である。ここでは、ｐ型ガードリング領域３の方がｐ型ＪＴＥ領域４よりもｐ型不純物の濃度が高いものとするが、ｐ型ガードリング領域３およびｐ型ＪＴＥ領域４のそれぞれの不純物濃度はどちらが高くてもよく、また、互いに同じ不純物濃度であってもよい。また、ｐ型ガードリング領域３およびｐ型ＪＴＥ領域４は同様の接合深さを有し、ｎ＋型フィールドストップ領域５はｐ型ＪＴＥ領域４よりも浅い接合深さを有しているが、それぞれの半導体領域の接合深さはこれに限られるものではない。ｎ＋型フィールドストップ領域５は、デバイスにかかる電界が半導体チップの端部に及ぶことを防ぐための半導体領域である。 The p-type guard ring region 3 and the p-type JTE region 4 are semiconductor regions formed by introducing p-type impurities (for example, Al (aluminum)) into the upper surface of the n − -type drift layer 2 made of SiC. Here, it is assumed that the p-type guard ring region 3 has a higher p-type impurity concentration than the p-type JTE region 4, but which of the impurity concentrations of the p-type guard ring region 3 and the p-type JTE region 4 is different. It may be high or may have the same impurity concentration. The p-type guard ring region 3 and the p-type JTE region 4 have the same junction depth, and the n + -type field stop region 5 has a shallower junction depth than the p-type JTE region 4. The junction depth of each semiconductor region is not limited to this. The n + type field stop region 5 is a semiconductor region for preventing the electric field applied to the device from reaching the end portion of the semiconductor chip.
　ｎ＋型基板１の裏面には裏面電極７が形成され、ｎ－型ドリフト層２上にはｎ－型ドリフト層２の上面に接して表面電極８、パッシべーション膜６およびフローティング電極９が形成されている。裏面電極７、表面電極８およびフローティング電極９は例えばＡｌ（アルミニウム）などからなり、パッシべーション膜６はｎ－型ドリフト層２の上面から上方に向かって順に積層された第１酸化シリコン膜６ａ、金属絶縁膜６ｂおよび第２酸化シリコン膜６ｃにより構成されている。第１酸化シリコン膜６ａの底面はＳｉＣからなるｎ－型ドリフト層２に接しており、また、金属絶縁膜６ｂの膜厚は０．３ｎｍ以上１０ｎｍ以下である。ここでは、金属絶縁膜６ｂの膜厚は例えば１ｎｍであるものとする。なお、本願では絶縁性を有する金属化合物からなる膜を金属絶縁膜と呼ぶ。金属絶縁膜６ｂは、例えば酸化アルミニウム（例えばアルミナ（Ａｌ２Ｏ３））などからなる絶縁膜である。本願では、酸素（Ｏ）およびアルミニウム（Ａｌ）を含むアルミ酸化物を含む膜を酸化アルミニウム膜と呼ぶものとする。 A back surface electrode 7 is formed on the back surface of the n + type substrate 1, and a surface electrode 8, a passivation film 6 and a floating electrode 9 are in contact with the top surface of the n − type drift layer 2 on the n − type drift layer 2. Is formed. The back electrode 7, the front electrode 8, and the floating electrode 9 are made of, for example, Al (aluminum), and the passivation film 6 is a first silicon oxide film 6 a that is laminated in order from the upper surface of the n − -type drift layer 2. The metal insulating film 6b and the second silicon oxide film 6c are used. The bottom surface of the first silicon oxide film 6a is in contact with the n − type drift layer 2 made of SiC, and the film thickness of the metal insulating film 6b is not less than 0.3 nm and not more than 10 nm. Here, the film thickness of the metal insulating film 6b is assumed to be 1 nm, for example. In the present application, a film made of a metal compound having an insulating property is called a metal insulating film. The metal insulating film 6b is an insulating film made of, for example, aluminum oxide (for example, alumina (Al 2 O 3 )). In this application, a film containing an aluminum oxide containing oxygen (O) and aluminum (Al) is referred to as an aluminum oxide film.
　また、金属絶縁膜６ｂはチタン酸化物により形成することも考えられる。ただし、Ｔｉ（チタン）およびＡｌ（アルミニウム）からなる絶縁膜はＳｉＣに接していると電荷が注入されやすいため、ここでは金属絶縁膜６ｂの下面および上面を第１酸化シリコン膜６ａおよび第２酸化シリコン膜６ｃにより覆っている。 It is also conceivable that the metal insulating film 6b is formed of titanium oxide. However, since an electric charge is easily injected into the insulating film made of Ti (titanium) and Al (aluminum) when in contact with SiC, the lower surface and the upper surface of the metal insulating film 6b are used here as the first silicon oxide film 6a and the second oxide film. It is covered with a silicon film 6c.
　ｎ＋型フィールドストップ領域５の上面にはフローティング電極９が電気的に接続されており、表面電極８はアクティブ領域のｎ－型ドリフト層２の上面に形成された高耐圧ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）のソース電極（図示しない）などに電気的に接続されている。表面電極８およびフローティング電極９のそれぞれの一部はパッシべーション膜６の端部の上に乗り上げるように形成されている。フローティング電極９は、ｎ＋型フィールドストップ領域５の電位を固定するための電極である。 A floating electrode 9 is electrically connected to the upper surface of the n + -type field stop region 5, and the surface electrode 8 is a high voltage MOSFET (Metal Oxide Semiconductor Field) formed on the upper surface of the n − -type drift layer 2 in the active region. It is electrically connected to the source electrode (not shown) of Effect Transistor. A part of each of the surface electrode 8 and the floating electrode 9 is formed so as to run on the end portion of the passivation film 6. The floating electrode 9 is an electrode for fixing the potential of the n + type field stop region 5.
　パッシべーション膜６は、ｐ型ガードリング領域３の端部の上面、ｐ型ＪＴＥ領域４の上面、およびｎ＋型フィールドストップ領域５の端部の上面を覆うように配置されている。つまり、パッシべーション膜６は、ｐ型ガードリング領域３の一部の直上からｎ＋型フィールドストップ領域５の一部の直上にかけて形成され、ｐ型ＪＴＥ領域４の上面を全て覆っている。本願では、図１に示すような半導体チップの端部（エッジ部）の近傍の領域に形成された電界緩和を目的とするｐ型ガードリング領域３またはｐ型ＪＴＥ領域４半導体領域などを含む構造をターミネーション構造と呼ぶ。パッシべーション膜６の上部には、パッシべーション膜６、表面電極８、フローティング電極９を覆うような絶縁膜をさらに備えていてもよい。前記絶縁膜の材料としては、酸化シリコン膜などの絶縁膜またはポリイミドなどの樹脂を用いることが考えられる。 The passivation film 6 is arranged so as to cover the upper surface of the end portion of the p-type guard ring region 3, the upper surface of the p-type JTE region 4, and the upper surface of the end portion of the n + -type field stop region 5. That is, the passivation film 6 is formed from a portion directly above the p-type guard ring region 3 to a portion directly above the n + -type field stop region 5 and covers the entire upper surface of the p-type JTE region 4. In the present application, a structure including a p-type guard ring region 3 or a p-type JTE region 4 semiconductor region for the purpose of electric field relaxation formed in a region near an end portion (edge portion) of a semiconductor chip as shown in FIG. Is called a termination structure. An insulating film that covers the passivation film 6, the surface electrode 8, and the floating electrode 9 may be further provided above the passivation film 6. As the material of the insulating film, it is conceivable to use an insulating film such as a silicon oxide film or a resin such as polyimide.
　このターミネーション構造を有する半導体装置の動作時であって、裏面電極７と表面電極８との間に電圧が印加されたブロッキング状態においては、裏面電極７から表面電極８に向かって電気力線が伸びる。表面電極８のエッジ部分、つまりｎ－型ドリフト層２に接する表面電極８の端部には電気力線が集中しやすいが、ｐ型ガードリング領域３およびｐ型ＪＴＥ領域４によって電気力線が横方向に広げられるため、表面電極８のエッジ部分における電界集中を緩和できる。また、以下に説明するように、パッシべーション膜６には負電荷を持つ金属絶縁膜６ｂを用いているため、パッシべーション膜６にかかる高電界によって実効的なパッシべーション膜６内の電荷が変動したとしても、表面電極８への電気力線の集中を防ぐことができる。このため、耐圧変動を抑制することが可能である。 During operation of the semiconductor device having this termination structure, in a blocking state in which a voltage is applied between the back electrode 7 and the front electrode 8, electric lines of force extend from the back electrode 7 toward the front electrode 8. . The electric lines of force tend to concentrate on the edge portion of the surface electrode 8, that is, the end of the surface electrode 8 in contact with the n − type drift layer 2, but the electric line of force is generated by the p-type guard ring region 3 and the p-type JTE region 4. Since it is spread in the lateral direction, the electric field concentration at the edge portion of the surface electrode 8 can be relaxed. Further, as will be described below, since the metal insulating film 6b having a negative charge is used for the passivation film 6, an effective inside of the passivation film 6 is caused by a high electric field applied to the passivation film 6. Even if the charge fluctuates, concentration of electric lines of force on the surface electrode 8 can be prevented. For this reason, it is possible to suppress withstand voltage fluctuation.
　本発明の実施の形態の半導体装置は、ＳｉＣパワーデバイスのターミネーション構造を形成するｐ型不純物領域上のパッシべーション膜が、ＳｉＣ（ｎ－型ドリフト層２）と接する第１酸化シリコン膜と、第１酸化シリコン膜より上部に位置する金属絶縁膜と、金属絶縁膜より上部に位置する第２酸化シリコン膜とを有し、その金属絶縁膜の膜厚が０．３ｎｍ以上１０ｎｍ以下であることを特徴とするものである。 A semiconductor device according to an embodiment of the present invention includes a first silicon oxide film in which a passivation film on a p-type impurity region forming a termination structure of an SiC power device is in contact with SiC (n − type drift layer 2), It has a metal insulating film located above the first silicon oxide film and a second silicon oxide film located above the metal insulating film, and the thickness of the metal insulating film is not less than 0.3 nm and not more than 10 nm. It is characterized by.
　以下に、グラフを用いて本実施の形態の半導体装置の効果を説明する。 Hereinafter, effects of the semiconductor device of the present embodiment will be described using graphs.
　図２に、実効的なパッシべーション膜電荷とデバイスの耐圧との関係を表したグラフを示す。グラフの縦軸はパワーデバイスの耐圧であり、パッシべーション膜の電荷量が０のときの耐圧を１と定義している。グラフの横軸はパッシべーション膜内の電荷量を示している。実効的なパッシべーション膜電荷が正の場合、正電荷が増えると耐圧が急激に低下する。つまり、グラフの右側ではパッシべーション膜の電荷量が変化することで耐圧が急激に変動する。 FIG. 2 is a graph showing the relationship between the effective passivation film charge and the breakdown voltage of the device. The vertical axis of the graph represents the breakdown voltage of the power device, and the breakdown voltage when the charge amount of the passivation film is 0 is defined as 1. The horizontal axis of the graph indicates the amount of charge in the passivation film. In the case where the effective passivation film charge is positive, the breakdown voltage sharply decreases as the positive charge increases. That is, on the right side of the graph, the withstand voltage changes rapidly as the charge amount of the passivation film changes.
　一方、実効的なパッシべーション膜電荷が負の場合は、電荷による耐圧の変動がほとんど見られない。つまり、パッシべーション膜電荷が負の場合、パッシべーション膜電荷が多少正または負に増減しても、パッシべーション膜電荷が正の場合のように急激に耐圧が変化するようなことがない。特に、ブロッキング状態ではパッシべーション膜には正電荷が増加するが、元々のパッシべーション膜電荷が負であれば、図２に示すようにパッシべーション膜電荷が正に変動しても高い耐圧を保つことができる。 On the other hand, when the effective passivation film charge is negative, there is almost no fluctuation in breakdown voltage due to the charge. In other words, if the passivation film charge is negative, even if the passivation film charge increases or decreases somewhat positively or negatively, the withstand voltage may suddenly change as in the case where the passivation film charge is positive. Absent. In particular, in the blocking state, the positive charge increases in the passivation film. However, if the original passivation film charge is negative, it is high even if the passivation film charge varies positively as shown in FIG. The breakdown voltage can be maintained.
　Ａｌ（アルミニウム）またはＴｉ（チタン）を含む金属絶縁膜は負電荷を有するので、これらをパッシべーション膜に用いることにより、耐圧変動が少ない安定したターミネーション構造を実現できる。また、図１に示すように、金属絶縁膜６ｂの下層と上層に第１酸化シリコン膜６ａ、第２酸化シリコン膜６ｃをそれぞれ配置することにより、パッシべーション膜６に高電界がかかる場合でも金属絶縁膜６ｂへの電荷の注入を抑制することができる。これにより、パッシべーション膜６の電荷変動を抑えることができる。 Since a metal insulating film containing Al (aluminum) or Ti (titanium) has a negative charge, a stable termination structure with little fluctuation in breakdown voltage can be realized by using these for the passivation film. In addition, as shown in FIG. 1, the first silicon oxide film 6a and the second silicon oxide film 6c are disposed on the lower layer and the upper layer of the metal insulating film 6b, respectively, so that a high electric field is applied to the passivation film 6. Charge injection into the metal insulating film 6b can be suppressed. Thereby, the charge fluctuation of the passivation film 6 can be suppressed.
　本発明者らが検討した結果、酸化アルミニウム膜の膜厚と負電荷量は図３のグラフに示すような関係があることが明らかになった。図３において、縦軸は酸化アルミニウム膜を含むパッシべーション膜の実効的な負電荷量ＱＦの絶対値を示しており、酸化アルミニウム膜の膜厚が２０ｎｍのときの前記負電荷量を１として定義している。グラフの横軸は酸化アルミニウム膜の膜厚を示している。酸化アルミニウム膜の膜厚を０ｎｍから厚くすると負電荷量が急激に増加するが、膜厚が０．３ｎｍ以上になると負電荷量の増加が非常に緩やかになる。つまり、酸化アルミニウム膜の膜厚が０．３ｎｍ以上あれば、酸化アルミニウム膜内に所望の負電荷を持たせることができる。 As a result of studies by the present inventors, it has been clarified that the film thickness of the aluminum oxide film and the negative charge amount have a relationship as shown in the graph of FIG. 3, the vertical axis represents the absolute value of the effective negative charge amount Q F of passivation film including an aluminum oxide film, the negative charge amount when the film thickness of the aluminum oxide film is 20 nm 1 It is defined as The horizontal axis of the graph indicates the film thickness of the aluminum oxide film. When the thickness of the aluminum oxide film is increased from 0 nm, the negative charge amount increases rapidly. However, when the film thickness is 0.3 nm or more, the increase in the negative charge amount becomes very gradual. That is, if the film thickness of the aluminum oxide film is 0.3 nm or more, a desired negative charge can be provided in the aluminum oxide film.
　一方で、酸化アルミニウム膜の膜厚が厚過ぎると、電気ストレスを与えた際に酸化アルミニウム膜の電荷量が変動しやすくなる。本発明者らの検討の結果、酸化アルミニウム膜の膜厚と、電気ストレスを与えた際のパッシべーション膜の電荷の変動量とは図４のグラフに示すような関係にあることが明らかになった。図４において、縦軸は電気ストレスによる酸化アルミニウム膜を含むパッシべーション膜の電荷の変動量を示しており、膜厚２０ｎｍのときの前記電荷の変動量を１として定義している。グラフの横軸は酸化アルミニウム膜の膜厚を示している。 On the other hand, if the thickness of the aluminum oxide film is too thick, the electric charge of the aluminum oxide film is likely to fluctuate when an electrical stress is applied. As a result of the study by the present inventors, it is clear that the film thickness of the aluminum oxide film and the amount of change in the charge of the passivation film when an electrical stress is applied have a relationship as shown in the graph of FIG. became. In FIG. 4, the vertical axis indicates the amount of change in the charge of the passivation film including the aluminum oxide film due to electrical stress. The amount of change in the charge when the film thickness is 20 nm is defined as 1. The horizontal axis of the graph indicates the film thickness of the aluminum oxide film.
　酸化アルミニウム膜の膜厚が薄いと電荷の変動量が少なくて安定しているが、膜厚が５ｎｍを超えると電荷変動量が大きくなり、さらに１０ｎｍを超えると酸化アルミニウム膜を用いない場合、すなわち図８に示すようにパッシべーション膜１１がＳｉＯ２のみからなるの場合に比べて電荷変動量が５倍以上になってしまう。特にＳｉＣパワーデバイスのようにパッシべーション膜に高電界がかかる場合には電気ストレスが強いために高電界による影響を受けやすい。 If the thickness of the aluminum oxide film is small, the amount of fluctuation in the charge is small and stable, but if the thickness exceeds 5 nm, the amount of fluctuation in the charge increases, and if it exceeds 10 nm, the aluminum oxide film is not used. As shown in FIG. 8, the charge fluctuation amount is five times or more compared to the case where the passivation film 11 is made of only SiO 2 . In particular, when a high electric field is applied to the passivation film as in a SiC power device, it is easily affected by the high electric field due to strong electrical stress.
　上記の事実により、金属絶縁膜の膜厚は０．３ｎｍ以上１０ｎｍ以下であることが重要となる。つまり、金属絶縁膜の膜厚が０．３ｎｍ以上あれば十分な電荷量を持たせることができるが、膜厚が１０ｎｍよりも大きくなると金属絶縁膜内の電荷量が不安定になるため、膜厚を１０ｎｍ以下とする必要がある。また、より好ましくは、金属絶縁膜の膜厚は０．３ｎｍ以上５ｎｍ以下であることが望ましい。これにより、電気ストレスに対してより安定した電荷を有するパッシべーション膜を提供できる。 Due to the above facts, it is important that the thickness of the metal insulating film is not less than 0.3 nm and not more than 10 nm. That is, if the thickness of the metal insulating film is 0.3 nm or more, a sufficient amount of charge can be provided, but if the thickness is larger than 10 nm, the amount of charge in the metal insulating film becomes unstable. The thickness needs to be 10 nm or less. More preferably, the thickness of the metal insulating film is from 0.3 nm to 5 nm. Thereby, a passivation film having a more stable charge against electrical stress can be provided.
　また、基板の主面がドライエッチングによってダメージを受けることを避けることなどを目的として、ウェットエッチングによって金属絶縁膜を加工する場合には、金属絶縁膜の膜厚は０．３ｎｍ以上１ｎｍ以下であることがさらに望ましい。これにより、エッチング残りがなく、金属絶縁膜と、その上下に位置する酸化シリコン膜を連続して加工することが可能である。 When the metal insulating film is processed by wet etching for the purpose of avoiding damage to the main surface of the substrate by dry etching, the thickness of the metal insulating film is not less than 0.3 nm and not more than 1 nm. More desirable. Thereby, there is no etching residue, and the metal insulating film and the silicon oxide film positioned above and below the metal insulating film can be processed continuously.
　なお、ターミネーション構造のｐ型不純物領域の濃度、幅、深さ等の構造設計によってパッシべーション膜にかかる電界を制御できるため、厚膜のｈｉｇｈ－ｋ膜を形成せずともパッシべーション膜の絶縁破壊の防止およびリーク電流の低減が可能であり、デバイスを高耐圧化できる。したがって、図１に示すように、必ずしもパッシべーション膜６内に誘電率が高く膜厚が厚いｈｉｇｈ－ｋ膜を形成する必要はない。膜厚が厚いｈｉｇｈ－ｋ膜は電気ストレスが印加された際に絶縁膜電荷量の安定性が低くなるが、図１に示す半導体装置では、パッシべーション膜６内に膜厚が厚いｈｉｇｈ－ｋ膜を形成していないため、パッシべーション膜６の電荷量が変動することを防ぐことが可能である。 Since the electric field applied to the passivation film can be controlled by the structure design such as the concentration, width, and depth of the p-type impurity region of the termination structure, the thickness of the passivation film can be reduced without forming a thick high-k film. Insulation breakdown can be prevented and leakage current can be reduced, and the device can have a high breakdown voltage. Therefore, as shown in FIG. 1, it is not always necessary to form a high-k film having a high dielectric constant and a large film thickness in the passivation film 6. Although the high-k film having a large film thickness is less stable in the charge amount of the insulating film when an electrical stress is applied, in the semiconductor device shown in FIG. 1, the high-k film having a large film thickness in the passivation film 6 is used. Since the k film is not formed, it is possible to prevent the charge amount of the passivation film 6 from fluctuating.
　本実施の形態の半導体装置では、図１に示すように膜厚が０．３ｎｍ以上１０ｎｍ以下である金属絶縁膜６ｂを用いてパッシべーション膜６を構成することにより、電界の影響を受けにくく安定した電荷を保つことができるターミネーション構造を実現している。また、金属絶縁膜６ｂを酸化アルミニウム膜により構成することで金属絶縁膜６ｂを負電荷を持つ絶縁膜としているため、図２を用いて説明したように、ブロッキング状態における高電界によりパッシべーション膜６内の正電荷が増大しても、パッシべーション膜６の高い耐圧を保つことができる。 In the semiconductor device of the present embodiment, as shown in FIG. 1, the passivation film 6 is formed using a metal insulating film 6b having a film thickness of 0.3 nm or more and 10 nm or less, so that it is hardly affected by an electric field. A termination structure that can maintain a stable charge is realized. Further, since the metal insulating film 6b is made of an aluminum oxide film, the metal insulating film 6b is an insulating film having a negative charge. Therefore, as described with reference to FIG. 2, the passivation film is formed by a high electric field in the blocking state. Even if the positive charge in 6 increases, the high breakdown voltage of the passivation film 6 can be maintained.
　したがって、ＳｉＣパワーデバイスを有する半導体装置のターミネーション領域において、高電界が印加されてもパッシべーション膜内の電荷を安定させることができ、パッシべーション膜の耐圧の変動量を低減し、高い耐圧を安定して維持することができる。このため、表面電極８のエッジ部へ電気力線が集中することで流れるリーク電流の発生を防ぎ、絶縁膜の信頼性（電気ストレス印加による絶縁膜電荷量の安定性）を向上し、パワーデバイスの耐圧、すなわちダイオードのアノード－カソード間耐圧またはトランジスタのソース－ドレイン耐圧などが変動してしまうことを防ぐことができる。これにより、半導体装置の信頼性を向上することができる。 Therefore, in the termination region of a semiconductor device having a SiC power device, the charge in the passivation film can be stabilized even when a high electric field is applied, and the amount of fluctuation in the breakdown voltage of the passivation film is reduced, resulting in a high breakdown voltage. Can be maintained stably. For this reason, the generation of leakage current that flows due to the concentration of electric lines of force on the edge portion of the surface electrode 8 is prevented, and the reliability of the insulating film (the stability of the charge amount of the insulating film due to the application of electrical stress) is improved. It is possible to prevent the withstand voltage of the transistor, that is, the anode-cathode withstand voltage of the diode or the source-drain withstand voltage of the transistor from fluctuating. Thereby, the reliability of the semiconductor device can be improved.
　つまり、パッシべーション膜６中に負の固定電荷を有する金属絶縁膜６ｂを挿入することにより、実効的なパッシべーション膜電荷を負にすることができる。これにより、パッシべーション膜への高電界印加があっても、耐圧変動が少ない安定なターミネーション構造を提供することを可能としている。 That is, by inserting the metal insulating film 6 b having a negative fixed charge into the passivation film 6, the effective passivation film charge can be made negative. As a result, it is possible to provide a stable termination structure with little fluctuation in breakdown voltage even when a high electric field is applied to the passivation film.
　以下に、本実施の形態の半導体装置の製造方法を図面を用いて説明する。図５～図１０は、製造工程中の半導体装置の断面図を示すものである。なお、ここではアクティブ領域は図示せず、アクティブ領域に形成される高耐圧素子の製造工程の説明は省略するが、ターミネーション構造の形成と同時に、アクティブ領域についてもデバイス構造に従って半導体素子が形成されることは言うまでもない。 Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to the drawings. 5 to 10 are cross-sectional views of the semiconductor device during the manufacturing process. Here, the active region is not shown, and the description of the manufacturing process of the high breakdown voltage element formed in the active region is omitted, but at the same time as the termination structure is formed, a semiconductor element is formed in the active region according to the device structure. Needless to say.
　まず、図５に示すように、ＳｉＣ基板であるｎ＋型基板１上に、ｎ－型ドリフト層２が積層された基体を準備する。ｎ－型ドリフト層２はエピタキシャル成長法によりｎ＋型基板１上に形成されたｎ型のＳｉＣ膜である。 First, as shown in FIG. 5, a base is prepared in which an n − type drift layer 2 is laminated on an n + type substrate 1 which is a SiC substrate. The n − type drift layer 2 is an n type SiC film formed on the n + type substrate 1 by an epitaxial growth method.
　次に、図６に示すように、ｎ－型ドリフト層２の上面に酸化シリコン膜などからなる絶縁膜を形成した後、当該絶縁膜をパターニングすることでイオン注入用のマスクＭ１を形成し、続いてｐ型の不純物（例えばＡｌ（アルミニウム））をｎ－型ドリフト層２の上面にイオン注入してｐ型ガードリング領域３を形成する。このときｐ型ガードリング領域３は、ドーピング濃度を１×１０１８ｃｍ－３～２×１０２０ｃｍ－３程度とし、厚さ（接合深さ）を０．５～２．０μｍ程度として形成する。 Next, as shown in FIG. 6, after forming an insulating film made of a silicon oxide film or the like on the upper surface of the n − type drift layer 2, the insulating film is patterned to form an ion implantation mask M1. Subsequently, p-type impurities (for example, Al (aluminum)) are ion-implanted into the upper surface of the n − -type drift layer 2 to form the p-type guard ring region 3. At this time, the p-type guard ring region 3 is formed with a doping concentration of about 1 × 10 18 cm −3 to 2 × 10 20 cm −3 and a thickness (junction depth) of about 0.5 to 2.0 μm. .
　次に、図７に示すように、マスクＭ１を除去した後、ｎ－型ドリフト層２上およびｐ型ガードリング領域３上に酸化シリコン膜などからなるパターニングされたイオン注入用のマスクＭ２を形成する。続いて、マスクＭ２から露出しているｎ－型ドリフト層２の上面にｐ型の不純物（例えばＡｌ（アルミニウム））をイオン注入してｐ型ＪＴＥ領域４を形成する。このときｐ型ＪＴＥ領域４は、ドーピング濃度を５×１０１６ｃｍ－３～１×１０１８ｃｍ－３程度とし、厚さ０．５～２．０μｍ程度で形成する。ここでは、ｐ型ガードリング領域３に隣接させてｐ型ＪＴＥ領域４を形成させる。 Next, as shown in FIG. 7, after removing the mask M1, a patterned ion implantation mask M2 made of a silicon oxide film or the like is formed on the n − -type drift layer 2 and the p-type guard ring region 3. To do. Subsequently, p-type impurities (for example, Al (aluminum)) are ion-implanted into the upper surface of the n − -type drift layer 2 exposed from the mask M2, thereby forming the p-type JTE region 4. At this time, the p-type JTE region 4 is formed with a doping concentration of about 5 × 10 16 cm −3 to 1 × 10 18 cm −3 and a thickness of about 0.5 to 2.0 μm. Here, the p-type JTE region 4 is formed adjacent to the p-type guard ring region 3.
　次に、図８に示すように、マスクＭ２を除去した後、ｎ－型ドリフト層２上、ｐ型ガードリング領域３上およびｐ型ＪＴＥ領域４上に酸化シリコン膜などからなるパターニングされたイオン注入用のマスクＭ３を形成する。続いて、マスクＭ３から露出しているｎ－型ドリフト層２の上面にｎ型の不純物（例えばＮ（窒素））をイオン注入してｎ＋型フィールドストップ領域５を形成する。ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５は、ｎ－型ドリフト層２上面のアクティブ領域（図示しない）を囲むようにアクティブ領域の外側に向かって順に形成する。 Next, as shown in FIG. 8, after removing the mask M2, patterned ions made of a silicon oxide film or the like on the n − type drift layer 2, the p type guard ring region 3 and the p type JTE region 4 are formed. An implantation mask M3 is formed. Subsequently, an n + type field stop region 5 is formed by ion implantation of an n type impurity (for example, N (nitrogen)) on the upper surface of the n − type drift layer 2 exposed from the mask M3. The p-type guard ring region 3, the p-type JTE region 4 and the n + -type field stop region 5 are formed in order toward the outside of the active region so as to surround the active region (not shown) on the upper surface of the n − -type drift layer 2. .
　つまり、後にｎ＋型基板１をダイシングにより個片化して形成する半導体チップの中央部のアクティブ領域を囲むように、前記中央部（図８の左側）から半導体チップの端部（図８の右側）に向かってｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５が順に配置されている。平面視においては、ｎ－型ドリフト層２の上面のアクティブ領域を囲むようにｐ型ガードリング領域３を形成し、ｐ型ガードリング領域３を囲むようにｐ型ＪＴＥ領域４を形成し、ｐ型ＪＴＥ領域４を囲むようにｎ＋型フィールドストップ領域５を形成する。続いて、マスクＭ３を除去した後、注入されたＡｌ（アルミニウム）およびＮ（窒素）を活性化するためにｎ＋型基板１を含む製造工程中の半導体装置を例えば１７００℃で熱処理する。 That is, from the central portion (left side in FIG. 8) to the end portion of the semiconductor chip (right side in FIG. 8) so as to surround the active region in the central portion of the semiconductor chip that is formed by dicing the n + type substrate 1 later by dicing. P-type guard ring region 3, p-type JTE region 4 and n + -type field stop region 5 are arranged in this order. In plan view, the p-type guard ring region 3 is formed so as to surround the active region on the upper surface of the n − -type drift layer 2, the p-type JTE region 4 is formed so as to surround the p-type guard ring region 3, and p An n + type field stop region 5 is formed so as to surround the type JTE region 4. Subsequently, after removing the mask M3, the semiconductor device in the manufacturing process including the n + type substrate 1 is heat-treated at, for example, 1700 ° C. in order to activate the implanted Al (aluminum) and N (nitrogen).
　次に、図９に示すように、熱酸化またはＣＶＤ（Chemical Vapor Deposition：化学気相成長）法、もしくはその両者の組合せによりｎ－型ドリフト層２上に第１酸化シリコン膜６ａを形成する。次に第１酸化シリコン膜６ａ上に金属絶縁膜６ｂおよび第２酸化シリコン膜６ｃをＣＶＤ法などを用いて順次形成し、第１酸化シリコン膜６ａ、金属絶縁膜６ｂおよび第２酸化シリコン膜６ｃからなるパッシべーション膜６を形成する。第１酸化シリコン膜６ａおよび第２酸化シリコン膜６ｃはＳｉＯ２膜であり、金属絶縁膜６ｂはアルミ酸化物を含む絶縁膜であり、ここではＡｌ２Ｏ３膜により構成する。また、金属絶縁膜６ｂの膜厚は０．３ｎｍ以上１０ｎｍ以下である。 Next, as shown in FIG. 9, a first silicon oxide film 6a is formed on the n − -type drift layer 2 by thermal oxidation, CVD (Chemical Vapor Deposition), or a combination of both. Next, a metal insulating film 6b and a second silicon oxide film 6c are sequentially formed on the first silicon oxide film 6a using a CVD method or the like, and the first silicon oxide film 6a, the metal insulating film 6b, and the second silicon oxide film 6c are formed. A passivation film 6 is formed. The first silicon oxide film 6a and the second silicon oxide film 6c are SiO 2 films, and the metal insulating film 6b is an insulating film containing aluminum oxide, and here is composed of an Al 2 O 3 film. The thickness of the metal insulating film 6b is not less than 0.3 nm and not more than 10 nm.
　続いて、パッシべーション膜６上にパターニングされたマスクＭ４を形成し、パッシべーション膜６をドライエッチまたはウェットエッチにより加工することで、ｐ型ガードリング領域３およびｎ＋型フィールドストップ領域５を露出させる。マスクＭ４は例えばフォトリソグラフィ技術を用いて形成したフォトレジスト膜であるものとする。 Subsequently, a patterned mask M4 is formed on the passivation film 6, and the passivation film 6 is processed by dry etching or wet etching, so that the p-type guard ring region 3 and the n + -type field stop region 5 are processed. To expose. The mask M4 is assumed to be a photoresist film formed using, for example, a photolithography technique.
　次に、図１０に示すように、マスクＭ４を除去した後、ｎ＋型基板１の主面の反対側の表面である裏面に裏面電極７を形成する。裏面電極７は例えばＡｌ（アルミニウム）をスパッタリングするなどして形成しても良いが、ＮｉＳｉまたはＴｉＳｉなどにより形成してもよい。次に、ｎ－型ドリフト層２の上面およびパッシべーション膜６の表面を覆うように例えばＡｌ（アルミニウム）からなる金属膜をスパッタリング法などにより形成した後、前記金属膜をパターニングしてパッシべーション膜６の上面を露出させる。このとき、パッシべーション膜６の両端の上面は露出させない。したがって、環状の平面形状を有するパッシべーション膜６の内側（アクティブ領域側）および外側に前記金属膜からなる表面電極８およびフローティング電極９がそれぞれ形成される。つまり、表面電極８はパッシべーション膜６に対してアクティブ領域側に形成され、フローティング電極９はパッシべーション膜６に対してアクティブ領域の反対側に形成される。表面電極８およびフローティング電極９は、いずれもその一部がパッシべーション膜６の端部の乗り上げるように形成される。 Next, as shown in FIG. 10, after removing the mask M < b > 4, the back surface electrode 7 is formed on the back surface that is the surface opposite to the main surface of the n + type substrate 1. The back electrode 7 may be formed by sputtering Al (aluminum), for example, but may be formed by NiSi or TiSi. Next, after forming a metal film made of, for example, Al (aluminum) so as to cover the upper surface of the n − -type drift layer 2 and the surface of the passivation film 6, the metal film is patterned to form a passivation film. The upper surface of the passivation film 6 is exposed. At this time, the upper surfaces of both ends of the passivation film 6 are not exposed. Accordingly, the surface electrode 8 and the floating electrode 9 made of the metal film are formed on the inner side (active region side) and the outer side of the passivation film 6 having an annular planar shape, respectively. That is, the surface electrode 8 is formed on the active region side with respect to the passivation film 6, and the floating electrode 9 is formed on the opposite side of the active region with respect to the passivation film 6. Both the surface electrode 8 and the floating electrode 9 are formed so that a part thereof rides on the end portion of the passivation film 6.
　以上のようにして、アクティブ領域においてパワーデバイスの一部と電気的に接続される表面電極８と、ｎ＋型フィールドストップ領域５に電気的に接続するフローティング電極９とを形成することにより、図１０に示すターミネーション構造が完成する。なお、ｐ型ガードリング領域３とｐ型ＪＴＥ領域４の深さは同一である必要はない。また、ｐ型ＪＴＥ領域４は単一の領域である必要はなく、複数の領域で形成されていてもよい。つまり、ｐ型ＪＴＥ領域４を比較的不純物濃度が高い半導体領域と、それよりも不純物濃度が低い半導体領域とで形成し、ｐ型ＪＴＥ領域４に濃度勾配を持たせてもよい。また、ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４、およびｎ＋型フィールドストップ領域５の形成順序は上記の通りである必要はない。 As described above, the surface electrode 8 electrically connected to a part of the power device in the active region and the floating electrode 9 electrically connected to the n + type field stop region 5 are formed. The termination structure shown in FIG. 10 is completed. Note that the p-type guard ring region 3 and the p-type JTE region 4 need not have the same depth. Further, the p-type JTE region 4 does not have to be a single region, and may be formed of a plurality of regions. That is, the p-type JTE region 4 may be formed of a semiconductor region having a relatively high impurity concentration and a semiconductor region having a lower impurity concentration, and the p-type JTE region 4 may have a concentration gradient. Further, the order of forming the p-type guard ring region 3, the p-type JTE region 4, and the n + -type field stop region 5 need not be as described above.
　この後は、ｎ＋型基板１をダイシングをすることで個片化して複数の半導体チップを形成することで本実施の形態の半導体装置が完成する。ダイシングを行う前にｎ＋型基板１上の全面を覆う絶縁膜を形成しても構わない。また、半導体チップをポリイミドなどからなる樹脂膜により覆ってもよい。なお、ｎ＋型フィールドストップ領域５はダイシングにより形成された半導体チップの端部に近い領域に位置し、ｐ型ガードリング領域３はｎ＋型フィールドストップ領域５よりも半導体チップの中心部に近い領域位置することになる。 Thereafter, the semiconductor device of the present embodiment is completed by dicing the n + type substrate 1 into pieces to form a plurality of semiconductor chips. An insulating film covering the entire surface of the n + type substrate 1 may be formed before dicing. Further, the semiconductor chip may be covered with a resin film made of polyimide or the like. The n + -type field stop region 5 is located near the end of the semiconductor chip formed by dicing, and the p-type guard ring region 3 is closer to the center of the semiconductor chip than the n + -type field stop region 5. The area will be located.
　本実施の形態においては金属絶縁膜６ｂの部材としてアルミ酸化物を例示したが、本発明はこれに限定されるものではなくアルミ窒化物またはチタン酸化物であってもよい。つまり、金属絶縁膜６ｂは負の電荷を有する絶縁膜であればよいため、様々な部材を用いることができる。 In the present embodiment, aluminum oxide is exemplified as a member of the metal insulating film 6b, but the present invention is not limited to this, and may be aluminum nitride or titanium oxide. That is, since the metal insulating film 6b may be an insulating film having a negative charge, various members can be used.
　また、上述したように、金属絶縁膜６ｂの膜厚は０．３ｎｍ以上５ｎｍ以下であることがより好ましい。これにより、電気ストレスに対して安定なパッシべーション膜を提供できる。 Further, as described above, the thickness of the metal insulating film 6b is more preferably 0.3 nm or more and 5 nm or less. As a result, a passivation film that is stable against electrical stress can be provided.
　また、ウェットプロセスによって金属絶縁膜６ｂを加工する場合には、金属絶縁膜６ｂの膜厚は０．３ｎｍ以上１ｎｍ以下であることがさらに好ましい。これにより、エッチング残りがなく、金属絶縁膜６ｂと、その上下に位置する第１酸化シリコン膜６ａとを連続して加工することが可能である。 Further, when the metal insulating film 6b is processed by a wet process, the thickness of the metal insulating film 6b is more preferably 0.3 nm or more and 1 nm or less. As a result, there is no etching residue, and the metal insulating film 6b and the first silicon oxide film 6a positioned above and below the metal insulating film 6b can be processed continuously.
　また、本実施の形態においてはターミネーション構造をＪＴＥとしたが、図１１に示すように、ターミネーション構造をＦＬＲとしても同様の効果を得ることが可能である。図１１は本実施の形態の半導体装置の変形例を示す断面図であり、ｎ－型ドリフト層２の上面にはｐ型ＪＴＥ領域４の代わりにｐ型半導体領域４ａが複数形成されている。複数のｐ型半導体領域４ａのそれぞれはｐ型ガードリング領域３と同様に環状の平面形状を有し、アクティブ領域およびｐ型ガードリング領域３を囲むように配置されている。このように複数のｐ型半導体領域４ａを形成することにより、ターミネーション領域に印加される電界を緩和することができる。 In this embodiment, the termination structure is JTE. However, as shown in FIG. 11, the same effect can be obtained even if the termination structure is FLR. FIG. 11 is a cross-sectional view showing a modification of the semiconductor device according to the present embodiment. A plurality of p-type semiconductor regions 4 a are formed on the upper surface of the n − -type drift layer 2 instead of the p-type JTE region 4. Each of the plurality of p-type semiconductor regions 4 a has an annular planar shape like the p-type guard ring region 3 and is disposed so as to surround the active region and the p-type guard ring region 3. By forming the plurality of p-type semiconductor regions 4a in this way, the electric field applied to the termination region can be relaxed.
　また、第１酸化シリコン膜６ａを形成する際に、一酸化窒素または一酸化二窒素などで酸窒化するか、もしくはアニールを行うと第１酸化シリコン膜６ａのＳｉＣからなるｎ－型ドリフト層２との界面近傍の第１酸化シリコン膜６ａ内にＮ（窒素）を導入することができる。これによりｎ－型ドリフト層２とパッシべーション膜６との界面におけるトラップ（トラップ準位）を低減することは、実効的なパッシべーション膜電荷の変動を抑制するために効果的である。 Further, when the first silicon oxide film 6a is formed, the n − type drift layer 2 made of SiC of the first silicon oxide film 6a is formed by oxynitriding with nitrogen monoxide or dinitrogen monoxide or annealing. N (nitrogen) can be introduced into the first silicon oxide film 6a in the vicinity of the interface. Thus, reducing the trap (trap level) at the interface between the n − -type drift layer 2 and the passivation film 6 is effective for suppressing the fluctuation of the effective passivation film charge.
　上記の製造工程により形成された本実施の形態の半導体装置では、０．３ｎｍ以上１０ｎｍ以下の膜厚で負の電荷を有する金属絶縁膜をパッシべーション膜内に設けることにより、上述したようにＳｉＣパワーデバイスを有する装置のターミネーション領域において、高電界が印加されてもパッシべーション膜内の電荷を安定させることができる。したがって、パワーデバイスの耐圧が変動することを防ぐことができるため、半導体装置の信頼性を向上することができる。 In the semiconductor device of the present embodiment formed by the manufacturing process described above, a metal insulating film having a thickness of 0.3 nm to 10 nm and having a negative charge is provided in the passivation film, as described above. In the termination region of an apparatus having a SiC power device, the charge in the passivation film can be stabilized even when a high electric field is applied. Therefore, it is possible to prevent the breakdown voltage of the power device from fluctuating, so that the reliability of the semiconductor device can be improved.
　（実施の形態２）
　本実施の形態によるＳｉＣを含む半導体装置のターミネーション領域の断面図を図１２を用いて説明する。図１２は本実施の形態の半導体装置の断面図であり、図１に示すターミネーション構造とほぼ同様の構造を示している。ただし、本実施の形態の半導体装置は、パッシべーション膜６が基板上に順に積層された第１酸化シリコン膜６ａ、窒化シリコン（ＳｉＮ）膜６ｄ、金属絶縁膜６ｂ、窒化シリコン膜６ｅおよび第２酸化シリコン膜６ｃの５層を少なくとも有する点で前記実施の形態１とは異なる。 (Embodiment 2)
A cross-sectional view of the termination region of the semiconductor device containing SiC according to the present embodiment will be described with reference to FIG. FIG. 12 is a cross-sectional view of the semiconductor device according to the present embodiment, and shows a structure substantially similar to the termination structure shown in FIG. However, in the semiconductor device of the present embodiment, the first silicon oxide film 6a, the silicon nitride (SiN) film 6d, the metal insulating film 6b, the silicon nitride film 6e, and the first film in which the passivation film 6 is sequentially stacked on the substrate. It differs from the first embodiment in that it has at least five layers of the silicon dioxide film 6c.
　つまり、パッシべーション膜６はｎ－型ドリフト層２の上面上に順に積層された第１酸化シリコン膜６ａ、窒化シリコン膜６ｄ、金属絶縁膜６ｂ、窒化シリコン膜６ｅおよび第２酸化シリコン膜６ｃからなる積層膜により構成されており、金属絶縁膜６ｂは例えばアルミ酸化物などの金属酸化膜からなる。金属絶縁膜６ｂの膜厚は０．３ｎｍ以上であり、窒化シリコン膜６ｄ、金属絶縁膜６ｂおよび窒化シリコン膜６ｅの膜厚の和は１０ｎｍ以下である。なお、パッシべーション膜６の上部に絶縁膜をさらに備えていてもよい。 That is, the passivation film 6 includes the first silicon oxide film 6a, the silicon nitride film 6d, the metal insulating film 6b, the silicon nitride film 6e, and the second silicon oxide film 6c that are sequentially stacked on the upper surface of the n − type drift layer 2. The metal insulating film 6b is made of a metal oxide film such as aluminum oxide, for example. The thickness of the metal insulating film 6b is 0.3 nm or more, and the sum of the thicknesses of the silicon nitride film 6d, the metal insulating film 6b, and the silicon nitride film 6e is 10 nm or less. Note that an insulating film may be further provided on the passivation film 6.
　このターミネーション構造の動作としては、裏面電極７と表面電極８との間に電圧が印加されたブロッキング状態においては、裏面電極７から表面電極８に向かって電気力線が伸びる。表面電極８のエッジ部分には電気力線が集中しやすいが、ｐ型ガードリング領域３とｐ型ＪＴＥ領域４によって電気力線が横方向に広げられるため、表面電極８のエッジ部分における電界集中を緩和できる。パッシべーション膜６には負電荷を持つ金属絶縁膜６ｂを用いているため、パッシべーション膜６にかかる高電界によって実効的なパッシべーション膜電荷が変動したとしても表面電極８への電気力線の集中を防ぐことができる。このため、耐圧変動を抑制することが可能である。 As an operation of this termination structure, in the blocking state in which a voltage is applied between the back electrode 7 and the front electrode 8, electric lines of force extend from the back electrode 7 to the front electrode 8. Electric field lines tend to concentrate on the edge portion of the surface electrode 8, but the electric field lines are spread laterally by the p-type guard ring region 3 and the p-type JTE region 4. Can be relaxed. Since the metal film 6b having a negative charge is used for the passivation film 6, even if the effective passivation film charge fluctuates due to a high electric field applied to the passivation film 6, the electricity to the surface electrode 8 is changed. Concentration of field lines can be prevented. For this reason, it is possible to suppress withstand voltage fluctuation.
　本実施の形態で示した酸化シリコン膜、窒化シリコン膜、金属絶縁膜からなる積層絶縁膜からなるパッシべーション膜においては、窒化シリコン膜がない積層絶縁膜に比べて膜自体の信頼性が向上する。具体的には絶縁破壊するまでの寿命、および実効的な絶縁膜電荷の安定性などが向上する。 In the passivation film made of a laminated insulating film made of a silicon oxide film, a silicon nitride film, or a metal insulating film shown in this embodiment, the reliability of the film itself is improved as compared with a laminated insulating film without a silicon nitride film. To do. Specifically, the life until dielectric breakdown and the stability of effective insulating film charge are improved.
　なお、本実施の形態のように窒化シリコン膜により金属絶縁膜を挟んでいる場合、窒化シリコン膜の膜厚が厚すぎると、図４を用いて説明した特性と同様に、金属絶縁膜の電荷の変動量が大きくなる。このため、本実施の形態では窒化シリコン膜６ｄ、金属絶縁膜６ｂおよび窒化シリコン膜６ｅの膜厚の総和を１０ｎｍ以下とすることで、パッシベーション膜６内の電荷を安定させ、デバイスの耐圧を向上させることを可能としている。 Note that in the case where the metal insulating film is sandwiched between silicon nitride films as in this embodiment, if the silicon nitride film is too thick, the charge of the metal insulating film is similar to the characteristics described with reference to FIG. The fluctuation amount of becomes larger. For this reason, in this embodiment, the total film thickness of the silicon nitride film 6d, the metal insulating film 6b, and the silicon nitride film 6e is set to 10 nm or less, thereby stabilizing the charge in the passivation film 6 and improving the breakdown voltage of the device. It is possible to make it.
　本実施の形態の半導体装置を製造する際は、前記実施の形態１で図５～図１０を用いて説明した工程とほぼ同様の工程を行うことで図１２に示す半導体装置を形成することができるが、パッシべーション膜６の構造が前記実施の形態１とは異なる。したがって、図９を用いて説明した工程では、熱酸化またはＣＶＤ法、もしくはその両者の組合せにより第１酸化シリコン膜６ａを形成した後に、窒化シリコン膜６ｄ、金属絶縁膜６ｂ、窒化シリコン膜６ｅ、第２酸化シリコン膜６ｃを順次ＣＶＤ法などを用いて積層し、これにより形成された積層絶縁膜をパターニングすることでパッシべーション膜６を形成する。 When manufacturing the semiconductor device of this embodiment, the semiconductor device shown in FIG. 12 can be formed by performing substantially the same steps as those described in Embodiment 1 with reference to FIGS. However, the structure of the passivation film 6 is different from that of the first embodiment. Therefore, in the process described with reference to FIG. 9, after the first silicon oxide film 6a is formed by thermal oxidation or CVD, or a combination of both, the silicon nitride film 6d, the metal insulating film 6b, the silicon nitride film 6e, The passivation film 6 is formed by sequentially laminating the second silicon oxide film 6c using the CVD method or the like and patterning the laminated insulating film formed thereby.
　ここで金属絶縁膜６ｂの膜厚は０．３ｎｍ以上であり、窒化シリコン膜６ｄ、金属絶縁膜６ｂおよび窒化シリコン膜６ｅの膜厚の和は１０ｎｍ以下である。金属絶縁膜は例えばアルミ酸化物である。この後の工程は前記実施の形態１と同様に行うことで、図１２に示すターミネーション構造が完成する。なお、ｐ型ガードリング領域３とｐ型ＪＴＥ領域４の深さは同一である必要はない。また、ｐ型ＪＴＥ領域４は単一の領域である必要はなく、複数の領域で形成されていてもよい。 Here, the film thickness of the metal insulating film 6b is 0.3 nm or more, and the sum of the film thicknesses of the silicon nitride film 6d, the metal insulating film 6b, and the silicon nitride film 6e is 10 nm or less. The metal insulating film is, for example, aluminum oxide. The subsequent steps are performed in the same manner as in the first embodiment, thereby completing the termination structure shown in FIG. Note that the p-type guard ring region 3 and the p-type JTE region 4 need not have the same depth. Further, the p-type JTE region 4 does not have to be a single region, and may be formed of a plurality of regions.
　本実施の形態で示した酸化シリコン膜、窒化シリコン膜、金属絶縁膜からなる積層絶縁膜においては、窒化シリコン膜がない積層絶縁膜に比べて積層絶縁膜自体の信頼性が向上することが確認できた。具体的には絶縁破壊するまでの寿命、実効的な絶縁膜電荷の安定性などが向上した。 It has been confirmed that the reliability of the stacked insulating film itself is improved in the stacked insulating film including the silicon oxide film, the silicon nitride film, and the metal insulating film described in this embodiment as compared with the stacked insulating film without the silicon nitride film. did it. Specifically, the life until breakdown and the stability of the effective insulating film charge were improved.
　本実施の形態においては金属絶縁膜としてアルミ酸化物を例示したが、本発明はこれに限定されるものではなくアルミ窒化物またはチタン酸化物であってもよい。また、本実施の形態においてはターミネーション構造をＪＴＥとしたが、ターミネーション構造をＦＬＲとしても同様の効果を得ることが可能である。 In the present embodiment, aluminum oxide is exemplified as the metal insulating film, but the present invention is not limited to this and may be aluminum nitride or titanium oxide. In the present embodiment, the termination structure is JTE, but the same effect can be obtained even if the termination structure is FLR.
　また、第１酸化シリコン膜６ａを形成する際に、一酸化窒素または一酸化二窒素などで酸窒化するか、もしくはアニールを行うと第１酸化シリコン膜６ａのＳｉＣからなるｎ－型ドリフト層２との界面近傍の第１酸化シリコン膜６ａ内にＮ（窒素）を導入することができる。これによりｎ－型ドリフト層２とパッシべーション膜６との界面におけるトラップを低減することは、実効的なパッシべーション膜電荷の変動を抑制するために効果的である。 Further, when the first silicon oxide film 6a is formed, the n − type drift layer 2 made of SiC of the first silicon oxide film 6a is formed by oxynitriding with nitrogen monoxide or dinitrogen monoxide or annealing. N (nitrogen) can be introduced into the first silicon oxide film 6a in the vicinity of the interface. Thus, reducing traps at the interface between the n − -type drift layer 2 and the passivation film 6 is effective for suppressing fluctuations in effective passivation film charge.
　（実施の形態３）
　本実施の形態におけるＳｉＣ基板上のアクティブ領域に形成されたＭＯＳＦＥＴおよびターミネーション領域を含む断面図を図１３に示す。図１３に示すように、図の右側のターミネーション領域は図１に示す前記実施の形態１のターミネーション構造と同様の構造を有している。ただし、パッシべーション膜２７はｎ－型ドリフト層２上に順に形成された第１酸化シリコン膜２７ａ、金属絶縁膜２７ｂ、第２酸化シリコン膜２７ｃおよび絶縁膜２７ｄにより構成されている。 (Embodiment 3)
FIG. 13 shows a cross-sectional view including the MOSFET and termination region formed in the active region on the SiC substrate in the present embodiment. As shown in FIG. 13, the termination region on the right side of the figure has the same structure as the termination structure of the first embodiment shown in FIG. However, the passivation film 27 includes a first silicon oxide film 27a, a metal insulating film 27b, a second silicon oxide film 27c, and an insulating film 27d that are sequentially formed on the n − type drift layer 2.
　また、図１３の左側に示すアクティブ領域には高耐圧なＭＯＳＦＥＴが形成されている。ＭＯＳＦＥＴはｎ－型ドリフト層２上にｎ－型ドリフト層２上側から順に積層された第１酸化シリコン膜２４ａ、金属絶縁膜２４ｂおよび第２酸化シリコン膜２４ｃからなるゲート絶縁膜２４を介して形成されたゲート電極２５と、ゲート電極２５の両側のｎ－型ドリフト層２の上面に形成されたｎ＋型ソース領域２２と、ドレイン領域であるｎ＋型基板１とを有している。つまり、ｎ＋型基板１に接する裏面電極７はＭＯＳＦＥＴのドレイン領域に電位を供給するドレイン電極である。また、ｎ＋型ソース領域２２に電気的に接続されている表面電極８は、ｎ＋型ソース領域２２に電位を供給するソース電極である。 Further, a high breakdown voltage MOSFET is formed in the active region shown on the left side of FIG. MOSFET the n - formed via a gate insulating film 24 made of the first silicon oxide film 24a from the type drift layer 2 above are laminated in this order, a metal insulating film 24b and the second silicon oxide film 24c - -type drift layer 2 on the n Gate electrode 25, n + type source region 22 formed on the upper surface of n − type drift layer 2 on both sides of gate electrode 25, and n + type substrate 1 serving as a drain region. That is, the back electrode 7 in contact with the n + type substrate 1 is a drain electrode that supplies a potential to the drain region of the MOSFET. The surface electrode 8 to the n + -type source regions 22 are electrically connected is a source electrode supplying a potential to the n + -type source region 22.
　ゲート絶縁膜２４はｎ－型ドリフト層２および当該ｎ－型ドリフト層２の両側にそれぞれ形成されたｐ型ベース領域２１およびｎ＋型ソース領域２２のいずれの上面にも接しており、ゲート電極２５は、平面視においてｎ－型ドリフト層２および当該ｎ－型ドリフト層２の両側にそれぞれ形成されたｐ型ベース領域２１およびｎ＋型ソース領域２２のいずれとも重なる位置に形成されている。つまりゲート絶縁膜２４は、ｎ－型ドリフト層２、ｐ型ベース領域２１およびｎ＋型ソース領域２２のそれぞれの直上において連続的に形成されており、ゲート電極２５も、ｎ－型ドリフト層２、ｐ型ベース領域２１およびｎ＋型ソース領域２２のそれぞれの直上において連続的に形成されている。 The gate insulating film 24 is in contact with the upper surfaces of the n − type drift layer 2 and the p type base region 21 and the n + type source region 22 formed on both sides of the n − type drift layer 2, respectively. 25, n in plan view - it is formed in either the even positions overlapping the p-type is formed on both sides of the type drift layer 2 base region 21 and n + -type source region 22 - -type drift layer 2 and the n. That is, the gate insulating film 24 is continuously formed immediately above each of the n − type drift layer 2, the p type base region 21 and the n + type source region 22, and the gate electrode 25 is also formed of the n − type drift layer 2. , P type base region 21 and n + type source region 22 are formed immediately above each.
　ゲート電極２５の両側のｎ－型ドリフト層２の上面に形成されたｎ＋型ソース領域２２のさらに外側にはｐ＋型コンタクト領域２３が形成されており、ｎ－型ドリフト層２の上面には、ｎ＋型ソース領域２２およびｐ＋型コンタクト領域２３からなる半導体領域の底部および側面を覆うようにｐ型ベース領域２１が形成されている。ｎ＋型ソース領域２２およびｐ＋型コンタクト領域２３の上面には表面電極８が接して形成されており、ｐ＋型コンタクト領域２３はｐ型ベース領域２１に電位を供給する役割を有している。ｐ型ベース領域２１はＭＯＳＦＥＴのチャネル領域が形成されるｐ型の半導体領域であり、ｎ＋型ソース領域２２およびｐ＋型コンタクト領域２３よりも深い接合深さを有している。ここでは、ｐ型ベース領域２１の側面はｐ型ガードリング領域３の側面に接しており、ｐ型ベース領域２１、ｐ型ガードリング領域３およびｐ型ＪＴＥ領域４の接合深さはほぼ同一であるものとする。ただし、これらの半導体領域の接合深さは適宜変更することができる。 A p + -type contact region 23 is formed further outside the n + -type source region 22 formed on the upper surface of the n − -type drift layer 2 on both sides of the gate electrode 25, and is formed on the upper surface of the n − -type drift layer 2. The p-type base region 21 is formed so as to cover the bottom and side surfaces of the semiconductor region formed of the n + -type source region 22 and the p + -type contact region 23. The surface electrode 8 is formed in contact with the upper surfaces of the n + -type source region 22 and the p + -type contact region 23, and the p + -type contact region 23 has a role of supplying a potential to the p-type base region 21. Yes. The p-type base region 21 is a p-type semiconductor region in which a MOSFET channel region is formed, and has a deeper junction depth than the n + -type source region 22 and the p + -type contact region 23. Here, the side surface of the p-type base region 21 is in contact with the side surface of the p-type guard ring region 3, and the junction depths of the p-type base region 21, the p-type guard ring region 3 and the p-type JTE region 4 are substantially the same. It shall be. However, the junction depth of these semiconductor regions can be changed as appropriate.
　ゲート絶縁膜２４の直上には、ゲート電極２５の表面およびゲート電極２５の端部の上面を覆うように絶縁膜２６が形成されている。表面電極８は、パッシべーション膜２７の一方の端部の上面、ｐ型ガードリング領域３、ｐ型ベース領域２１、ｎ＋型ソース領域２２、ｐ＋型コンタクト領域２３、ゲート絶縁膜２４の側壁および絶縁膜２６の表面に接して連続的に形成されている。つまり、ゲート絶縁膜２４および絶縁膜２６は表面電極８により覆われている。 An insulating film 26 is formed immediately above the gate insulating film 24 so as to cover the surface of the gate electrode 25 and the upper surface of the end of the gate electrode 25. The surface electrode 8 includes an upper surface of one end of the passivation film 27, a p-type guard ring region 3, a p-type base region 21, an n + -type source region 22, a p + -type contact region 23, and a gate insulating film 24. It is continuously formed in contact with the sidewall and the surface of the insulating film 26. That is, the gate insulating film 24 and the insulating film 26 are covered with the surface electrode 8.
　図１３に示すように、ゲート絶縁膜２４はＳｉＣを含む基板上に第１酸化シリコン膜２４ａ、金属絶縁膜２４ｂおよび第２酸化シリコン膜２４ｃを順次形成した積層膜により構成されている。パッシべーション膜２７はゲート絶縁膜２４と同一の構造、すなわち第１酸化シリコン膜２７ａ、金属絶縁膜２７ｂおよび第２酸化シリコン膜２７ｃをその膜内に有し、さらに第２酸化シリコン膜２７ｃ上に形成された絶縁膜２７ｄを有している。金属絶縁膜２４ｂ、２７ｂは例えばアルミ酸化物などの金属酸化膜からなり、それらの膜厚は０．３ｎｍ以上１０ｎｍ以下である。なお、ターミネーション領域のパッシべーション膜２７の上部に絶縁膜をさらに備えていてもよい。 As shown in FIG. 13, the gate insulating film 24 is composed of a laminated film in which a first silicon oxide film 24a, a metal insulating film 24b, and a second silicon oxide film 24c are sequentially formed on a substrate containing SiC. The passivation film 27 has the same structure as the gate insulating film 24, that is, has a first silicon oxide film 27a, a metal insulating film 27b, and a second silicon oxide film 27c in the film, and further on the second silicon oxide film 27c. The insulating film 27d is formed on the substrate. The metal insulating films 24b and 27b are made of, for example, a metal oxide film such as aluminum oxide, and their film thickness is not less than 0.3 nm and not more than 10 nm. Note that an insulating film may be further provided above the passivation film 27 in the termination region.
　このＭＯＳＦＥＴの動作としては、裏面電極（ドレイン電極）７と表面電極（ソース電極）８との間に電圧が印加された状態で、ゲート電極２５に正の電圧が印加されると、ｐ型ベース領域２１の表層に電子の反転層が形成される。その結果、裏面電極７から、ｎ＋型基板１、ｎ－型ドリフト層２、ｐ型ベース領域２１の表層およびｎ＋型ソース領域２２を経て、表面電極８に電流が流れる。一方、ターミネーション構造の動作としては、裏面電極７と表面電極８との間に電圧が印加された状態で、ゲート電極２５に０Ｖが印加されると、裏面電極７および表面電極８間に電流が流れないブロッキング状態となり、裏面電極７から表面電極８に向かって電気力線が伸びる。表面電極８のエッジ部分には電気力線が集中しやすいが、ｐ型ガードリング領域３およびｐ型ＪＴＥ領域４によって電気力線が横方向に広げられるため、表面電極８のエッジ部分における電界集中を緩和できる。パッシべーション膜２７には負電荷を持つ金属絶縁膜２７ｂを用いているため、パッシべーション膜２７にかかる高電界によって実効的なパッシべーション膜電荷が変動したとしても、表面電極８への電気力線の集中を防ぐことができる。このため、デバイスの耐圧変動を抑制することが可能である。 As an operation of this MOSFET, when a positive voltage is applied to the gate electrode 25 with a voltage applied between the back electrode (drain electrode) 7 and the front electrode (source electrode) 8, a p-type base is applied. An electron inversion layer is formed on the surface layer of the region 21. As a result, a current flows from the back electrode 7 to the surface electrode 8 through the n + type substrate 1, the n − type drift layer 2, the surface layer of the p type base region 21, and the n + type source region 22. On the other hand, as an operation of the termination structure, when a voltage is applied between the back electrode 7 and the front electrode 8 and 0 V is applied to the gate electrode 25, a current flows between the back electrode 7 and the front electrode 8. A blocking state that does not flow occurs, and electric lines of force extend from the back electrode 7 toward the front electrode 8. Electric field lines tend to concentrate on the edge portion of the surface electrode 8, but the electric field lines are laterally expanded by the p-type guard ring region 3 and the p-type JTE region 4. Can be relaxed. Since the metal film 27b having a negative charge is used for the passivation film 27, even if the effective passivation film charge fluctuates due to a high electric field applied to the passivation film 27, the passivation film 27 is applied to the surface electrode 8. Concentration of electric field lines can be prevented. For this reason, it is possible to suppress fluctuations in the breakdown voltage of the device.
　次に、本実施の形態におけるＭＯＳＦＥＴおよびターミネーション構造の製造方法を図１３を用いて説明する。ただし、本発明はターミネーション構造に関する発明であり、ＭＯＳＦＥＴについては周知の製造方法により形成するものであるから、製造工程中の半導体装置の図示は省略する。また、図１３の右側のターミネーション構造の製造工程は前記実施の形態１とほぼ同様である。 Next, a method of manufacturing the MOSFET and termination structure in the present embodiment will be described with reference to FIG. However, the present invention relates to a termination structure, and the MOSFET is formed by a well-known manufacturing method, and thus the illustration of the semiconductor device during the manufacturing process is omitted. Further, the manufacturing process of the termination structure on the right side of FIG. 13 is substantially the same as in the first embodiment.
　まず、ＳｉＣからなるｎ＋型基板１上にｎ－型ドリフト層２をエピタキシャル成長法により形成する。そして、ｎ－型ドリフト層２の上面に酸化シリコン膜などからなるハードマスクを形成してｐ型の不純物（例えばＡｌ（アルミニウム））をイオン注入することにより、ｐ型ガードリング領域３を形成する。このときｐ型ガードリング領域３は、ドーピング濃度を１×１０１８ｃｍ－３～２×１０２０ｃｍ－３程度とし、厚さを０．５～２．０μｍ程度として形成する。その後、同様にハードマスクを用いたイオン注入を行うことで、ｐ型ＪＴＥ領域４を形成する。このときｐ型ＪＴＥ領域４は、ドーピング濃度を５×１０１６ｃｍ－３～１×１０１８ｃｍ－３程度とし、厚さを０．５～２．０μｍ程度として形成する。その後、同様にハードマスクを用いてｎ－型ドリフト層２の上面にｎ型の不純物（例えばＮ（窒素））をイオン注入することで、ｎ＋型フィールドストップ領域５を形成する。 First, an n − type drift layer 2 is formed on an n + type substrate 1 made of SiC by an epitaxial growth method. Then, a p-type guard ring region 3 is formed by forming a hard mask made of a silicon oxide film or the like on the upper surface of the n − -type drift layer 2 and ion-implanting p-type impurities (for example, Al (aluminum)). . At this time, the p-type guard ring region 3 is formed with a doping concentration of about 1 × 10 18 cm −3 to 2 × 10 20 cm −3 and a thickness of about 0.5 to 2.0 μm. Thereafter, similarly, ion implantation using a hard mask is performed to form the p-type JTE region 4. At this time, the p-type JTE region 4 is formed with a doping concentration of about 5 × 10 16 cm −3 to 1 × 10 18 cm −3 and a thickness of about 0.5 to 2.0 μm. Thereafter, n + -type field stop region 5 is formed by ion-implanting n-type impurities (for example, N (nitrogen)) into the upper surface of n − -type drift layer 2 in the same manner using a hard mask.
　次に、ｎ－型ドリフト層２、ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４およびｎ＋型フィールドストップ領域５の上部にパターニングされたハードマスクを形成した後、アクティブ領域にて露出しているｎ－型ドリフト層２の上面にｐ型の不純物（例えばＡｌ（アルミニウム））をイオン注入することによりｐ型ベース領域２１を形成する。ｐ型ベース領域２１は、ドーピング濃度を１×１０１７ｃｍ－３～１×１０１８ｃｍ－３程度とし、厚さを０．５～３．０μｍ程度として形成する。続いて、ｎ－型ドリフト層２上にｐ型ベース領域２１の一部を露出するハードマスクを形成し、ｎ型の不純物（例えばＮ（窒素））をイオン注入することでｎ＋型ソース領域２２を形成する。続いて、ｎ－型ドリフト層２上に、ｎ＋型ソース領域２２を覆い、ｐ型ベース領域２１の一部を露出するハードマスクを形成し、ｐ型の不純物（例えばＡｌ（アルミニウム））をイオン注入することでｐ＋型コンタクト領域２３を形成する。続いて、ハードマスクを除去した後、注入されたＡｌ（アルミニウム）およびＮ（窒素）を活性化するために例えば１７００℃で熱処理を行う。 Next, a patterned hard mask is formed on the n − type drift layer 2, the p type guard ring region 3, the p type JTE region 4 and the n + type field stop region 5, and then exposed in the active region. A p-type base region 21 is formed by ion-implanting a p-type impurity (for example, Al (aluminum)) on the upper surface of the n − -type drift layer 2. The p-type base region 21 is formed with a doping concentration of about 1 × 10 17 cm −3 to 1 × 10 18 cm −3 and a thickness of about 0.5 to 3.0 μm. Subsequently, a hard mask that exposes a part of the p-type base region 21 is formed on the n − -type drift layer 2, and an n + -type source region is formed by ion implantation of an n-type impurity (for example, N (nitrogen)). 22 is formed. Subsequently, a hard mask is formed on the n − type drift layer 2 so as to cover the n + type source region 22 and expose a part of the p type base region 21, and p type impurities (for example, Al (aluminum)) are formed. A p + -type contact region 23 is formed by ion implantation. Subsequently, after removing the hard mask, heat treatment is performed at 1700 ° C., for example, to activate the implanted Al (aluminum) and N (nitrogen).
　次に、１０００～１３００℃程度のプロセス温度範囲内において熱酸化を行うことにより、ｎ－型ドリフト層２上に酸化シリコンからなる第１絶縁膜を形成する。続いて、第１絶縁膜上にＣＶＤ法などにより金属を含む第２絶縁膜および酸化シリコンからなる第３絶縁膜を順次形成する。その後、多結晶シリコン膜を第３絶縁膜上にＣＶＤ法などにより形成した後、前記多結晶シリコン膜をパターニングすることで、アクティブ領域の二つのｐ型ベース領域２１の間の領域の直上にゲート電極２５を形成する。続いて、ゲート電極２５を覆うように、第３絶縁膜上に例えば酸化シリコンからなる第４絶縁膜を形成する。 Next, a first insulating film made of silicon oxide is formed on the n − -type drift layer 2 by performing thermal oxidation within a process temperature range of about 1000 to 1300 ° C. Subsequently, a second insulating film containing metal and a third insulating film made of silicon oxide are sequentially formed on the first insulating film by a CVD method or the like. After that, after a polycrystalline silicon film is formed on the third insulating film by a CVD method or the like, the polycrystalline silicon film is patterned to form a gate directly above the region between the two p-type base regions 21 in the active region. The electrode 25 is formed. Subsequently, a fourth insulating film made of, for example, silicon oxide is formed on the third insulating film so as to cover the gate electrode 25.
　次に、アクティブ領域の二つのｐ型ベース領域２１の間の領域の直上およびターミネーション領域の一部を覆うハードマスクをそれぞれ形成した後、ドライエッチング法またはウェットエッチング法を用いて第１～第４絶縁膜をパターニングする。これにより、アクティブ領域の二つのｐ型ベース領域２１の間の領域の直上に第１絶縁膜からなる第１酸化シリコン膜２４ａ、第２絶縁膜からなる金属絶縁膜２４ｂおよび第３絶縁膜からなる第２酸化シリコン膜２４ｃが順に積層された積層膜からなるゲート絶縁膜２４を形成する。また、それと同時にターミネーション領域には第１絶縁膜からなる第１酸化シリコン膜２７ａ、第２絶縁膜からなる金属絶縁膜２７ｂ、第３絶縁膜からなる第２酸化シリコン膜２７ｃ、第４絶縁膜からなる絶縁膜２７ｄが順に積層されたパッシべーション膜２７が形成される。ここで金属絶縁膜２４ｂ、２７ｂの膜厚は０．３ｎｍ以上１０ｎｍ以下であり、ゲート絶縁膜２４の全体膜厚は３０ｎｍ以上１００ｎｍ以下である。金属絶縁膜２４ｂ、２７ｂは例えばアルミ酸化物からなる。このように、ゲート絶縁膜２４を形成する工程において、後に形成されるパッシべーション膜２７の一部である第１酸化シリコン膜２７ａ、金属絶縁膜２７ｂおよび第２酸化シリコン膜２７ｃも同時に形成される。つまり、パッシベーション膜２７はゲート絶縁膜２４と同一の構造を含むことになる。 Next, after forming a hard mask directly over the region between the two p-type base regions 21 in the active region and covering a part of the termination region, the first to fourth layers are formed using a dry etching method or a wet etching method. The insulating film is patterned. Thus, the first silicon oxide film 24a made of the first insulating film, the metal insulating film 24b made of the second insulating film, and the third insulating film are formed immediately above the region between the two p-type base regions 21 in the active region. A gate insulating film 24 made of a laminated film in which the second silicon oxide film 24c is sequentially laminated is formed. At the same time, the termination region includes a first silicon oxide film 27a made of a first insulating film, a metal insulating film 27b made of a second insulating film, a second silicon oxide film 27c made of a third insulating film, and a fourth insulating film. A passivation film 27 in which insulating films 27d are sequentially stacked is formed. Here, the film thickness of the metal insulating films 24b and 27b is 0.3 nm or more and 10 nm or less, and the total film thickness of the gate insulating film 24 is 30 nm or more and 100 nm or less. The metal insulating films 24b and 27b are made of, for example, aluminum oxide. Thus, in the step of forming the gate insulating film 24, the first silicon oxide film 27a, the metal insulating film 27b, and the second silicon oxide film 27c, which are part of the passivation film 27 to be formed later, are also formed at the same time. The That is, the passivation film 27 includes the same structure as the gate insulating film 24.
　このとき、第２酸化シリコン膜２４ｃ上には、前記第４絶縁膜からなる絶縁膜２６が形成される。絶縁膜２６はゲート電極２５の表面を覆うように形成されており、ゲート絶縁膜２４の直上にゲート絶縁膜２４と同じ幅で形成される。つまり、ゲート電極２５のゲート長方向の幅は、ゲート絶縁膜２４の同方向の幅よりも狭く形成される。これにより、アクティブ領域の二つのｐ型ベース領域２１の間の領域の直上にゲート絶縁膜２４を介してゲート電極２５が形成される。 At this time, an insulating film 26 made of the fourth insulating film is formed on the second silicon oxide film 24c. The insulating film 26 is formed so as to cover the surface of the gate electrode 25, and is formed with the same width as the gate insulating film 24 immediately above the gate insulating film 24. That is, the width of the gate electrode 25 in the gate length direction is narrower than the width of the gate insulating film 24 in the same direction. As a result, the gate electrode 25 is formed via the gate insulating film 24 immediately above the region between the two p-type base regions 21 in the active region.
　その後、ｎ＋型基板１の裏面にスパッタリング法などを用いて裏面電極（ドレイン電極）７を形成し、続いてｎ－型ドリフト層２上の全面に金属膜を形成した後、前記金属膜をパターニングすることで、ｎ＋型ソース領域２２およびｐ＋型コンタクト領域２３に電気的に接続された表面電極８およびｎ＋型フィールドストップ領域５に電気的に接続されたフローティング電極９を形成する。これにより、図１３に示すＭＯＳＦＥＴおよびターミネーション構造が完成する。なお、ｐ型ガードリング領域３とｐ型ＪＴＥ領域４の深さは同一である必要はない。また、ｐ型ＪＴＥ領域４は単一の領域である必要はなく、複数の領域で形成されていてもよい。さらに、ｐ型ガードリング領域３、ｐ型ＪＴＥ領域４、ｎ＋型フィールドストップ領域５、ｐ型ベース領域２１、ｎ＋型ソース領域２２、およびｐ＋型コンタクト領域２３の形成順序は上記の通りである必要はない。 Thereafter, a back electrode (drain electrode) 7 is formed on the back surface of the n + -type substrate 1 using a sputtering method or the like, and subsequently a metal film is formed on the entire surface of the n − -type drift layer 2. By patterning, the surface electrode 8 electrically connected to the n + type source region 22 and the p + type contact region 23 and the floating electrode 9 electrically connected to the n + type field stop region 5 are formed. Thereby, the MOSFET and termination structure shown in FIG. 13 are completed. Note that the p-type guard ring region 3 and the p-type JTE region 4 need not have the same depth. Further, the p-type JTE region 4 does not have to be a single region, and may be formed of a plurality of regions. Further, the formation order of the p-type guard ring region 3, the p-type JTE region 4, the n + -type field stop region 5, the p-type base region 21, the n + -type source region 22, and the p + -type contact region 23 is as described above. Need not be.
　以上のようにして高耐圧のＭＯＳＦＥＴ（パワーデバイス）をアクティブ領域に有する半導体装置において、図１３に示すように膜厚０．３ｎｍ以上１０ｎｍ以下の金属絶縁膜２７ｂを含むパッシべーション膜２７を形成することで、前記実施の形態１と同様の効果を得ることができる。なお、ゲート絶縁膜２４はＭＯＳＦＥＴのゲート絶縁膜であるから、必要以上に膜厚を厚くすることはできないため、ここではその膜厚を３０ｎｍ以上１００ｎｍ以下としている。この場合、パッシべーション膜２７を構成する第１酸化シリコン膜２７ａ、金属絶縁膜２７ｂおよび第２酸化シリコン膜２７ｃのみでパッシべーション膜を構成すると、膜厚が不足して耐圧を確保することができないため、ここでは絶縁膜２７ｄを設けて絶縁膜２７ｄの膜厚を大きくしている。具体的には、パッシべーション膜２７の膜厚は数百ｎｍ～数μｍ必要となる。 In the semiconductor device having the high breakdown voltage MOSFET (power device) in the active region as described above, the passivation film 27 including the metal insulating film 27b having a film thickness of 0.3 nm to 10 nm is formed as shown in FIG. As a result, the same effect as in the first embodiment can be obtained. Since the gate insulating film 24 is a gate insulating film of a MOSFET, the film thickness cannot be increased more than necessary. Therefore, the film thickness is set to 30 nm to 100 nm. In this case, if the passivation film is constituted only by the first silicon oxide film 27a, the metal insulating film 27b, and the second silicon oxide film 27c constituting the passivation film 27, the film thickness is insufficient and the breakdown voltage is secured. Therefore, the insulating film 27d is provided here to increase the thickness of the insulating film 27d. Specifically, the thickness of the passivation film 27 needs to be several hundred nm to several μm.
　本実施の形態においては金属絶縁膜としてアルミ酸化物を例示したが、本発明はこれに限定されるものではなくアルミ窒化物またはチタン酸化物であってもよい。また、本実施の形態においてはターミネーション構造をＪＴＥとしたが、ターミネーション構造をＦＬＲとしても同様の効果を得ることが可能である。 In the present embodiment, aluminum oxide is exemplified as the metal insulating film, but the present invention is not limited to this and may be aluminum nitride or titanium oxide. In the present embodiment, the termination structure is JTE, but the same effect can be obtained even if the termination structure is FLR.
　また、第１酸化シリコン膜２４ａ、２７ａを形成する際に、一酸化窒素または一酸化二窒素などで酸窒化するか、もしくはアニールを行うと、第１酸化シリコン膜２４ａ、２７ａとＳｉＣからなるｎ－型ドリフト層２との界面近傍の第１酸化シリコン膜２４ａ内および２７ａ内にＮ（窒素）を導入することができる。これによりＳｉＣからなるｎ－型ドリフト層２と第１酸化シリコン膜２７ａ、およびｎ－型ドリフト層２とゲート絶縁膜２４との界面のトラップを低減することは、実効的なパッシべーション膜電荷の変動を抑制するため、およびＭＯＳＦＥＴのオン抵抗低減のために効果的である。これは、トラップを低減することで、チャネル内のキャリアの移動度を向上させることができるためである。 Further, when the first silicon oxide films 24a and 27a are formed, if they are oxynitrided with nitrogen monoxide or dinitrogen monoxide or annealed, the first silicon oxide films 24a and 27a and n made of SiC are formed. N (nitrogen) can be introduced into the first silicon oxide film 24 a and 27 a in the vicinity of the interface with the − type drift layer 2. This reduces traps at the interface between the n − type drift layer 2 and the first silicon oxide film 27a made of SiC, and the n − type drift layer 2 and the gate insulating film 24. This is effective for suppressing the fluctuation of the MOSFET and for reducing the on-resistance of the MOSFET. This is because the mobility of carriers in the channel can be improved by reducing traps.
　以上、本発明者らによってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　本発明は、ＳｉＣ基板を含む半導体装置の製造技術に適用して有効である。 The present invention is effective when applied to a manufacturing technique of a semiconductor device including a SiC substrate.
１　　　ｎ＋型基板
２　　　ｎ－型ドリフト層
３　　　ｐ型ガードリング領域
４　　　ｐ型ＪＴＥ領域
４ａ　　ｐ型半導体領域
５　　　ｎ＋型フィールドストップ領域
６　　　パッシベーション膜
６ａ　　第１酸化シリコン膜
６ｂ　　金属絶縁膜
６ｃ　　第２酸化シリコン膜
６ｄ　　窒化シリコン膜
６ｅ　　窒化シリコン膜
７　　　裏面電極
８　　　表面電極
９　　　フローティング電極
１１　　パッシベーション膜
２１　　ｐ型ベース領域
２２　　ｎ＋型ソース領域
２３　　ｐ＋型コンタクト領域
２４　　ゲート絶縁膜
２４ａ　第１酸化シリコン膜
２４ｂ　金属絶縁膜
２４ｃ　第２酸化シリコン膜
２５　　ゲート電極
２６　　絶縁膜
２７　　パッシベーション膜
２７ａ　第１酸化シリコン膜
２７ｂ　金属絶縁膜
２７ｃ　第２酸化シリコン膜
２７ｄ　絶縁膜
Ｍ１～Ｍ４　　マスク 1 n + type substrate 2 n − type drift layer 3 p type guard ring region 4 p type JTE region 4a p type semiconductor region 5 n + type field stop region 6 passivation film 6a first silicon oxide film 6b metal insulating film 6c second Silicon oxide film 6d Silicon nitride film 6e Silicon nitride film 7 Back electrode 8 Front electrode 9 Floating electrode 11 Passivation film 21 P-type base region 22 n + -type source region 23 p + -type contact region 24 Gate insulating film 24a First silicon oxide film 24b Metal insulating film 24c Second silicon oxide film 25 Gate electrode 26 Insulating film 27 Passivation film 27a First silicon oxide film 27b Metal insulating film 27c Second silicon oxide film 27d Insulating films M1 to M4 Mask

Claims (17)

  1. 　第１導電型を有する炭化ケイ素を含む半導体基板と、
    　前記半導体基板上に形成され、前記第１導電型を有し、前記半導体基板よりも不純物濃度が低く炭化ケイ素を含むドリフト層と、
    　前記ドリフト層内の上面に形成された前記第１導電型と異なる第２導電型を有する半導体領域と、
    　前記ドリフト層上に形成されたパッシベーション膜と、
    　前記ドリフト層上に形成された電極と、
    　前記ドリフト層の裏面に接して形成された裏面電極と、
    を含み、
    　前記パッシベーション膜は、
    　前記ドリフト層の上面に接して形成された第１絶縁膜と、
    　前記第１絶縁膜上に形成された金属絶縁膜と、
    　前記金属絶縁膜上に形成された第２絶縁膜と、
    を有し、
    　前記金属絶縁膜の膜厚は０．３ｎｍ以上１０ｎｍ以下の範囲にあることを特徴とする半導体装置。     A semiconductor substrate comprising silicon carbide having a first conductivity type;
    A drift layer formed on the semiconductor substrate, having the first conductivity type, having a lower impurity concentration than the semiconductor substrate and containing silicon carbide;
    A semiconductor region having a second conductivity type different from the first conductivity type formed on an upper surface in the drift layer;
    A passivation film formed on the drift layer;
    An electrode formed on the drift layer;
    A back electrode formed in contact with the back surface of the drift layer;
    Including
    The passivation film is
    A first insulating film formed in contact with the upper surface of the drift layer;
    A metal insulating film formed on the first insulating film;
    A second insulating film formed on the metal insulating film;
    Have
    The semiconductor device is characterized in that the metal insulating film has a thickness in a range of 0.3 nm to 10 nm.
  2. 　前記金属絶縁膜はアルミ酸化物を含むことを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the metal insulating film contains aluminum oxide.
  3. 　前記金属絶縁膜はアルミ窒化物を含むことを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the metal insulating film contains aluminum nitride.
  4. 　前記金属絶縁膜はチタン酸化物を含むことを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the metal insulating film contains titanium oxide.
  5. 　前記金属絶縁膜の膜厚は５ｎｍ以下であることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the thickness of the metal insulating film is 5 nm or less.
  6. 　前記金属絶縁膜の膜厚は１ｎｍ以下であることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the thickness of the metal insulating film is 1 nm or less.
  7. 　前記第１絶縁膜および前記第２絶縁膜は酸化シリコンを含むことを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film contain silicon oxide.
  8. 　前記第１絶縁膜と前記ドリフト層との界面近傍の前記第１絶縁膜内に窒素が導入されていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein nitrogen is introduced into the first insulating film in the vicinity of the interface between the first insulating film and the drift layer.
  9. 　前記ドリフト層の上面に形成され、前記第２導電型を有するベース領域と、
    　前記ベース領域の上面に形成され、前記第１導電型を有し、かつ前記ドリフト層よりも不純物濃度が高いソース領域と、
    　前記ベース領域の上面に形成され、前記第２導電型を有し、かつ前記ベース領域よりも不純物濃度が高いコンタクト領域と、
    　前記ドリフト層および前記ベース領域の直上にゲート絶縁膜を介して形成されたゲート電極と、
    を有し、
    　前記電極は前記ソース領域および前記コンタクト領域に電気的に接続され、
    　前記ゲート絶縁膜は、
    　前記ドリフト層の上面に接して形成された第３絶縁膜と、
    　前記第３絶縁膜上に形成された金属絶縁膜と、
    　前記金属絶縁膜上に形成された第４絶縁膜と、
    を有し、
    　前記金属絶縁膜の膜厚は０．３ｎｍ以上１０ｎｍ以下の範囲にあり、
    　前記ゲート絶縁膜の膜厚は３０以上１００ｎｍ以下の範囲にあり、
    　前記パッシベーション膜は前記ゲート絶縁膜と同一の構造を含むことを特徴とする請求項１記載の半導体装置。     A base region formed on an upper surface of the drift layer and having the second conductivity type;
    A source region formed on an upper surface of the base region, having the first conductivity type and having an impurity concentration higher than that of the drift layer;
    A contact region formed on an upper surface of the base region, having the second conductivity type and having a higher impurity concentration than the base region;
    A gate electrode formed directly over the drift layer and the base region via a gate insulating film;
    Have
    The electrode is electrically connected to the source region and the contact region;
    The gate insulating film is
    A third insulating film formed in contact with the upper surface of the drift layer;
    A metal insulating film formed on the third insulating film;
    A fourth insulating film formed on the metal insulating film;
    Have
    The thickness of the metal insulating film is in the range of 0.3 nm to 10 nm,
    The gate insulating film has a thickness in the range of 30 to 100 nm,
    The semiconductor device according to claim 1, wherein the passivation film includes the same structure as the gate insulating film.
  10. 　前記パッシベーション膜は前記第２絶縁膜上に形成された第５絶縁膜を含むことを特徴とする請求項９記載の半導体装置。 10. The semiconductor device according to claim 9, wherein the passivation film includes a fifth insulating film formed on the second insulating film.
  11. 　前記第３絶縁膜と前記ドリフト層との界面近傍の前記第３絶縁膜内に窒素が導入されていることを特徴とする請求項９記載の半導体装置。 10. The semiconductor device according to claim 9, wherein nitrogen is introduced into the third insulating film in the vicinity of the interface between the third insulating film and the drift layer.
  12. 　前記第３絶縁膜および前記第４絶縁膜は酸化シリコンを含むことを特徴とする請求項９記載の半導体装置。 10. The semiconductor device according to claim 9, wherein the third insulating film and the fourth insulating film contain silicon oxide.
  13. 　第１導電型を有する炭化ケイ素を含む半導体基板と、
    　前記半導体基板上に形成され、前記第１導電型を有し、前記半導体基板よりも不純物濃度が低く炭化ケイ素を含むドリフト層と、
    　前記ドリフト層内の上面に形成された前記第１導電型と異なる第２導電型を有する半導体領域と、
    　前記ドリフト層上に形成されたパッシベーション膜と、
    　前記ドリフト層上に形成された電極と、
    　前記ドリフト層の裏面に接して形成された裏面電極と、
    を含み、
    　前記パッシベーション膜は、
    　前記ドリフト層の上面に接して形成された第１絶縁膜と、
    　前記第１絶縁膜上に順に積層された第１窒化膜、金属絶縁膜、第２窒化膜および第２絶縁膜と、
    を有し、
    　前記金属絶縁膜の膜厚は０．３ｎｍ以上であり、
    　前記第１窒化膜、前記金属絶縁膜および前記第２窒化膜の膜厚の和は１０ｎｍ以下であることを特徴とする半導体装置。     A semiconductor substrate comprising silicon carbide having a first conductivity type;
    A drift layer formed on the semiconductor substrate, having the first conductivity type, having a lower impurity concentration than the semiconductor substrate and containing silicon carbide;
    A semiconductor region having a second conductivity type different from the first conductivity type formed on an upper surface in the drift layer;
    A passivation film formed on the drift layer;
    An electrode formed on the drift layer;
    A back electrode formed in contact with the back surface of the drift layer;
    Including
    The passivation film is
    A first insulating film formed in contact with the upper surface of the drift layer;
    A first nitride film, a metal insulating film, a second nitride film, and a second insulating film, which are sequentially stacked on the first insulating film;
    Have
    The metal insulating film has a thickness of 0.3 nm or more,
    The sum of the film thicknesses of the first nitride film, the metal insulating film, and the second nitride film is 10 nm or less.
  14. 　前記金属絶縁膜はアルミ酸化物を含むことを特徴とする請求項１３記載の半導体装置。 14. The semiconductor device according to claim 13, wherein the metal insulating film contains aluminum oxide.
  15. 　前記金属絶縁膜はアルミ窒化物を含むことを特徴とする請求項１３記載の半導体装置。 14. The semiconductor device according to claim 13, wherein the metal insulating film includes aluminum nitride.
  16. 　前記金属絶縁膜はチタン酸化物を含むことを特徴とする請求項１３記載の半導体装置。 14. The semiconductor device according to claim 13, wherein the metal insulating film contains titanium oxide.
  17. 　前記第１絶縁膜と前記ドリフト層との界面近傍の前記第１絶縁膜内に窒素が導入されていることを特徴とする請求項１３記載の半導体装置。 14. The semiconductor device according to claim 13, wherein nitrogen is introduced into the first insulating film in the vicinity of the interface between the first insulating film and the drift layer.
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JP2016081981A (en) 2014-10-14 2016-05-16 株式会社日立製作所 Semiconductor device and manufacturing method of the same
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