WO2017154408A1 - POWER SEMICONDUCTOR MODULE, SiC SEMICONDUCTOR ELEMENT TO BE MOUNTED ON SAME, AND METHOD OF MANUFACTURING SiC SEMICONDUCTOR ELEMENT - Google Patents

POWER SEMICONDUCTOR MODULE, SiC SEMICONDUCTOR ELEMENT TO BE MOUNTED ON SAME, AND METHOD OF MANUFACTURING SiC SEMICONDUCTOR ELEMENT Download PDF

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Publication number
WO2017154408A1
WO2017154408A1 PCT/JP2017/003260 JP2017003260W WO2017154408A1 WO 2017154408 A1 WO2017154408 A1 WO 2017154408A1 JP 2017003260 W JP2017003260 W JP 2017003260W WO 2017154408 A1 WO2017154408 A1 WO 2017154408A1
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inorganic layer
sic
sic semiconductor
semiconductor element
semiconductor module
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PCT/JP2017/003260
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French (fr)
Japanese (ja)
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和弘 鈴木
谷口　隆文
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株式会社日立製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present invention relates to a mounting structure of a SiC semiconductor element of a high voltage power semiconductor module mounted with a SiC semiconductor element and a manufacturing method thereof.
  • Power control systems using power semiconductor modules have become indispensable against the background of regulations and requests for energy saving, resource saving, environmental conservation, and so on.
  • development of power semiconductor modules using SiC semiconductor elements that are excellent in low-loss characteristics, high insulation characteristics, and high-temperature operation characteristics is underway.
  • SiC semiconductor element is used for high breakdown voltage applications, dielectric breakdown tends to occur at the end of the element where the potential distribution is concentrated.
  • a guard ring is formed so as to surround a peripheral area (termination area) on the upper surface of the element, or technologies such as FLR (Field Limiting Ring) and JTE (Junction Termination Extension) are applied.
  • a power semiconductor module includes a SiC semiconductor element having a termination structure region at a peripheral portion and containing SiC, a silicone gel for sealing the SiC semiconductor element, and the termination A first inorganic layer disposed on the structural region, and a second inorganic layer disposed between the first inorganic layer and the silicone gel are provided.
  • an SiC semiconductor device is a SiC semiconductor device having a termination structure region at a peripheral portion and containing SiC, and includes a first inorganic layer on the termination structure region. A layer is provided, and a second inorganic layer is provided on the outermost part.
  • a method of manufacturing an SiC semiconductor device is a method of manufacturing the SiC semiconductor device of the present invention as described above, wherein the SiC wafer is formed on the SiC wafer on which the SiC semiconductor device is formed.
  • the method includes a step of adhering two inorganic layers, and a dicing step of separating the SiC wafer having the second inorganic layer disposed on the surface thereof into individual chips.
  • the SiC semiconductor element which can ensure a pressure
  • 1 is a schematic cross-sectional view of a power semiconductor module according to an embodiment of the present invention.
  • 1 is a schematic cross-sectional view of an entire SiC semiconductor device according to an embodiment of the present invention. It is a schematic cross section of the edge part of the SiC semiconductor element which concerns on one Embodiment of this invention.
  • It is a plane schematic diagram of the SiC semiconductor device concerning one embodiment of the present invention, Comprising: It is a plane schematic diagram of the separated SiC semiconductor device in case a SiC semiconductor device is a diode element.
  • FIG. 1 is a schematic plan view of an SiC semiconductor device according to an embodiment of the present invention, and is a schematic plan view of an individualized SiC semiconductor device when a gate pad and a sense pad of the SiC semiconductor device are arranged in the periphery of the device.
  • FIG. 3 is a schematic plan view of a SiC semiconductor device according to an embodiment of the present invention, wherein the SiC semiconductor device is separated into pieces when the gate pad of the SiC semiconductor device is disposed at the center of the device and the sense pad is disposed at the periphery of the device.
  • It is the plane schematic diagram of the SiC semiconductor element.
  • It is a schematic cross section of the edge part of the SiC semiconductor element which concerns on one Embodiment of this invention.
  • It is a figure which shows the formation method of the SiC semiconductor element which concerns on one Embodiment of this invention.
  • FIG. 1 shows a schematic cross section of a power semiconductor module 100 equipped with a SiC semiconductor element according to an embodiment of the present invention.
  • the SiC semiconductor element may be mounted as a switching element, may be mounted as a free wheel diode element, or may be mounted as both elements.
  • FIG. 1 illustrates an example in which an SiC semiconductor element is used for both the switching element and the diode element.
  • the power semiconductor module 100 includes a heat dissipation base 11, a ceramic circuit board 6, a SiC diode element 1 ⁇ / b> A, a SiC switching element 1 ⁇ / b> B, external output terminals 9 ⁇ / b> A and 9 ⁇ / b> B, and a module case 10.
  • the ceramic circuit board 6 is provided with wiring patterns 6A1 and 6A2 on one surface and a wiring pattern 6C on the other surface.
  • the wiring pattern 6C and the heat dissipation base 11 are bonded via the solder bonding layer 5B.
  • wiring pattern 6A1 and SiC semiconductor elements 1A and 1B are bonded via solder bonding layer 5A. Further, the external output terminal 9A (9) connected to the positive electrode side is directly joined to the wiring pattern 6A1 (6A) by ultrasonic bonding, and the external output terminal 9B (9) connected to the negative electrode side is connected to the wiring pattern 6A1 (6A). It is joined to the pattern 6A2 (6A) by direct ultrasonic joining.
  • the connection method between the external output terminal 9 and the wiring pattern 6A is ultrasonic bonding here, other bonding methods may be used. Note that the state of connection between the gate of the switching element 1B and the sense wiring is omitted in the drawing.
  • the external output terminals 9A and 9B are pulled out of the module case 10 and connected to other devices.
  • the surface opposite to the wiring pattern 6A1 side in the SiC semiconductor elements 1A and 1B is connected via the bonding wire 4 to the wiring pattern 6A2 to which the external output terminal 9B is connected.
  • the detailed structure of SiC switching element 1B will be described in detail below.
  • the module case 10 is fixed to the heat dissipation base 11 with an adhesive or the like, and the inside is filled with the silicone gel 3.
  • FIG. 2 is an enlarged view of the SiC semiconductor element mounting portion 110 of FIG.
  • An inorganic material 2B is arranged on the peripheral surface of the surface of the SiC semiconductor element 1B.
  • a more detailed structure of the end portion 120 of the SiC semiconductor device of FIG. 2 is shown in FIG.
  • the termination structure region at the periphery of the element shown in FIG. 3 is provided with an electric field relaxation structure including a guard ring, FLR, JTE, etc. (details are omitted), and electric field concentration occurs in this region. It is necessary to dispose a thick film insulating layer in this region.
  • a high voltage resistance resin is applied as the thick film insulating layer.
  • This material is a useful technique because a thick film can be formed by processing at a relatively low temperature.
  • an insulating material having a dielectric breakdown strength equal to or higher than that of the high voltage resistance resin.
  • the dielectric strength of the high withstand voltage resin is 200 to 300 kV / mm.
  • the dielectric breakdown strength of the inorganic material taken up in the present invention is as follows: silica glass: up to 200 kV / mm, alumina: up to 600 kV / mm, silicon nitride: up to 1000 kV / mm, SiC: 250 kV / mm
  • silica glass up to 200 kV / mm
  • alumina up to 600 kV / mm
  • silicon nitride up to 1000 kV / mm
  • SiC 250 kV / mm
  • the thermal expansion coefficient of these inorganic materials is about 1/10 that of a high withstand voltage resin and low thermal expansion, and the softening temperature is 1000 ° C. or more, which is excellent in heat resistance.
  • the said subject Since it has these characteristics, the said subject was able to be solved by using the said inorganic material. From the viewpoint of workability described later, it is advantageous to use silica-based glass, but it can be applied as long as the material has low thermal expansion and heat resistance comparable to the above materials, and is not limited to the above materials.
  • the first inorganic layer 2A such as SiO 2 is disposed on the SiC 25, and the protective layer 20 is formed thereon.
  • the protective layer is made of an organic material such as polyimide or an inorganic material such as silicon nitride, but is not limited to these materials.
  • the thickness of the second inorganic layer 2B is required to be 50 ⁇ m or more from the viewpoint of ensuring the pressure resistance, and can be applied to the case of the first inorganic layer 2A having a thickness of about several ⁇ m, such as vapor deposition, sputtering, and CVD. It is difficult to deposit directly on the device.
  • a method of arranging the second inorganic layer 2B with the adhesive layer 8 has been developed.
  • FIGS. 6 (2) schematic views are shown in the order of steps, and a plan view and a cross-sectional view are arranged for each step.
  • An adhesive 8A having a predetermined shape is applied on the SiC wafer (FIG. 6 (2)).
  • the adhesive for example, a polyimide resin, a polyamideimide resin, an organic-inorganic hybrid material, or the like can be used.
  • the material is not limited to the above materials as long as the material has excellent heat resistance and a low impurity content.
  • a method for applying the adhesive 8A a printing method or a dispensing method can be used.
  • the pattern-forming inorganic plate is made of the inorganic material.
  • a plate-like material made of the above-mentioned inorganic material is prepared, and openings having a predetermined shape are formed on the plate-like material, thereby obtaining [A] pattern-formed inorganic plate. Since this pattern formation inorganic board is equivalent to the 2nd inorganic layer of 2B of Drawing 5, the board thickness of a pattern formation inorganic board is adjusted according to a required pressure-resistant level.
  • a mask pattern having a predetermined shape is formed on the plate material by a photolithographic technique, and then an opening process is performed by etching with an etching agent according to the material.
  • the hard mask is put on the plate material and then opened by sandblasting.
  • Appropriate techniques can be applied from several methods including a method, a method of opening by laser irradiation, and a method of opening by applying mechanical or thermal stress after providing a marking line of a predetermined shape.
  • Bonding of the pattern-forming inorganic plate may be performed by applying pressure by pressing the inorganic plate while heating in a reduced pressure atmosphere using a vacuum hot press apparatus, or by using a laminator.
  • the adhesive is pressed and heated while being heated above the melting point of the adhesive layer 8A by hot pressing.
  • the application conditions differ depending on the type of adhesive, for example, in an inert atmosphere, the temperature is 320 ° C., the surface pressure is 0.3 MPa, and the pressing time is 1 minute. In this way, a SiC wafer to which an inorganic plate having a predetermined pattern of openings is bonded is completed.
  • FIG. 7 a dicing SiC semiconductor element can be obtained by dicing along a predetermined line of the SiC wafer (FIG. 7 (4)).
  • 4A, 4B, and 4C are plan views of the separated SiC semiconductor elements.
  • 4A shows a case of a diode element
  • FIG. 4B shows a case where a gate pad and a sense pad are arranged at the periphery of the element
  • FIG. 4C shows a case where the gate pad is arranged at the element central part and the sense pad is arranged at the element peripheral part. Is the case.
  • FIG. 3 is described as the configuration of the SiC semiconductor element, various configurations are possible, for example, a configuration excluding the protective layer as shown in FIG. 5 is also possible.
  • the first embodiment it is possible to dispose a thick film inorganic layer on the termination structure region at the periphery of the SiC semiconductor element. As a result, while maintaining the pressure resistance characteristics, it is possible to suppress the occurrence of warpage even in the wafer state, and to be excellent in productivity applicable to a large-diameter wafer.
  • the second embodiment is a modification of the first embodiment, and differs from the first embodiment in the bonding material of the bonding layer 5 that bonds the SiC semiconductor elements 1A and 1B.
  • solder is used for the bonding layer 5
  • sintered metal is used for the bonding layer 5.
  • the second embodiment is different from the first embodiment, but the other points are common to the first embodiment.
  • a predetermined pattern of a metal paste for sintering is formed on the wiring pattern 6A1 of the ceramic circuit board 6 by a printing method or a dispensing method. On this, the same SiC semiconductor element as in the first embodiment is placed. With this configuration, by performing a predetermined heat treatment, a sintered metal layer is formed, and the SiC semiconductor element is bonded. However, in this method, since the denseness of the sintered layer is low, in the case of application to a higher reliability, the sintered layer is made denser by pressurizing the SiC semiconductor element during the heat treatment. It is effective to make things.
  • the inorganic layer 2B having excellent heat resistance is disposed at the outermost peripheral portion, no abnormality such as sticking occurs even if the 2B portion is pressurized during heating. For this reason, it is possible to realize a dense sintered metal layer over the entire area of the element joint portion.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)

Abstract

The objective of the present invention is to provide a SiC semiconductor element with which an increase in wafer diameter can be supported while breakdown voltage characteristics are maintained, which can be bonded while pressure is being applied to the whole surface of a diced element, and which is advantageous for high heat resistant bonding, and also to provide a power semiconductor module with a SiC semiconductor element mounted thereon. To this end, the power semiconductor module with a SiC semiconductor element mounted thereon is provided with: a SiC semiconductor element 1B which has a terminating structure region in a peripheral edge portion (element edge portion 120) and which contains SiC; silicone gel 3 sealing the SiC semiconductor element 1B; a first inorganic layer 2A disposed on the terminating structure region; and a second inorganic layer 2B disposed between the first inorganic layer 2A and the silicone gel 3.

Description

パワー半導体モジュール、並びにそれに搭載されるＳｉＣ半導体素子およびその製造方法Power semiconductor module, SiC semiconductor element mounted thereon, and method for manufacturing the same
　本発明は、ＳｉＣ半導体素子を搭載した高耐圧パワー半導体モジュールのＳｉＣ半導体素子の実装構造及びその製造方法に関する。 The present invention relates to a mounting structure of a SiC semiconductor element of a high voltage power semiconductor module mounted with a SiC semiconductor element and a manufacturing method thereof.
　省エネルギー化、省資源、環境保全などへの規制・要請を背景に、パワー半導体モジュールを用いた電力制御システムが不可欠なものになっている。特に、低損失性、高絶縁特性、高温動作特性に優れるＳｉＣ半導体素子を用いたパワー半導体モジュールの開発が進められている。しかし、ＳｉＣ半導体素子を高耐圧の用途で用いようとすると、電位の分布が集中してしまう素子端部で、絶縁破壊が起こり易くなる。 Power control systems using power semiconductor modules have become indispensable against the background of regulations and requests for energy saving, resource saving, environmental conservation, and so on. In particular, development of power semiconductor modules using SiC semiconductor elements that are excellent in low-loss characteristics, high insulation characteristics, and high-temperature operation characteristics is underway. However, if an SiC semiconductor element is used for high breakdown voltage applications, dielectric breakdown tends to occur at the end of the element where the potential distribution is concentrated.
　そこで、従来の素子では、素子上面周辺領域（終端領域）を取り囲むようにガードリングを形成したり、ＦＬＲ（Field Limiting Ring）やＪＴＥ（Junction Termination Extension）などの技術が適用されている。 Therefore, in a conventional element, a guard ring is formed so as to surround a peripheral area (termination area) on the upper surface of the element, or technologies such as FLR (Field Limiting Ring) and JTE (Junction Termination Extension) are applied.
　従来、ＳｉＣ半導体素子搭載パワー半導体モジュールの耐圧特性を確保する技術として、絶縁性樹脂ワニスやペーストを用いて、ＳｉＣ半導体素子周辺部に絶縁性樹脂被膜を形成して耐圧特性を確保するものがあった（例えば、特許文献１参照）。 Conventionally, as a technology for ensuring the withstand voltage characteristics of a power semiconductor module mounted with an SiC semiconductor element, there has been a technique for ensuring the withstand voltage characteristics by forming an insulating resin film around the SiC semiconductor element using an insulating resin varnish or paste. (For example, see Patent Document 1).
特開２０１３－１９１７１６号公報JP 2013-191716 A
　ＳｉＣ半導体素子を用いたパワー半導体モジュールにおいても低コスト化の観点から、電流を流すアクティブ面積を広くすることが望まれている。このためには、素子周辺の終端領域を狭める必要がある。しかし、素子の終端構造を縮小すると、発生電界強度が増加し耐圧特性を確保できない。そこで特許文献１に開示されているパワー半導体モジュールでは、高耐圧性樹脂を素子終端部に配置して発生電界を緩和している。しかし、製造工程合理化のためにこの手法をダイシング前のウェハ状態で適用すると、樹脂膜の収縮応力によりウェハに反りが発生する。この発生反りは、樹脂膜の密着性や、ダイシング時のプロセス安定性などへの悪影響が懸念される。今後、ウェハのサイズが大きくなると発生反りは増加する方向なのでますます悪影響が懸念される。 Also in power semiconductor modules using SiC semiconductor elements, it is desired to increase the active area through which current flows from the viewpoint of cost reduction. For this purpose, it is necessary to narrow the termination region around the element. However, if the termination structure of the element is reduced, the generated electric field strength increases and the breakdown voltage characteristic cannot be ensured. Therefore, in the power semiconductor module disclosed in Patent Document 1, a high pressure resistant resin is arranged at the element termination portion to reduce the generated electric field. However, if this method is applied in a wafer state before dicing for rationalizing the manufacturing process, the wafer warps due to the shrinkage stress of the resin film. This generated warpage may have an adverse effect on the adhesiveness of the resin film and process stability during dicing. In the future, as the size of the wafer increases, the warping will increase, so there is a concern about the adverse effects.
　一方、今後の傾向として高温動作化が進められているが、そのためにはＳｉＣ半導体素子接合部の高耐熱化が必要になる。高耐熱接合材料として、例えば焼結金属系の接合材料の開発が進められているが、緻密な接合状態を実現させるには、接合時に素子を加圧することが有利である。しかし、特許文献１の樹脂膜を形成した素子では、貼り付きが発生するため、樹脂部分を加圧することができない。このため、樹脂膜を形成した素子周縁部を避け、素子中央部のみを加圧せざるを得ないため、均一な接合状態を実現することが難しい。 On the other hand, high-temperature operation is being promoted as a future trend. To that end, it is necessary to increase the heat resistance of the SiC semiconductor element junction. For example, a sintered metal-based bonding material has been developed as a high heat-resistant bonding material. However, in order to realize a dense bonding state, it is advantageous to pressurize the element during bonding. However, in the element in which the resin film of Patent Document 1 is formed, sticking occurs, and the resin portion cannot be pressurized. For this reason, it is difficult to realize a uniform bonded state because it is necessary to press only the central part of the element while avoiding the peripheral part of the element on which the resin film is formed.
　そこで、ウェハ状態で適用してもウェハ変形発生を抑制でき、個片化した素子では回路基板に接合する際に加圧領域の制限の無い耐圧特性を確保したＳｉＣ半導体素子並びにＳｉＣ半導体素子搭載パワー半導体モジュール装置を提供することが課題となる。 Therefore, even when applied in a wafer state, it is possible to suppress the occurrence of wafer deformation, and in the case of individualized elements, SiC semiconductor elements and SiC semiconductor element mounting powers that have ensured withstand voltage characteristics without limitation of the pressurizing region when bonded to a circuit board Providing a semiconductor module device is an issue.
　上記課題を解決するために、本発明に係るパワー半導体モジュールは、周縁部に終端構造領域を有すると共にＳｉＣを含んでなるＳｉＣ半導体素子と、前記ＳｉＣ半導体素子を封止するシリコーンゲルと、前記終端構造領域上に配置された第一の無機層と、前記第一の無機層と前記シリコーンゲルとの間に配置された第二の無機層とを備えることを特徴とする。 In order to solve the above-mentioned problems, a power semiconductor module according to the present invention includes a SiC semiconductor element having a termination structure region at a peripheral portion and containing SiC, a silicone gel for sealing the SiC semiconductor element, and the termination A first inorganic layer disposed on the structural region, and a second inorganic layer disposed between the first inorganic layer and the silicone gel are provided.
　また、上記課題を解決するために、本発明に係るＳｉＣ半導体素子は、周縁部に終端構造領域を有すると共にＳｉＣを含んでなるＳｉＣ半導体素子であって、前記終端構造領域上に第一の無機層を備えると共に、最表部に第二の無機層を備えることを特徴とする。 In order to solve the above-described problem, an SiC semiconductor device according to the present invention is a SiC semiconductor device having a termination structure region at a peripheral portion and containing SiC, and includes a first inorganic layer on the termination structure region. A layer is provided, and a second inorganic layer is provided on the outermost part.
　また、上記課題を解決するために、本発明に係るＳｉＣ半導体素子の製造方法は、上記の本発明のＳｉＣ半導体素子を製造する方法であって、前記ＳｉＣ半導体素子を形成するＳｉＣウェハに前記第二の無機層を接着する工程と、表面に前記第二の無機層が配置されたＳｉＣウェハを個々のチップに切り離すダイシング工程とを含むことを特徴とする。 In order to solve the above problems, a method of manufacturing an SiC semiconductor device according to the present invention is a method of manufacturing the SiC semiconductor device of the present invention as described above, wherein the SiC wafer is formed on the SiC wafer on which the SiC semiconductor device is formed. The method includes a step of adhering two inorganic layers, and a dicing step of separating the SiC wafer having the second inorganic layer disposed on the surface thereof into individual chips.
　本発明によれば、耐圧特性を確保し、ウェハ大口径化にも対応できると共に、個片化した素子全面を加圧しながら接合可能な、高耐熱性接合に有利なＳｉＣ半導体素子、並びにＳｉＣ半導体素子を搭載したパワー半導体モジュールを提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, the SiC semiconductor element which can ensure a pressure | voltage resistant characteristic, can respond to a wafer large-diameter, and can be joined while pressurizing the element whole surface, and is advantageous for high heat-resistant joining, and SiC semiconductor A power semiconductor module on which an element is mounted can be provided.
本発明の一実施形態に係るパワー半導体モジュールの模式断面図である。1 is a schematic cross-sectional view of a power semiconductor module according to an embodiment of the present invention. 本発明の一実施形態に係るＳｉＣ半導体素子の全体の模式断面図である。1 is a schematic cross-sectional view of an entire SiC semiconductor device according to an embodiment of the present invention. 本発明の一実施形態に係るＳｉＣ半導体素子の端部の模式断面図である。It is a schematic cross section of the edge part of the SiC semiconductor element which concerns on one Embodiment of this invention. 本発明の一実施形態に係るＳｉＣ半導体素子の平面模式図であって、ＳｉＣ半導体素子がダイオード素子である場合の個片化されたＳｉＣ半導体素子の平面模式図である。It is a plane schematic diagram of the SiC semiconductor device concerning one embodiment of the present invention, Comprising: It is a plane schematic diagram of the separated SiC semiconductor device in case a SiC semiconductor device is a diode element. 本発明の一実施形態に係るＳｉＣ半導体素子の平面模式図であって、ＳｉＣ半導体素子のゲートパッドおよびセンスパッドが素子周辺部に配置される場合の個片化されたＳｉＣ半導体素子の平面模式図である。1 is a schematic plan view of an SiC semiconductor device according to an embodiment of the present invention, and is a schematic plan view of an individualized SiC semiconductor device when a gate pad and a sense pad of the SiC semiconductor device are arranged in the periphery of the device. It is. 本発明の一実施形態に係るＳｉＣ半導体素子の平面模式図であって、ＳｉＣ半導体素子のゲートパッドが素子中央部に配置されると共にセンスパッドが素子周辺部に配置される場合の個片化されたＳｉＣ半導体素子の平面模式図である。FIG. 3 is a schematic plan view of a SiC semiconductor device according to an embodiment of the present invention, wherein the SiC semiconductor device is separated into pieces when the gate pad of the SiC semiconductor device is disposed at the center of the device and the sense pad is disposed at the periphery of the device. It is the plane schematic diagram of the SiC semiconductor element. 本発明の一実施形態に係るＳｉＣ半導体素子の端部の模式断面図である。It is a schematic cross section of the edge part of the SiC semiconductor element which concerns on one Embodiment of this invention. 本発明の一実施形態に係るＳｉＣ半導体素子の形成方法を示す図である。It is a figure which shows the formation method of the SiC semiconductor element which concerns on one Embodiment of this invention. 本発明の一実施形態に係るＳｉＣ半導体素子の形成方法を示す図である。It is a figure which shows the formation method of the SiC semiconductor element which concerns on one Embodiment of this invention.
　以下、本発明の実施形態のいくつかの例を図面に基づき説明する。 Hereinafter, some examples of embodiments of the present invention will be described with reference to the drawings.
　（第一の実施形態）
　本発明の実施形態に係るＳｉＣ半導体素子搭載パワー半導体モジュール１００の模式断面を図１に示す。ＳｉＣ半導体素子搭載パワー半導体モジュールは、ＳｉＣ半導体素子がスイッチング素子として搭載されていても良いし、フリーホイールダイオード素子として搭載されていても良いし、両方の素子として搭載されていても良い。 (First embodiment)
FIG. 1 shows a schematic cross section of a power semiconductor module 100 equipped with a SiC semiconductor element according to an embodiment of the present invention. In the SiC semiconductor element-mounted power semiconductor module, the SiC semiconductor element may be mounted as a switching element, may be mounted as a free wheel diode element, or may be mounted as both elements.
　図１では、スイッチング素子とダイオード素子の両方にＳｉＣ半導体素子を用いたものを例に説明する。本実施形態に係るパワー半導体モジュール１００は、放熱ベース１１、セラミックス回路基板６、ＳｉＣダイオード素子１Ａ、ＳｉＣスイッチング素子１Ｂ、外部出力端子９Ａ、９Ｂ、及びモジュールケース１０を有している。セラミックス回路基板６は、一方の面に、配線パターン６Ａ１、６Ａ２が設けられ、他方の面に、配線パターン６Ｃを備える。配線パターン６Ｃと放熱ベース１１は、はんだ接合層５Ｂを介して接合される。一方、配線パターン６Ａ１とＳｉＣ半導体素子１Ａ、１Ｂとは、はんだ接合層５Ａを介して接合される。また、正極側と接続される外部出力端子９Ａ（９）は、配線パターン６Ａ１（６Ａ）と直接超音波接合で接合されており、負極側と接続される外部出力端子９Ｂ（９）は、配線パターン６Ａ２（６Ａ）と直接超音波接合で接合されている。なお、ここでは外部出力端子９と配線パターン６Ａとの接続方法は超音波接合としたが、他の接合方法を用いても良い。なお、スイッチング素子１Ｂのゲート及びセンス配線の結線の様子は図中では省略している。 FIG. 1 illustrates an example in which an SiC semiconductor element is used for both the switching element and the diode element. The power semiconductor module 100 according to the present embodiment includes a heat dissipation base 11, a ceramic circuit board 6, a SiC diode element 1 </ b> A, a SiC switching element 1 </ b> B, external output terminals 9 </ b> A and 9 </ b> B, and a module case 10. The ceramic circuit board 6 is provided with wiring patterns 6A1 and 6A2 on one surface and a wiring pattern 6C on the other surface. The wiring pattern 6C and the heat dissipation base 11 are bonded via the solder bonding layer 5B. On the other hand, wiring pattern 6A1 and SiC semiconductor elements 1A and 1B are bonded via solder bonding layer 5A. Further, the external output terminal 9A (9) connected to the positive electrode side is directly joined to the wiring pattern 6A1 (6A) by ultrasonic bonding, and the external output terminal 9B (9) connected to the negative electrode side is connected to the wiring pattern 6A1 (6A). It is joined to the pattern 6A2 (6A) by direct ultrasonic joining. Although the connection method between the external output terminal 9 and the wiring pattern 6A is ultrasonic bonding here, other bonding methods may be used. Note that the state of connection between the gate of the switching element 1B and the sense wiring is omitted in the drawing.
　この外部出力端子９Ａ及び９Ｂは、モジュールケース１０の外部に引き出されて他の機器と接続される。 The external output terminals 9A and 9B are pulled out of the module case 10 and connected to other devices.
　ＳｉＣ半導体素子１Ａ、１Ｂにおける配線パターン６Ａ１側と反対側の面は、ボンディングワイヤー４を介して、外部出力端子９Ｂが接続される配線パターン６Ａ２に接続されている。なお、ＳｉＣスイッチング素子１Ｂの詳細構造については、下記で詳細に説明する。 The surface opposite to the wiring pattern 6A1 side in the SiC semiconductor elements 1A and 1B is connected via the bonding wire 4 to the wiring pattern 6A2 to which the external output terminal 9B is connected. The detailed structure of SiC switching element 1B will be described in detail below.
　モジュールケース１０は、放熱ベース１１に接着剤などを用いて固定されており、内部がシリコーンゲル３で満たされている。 The module case 10 is fixed to the heat dissipation base 11 with an adhesive or the like, and the inside is filled with the silicone gel 3.
　図２は図１のＳｉＣ半導体素子搭載部１１０を拡大したものである。ＳｉＣ半導体素子１Ｂの表面周縁部には無機材２Ｂが配置されている。図２のＳｉＣ半導体素子端部１２０のより詳細な構造を図３に示す。図３に示す素子周縁部の終端構造領域には、ガードリング、ＦＬＲ、ＪＴＥ等を含めた電界緩和構造が設けられており（詳細は省略する）、この領域内で電界集中が発生するため、この領域に厚膜絶縁層を配置する必要がある。本発明者らが特許文献１に開示した技術は、前記厚膜絶縁層として高耐電圧性樹脂を適用している。この材料は比較的低温度の処理で厚膜形成できるため有用な手法である。ただ前記課題を解決するためには、前記高耐電圧性樹脂と同等以上の絶縁破壊強さを有する絶縁材料を適することが可能である。前記高耐電圧樹脂の絶縁破壊強さは２００～３００ｋＶ/ｍｍである。本発明で取り上げた無機材料の絶縁破壊強さは、シリカ系ガラス：～２００ｋＶ/ｍｍ、アルミナ：～６００ｋＶ/ｍｍ、窒化珪素：～１０００ｋＶ/ｍｍ、ＳｉＣ：２５０ｋＶ/ｍｍと前記高耐電圧樹脂と同等以上の特性を有しており、前記高耐電圧樹脂厚膜と同程度の厚さ（５０～５００μｍ）のこれら材料を用いれば同等以上の耐圧特性を確保することができる。さらに、これら無機材料の熱膨張率は高耐電圧樹脂の１/１０程度と低熱膨張性である上に、軟化温度は１０００℃以上と耐熱性にも優れている。これらの特性を有するため、前記無機材料を用いることにより、前記課題を解決することができた。後述する加工性の面からはシリカ系ガラスを用いることが有利であるが、低熱膨張性並びに耐熱性が上記材料並みの材料であれば適用可能であり、上記材料に限定されるものではない。 FIG. 2 is an enlarged view of the SiC semiconductor element mounting portion 110 of FIG. An inorganic material 2B is arranged on the peripheral surface of the surface of the SiC semiconductor element 1B. A more detailed structure of the end portion 120 of the SiC semiconductor device of FIG. 2 is shown in FIG. The termination structure region at the periphery of the element shown in FIG. 3 is provided with an electric field relaxation structure including a guard ring, FLR, JTE, etc. (details are omitted), and electric field concentration occurs in this region. It is necessary to dispose a thick film insulating layer in this region. In the technique disclosed by the present inventors in Patent Document 1, a high voltage resistance resin is applied as the thick film insulating layer. This material is a useful technique because a thick film can be formed by processing at a relatively low temperature. However, in order to solve the above problems, it is possible to use an insulating material having a dielectric breakdown strength equal to or higher than that of the high voltage resistance resin. The dielectric strength of the high withstand voltage resin is 200 to 300 kV / mm. The dielectric breakdown strength of the inorganic material taken up in the present invention is as follows: silica glass: up to 200 kV / mm, alumina: up to 600 kV / mm, silicon nitride: up to 1000 kV / mm, SiC: 250 kV / mm The use of these materials having the same or higher characteristics and the same thickness (50 to 500 μm) as the high withstand voltage resin thick film can ensure the same or higher withstand voltage characteristics. Furthermore, the thermal expansion coefficient of these inorganic materials is about 1/10 that of a high withstand voltage resin and low thermal expansion, and the softening temperature is 1000 ° C. or more, which is excellent in heat resistance. Since it has these characteristics, the said subject was able to be solved by using the said inorganic material. From the viewpoint of workability described later, it is advantageous to use silica-based glass, but it can be applied as long as the material has low thermal expansion and heat resistance comparable to the above materials, and is not limited to the above materials.
　上記無機材料を図３の第二の無機層２Ｂに適用する構成としていくつかの手法がある。図３に示す構成では、ＳｉＣ２５の上にＳｉＯ２などの第一の無機層２Ａが配置し、その上に保護層２０が形成されている。保護層には、ポリイミドなどの有機物や窒化珪素などの無機物が用いられているが、これら材料に限定されるものではない。第二の無機層２Ｂの厚さは、耐圧確保の面から５０μｍ以上は必要であり、厚さ数μｍ程度の第一の無機層２Ａの場合に適用可能な、蒸着、スパッタ、ＣＶＤなどの手法で素子上に直接堆積させることは困難である。本発明では、接着層８で第二の無機層２Ｂを配置する方法を開発した。 There are several methods for applying the inorganic material to the second inorganic layer 2B of FIG. In the configuration shown in FIG. 3, the first inorganic layer 2A such as SiO 2 is disposed on the SiC 25, and the protective layer 20 is formed thereon. The protective layer is made of an organic material such as polyimide or an inorganic material such as silicon nitride, but is not limited to these materials. The thickness of the second inorganic layer 2B is required to be 50 μm or more from the viewpoint of ensuring the pressure resistance, and can be applied to the case of the first inorganic layer 2A having a thickness of about several μm, such as vapor deposition, sputtering, and CVD. It is difficult to deposit directly on the device. In the present invention, a method of arranging the second inorganic layer 2B with the adhesive layer 8 has been developed.
　具体的な製造方法を図６及び図７を用いて説明する。これらの図では、工程順に模式図を示しており、各工程毎に平面図と断面図を配置している。ＳｉＣウェハ上に、所定形状の接着剤８Ａを塗布する（図６(2)）。接着剤としては、例えばポリイミド系樹脂、ポリアミドイミド系樹脂、有機無機ハイブリッド系材料などを用いることができる。耐熱性に優れ、不純物含有量が少ない材料であれば、上記材料に限定されるものではない。接着剤８Ａの塗布手法としては、印刷手法、ディスペンス手法を用いて実施することができる。 A specific manufacturing method will be described with reference to FIGS. In these drawings, schematic views are shown in the order of steps, and a plan view and a cross-sectional view are arranged for each step. An adhesive 8A having a predetermined shape is applied on the SiC wafer (FIG. 6 (2)). As the adhesive, for example, a polyimide resin, a polyamideimide resin, an organic-inorganic hybrid material, or the like can be used. The material is not limited to the above materials as long as the material has excellent heat resistance and a low impurity content. As a method for applying the adhesive 8A, a printing method or a dispensing method can be used.
　この上に、接着剤塗布パターンに合せて予め加工された〔Ａ〕パターン形成無機板を、位置合せして載置して接着する（図６(3)）。〔Ａ〕パターン形成無機板は、上記無機材料で構成されている。上記無機材料の板状材料を作製し、これに所定形状の開口を形成して、〔Ａ〕パターン形成無機板を得ることができる。このパターン形成無機板が、図５の２Ｂの第二の無機層に相当するため、必要な耐圧レベルに応じて、パターン形成無機板の板厚を調整する。 On this, the [A] pattern-formed inorganic plate previously processed according to the adhesive application pattern is positioned and mounted and bonded (FIG. 6 (3)). [A] The pattern-forming inorganic plate is made of the inorganic material. A plate-like material made of the above-mentioned inorganic material is prepared, and openings having a predetermined shape are formed on the plate-like material, thereby obtaining [A] pattern-formed inorganic plate. Since this pattern formation inorganic board is equivalent to the 2nd inorganic layer of 2B of Drawing 5, the board thickness of a pattern formation inorganic board is adjusted according to a required pressure-resistant level.
　開口形成方法としては、上記板材にホトリソグラフィ手法で所定形状のマスクパターンを形成後、材料に応じたエッチング薬剤でエッチング処理して開口する方法、ハードマスクを上記板材に被せてからサンドブラストで開口する方法、レーザ照射して開口する方法、所定形状のケガキラインを設けてから機械的又は熱的ストレスを加えて開口する方法など含めていくつかの方法から適当な手法を適用することができる。 As an opening forming method, a mask pattern having a predetermined shape is formed on the plate material by a photolithographic technique, and then an opening process is performed by etching with an etching agent according to the material. The hard mask is put on the plate material and then opened by sandblasting. Appropriate techniques can be applied from several methods including a method, a method of opening by laser irradiation, and a method of opening by applying mechanical or thermal stress after providing a marking line of a predetermined shape.
　〔Ａ〕パターン形成無機板の接着は、真空ホットプレス装置を用いて、減圧雰囲気下、加熱しながら前記無機板を加圧して貼り付けても良いし、ラミネータを用いて貼り付けても良い。ホットプレスで接着層８Ａの融点以上に加熱しながら加圧して接着する。接着剤の種類によって貼付け条件は異なるが、例えば、不活性雰囲気中、３２０℃、面圧０．３ＭＰａ、加圧時間１分である。このようにして、所定パターンの開口を有する無機板を接着したＳｉＣウェハが完成する。 [A] Bonding of the pattern-forming inorganic plate may be performed by applying pressure by pressing the inorganic plate while heating in a reduced pressure atmosphere using a vacuum hot press apparatus, or by using a laminator. The adhesive is pressed and heated while being heated above the melting point of the adhesive layer 8A by hot pressing. Although the application conditions differ depending on the type of adhesive, for example, in an inert atmosphere, the temperature is 320 ° C., the surface pressure is 0.3 MPa, and the pressing time is 1 minute. In this way, a SiC wafer to which an inorganic plate having a predetermined pattern of openings is bonded is completed.
　次に、ＳｉＣウェハの所定のラインでダイシングすることにより、個片化されたＳｉＣ半導体素子を得ることができる（図７(4)）。個片化したＳｉＣ半導体素子の平面図を図４Ａ、図４Ｂ、図４Ｃに示す。図４Ａはダイオード素子の場合、図４Ｂはゲートパッド及びセンスパッドが素子周辺部に配置される場合、図４Ｃはゲートパッドが素子中央部に配置されると共にセンスパッドが素子周辺部に配置される場合である。 Next, a dicing SiC semiconductor element can be obtained by dicing along a predetermined line of the SiC wafer (FIG. 7 (4)). 4A, 4B, and 4C are plan views of the separated SiC semiconductor elements. 4A shows a case of a diode element, FIG. 4B shows a case where a gate pad and a sense pad are arranged at the periphery of the element, and FIG. 4C shows a case where the gate pad is arranged at the element central part and the sense pad is arranged at the element peripheral part. Is the case.
　ここでは、ＳｉＣ半導体素子の構成として図３の構成で説明したが、各種構成が可能であり、例えば図５に示すように保護層を除いた構成も可能である。 Here, although the configuration of FIG. 3 is described as the configuration of the SiC semiconductor element, various configurations are possible, for example, a configuration excluding the protective layer as shown in FIG. 5 is also possible.
　以上のように、第一の実施形態によれば、ＳｉＣ半導体素子周縁部の終端構造領域上に厚膜無機層を配置することが可能となる。その結果、耐圧特性を確保しつつ、ウェハ状態でも反り発生を抑えられ、大口径ウェハにも適用可能な生産性に優れる構成である。 As described above, according to the first embodiment, it is possible to dispose a thick film inorganic layer on the termination structure region at the periphery of the SiC semiconductor element. As a result, while maintaining the pressure resistance characteristics, it is possible to suppress the occurrence of warpage even in the wafer state, and to be excellent in productivity applicable to a large-diameter wafer.
　（第二の実施形態）
　本発明の第二の実施形態に係わるＳｉＣ半導体素子搭載パワー半導体モジュールを図１及び図２を用いて説明する。第二の実施形態は第一の実施形態の変形例であって、第一の実施形態と異なるのは、ＳｉＣ半導体素子１Ａ、１Ｂを接合する接合層５の接合材料である。第一の実施形態では接合層５にはんだを用いているが、第二の実施形態では接合層５に焼結金属を用いている。この点で、第二の実施形態は第一の実施形態と異なるが、それ以外の点は第一の実施形態と共通である。 (Second embodiment)
An SiC semiconductor element-mounted power semiconductor module according to a second embodiment of the present invention will be described with reference to FIGS. The second embodiment is a modification of the first embodiment, and differs from the first embodiment in the bonding material of the bonding layer 5 that bonds the SiC semiconductor elements 1A and 1B. In the first embodiment, solder is used for the bonding layer 5, but in the second embodiment, sintered metal is used for the bonding layer 5. In this respect, the second embodiment is different from the first embodiment, but the other points are common to the first embodiment.
　セラミックス回路基板６の配線パターン６Ａ１上に、焼結用金属ペーストの所定パターンを、印刷手法あるいはディスペンス手法で形成する。　この上に、第一の実施形態と同じＳｉＣ半導体素子を載置する。この構成で、所定の加熱処理を行うことにより、焼結金属層が形成され、ＳｉＣ半導体素子が接合される。但し、この方法では、焼結層の緻密性が低目であるため、より高信頼用途への応用の場合は、上記加熱処理時にＳｉＣ半導体素子を加圧することにより、焼結層をより緻密なものにすることが有効である。本発明によるＳｉＣ半導体素子では、最表層周縁部に耐熱性に優れる無機層２Ｂを配置しているため、加熱時に２Ｂ部分を加圧しても貼り付きなどの異常は発生しない。このため、素子接合部の全域に渡って緻密な焼結金属層を実現可能である。 A predetermined pattern of a metal paste for sintering is formed on the wiring pattern 6A1 of the ceramic circuit board 6 by a printing method or a dispensing method. On this, the same SiC semiconductor element as in the first embodiment is placed. With this configuration, by performing a predetermined heat treatment, a sintered metal layer is formed, and the SiC semiconductor element is bonded. However, in this method, since the denseness of the sintered layer is low, in the case of application to a higher reliability, the sintered layer is made denser by pressurizing the SiC semiconductor element during the heat treatment. It is effective to make things. In the SiC semiconductor device according to the present invention, since the inorganic layer 2B having excellent heat resistance is disposed at the outermost peripheral portion, no abnormality such as sticking occurs even if the 2B portion is pressurized during heating. For this reason, it is possible to realize a dense sintered metal layer over the entire area of the element joint portion.
　以上のように、第二の実施形態によれば、耐圧特性を確保しつつ、耐熱性に優れるＳｉＣ半導体素子接合を実現することが可能となる。 As described above, according to the second embodiment, it is possible to realize a SiC semiconductor element junction excellent in heat resistance while ensuring a withstand voltage characteristic.
　１Ａ…ダイオード素子、１Ｂ…スイッチング素子、
　１Ｂ１…主電流パッド、１Ｂ２…ゲートパッド、１Ｂ３…センスパッド、
　２…無機層、２Ａ…第一の無機層、２Ｂ…第二の無機層、
　３…シリコーンゲル、
　４…ボンディングワイヤー、
　４Ａ…主電流を流すワイヤー、４Ｂ…ゲートやセンス用ワイヤー、
　５Ａ、５Ｂ…接合層、
　６…セラミックス回路基板、
　６Ａ１、６Ａ２…配線パターン、６Ｂ…セラミックス絶縁板、６Ｃ…金属パターン、
　７Ａ、７Ｂ、７Ｃ…金属層、
　８…接着層、８Ａ…接着剤、
　９…外部出力電極端子、
　１０…ケース、１１…放熱ベース、
　２０…保護層、２５…ＳｉＣ、
　３０…開口部、
　４０…ダイシングライン  1A ... diode element, 1B ... switching element,
1B1 ... main current pad, 1B2 ... gate pad, 1B3 ... sense pad,
2 ... inorganic layer, 2A ... first inorganic layer, 2B ... second inorganic layer,
3 ... silicone gel,
4 ... bonding wire,
4A ... Wire that carries the main current, 4B ... Gate and sense wire,
5A, 5B ... bonding layer,
6 ... Ceramic circuit board,
6A1, 6A2 ... wiring pattern, 6B ... ceramic insulating plate, 6C ... metal pattern,
7A, 7B, 7C ... metal layer,
8 ... Adhesive layer, 8A ... Adhesive,
9: External output electrode terminal,
10 ... Case, 11 ... Heat dissipation base,
20 ... Protective layer, 25 ... SiC,
30 ... opening,
40 ... Dicing line

Claims (13)

  1. 　周縁部に終端構造領域を有すると共にＳｉＣを含んでなるＳｉＣ半導体素子と、
    　前記ＳｉＣ半導体素子を封止するシリコーンゲルと、
    　前記終端構造領域上に配置された第一の無機層と、
    　前記第一の無機層と前記シリコーンゲルとの間に配置された第二の無機層と
    を備えることを特徴とするパワー半導体モジュール。     A SiC semiconductor element having a termination structure region at the periphery and comprising SiC;
    A silicone gel for sealing the SiC semiconductor element;
    A first inorganic layer disposed on the termination structure region;
    A power semiconductor module comprising: a first inorganic layer disposed between the first inorganic layer and the silicone gel.
  2. 　請求項１に記載のパワー半導体モジュールにおいて、
    　前記第二の無機層は、ＳｉＯ２材料、セラミックス材料、ダイヤモンド材料、Ｓｉ材料、およびＳｉＣ材料の中から選ばれる材料である
    ことを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 1,
    The power semiconductor module, wherein the second inorganic layer is a material selected from SiO 2 material, ceramic material, diamond material, Si material, and SiC material.
  3. 　請求項１または２に記載のパワー半導体モジュールにおいて、
    　前記第二の無機層は、前記第一の無機層よりも厚い
    ことを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 1 or 2,
    The power semiconductor module, wherein the second inorganic layer is thicker than the first inorganic layer.
  4. 　請求項１ないし３のいずれか１項に記載のパワー半導体モジュールにおいて、
    　前記第二の無機層と前記第一の無機層との間に少なくとも１層の有機物層が介在している
    ことを特徴とするパワー半導体モジュール。     In the power semiconductor module according to any one of claims 1 to 3,
    A power semiconductor module comprising at least one organic layer interposed between the second inorganic layer and the first inorganic layer.
  5. 　請求項１ないし３のいずれか１項に記載のパワー半導体モジュールにおいて、
    　前記第二の無機層と前記第一の無機層との間に、前記第一の無機層とも前記第二の無機層とも異なる少なくとも１層の無機物層が介在している
    ことを特徴とするパワー半導体モジュール。     In the power semiconductor module according to any one of claims 1 to 3,
    A power characterized in that at least one inorganic layer different from both the first inorganic layer and the second inorganic layer is interposed between the second inorganic layer and the first inorganic layer. Semiconductor module.
  6. 　請求項１ないし５のいずれか１項に記載のパワー半導体モジュールにおいて、
    　前記第二の無機層はシリカ系ガラス材料である
    ことを特徴とするパワー半導体モジュール。     The power semiconductor module according to any one of claims 1 to 5,
    The power semiconductor module, wherein the second inorganic layer is a silica-based glass material.
  7. 　請求項１ないし６のいずれか１項に記載のパワー半導体モジュールにおいて、
    　前記ＳｉＣ半導体素子は、ダイオード素子およびスイッチング素子の少なくともいずれか一方である
    ことを特徴とするパワー半導体モジュール。     The power semiconductor module according to any one of claims 1 to 6,
    The power semiconductor module, wherein the SiC semiconductor element is at least one of a diode element and a switching element.
  8. 　請求項１ないし７のいずれか１項に記載のパワー半導体モジュールにおいて、
    　前記ＳｉＣ半導体素子は、焼結金属材料で接合されている
    ことを特徴とするパワー半導体モジュール。     The power semiconductor module according to any one of claims 1 to 7,
    The power semiconductor module, wherein the SiC semiconductor element is bonded with a sintered metal material.
  9. 　周縁部に終端構造領域を有すると共にＳｉＣを含んでなるＳｉＣ半導体素子であって、
    　前記終端構造領域上に第一の無機層を備えると共に、最表部に第二の無機層を備える
    ことを特徴とするＳｉＣ半導体素子。     A SiC semiconductor element having a termination structure region at the periphery and comprising SiC,
    A SiC semiconductor device comprising a first inorganic layer on the termination structure region and a second inorganic layer on the outermost portion.
  10. 　請求項９に記載のＳｉＣ半導体素子において、
    　前記第二の無機層と前記第一の無機層との間に少なくとも１層の有機物層が介在している
    ことを特徴とするＳｉＣ半導体素子。     The SiC semiconductor device according to claim 9, wherein
    An SiC semiconductor element, wherein at least one organic layer is interposed between the second inorganic layer and the first inorganic layer.
  11. 　請求項９に記載のＳｉＣ半導体素子において、
    　前記第二の無機層と前記第一の無機層との間に、前記第一の無機層とも前記第二の無機層とも異なる少なくとも１層の無機物層が介在している
    ことを特徴とするＳｉＣ半導体素子。     The SiC semiconductor device according to claim 9, wherein
    SiC having at least one inorganic layer different from both the first inorganic layer and the second inorganic layer is interposed between the second inorganic layer and the first inorganic layer. Semiconductor element.
  12. 　請求項９ないし１１のいずれか１項に記載のＳｉＣ半導体素子において、
    　前記第二の無機層はシリカ系ガラス材料である
    ことを特徴とするＳｉＣ半導体素子。     The SiC semiconductor device according to any one of claims 9 to 11,
    The SiC semiconductor element, wherein the second inorganic layer is a silica-based glass material.
  13. 　請求項９ないし１２のいずれか１項に記載のＳｉＣ半導体素子を製造する方法であって、
    　前記ＳｉＣ半導体素子を形成するＳｉＣウェハに前記第二の無機層を接着する工程と、
    　表面に前記第二の無機層が配置されたＳｉＣウェハを個々のチップに切り離すダイシング工程と
    を含むことを特徴とするＳｉＣ半導体素子の製造方法。     A method for producing a SiC semiconductor device according to any one of claims 9 to 12,
    Bonding the second inorganic layer to a SiC wafer forming the SiC semiconductor element;
    And a dicing step of separating the SiC wafer having the second inorganic layer disposed on the surface thereof into individual chips.
PCT/JP2017/003260 2016-03-10 2017-01-31 POWER SEMICONDUCTOR MODULE, SiC SEMICONDUCTOR ELEMENT TO BE MOUNTED ON SAME, AND METHOD OF MANUFACTURING SiC SEMICONDUCTOR ELEMENT WO2017154408A1 (en)

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