Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
  • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/04—Speed or phase control by synchronisation signals
  • H04L7/10—Arrangements for initial synchronisation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0264—Arrangements for coupling to transmission lines
  • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
  • H04L25/0276—Arrangements for coupling common mode signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/0091—Transmitter details

Definitions

• the present invention relates to a circuit arrangement according to the preamble of claim 1 and a method according to the preamble of claim 12.
• the physical layer is the lowest layer in the 0 [pen] S [ystems] [nterconnection] layer model, also known as the OSI reference model, which denotes a layer model of the International Organization for Standardization (ISO) serves as a design basis for communication protocols in computer networks.
• OSI International Organization for Standardization
• the Physical Layer is responsible for Combining, F [orward] E [rror] C [orrection], Modulation, Power Control, Spreading (C [ode] D [ivision] M [ultiple] A [ccess]) and the like and knows neither data nor applications, but only zeros and ones.
• PHY provides logical channels to the overlying link layer (D [ata] L [ink] L [ayer]), especially to a sublayer called M [edia] A [ccess] C [ontrol] layer (transport channels at U [niversal ] M [obile] T [elecommunications] S [ystem]).
• D-PHY basically enables a flexible, cost-effective and fast serial interface for communication links between components within a mobile device.
• a data source such as an application processor provides image data on the M [obile] l [ndustry] P [rocessor] l [nterface] - D [isplay] S [erial] l [nterface] as D-PHY signals for display on a connected data sink, for example on a connected display.
• a data sink such as an application processor, may receive image data from a connected data source, such as a connected camera, in D-PHY format via a MIPI-C [Amera] serial interface.
• a D-PHY protocol-based DSI or DSI-2 or CSI or CSI-2 or CSI-3 includes up to four differential data lines and a differential clock line that electrically connects the application processor to the display and / or camera with copper cable connect.
• the data rate per differential data line is up to 1.5 Gbps (gigabits per second).
• Data transmission required (for example, four times two data lines and once two clock lines).
• the object of the present invention is to further develop a circuit arrangement of the type mentioned at the outset and a method of the type mentioned at the outset. that a serialized signal transmission is always error-free and stable.
• Such a (reference) clock can be specified by at least one clock generator, in particular by at least one phase-locked loop (PLL), for example by at least one clock multiplier unit (CMU).
• PLL phase-locked loop
• CMU clock multiplier unit
• the fundamental problem in starting up the serial data connection is that the clock generator in the transmit arrangement is at the reference clock and then a C [lock /] D [ata] R [ecovery] or clock recovery in the receive arrangement on the
• the time required for the complete synchronization of the transmission link is known in the order of magnitude and depends, among other things, on the data rate at the serial interface. However, there are other dependencies on environmental conditions, such as the operating voltage, the temperature and also the process parameters of the semiconductor technology used.
• the data source in particular the D-PHY data source, waits for a certain minimum time after application of the reference clock plus safety margin before data is created.
• the receiving arrangement according to the invention communicates with the transmission arrangement when the
• Reception arrangement in particular complete synchronization has achieved; this information is then made available to the data source, in particular the D-PHY data source, by the transmitting device.
• the transmission arrangement expediently begins only after receipt of the message of the synchronization by passing through the high-level data actually applied to the transmission arrangement, so that a fault-free and stable serial transmission of the signals, in particular the D-PHY signals, ie data losses and bit errors during serialization of the differential data lines and the differential clock line of the D [isplay] S [erial] l [nterface] and / or the C [amera] S [erial] Interface can be reliably avoided.
• the present invention can be used for synchronizing at least one serial and / or bundled, in particular CSI protocol-based and / or CSI-2 protocol-based and / or CSI-3 protocol-based and / or DSI protocol-based and / or DSI-2 protocol-based , Transmission of both single-ended, logic level based data and clock signals as well as differential, in particular common mode based, data and clock signals, in particular of D-PHY data signals and D-PHY clock signals, for example up to four-bit wide MIPI-D-PHY data signals and MIPI-D-PHY clock signals, between at least one data source, in particular at least one, for example, high-resolution and / or acting as an image source camera and / or at least one application processor, and at least a data sink, in particular at least one application processor and / or at least one, for example, high-resolution and / or for B
• acting as a picture sink, display unit for example, at least one display or at least one monitor apply.
• Fig. 1A is a conceptual schematic representation of an embodiment of the transmission arrangement according to the present invention operating according to the method of the present invention
• FIG. 1 B in conceptual-schematic detail representation of an embodiment of the framer of the transmission arrangement of Fig. 1A
• Fig. 2A is a conceptual schematic representation of an embodiment of the receiving arrangement associated with the transmitting arrangement of Fig. 1A, operating in accordance with the method of the present invention
• FIG. 2B is a conceptual-schematic detailed illustration of an exemplary embodiment of the defibrillator of the receiving arrangement from FIG. 2A;
• FIG. 2B is a conceptual-schematic detailed illustration of an exemplary embodiment of the defibrillator of the receiving arrangement from FIG. 2A;
• FIG. 2B is a conceptual-schematic detailed illustration of an exemplary embodiment of the defibrillator of the receiving arrangement from FIG. 2A;
• Fig. 3 is a conceptual schematic of an embodiment of the circuitry of the present invention operating according to the method of the present invention
• Fig. 4A is a conceptual schematic illustration of an example of a prior art arrangement.
• Fig. 4B is a conceptual schematic representation of an example of the arrangement of Fig. 4A underlying interface configuration with two data channels and a clock line.
• optical basis in particular based on at least one optical medium, for example on the basis of at least one optical waveguide OM (see in detail Fig. 1A, Fig. 2A), such as on the basis of at least one glass fiber and / or based on at least one plastic fiber, and / or
• FIG. 1A shows an exemplary embodiment of the basic structure of a transmission arrangement S for connection to a display interface [interface] data transmission interface IS or else to a C [amera] serial interface Brook interface IS.
• the image data generated in the application processor AP or in the camera KA are transmitted on four data lines or channels CH0 +, CH0-, CH1 +, CH1-, CH2 +, CH2-, CH3 +, CH3- as D-PHY signals up to four bits wide Data transmission interface IS together with D-PH Y-correct clock signals CLK +, CLK- provided.
• the transmission arrangement S receives these signals at an integrated interface logic LS, whose blocks each have at least one state machine for correct interpretation of the D-PHY logic signals and for distinguishing between high-frequency data streams (so-called H [igh] S [peed] data) and low-frequency data streams (so-called L [ow] S [peed] data) may have.
• a framer FR following in the transmission arrangement S ensures the D [irect] C [urrent] balancing of the input signal and generates a frame which can be recognized on the reception side (see FIG Fig. 2A) allows the receiving device E to reassign the received data to the correct output data lines or output channels CH0 +, CH0-, CH1 +, CH1-, CH2 +, CH2-, CH3 +, CH3-.
• the framer FR according to FIG. 1B can be used both with the single-ended logic level-based data signals HSD0, HSD1, HSD2, HSD3 and with the differential data signals DD0 +, DD0-, DD1 +, DD1-, DD2 +, DD2- , DD3 +, DD3- be applied.
• the framer FR By means of its coder KO designed as a 5b / 6b coding block, the framer FR according to FIG. 1 B embeds these differential data signals DD0 +, DD0-, DD1 +, DD1-, DD2 +, DD2-, DD3 +, DD3- into the current of the single-ended logic level based data signals HSDO, HSD1, HSD2, HSD3.
• a multiplexer MU following the framer FR in particular H [igh] S [peed] -mux, generates with the aid of a phase-locked loop, in particular C [lock] M [ultiplier] U [nit], trained clock generator PS the high-frequency serial or bundled transmission signal, which is the output AS of the transmitting device S by means of an output driver AT available.
• the framer FR and the multiplexer MU together form the serializer SE.
• the D-PHY clock signal provided via the clock port CLK +, CLK- and via the clock module CS of the interface logic LS by means of the clock generator PS serves as (clock reference for the serializer SE, in particular for its multiplexer MU, and is described in US Pat This means that the common signal stream S1 is produced, which is transmitted to the receiving arrangement E (see FIG.
• the output driver AT is an integrated laser driver for controlling at least one directly connected laser LA, in particular for controlling at least one directly connected one
• FIG. 2A shows an exemplary embodiment of the basic structure of the receiving arrangement E for connection to a display interface [interface] data transmission interface IE or else to a C [amera] serial interface Brook interface IE.
• serial or bundled data transmitted by the transmitting arrangement S are received via an input amplifier EV of the receiving arrangement E and supplied to an integrated clock and data recovery CD.
• This integrated clock and data recovery CD regenerates from the common signal stream Sl the original D-PHY clock, which via the clock module CE of the interface logic LE directly to the D [isplay] S [erial] l [nterface] or the C [amera ] S [erial] l [nterface] is made available again.
• the remaining serial data stream is unbundled via a demultiplexer DM and parallelized and transferred to a deframer DF (see in more detail FIG. 2B), which is fundamentally mirror-inverted to the frame FR according to FIG.
• the demultiplexer DM and the deframer DF together form the deserializer DS.
• the deframer FR can, by means of its decoder DK embodied as a 6b / 5b decoding block, derive the differential data signals DD0 +, DD0-, DD1 +, DD1-, DD2 +, DD2-, DD3 +, DD3- from the single-ended, based on logic levels Separate data signals HSDO, HSD1, HSD2, HSD3 and re-allocate the re-aligned data signals to the respective data lines CHO +, CHO-, CH1 +, CH1-, CH2 +, CH2-, CH3 +, CH3-.
• the interface logic blocks LE represented in the receiving arrangement E can each have at least one state machine for correct interpretation of the D-PHY logic signals and for distinguishing between high-frequency data streams and low-frequency data streams. As the illustration of FIG. 2A can be further removed, is the
• Input amplifier EV designed as an integrated transimpedance amplifier, which makes it possible to connect a photodiode FD directly to the receiving device E.
• Fig. 3 shows an embodiment for the synopsis of the transmission arrangement S (see.
• Fig. 1A and the receiving arrangement E (see Fig. 2A). It is a D-PHY transmission line with serial connection or with serialized data stream.
• the D-PHY-H [igh] S [peed] / L [ow] P [ower] data are transmitted by the transmission arrangement S essentially having the serializer SE, and here in particular the multiplexer MU (see FIGS ) and transmitted as a serial data stream to the receiving device E (see Fig. 2A).
• This receiving arrangement E which essentially has the deserializer DS, and in this case in particular the demultiplexer DM (see Fig. 2A), unbundles the serial
• D-PHY-H [igh] S [peed] / L [ow] P [ower] data The D-PHY-CL [oc] K applied to the transmission arrangement S (see Fig. 1A) serves as clock reference for the serializer SE and is embedded in the serial data stream.
• the receiving device E regenerates this clock and outputs it as D-PHY-CL [oc] K again.
• the outputs AE of the receiving arrangement E by at least one, in particular acted upon by at least one logic module GE, switch WE (in Fig. 2A only for reasons of clarity of illustration not shown) with another or further terminal EZ of the receiving arrangement E (see Fig. 2A) are connected.
• This transmission-side connection AZ and this reception-side connection EZ are connected to one another by means of at least one electrical or galvanic connection GA, in particular by means of at least one copper cable one bit wide or by means of at least one electrical line arranged, for example, on at least one printed circuit board.
• This electrical or galvanic connection GA between the transmission-side connection AZ and the reception-side connection EZ is opened during the startup of the serial transmission path on both sides by means of the transmission-side switch WS or by means of the reception-side switch WS in order to address the fundamental problem when starting the serial data connection Referring to Fig.
• the clock generator PS in the transmit array S is referenced to the reference clock and thereafter a C [lock /] D [ata] R [ecovery] or clock recovery CD in the receive array E (see Figs 2A) must synchronize to the data rate of the serial data stream as well as to the frame positions of the data. If data is applied to the serializer SE, in particular to its multiplexer MU, before the entire data transmission path has been completely synchronized, then this data is lost.
• the demultiplexer DM contained in the receiving-side deserializer DS signals the achievement of complete synchronization with the
• This receiving-side block logic GE sends a signature S1 via the electrical or galvanic connection GA to the logic module or the block logic GS in the transmission arrangement S or in the transmission block.
• This transmission-side block logic GS in turn outputs a ready signal SF at the synchronization port SY of the transmission block S.
• This synchronization port SY can be read from the data source, in particular from the D-PHY data source. As soon as the data source recognizes the state of reaching the complete synchronization in this way, the data source via the input ES of the transmission block S immediately data, in particular D-PHY data to create the S sender.
• DD0 ⁇ differential, in particular common mode based, data signal on first data line or first channel CH0 ⁇
• DK decoder in particular 6b / 5b decoding block, of the defiler DF
• EV input amplifiers in particular transimpedance amplifiers
• GA electrical or galvanic connection in particular copper cable or, for
• KO coder especially 5b / 6b coding block, of Framer FR
• optical medium in particular optical waveguide, for example glass fiber and / or plastic fiber
• PS clock generator in particular phase-locked loop, for example Clock Multiplier

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Power Engineering (AREA)
• Dc Digital Transmission (AREA)
• Information Transfer Systems (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Logic Circuits (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Related Child Applications (1)

Publications (2)

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ID=47556994

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• 2012
  • 2012-08-16 JP JP2014525314A patent/JP6126599B2/ja not_active Expired - Fee Related
  • 2012-08-16 EP EP12813746.0A patent/EP2745458B1/de active Active
  • 2012-08-16 DE DE112012003367.1T patent/DE112012003367A5/de not_active Withdrawn
  • 2012-08-16 WO PCT/DE2012/200050 patent/WO2013023652A2/de not_active Ceased
• 2014
  • 2014-02-14 US US14/181,407 patent/US9455826B2/en active Active

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