WO2013010389A1 - 发光二极管封装结构及其制造方法 - Google Patents

发光二极管封装结构及其制造方法 Download PDF

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WO2013010389A1
WO2013010389A1 PCT/CN2012/072310 CN2012072310W WO2013010389A1 WO 2013010389 A1 WO2013010389 A1 WO 2013010389A1 CN 2012072310 W CN2012072310 W CN 2012072310W WO 2013010389 A1 WO2013010389 A1 WO 2013010389A1
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type layer
electrode
layer
insulating substrate
package structure
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PCT/CN2012/072310
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English (en)
French (fr)
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李晋闽
杨华
伊晓燕
王军喜
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中国科学院半导体研究所
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Priority claimed from CN 201110198226 external-priority patent/CN102255034B/zh
Priority claimed from CN 201110198263 external-priority patent/CN102231421B/zh
Application filed by 中国科学院半导体研究所 filed Critical 中国科学院半导体研究所
Priority to US14/232,443 priority Critical patent/US9246052B2/en
Publication of WO2013010389A1 publication Critical patent/WO2013010389A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body

Definitions

  • the invention belongs to the field of semiconductor technology, and in particular to a light emitting diode package structure prepared by a wafer level in-situ packaging technology and a manufacturing method thereof. Background technique
  • the preparation process of LEDs is generally divided into three main steps: material epitaxy, chip process, and chip packaging.
  • material epitaxy is generally divided into three main steps: material epitaxy, chip process, and chip packaging.
  • the basic function of a semiconductor device package is to connect tiny-sized chip electrodes to a relatively large-sized electrode structure for practical use.
  • the LED packaging process generally uses a certain substrate, a package or a bracket, and the LED chip is bonded to the substrate, the tube or the bracket in some manner, and then the electrodes on the upper part of the chip are connected by a gold ball bonding process. Connect to the corresponding electrode on the substrate, the tube case or the bracket to achieve electrical connection, and finally seal or cover the substrate, the tube case or the bracket with a transparent encapsulating material in some way, sometimes forming the transparent material into a certain macroscopic
  • the shape is used to improve the light extraction efficiency, and the corresponding fluorescent material is used for sealing or covering, in order to realize the special purpose patents US2010267174A1, US2005151142AU CN201081157Y, CN201074776Y.
  • An object of the present invention is to provide an LED package structure capable of integrating a chip of a light emitting diode
  • the preparation process and the chip packaging process use the substrate of the chip itself as a package substrate, simplify the process path of the light emitting diode, reduce the overall process cost, provide the minimum light emitting diode package volume, minimize the total process steps, and reduce the heat resistance of the device package. Better control of the electrical and optical properties of LEDs, with the advantages of simplicity and low cost.
  • the present invention provides an LED package structure comprising: an insulating substrate having through holes on both sides thereof, the through holes being filled with a conductive metal; and an n-type layer formed on the insulating liner On the bottom, and covering a large area of the insulating substrate, one side of the insulating substrate is formed with a surface, and the n-type layer on the other side of the mesa is matched with a through hole of the insulating substrate to form a hole therein. Filled with a conductive metal;
  • An active layer is formed on the n-type layer, the active layer having an area smaller than an area of the n-type layer and located on one side of the n-type layer;
  • a p-type layer being formed on the active layer
  • An insulating layer is located on one side of the n-type layer, the active layer and the p-type layer and covers an upper surface of the partial p-type layer;
  • a P electrode covering the insulating layer and covering an upper surface of a portion of the P-type layer, the P electrode being connected to a conductive metal in the via hole on the insulating substrate;
  • An n-electrode formed on a side above the n-type layer and a conductive gold first back electrode in the via hole on the insulating substrate, the first back electrode being formed on a side of the back surface of the insulating substrate, The first back electrode is connected to the P electrode through a conductive metal in the via hole on the insulating substrate;
  • the second back electrode is formed on the other side of the back surface of the insulating substrate, and the second back electrode is connected to the n electrode through a conductive metal in the via hole on the insulating substrate; a substrate; an optical component, the optical component is packaged on a substrate to complete fabrication of the device.
  • the material of the insulating substrate is sapphire or silicon carbide or aluminum nitride.
  • the material of the n-type layer is n-type gallium nitride.
  • the material of the active layer is a quantum well structure made of a gallium nitride material.
  • the material of the p-type layer is P-type gallium nitride.
  • the material of the insulating layer is silicon oxide or silicon nitride.
  • the P electrode, the n electrode, the first back electrode and the second back electrode are conductive metals.
  • the optical element is a resin, silica gel or glass, or a combination thereof. The invention also provides a method for fabricating a light emitting diode package structure, comprising the following steps:
  • the n-type layer and the p-type layer in the epitaxial structure are upright or inverted.
  • the material of the insulating substrate is sapphire or silicon carbide or aluminum nitride.
  • the material of the n-type layer is n-type gallium nitride.
  • the material of the active layer is a quantum well structure made of a gallium nitride material.
  • the material of the p-type layer is P-type gallium nitride.
  • the material of the insulating layer is silicon oxide or silicon nitride.
  • the P electrode, the n electrode, the first back electrode and the second back electrode are conductive metals.
  • the optical element is a resin, silica gel or glass, or a combination thereof.
  • FIG. 1 is a cross-sectional view showing the in-situ package structure of the light emitting diode of the present invention. detailed description
  • the present invention provides an LED package structure including: an insulating substrate 11 having through holes 111 on both sides thereof, the through holes 111 are filled with a conductive metal, and the insulating liner
  • the material of the bottom 11 is sapphire or silicon carbide or aluminum nitride, and the insulating property is good; the thickness of the insulating substrate 11 can be thinner than the conventional process, less than 1000 um, which can effectively reduce the thermal resistance of the device;
  • the through hole 111 a circular hole or a groove;
  • the conductive metal filled in the through hole 111 is completely filled or partially filled, and the partial filling means that a sidewall of the through hole 111 is filled with a conductive metal;
  • An n-type layer 12 is formed on the insulating substrate 11 and covers a majority of the area of the insulating substrate 11, such that one side of the insulating substrate 11 forms a first mesa 112, and the other side of the mesa 112
  • the n-type layer 12 is matched with the through hole 111 of the insulating substrate 11 with a hole 121 filled with a conductive metal, and the material of the n-type layer 12 is n-type gallium nitride;
  • the active layer 13, the active layer 13 is formed on the n-type layer 12, the active layer 13 has an area smaller than the area of the n-type layer 12, and is located on one side of the n-type layer 12, the active layer 13
  • the material is a quantum well structure made of a gallium nitride material
  • the p-type layer 14 is formed on the active layer 13, and the material of the p-type layer 14 is p-type gallium nitride;
  • An insulating layer 15 is located on one side of the n-type layer 12, the active layer 13 and the p-type layer 14 and covers an upper surface of a portion of the P-type layer 14.
  • the insulating layer 15 is made of silicon oxide or nitrogen. Silicon
  • the p electrode 16 covers the insulating layer 15, and covers the upper surface of a portion of the p-type layer 14, and the p-electrode 16 is connected to the conductive metal in the via hole 111 on the insulating substrate 11;
  • the n electrode 17 is formed on one side of the n-type layer 12, and is connected to the conductive metal in the via hole 111 on the insulating substrate 11;
  • a second back electrode 19 which is formed on the other side of the back surface of the insulating substrate 11, and the second back electrode 19 is connected to the n electrode 17 through a conductive metal in the through hole 111 on the insulating substrate 11. ;
  • the P electrode 16, the n electrode 17, the first back electrode 18, and the second back electrode 19 are non-metal conductive materials or conductive metals; wherein the first back electrode 18 and the second back electrode 19 are solderable. Metal or alloy to facilitate soldering the package structure to other circuit structures; Each of the foregoing portions forms a substrate of the device;
  • the optical component 20 is encapsulated on a substrate to complete fabrication of the device.
  • the optical element 20 is made of resin or silica gel or glass or other transparent material alone or in combination; the optical element 20 can adjust the external light field distribution; the optical element 20 can protect the substrate of the device from moisture, dust and The intrusion of harmful gases; the optical element 20 can enhance the luminous efficiency of the device; wherein the optical element 20 can function as a fluorescent conversion.
  • the present invention provides a method for fabricating an LED package structure, comprising the steps of: sequentially growing an n-type layer 12, an active layer 13 and a P-type on a dielectric substrate by means of metal organic vapor phase epitaxy.
  • the layer 14 is formed with an epitaxial layer; wherein the material of the insulating substrate 11 is sapphire or silicon carbide or aluminum nitride; wherein the n-type layer 12 and the p-type layer 14 in the epitaxial structure are upright or inverted.
  • the material of the n-type layer 12 is n-type gallium nitride, wherein the material of the active layer 13 is a quantum well structure made of a gallium nitride material, wherein the material of the p-type layer 14 is p-type gallium nitride.
  • one side of the P-type layer 14 is etched downward, and the etching depth reaches the surface of the n-type layer 11 to form a first mesa 112, and the other side of the p-type layer 14 is etched downward.
  • the etching depth reaches the surface of the insulating substrate 12 to form a second mesa 122; the etching method of the p-type layer 14 is dry etching or wet etching;
  • a conductive via 111 is formed on the first mesa 112 and the second mesa 122, and a conductive metal is formed in the conductive via 111.
  • the conductive via 111 may be a circular hole or a groove; the conductive via 111 is processed by laser Hole or dry etching or optically assisted wet etching; the number of the conductive vias 111 is not limited; the method of filling the metal in the conductive via 111 is plasma sputtering or electron beam evaporation or electroless plating or electrochemical plating or Mechanical filling
  • An insulating layer 15 is formed on a side close to the epitaxial layer of the first mesa 112 and covering a portion of the upper surface of the p-type layer 14; wherein the insulating layer 15 is made of silicon oxide or silicon nitride; and the insulating layer 15 is made of electrons. Number evaporation or PECVD or ion sputtering;
  • a p-electrode 16 is formed on the insulating layer 15 and covered with the insulating layer 15, and the p-electrode 16 covers a portion of the p-type layer 14 and is connected to the conductive metal in the conductive via 111; the p-electrode 16 forms an ohmic contact with the p-type layer 14. And forming a good current spread on the p-type layer 14;
  • n-electrode 17 is formed on the conductive via 111 on the second mesa 122, the n-electrode 17 being connected to the conductive metal in the conductive via 111; the n-electrode 17 is in ohmic contact with the n-type layer 12, and is in the n-type layer Forming a good current spread on 12;
  • the P electrode 16 and the n electrode 17 contain a conductive metal.
  • An optical component 20 is packaged on the substrate of the device.
  • the optical element 20 is a resin, a silica gel, a glass or The transparent material 20 can be used to support the device; wherein the optical element 20 can protect the device from moisture, harmful gas or dust; wherein the optical element 20 can To improve the luminous efficiency of the device; wherein the optical element 20 can function as a fluorescent conversion; wherein the optical element 20 can function to regulate the external light field distribution.
  • the insulating substrate 11 is thinned, and the substrate can be thinner than a conventional process due to the presence of the optical element 20, so that the device can have a lower thermal resistance;
  • a first back electrode 18 and a second back electrode 19 are respectively formed on both sides of the back surface of the thinned insulating substrate 11, and the first back electrode 18 and the second back electrode 19 respectively pass through the conductive metal in the conductive via 111 and The p electrode 16 and the n electrode 17 are connected, and the substrate of the device is obtained above; wherein the first back electrode 18 and the second back electrode 19 are conductive metals; wherein the first back electrode 18 and the second back electrode 19 are solderable The metal or alloy facilitates soldering of the package structure to other circuit structures.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Devices (AREA)

Abstract

本发明提供一种发光二极管封装结构及其制作方法。发光二极管封装结构，包括：绝缘衬底的两侧开有通孔，并填充有导电金属；n型层制作在绝缘衬底上，其上开有孔，并填充有导电金属；有源层制作在n型层上；p型层制作在有源层上；绝缘层位于前述n型层、有源层和p型层的一侧并覆盖部分p型层的上表面；p电极覆盖绝缘层，并覆盖部分p型层的上表面；n电极制作在n型层上面的一侧，与绝缘衬底上的通孔中的导电金属连接；第一背电极制作在绝缘衬底的背面的一侧，该第一背电极通过绝缘衬底上的通孔中的导电金属与p电极连接；第二背电极制作在绝缘衬底的背面的另一侧，该第二背电极通过绝缘衬底上的通孔中的导电金属与n电极连接；前述各部分形成器件的基底；光学元件封装于基底上，完成器件的制作。

Description

发光二极管封装结构及其制造方法 技术领域
本发明属于半导体技术领域， 特别是指利用晶圆级原位封装技术制备的发光二 极管封装结构及其制造方法。 背景技术
目前发光二极管的制备工艺一般分为材料外延、 芯片工艺、 芯片封装三个主要 的步骤。 半导体器件封装的基本功能就是将微小尺寸的芯片电极连接到尺寸相对较 大的电极结构上， 以方便实际使用。
发光二极管封装工艺一般都要使用某种基板、 管壳或者支架， 将发光二极管芯 片通过某种方式粘结在该基板、 管壳或者支架上， 然后通过金丝球焊工艺将芯片上 部的电极连接到基板、 管壳或者支架上的相应电极上以实现电连接， 最后通过某种 方式在该基板、 管壳或者支架上使用透明封装材料加以密封或者覆盖， 有时也将该 透明材料形成某种宏观形状以提高光提取效率， 也有使用相应的具有荧光功能的材 料进行密封或者覆盖， 以实现专门的用途专利 US2010267174A1、 US2005151142AU CN201081157Y、 CN201074776Y . US2008089064A1、 CN201074776Y CN101222012A. CN101409266A、 CN10137137B、 CN101060116B、 EP2270889A2中分别描述了各种封装 形式及其专门的用途。 随着技术的进步， 外延与芯片工艺在发光二极管成本中所占 的比例相对降低， 而封装步骤由于耗费材料和工艺步骤较多且技术含量较低， 其成 本难以降低。 因此发光二极管封装的集成化、 小型化是一个发展的趋势， 目前巳有 一些发光二极管的晶圆级封装方法被公布基本上都是利用某种其它类型的晶圆（如 硅片、 陶瓷片等)作为基板支撑发光二极管芯片， 如采钰科技的 A1N基板上的发光二 极管封装形式。 一些芯片尺度的发光二极管封装（日月光半导体制造股份有限公司 ZL200610108560. 4 , 中国台湾晶元光电股份有限公司 US20100163907A1)也被公开， 但是均仍需要多次转移衬底或多个衬底， 其材料成本和工艺成本仍然较高。 目前绝 大多数发光二极管均使用上述各种封装结构。 发明内容
本发明的目的是提供一种发光二极管封装结构， 其可整合发光二极管的芯片制 备工艺和芯片封装工艺， 利用芯片本身的衬底作为封装基板， 简化发光二极管的工 艺路径， 降低全工艺成本， 提供最小的发光二极管封装体积， 最少的全工艺步骤， 降低器件封装热阻， 实现对发光二极管电学和光学性能更好的控制， 并具有简单、 成本低等优点。
本发明提供一种发光二极管封装结构， 包括- 绝缘衬底， 该绝缘衬底上面的两侧开有通孔， 该通孔中填充有导电金属； n型层， 该 n型层制作在绝缘衬底上， 并覆盖绝缘衬底的大部分面积， 使绝缘 衬底的一侧形成一台面， 该台面的另一侧的 n型层上与绝缘衬底的通孔配合开有一 孔， 该孔中填充有导电金属；
有源层， 该有源层 制作在 n型层上， 该有源层的面积小于 n型层的面积， 而位 于 n型层的一侧；
p型层， 该 p型层制作在有源层上；
绝缘层， 该绝缘层位于前述 n型层、 有源层和 p型层的一侧并覆盖部分 p型层 的上表面；
P电极， 该 P电极覆盖绝缘层， 并覆盖部分 P型层的上表面， 该 P电极与绝缘 衬底上的通孔中的导电金属连接；
n电极， 该 n电极制作在 n型层上面的一侧， 与绝缘衬底上的通孔中的导电金 第一背电极， 该第一背电极制作在绝缘衬底的背面的一侧， 该第一背电极通过 绝缘衬底上的通孔中的导电金属与 P电极连接；
第二背电极， 该第二背电极制作在绝缘衬底的背面的另一侧， 该第二背电极通 过绝缘衬底上的通孔中的导电金属与 n电极连接； 前述各部分形成器件的基底； 光学元件， 该光学元件封装于基底上， 完成器件的制作。
根据本发明的一方面， 绝缘衬底的材料为蓝宝石或碳化硅或氮化铝。
根据本发明的一方面， n型层的材料为 n型氮化镓。
根据本发明的一方面， 有源层的材料为氮化镓材料制作的量子阱结构。
根据本发明的一方面， P型层的材料为 P型氮化镓。
根据本发明的一方面， 绝缘层的材料为氧化硅或氮化硅。
根据本发明的一方面， P电极、 n电极、 第一背电极和第二背电极为导电金属。 根据本发明的一方面， 光学元件为树脂、 硅胶或玻璃， 或及其组合。 本发明还提供一种发光二极管封装结构的制作方法， 包括以下步骤：
1)在绝缘衬底上利用金属有机物气相外延的方法依次生长 n型层、 有源层和 p型 层， 形成外延层；
2)采用光刻工艺在 p型层上面的一侧向下刻蚀， 刻蚀深度到达 n型层的表面形成 第一台面， 在 P型层上面的另一侧向下刻蚀， 刻蚀深度到达绝缘衬底的表面， 形成第 二台面；
3)在第一台面及第二台面上制作导电通孔， 在导电通孔内填充导电金属；
4)在靠近第二台面外延层的一侧并覆盖部分 p型层的上表面， 制作绝缘层；
5)在绝缘层上并覆盖绝缘层制作 p电极， 该 p电极覆盖部分 p型层， 并与导电通孔 中的导电金属连接；
6)在第一台面上的导电通孔上制作 n电极， 该 n电极与导电通孔中的导电金属连 接；
7)将绝缘衬底减薄；
8)在减薄后的绝缘衬底的背面的两侧分别制作第一背电极和第二背电极， 该第 一背电极和第二背电极分别通过导电通孔中的导电金属与 P电极和 n电极连接， 以上 得到器件的基底；
9)在器件的基底上封装一光学元件， 完成基底上器件的制作；
10)采用机械方式将基底上器件切割成独立的器件。
根据本发明的一方面， 所述外延结构中的 n型层和 p型层为正置或颠倒。
根据本发明的- -方面， 绝缘衬底的材料为蓝宝石或碳化硅或氮化铝。
根据本发明的- -方面， n型层的材料为 n型氮化镓。
根据本发明的- -方面， 有源层的材料为氮化镓材料制作的量子阱结构。
根据本发明的- -方面， P型层的材料为 P型氮化镓。
根据本发明的- -方面， 绝缘层的材料为氧化硅或氮化硅。
根据本发明的- -方面， P电极、 n电极、 第一背电极和第二背电极为导电金属。 根据本发明的- -方面， 光学元件为树脂、 硅胶或玻璃， 或及其组合。 附图说明
为了说明本发明的具体内容， 以下结合具体实施例及附图详细说明如后， 其中 : 图 1是本发明中发光二极管原位封装结构剖面图。 具体实施方式
参阅图 1， 本发明提供一种发光二极管封装结构， 包括- 绝缘衬底 11， 该绝缘衬底 11上面的两侧开有通孔 111， 该通孔 111中填充有导 电金属， 所述绝缘衬底 11的材料为蓝宝石或碳化硅或氮化铝， 其绝缘性能良好； 所 述绝缘衬底 11的厚度可以比常规工艺更薄， 小于 l OOum, 能够有效降低器件热阻； 所述通孔 111为圆孔或槽；所述通孔 111中填充的导电金属为全部填充或部分填充， 所述部分填充是指在通孔 111的侧壁上填充一层导电金属；
n型层 12， 该 n型层 12制作在绝缘衬底 11上， 并覆盖绝缘衬底 11的大部分面 积， 使绝缘衬底 11的一侧形成第一台面 112， 该台面 112的另一侧的 n型层 12上 与绝缘衬底 11的通孔 111配合开有孔 121， 该孔 121中填充有导电金属， 所述 n型 层 12的材料为 n型氮化镓；
有源层 13， 该有源层 13 制作在 n型层 12上， 该有源层 13的面积小于 n型层 12的面积， 而位于 n型层 12的一侧， 所述有源层 13的材料为氮化镓材料制作的量 子阱结构；
P型层 14， 该 p型层 14制作在有源层 13上， 所述 p型层 14的材料为 p型氮化 镓；
绝缘层 15， 该绝缘层 15位于前述 n型层 12、 有源层 13和 p型层 14的一侧并 覆盖部分 P型层 14的上表面， 所述绝缘层 15的材料为氧化硅或氮化硅；
P电极 16， 该 p电极 16覆盖绝缘层 15， 并覆盖部分 p型层 14的上表面， 该 p 电极 16与绝缘衬底 11上的通孔 111中的导电金属连接；
n电极 17， 该 n电极 17制作在 n型层 12上面的一侧， 与绝缘衬底 11上的通孔 111中的导电金属连接；
第一背电极 18， 该第一背电极 18制作在绝缘衬底 11的背面的一侧， 该第一背 电极 18通过绝缘衬底 11上的通孔 111中的导电金属与 p电极 16连接；
第二背电极 19， 该第二背电极 19制作在绝缘衬底 11的背面的另一侧， 该第二 背电极 19通过绝缘衬底 11上的通孔 111中的导电金属与 n电极 17连接；
其中所述 P电极 16、 n电极 17、 第一背电极 18和第二背电极 19为非金属导电 材料或导电金属； 其中所述第一背电极 18和第二背电极 19为具有易焊接性的金属 或合金， 便于将本封装结构焊接于其他电路结构中； 前述各部分形成器件的基底；
光学元件 20， 该光学元件 20封装于基底上， 完成器件的制作。 所述光学元件 20为树脂或硅胶或玻璃或其他透明材料单独或组合而成； 所述光学元件 20可以调 节外部光场分布作用； 所述光学元件 20可以保护器件的基底不受水汽、灰尘和有害 气体的侵入作用； 所述光学元件 20 可以提高器件的发光效率作用； 其中光学元件 20可以起到荧光转换作用。
再次参阅图 1，本发明提供一种发光二极管封装结构的制作方法，包括以下步骤： 在一绝缘衬底 11上利用金属有机物气相外延的方法依次生长 n型层 12、有源层 13 和 P型层 14， 形成外延层； 其中绝缘衬底 11的材料为蓝宝石或碳化硅或氮化铝； 其中 所述外延结构中的 n型层 12和 p型层 14为正置或颠倒。 其中 n型层 12的材料为 n型氮化 镓， 其中有源层 13的材料为氮化镓材料制作的量子阱结构， 其中 p型层 14的材料为 p 型氮化镓。
采用光刻工艺在 P型层 14上面的一侧向下刻蚀， 刻蚀深度到达 n型层 11的表面形 成第一台面 112， 在 p型层 14上面的另一侧向下刻蚀， 刻蚀深度到达绝缘衬底 12的表 面， 形成第二台面 122; 该 p型层 14的刻蚀方法为干法刻蚀或湿法腐蚀；
在第一台面 112及第二台面 122上制作导电通孔 111， 在导电通孔 111内制作导电 金属； 该导电通孔 111可以为圆孔或槽； 该导电通孔 111的加工方法为激光打孔或干 法刻蚀或光学辅助湿法腐蚀； 该导电通孔 111的数量不限； 该导电通孔 111内填充金 属的方法为等离子体溅射或电子束蒸发或化学镀或电化学镀或机械填充；
在靠近第一台面 112外延层的一侧并覆盖部分 p型层 14的上表面，制作绝缘层 15; 其中绝缘层 15的材料为氧化硅或氮化硅； 该绝缘层 15的制作方法为电子数蒸发或 PECVD或离子溅射；
在绝缘层 15上并覆盖绝缘层 15制作 p电极 16， 该 p电极 16覆盖部分 p型层 14， 并与 导电通孔 111中的导电金属连接； 该 p电极 16与 p型层 14形成欧姆接触， 并在 p型层 14 上形成良好电流扩展；
在第二台面 122上的导电通孔 111上制作 n电极 17，该 n电极 17与导电通孔 111中的 导电金属连接； 该 n电极 17与 n型层 12形成欧姆接触， 并在 n型层 12上形成良好电流扩 展；
其中 P电极 16、 n电极 17包含导电金属。
在器件的基底上封装一光学元件 20。 其中光学元件 20为树脂、 硅胶、 玻璃或其 他透明材料单独或组合而成； 其中光学元件 20可以起到对器件的支撑作用； 其中光 学元件 20可以起到对器件的保护作用防止水汽、 有害气体或灰尘侵入作用； 其中光 学元件 20可以起到提高器件发光效率作用；其中光学元件 20可以起到荧光转换作用； 其中光学元件 20可以起到调节外部光场分布作用。
将绝缘衬底 11减薄， 由于光学元件 20的存在， 衬底可以比常规工艺更薄， 因而 器件可以具有更低的热阻；
在减薄后的绝缘衬底 11的背面两侧分别制作第一背电极 18和第二背电极 19， 该第一背电极 18和第二背电极 19分别通过导电通孔 111中的导电金属与 p电极 16 和 n电极 17连接， 以上得到器件的基底； 其中第一背电极 18和第二背电极 19为导 电金属； 其中所述第一背电极 18和第二背电极 19为具有易焊接性的金属或合金， 便于将本封装结构焊接于其他电路结构中。
以上所述的具体实施方式， 对本发明的目的、 技术方案和有益效果进行了进一 步的详细说明， 所应理解的是， 以上所述仅为本发明的具体实施方式而巳， 并不用 于限制本发明， 凡在本发明的精神和原则之内， 所做的任何修改、 等同替换、 改进 等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求
1.一种发光二极管封装结构， 包括- 绝缘衬底， 该绝缘衬底上面的两侧开有通孔， 该通孔中填充有导电金属； n型层， 该 n型层制作在绝缘衬底上， 并覆盖绝缘衬底的大部分面积， 使绝缘 衬底的一侧形成台面， 该台面的另一侧的 n型层上与绝缘衬底的通孔配合开有孔， 该孔中填充有导电金属；
有源层， 该有源层 制作在 n型层上， 该有源层的面积小于 n型层的面积， 而位 于 n型层的一侧；
p型层， 该 p型层制作在有源层上；
绝缘层， 该绝缘层位于前述 n型层、 有源层和 p型层的一侧并覆盖部分 p型层 的上表面；
p电极， 该 p电极覆盖绝缘层， 并覆盖部分 p型层的上表面， 该 p电极与绝缘 衬底上的通孔中的导电金属连接；
n电极， 该 n电极制作在 n型层上面的一侧， 与绝缘衬底上的通孔中的导电金 属连接；
第一背电极， 该第一背电极制作在绝缘衬底的背面的一侧， 该第一背电极通过 绝缘衬底上的通孔中的导电金属与 P电极连接；
第二背电极， 该第二背电极制作在绝缘衬底的背面的另一侧， 该第二背电极通 过绝缘衬底上的通孔中的导电金属与 n电极连接； 前述各部分形成器件的基底； 光学元件， 该光学元件封装于基底上， 完成器件的制作。
2.根据权利要求 1所述的发光二极管封装结构， 其中绝缘衬底的材料为蓝宝石 或碳化硅或氮化铝。
3.根据权利要求 1所述的发光二极管封装结构， 其中 n型层的材料为 n型氮化 镓。
4.根据权利要求 1所述的发光二极管封装结构， 其中有源层的材料为氮化镓材 料制作的量子阱结构。
5.根据权利要求 1所述的发光二极管封装结构， 其中 P型层的材料为 P型氮化 镓。
6.根据权利要求 1所述的发光二极管封装结构， 其中绝缘层的材料为氧化硅或 氮化硅。
7.根据权利要求 1所述的发光二极管封装结构， 其中 p电极、 n电极、 第一背 电极和第二背电极为导电金属。
8.根据权利要求 1所述的发光二极管封装结构， 其中光学元件为树脂、 硅胶或 玻璃， 或及其组合。
9.一种发光二极管封装结构的制作方法， 包括以下步骤-
1)在绝缘衬底上利用金属有机物气相外延的方法依次生长 n型层、 有源层和 p 型层， 形成外延层；
2)采用光刻工艺在 p型层上面的一侧向下刻蚀， 刻蚀深度到达 n型层的表面形 成第一台面， 在 P型层上面的另一侧向下刻蚀， 刻蚀深度到达绝缘衬底的表面， 形 成第二台面；
3)在第一台面及第二台面上制作导电通孔， 在导电通孔内填充导电金属；
4)在靠近第二台面外延层的一侧并覆盖部分 p型层的上表面， 制作绝缘层；
5)在绝缘层上并覆盖绝缘层制作 p电极， 该 p电极覆盖部分 p型层， 并与导电 通孔中的导电金属连接；
6)在第一台面上的导电通孔上制作 n电极， 该 n电极与导电通孔中的导电金属 连接；
7)将绝缘衬底减薄；
8)在减薄后的绝缘衬底的背面的两侧分别制作第一背电极和第二背电极， 该第 一背电极和第二背电极分别通过导电通孔中的导电金属与 P电极和 n电极连接， 以 上得到器件的基底；
9)在器件的基底上封装一光学元件， 完成基底上器件的制作；
10)采用机械方式将基底上器件切割成独立的器件。
10.根据权利要求 1所述的发光二极管封装结构的制作方法，其中所述外延结构 中的 n型层和 p型层为正置或颠倒。
11.根据权利要求 1所述的发光二极管封装结构的制作方法，其中绝缘衬底的材 料为蓝宝石或碳化硅或氮化铝。
12.根据权利要求 1所述的发光二极管封装结构的制作方法，其中 n型层的材料 为 n型氮化镓。
13.根据权利要求 1所述的发光二极管封装结构的制作方法，其中有源层的材料 为氮化镓材料制作的量子阱结构。
14.根据权利要求 1所述的发光二极管封装结构的制作方法，其中 p型层的材料 为 P型氮化镓。
15.根据权利要求 1所述的发光二极管封装结构的制作方法，其中绝缘层的材料 为氧化硅或氮化硅。
16.根据权利要求 1所述的发光二极管封装结构的制作方法， 其中 p电极、 n电 极、 第一背电极和第二背电极为导电金属。
17.根据权利要求 1所述的发光二极管封装结构的制作方法，其中光学元件为树 脂、 硅胶或玻璃， 或及其组合。
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