WO2013008587A1 - Circuit intégré à semi-conducteur et module sur lequel ce dernier est monté - Google Patents

Circuit intégré à semi-conducteur et module sur lequel ce dernier est monté Download PDF

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Publication number
WO2013008587A1
WO2013008587A1 PCT/JP2012/065584 JP2012065584W WO2013008587A1 WO 2013008587 A1 WO2013008587 A1 WO 2013008587A1 JP 2012065584 W JP2012065584 W JP 2012065584W WO 2013008587 A1 WO2013008587 A1 WO 2013008587A1
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Prior art keywords
final stage
power amplifier
semiconductor chip
amplifying element
unit transistors
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PCT/JP2012/065584
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English (en)
Japanese (ja)
Inventor
健一 那倉
雅志 岡野
靜城 中島
大部　功
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株式会社村田製作所
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Publication of WO2013008587A1 publication Critical patent/WO2013008587A1/fr

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Definitions

  • the present invention relates to a semiconductor integrated circuit and a module on which the semiconductor integrated circuit is mounted, and particularly relates to a technique effective in eliminating the restriction on the arrangement direction of an amplification element on a semiconductor chip surface.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • EDGE is an abbreviation for Enhanced Data for GSM Evolution
  • Enhanced Data for GPRS is an abbreviation for Wideband, Code, Division, Multiple, Access.
  • Patent Document 1 describes an RF power amplification element called LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Filed Effect Transistor) integrated in a semiconductor integrated circuit built in an RF power amplifier.
  • LDMOSFET Layer Diffused Metal-Oxide-Semiconductor Filed Effect Transistor
  • one drain region formed in a rectangle is formed in the central portion between two gate electrodes formed in a rectangle.
  • Two source regions formed in a rectangular shape are formed in the outer part on the outside.
  • the source region and the source back electrode formed on the back surface of the single crystal silicon substrate are a low-resistance p-type polysilicon film doped with impurities at a high concentration or It is electrically connected by a punching layer formed of a low-resistance metal film.
  • a drain wiring of a multilayer wiring is formed in the drain region, and a plurality of source regions are connected to each other by a source wiring having a wiring layer smaller than the multilayer wiring of the drain wiring. Is electrically connected.
  • Multimode supports communication using multiple communication systems such as GSM and WCDMA
  • multiband supports transmission of multiple frequency bands such as GSM low band, GSM high band, WCDMA low band, and WCDMA high band.
  • GSM low band includes two frequency bands of GSM850 (824 to 849 MHz) and GSM900 (880 to 915 MHz)
  • GSM high band includes two frequency bands of DCS1800 (1710 to 1785 MHz) and PCS1900 (1850 to 1910 MHz). Is included.
  • DCS is an abbreviation for Digital Cellar System
  • PCS is an abbreviation for Personal Communication System.
  • the WCDMA low band includes band 5 (824 to 849 MHz) and band 8 (880 to 915 MHz)
  • the WCDMA high band includes band 1 (1920 to 1980 MHz), band 2 (1850 to 1910 MHz), and band 4 (1710 to 1755 MHz). ).
  • FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention.
  • one drain D region formed in a rectangular shape is formed in the central portion between the two gate electrodes G, and an outer portion outside the two gate electrodes G is formed in the outer portion.
  • Two source regions S formed in a rectangular shape are formed.
  • a contact 7 for connecting to the gate wiring for commonly connecting the gate electrodes of the plurality of LDMOSFETs is formed on the upper and lower portions of each gate electrode of the two gate electrodes G.
  • a plurality of punched layers 4 are formed in each source region of the two source regions S.
  • FIG. 2 is a diagram showing a cross-sectional structure of an RF power amplifying element called LDMOSFET, which was studied by the present inventors prior to the present invention.
  • 1 is a semiconductor chip (P-type single crystal silicon substrate), 2 is a P-type single crystal silicon epitaxial layer, 3 is a groove, 4 is a punched layer, 5 is a P-type well region, and 6 is a gate.
  • Insulating film 7 is a gate electrode, 8 is a cap insulating film, 9 is an N ⁇ type offset drain region, 10 is an N ⁇ type source region, 11 is a P type halo region, and 12 is a sidewall spacer.
  • 13 are N-type offset drain regions, 15 is an N + -type drain region, 16 is an N + -type source region, and 17 is a P + -type semiconductor region.
  • a P-type single crystal silicon epitaxial layer 2 is formed on the P-type single crystal silicon substrate 1.
  • a drain region D including an N-type offset drain region 13 and an N + -type drain region 15 is formed in the central portion between the two gate electrodes G.
  • a source region S including an N ⁇ -type source region 10, a P-type halo region 11, and an N + -type source region 16 is formed in an external portion outside the two gate electrodes G.
  • a P-type well region 5 is formed under the channel formation region, the N ⁇ -type source region 10, the P-type halo region 11, and the N + -type source region 16 immediately below the gate electrode G.
  • the plurality of N + type source regions 16 of the plurality of LDMOSFETs are electrically short-circuited to each other by the P + type semiconductor region 17.
  • a groove 3 is formed so as to penetrate the P-type well region 5 and the P-type single crystal silicon epitaxial layer 2 and reach the upper surface of the P-type single crystal silicon substrate 1.
  • a punching layer 4 made of a silicon film or a low resistance metal film is formed.
  • the N + type source regions 16 of the plurality of LDMOSFETs are electrically connected to the source back electrode 36 via the P + type semiconductor region 17, the punching layer 4, and the P type single crystal silicon substrate 1.
  • the source back electrode 36 is connected to the ground wiring of the RF power amplifier module, and this ground wiring is connected to the ground wiring of the mother board of the mobile communication terminal.
  • FIG. 3 is a diagram showing a configuration of the RF power amplifier module PA_MD studied by the present inventors prior to the present invention.
  • the RF power amplifier module PA_MD includes a high band RF power amplifier 100, a low band RF power amplifier 200, and a bias control unit 300.
  • Each of the RF power amplifiers of the high-band RF power amplifier 100 and the low-band RF power amplifier 200 includes an LDMOSFET Q1 as a first stage amplifying element, an LDMOSFET Q2 as a second stage amplifying element, and an LDMOSFET Q3 as a last stage amplifying element.
  • each RF power amplifier the sources of the plurality of LDMOSFETs Q1 to Q3 are connected to the ground voltage GND, and the power supply voltage Vdd is supplied to the drains of the plurality of LDMOSFETs Q1, Q2, and Q3 via the load inductors L1, L2, and L3.
  • the high-band RF transmission input signal Pin_HB is supplied to the gate of the FET Q1 of the first stage amplifying element via the input matching circuit InMN, and the amplified signal of the drain of the FET Q1 is passed through the inter-stage matching circuit MN.
  • the amplified signal of the FET Q2 is supplied to the gate of the FET Q3 of the final stage amplification element via the interstage matching circuit MN, and the amplified signal of the FET Q3 is supplied to the gate of the FET Q2 of the second stage amplification element via the output matching circuit OutMN. And output as a high-band RF transmission output signal Pout_HB.
  • the low-band RF transmission input signal Pin_LB is supplied to the gate of the FET Q1 of the first stage amplification element through the input matching circuit InMN, and the amplified signal at the drain of the FET Q1 is two-staged through the interstage matching circuit MN.
  • the amplified signal of the FET Q2 is supplied to the gate of the FET Q3 of the final stage amplification element through the interstage matching circuit MN, and the amplified signal of the FET Q3 is supplied to the low band through the output matching circuit OutMN.
  • An RF transmission output signal Pout_LB is output.
  • the bias control unit 300 is supplied with the automatic power control signal Vapc and a plurality of control input signals Cont, so that the bias control unit 300 includes a plurality of RF power amplifiers of the high-band RF power amplifier 100 and the low-band RF power amplifier 200.
  • the gate bias voltage supplied to the gates of the LDMOSFETs Q1, Q2, and Q3 is generated.
  • FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit built in the RF power amplifier module studied by the present inventors prior to the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit built in the RF power amplifier module includes a plurality of LDMOSFETs Q1, Q2, Q3 of the high-band RF power amplifier 100 and a plurality of LDMOSFETs Q1, of the low-band RF power amplifier 200.
  • Q2 and Q3 and the bias control unit 300 are integrated.
  • the extending direction of the long sides of the rectangles of the two gate electrodes of each of the plurality of LDMOSFETs Q1, Q2, and Q3 of the high-band RF power amplifier 100 is the Y direction of the semiconductor chip 1.
  • the direction of the line AA ′ is unified.
  • the extension direction of the long side of the two gate electrodes of the plurality of LDMOSFETs Q1, Q2, and Q3 of the low-band RF power amplifier 200 is also unified to the direction of the AA ′ line that is the Y direction of the semiconductor chip 1 Has been.
  • the conductance which is the amplification gain of the LDMOSFET
  • W / L the gate width W, which is the long side of the rectangle
  • the gate length L which is the short side of the rectangle
  • the gate electrode in the manufacturing process of the semiconductor chip 1
  • the formed photolithography has different dimensional deviations in the X direction and the Y direction of the semiconductor chip 1. Therefore, the extending direction of the long side of the rectangular electrode of one LDMOSFET is the AA ′ line which is the Y direction of the semiconductor chip 1, while the extending direction of the long side of the rectangular electrode of the gate electrode of the other LDMOSFET. Is a BB ′ line in the X direction of the semiconductor chip 1.
  • the gate length L of one LDMOSFET increases, while the gate width W of the other LDMOSFET increases.
  • the conductance of the amplification gain of one LDMOSFET decreases, while the conductance of the amplification gain of the other LDMOSFET increases.
  • the extension direction of the long side of the rectangular gate electrode of each of the LDMOSFETs Q1, Q2, Q3 integrated in the semiconductor chip 1 is the direction of the AA ′ line which is the Y direction of the semiconductor chip 1 To be unified.
  • the first stage amplifier element Q1 generates a relatively small RF output
  • the second stage amplifier element Q2 generates an intermediate RF output.
  • the final stage amplifying element Q3 generates a relatively large RF output. That is, in each RF power amplifier, in order to realize high power efficiency by amplifying a relatively small RF output in the first stage, the first stage amplifying element Q1 has a small element size. Further, in each RF power amplifier, in order to realize high power efficiency by amplification of the intermediate RF output at the second stage, the amplification element Q2 at the second stage has an intermediate element size. Further, in each RF power amplifier, in order to realize high power efficiency by amplification of a relatively large RF output at the final stage, the final stage amplifying element Q3 has a relatively large element size.
  • the plurality of LDMOSFETs Q1, Q2, and Q3 of the high-band RF power amplifier 100 are formed on the rectangular semiconductor chip 1 in the semiconductor integrated circuit studied by the inventors prior to the present invention shown in FIG.
  • a plurality of LDMOSFETs Q1, Q2, and Q3 of the low-band RF power amplifier 200 are arranged on the long side of the semiconductor chip 1 on the lower long side of the rectangular semiconductor chip 1 and arranged in the direction of the BB ′ line that is the X direction of the semiconductor chip 1 It is arranged in the direction of the BB ′ line, which is the X direction.
  • the LDMOSFET of the RF power amplifier is not arranged on the right short side and the left short side of the rectangular semiconductor chip 1, but only the pads of the plurality of input terminals of the bias control unit 300 are arranged. .
  • FIG. 5 is a diagram showing the configuration of another semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit built in the RF power amplifier module includes a plurality of LDMOSFETs Q1, Q2, and Q3 of a GSM type high band RF power amplifier (GSM_HB) 100 and a GSM type low band RF power amplifier.
  • GSM_LB 200 LDMOSFETs Q1, Q2, Q3, WCDMA high band RF power amplifier (WCDMA_HB) 400 LDMOSFETs Q1, Q2 and WCDMA low band RF power amplifier (WCDMA_LB) 500 LDMOSFETs Q1, Q2
  • a bias controller 300 is integrated.
  • the extending direction of the long sides of the rectangular gate electrodes of all the FETs Q1, Q2, and Q3 integrated on the semiconductor chip 1 for the reasons described above is The direction of the semiconductor chip 1 is unified in the direction of the AA ′ line which is the Y direction.
  • the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier (GSM_HB) 100 and the plurality of LDMOSFETs Q1 and Q2 of the WCDMA high band RF power amplifier (WCDMA_HB) 400 are the upper length of the rectangular semiconductor chip 1.
  • the plurality of 500 LDMOSFETs Q1 and Q2 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
  • the right short side and the left short side of the rectangular semiconductor chip 1 are not provided with the LDMOSFET of the RF power amplifier, but only the pads of the plurality of input terminals of the bias control unit 300 are provided. It was.
  • the drain output signal of the last stage amplifying element Q3 of the GSM high-band RF power amplifier 100 and the drain output signal of the last stage amplifying element Q2 of the WCDMA high-band RF power amplifier 400 are from the upper long side of the rectangular semiconductor chip 1. It must be derived to the output matching circuit OutMN outside the semiconductor chip 1. Exactly in the same way, the drain output signal of the last stage amplifying element Q3 of the GSM low band RF power amplifier 200 and the drain output signal of the last stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 are the lower long side of the rectangular semiconductor chip 1. To the output matching circuit OutMN outside the semiconductor chip 1.
  • FIG. 6 is a diagram showing a configuration of an RF power amplifier module studied by the present inventors prior to the present invention incorporating the semiconductor integrated circuit shown in FIG.
  • a semiconductor chip 1 of a semiconductor integrated circuit incorporating a system low-band RF power amplifier 200 and a WCDMA system low-band RF power amplifier 500 is mounted.
  • the drain output signal of the final stage amplifying element Q3 of the RF power amplifier 100 and the drain output signal of the final stage amplifying element Q2 of the RF power amplifier 400 are the external RF power of the semiconductor chip 1 from the upper long side of the rectangular semiconductor chip 1. It is necessary to be supplied to the passive component 44 of the output matching circuit in the upper part of the wiring board 42 of the amplifier module.
  • the drain output signal of the final stage amplifying element Q3 of the RF power amplifier 200 and the drain output signal of the final stage amplifying element Q2 of the RF power amplifier 500 are from the lower long side of the rectangular semiconductor chip 1 to the external RF of the semiconductor chip 1. It is necessary to be supplied to the passive component 44 of the output matching circuit in the lower part of the wiring board 42 of the power amplifier module. As described above, since the drain output signal of the final stage amplifying element is not derived from the right short side and the left short side of the rectangular semiconductor chip 1, the right side portion and the left side portion of the wiring board 42 of the RF power amplifier module are not provided. Only the wiring 43 connected to the pads of the plurality of input terminals of the bias control unit 300 is arranged.
  • the rectangular semiconductor chip 1 is in the X direction of the semiconductor chip 1. Since the length increases in the direction of the line BB ′, the chip size of the semiconductor chip 1 increases. Further, since the RF signal output wiring of the wiring board 42 of the RF power amplifier module incorporating the rectangular semiconductor chip 1 long in the X direction is concentrated only on the upper part and the lower part of the wiring board 42, the wiring layout is reduced. As a result of studies by the present inventors prior to the present invention, the problem that the area and cost of the wiring board 42 are increased due to many restrictions has been clarified.
  • the present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.
  • an object of the present invention is to eliminate restrictions on the arrangement direction of the amplifying element on the semiconductor chip surface.
  • a typical embodiment of the present invention is a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500).
  • the first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at right angles.
  • a first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier ( 500) of the second final stage amplification element (Q2).
  • Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor,
  • the planar shape of the active region is a rectangle.
  • the extending direction of the long sides of the plurality of rectangular regions of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
  • the direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2)
  • the direction of the repeated enlargement is selected in the length direction of the second side (see FIGS. 7 and 8).
  • FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention.
  • FIG. 1 shows a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. It is a figure which shows the planar structure of LDMOSFET integrated.
  • FIG. 2 is a diagram showing a cross-sectional structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention, and is shown in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. It is a figure which shows the cross-section of LDMOSFET integrated.
  • FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention.
  • FIG. 1 shows a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. It is a figure which shows the plan
  • FIG. 3 is a diagram showing a configuration of the RF power amplifier module PA_MD studied by the inventors prior to the present invention, and is integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing the configuration of a high band RF power amplifier 100, a low band RF power amplifier 200, and a bias control unit 300.
  • FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention.
  • FIG. 5 is a diagram showing the configuration of another semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention.
  • FIG. 6 is a diagram showing a configuration of an RF power amplifier module studied by the present inventors prior to the present invention incorporating the semiconductor integrated circuit shown in FIG.
  • FIG. 7 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 8 shows the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, which has a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1.
  • FIG. 2 is a diagram showing a state in which a final stage amplification element Q3 and a large stage size final stage amplification element Q2 of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 are configured.
  • FIG. 9 is a diagram showing a specific state in which the large-amplifier final stage amplification element Q3 of the GSM high-band RF power amplifier 100 according to the first embodiment of the present invention shown in FIG. 8 is configured.
  • FIG. 10 is a diagram illustrating a main part of a specific configuration of the final-stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention illustrated in FIG.
  • FIG. 11 is a diagram illustrating a specific state in which the large-amplifier final stage amplification element Q2 of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention illustrated in FIG. 8 is configured.
  • FIG. 10 is a diagram illustrating a main part of a specific configuration of the final-stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention illustrated in FIG.
  • FIG. 11 is a
  • FIG. 12 is a diagram showing a main part of a specific configuration of final-stage amplifying element Q2 having a large element size of WCDMA low-band RF power amplifier 500 according to Embodiment 1 of the present invention shown in FIG. 13 shows a three-dimensional intersection of the gate electrode G of the LDMOSFET of the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 12 and the first drain wiring DM1.
  • FIG. 6 is a cross-sectional view showing a state where a source wiring electrically connected to a source region S connected to a ground voltage GND functions as an electrostatic shield layer in a portion to be operated.
  • FIG. 14 shows the characteristics of the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 of FIG. 7 shown in FIG. 9 and
  • FIG. 13 is a diagram comparing characteristics of a final stage amplifying element Q2 having a large element size of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 of FIG. 7 shown in FIG.
  • FIG. 15 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 16 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 17 is a diagram showing a planar structure and a sectional structure of a unit transistor Unit_TRS of a planar bipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3.
  • FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3.
  • FIG. 19 is a diagram showing a planar structure and a cross-sectional structure of a unit transistor Unit_TRS of a mesa type heterobipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 20 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region.
  • FIG. 21 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region.
  • FIG. 22 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 23 shows a GSM high-band RF power amplifier 100, a GSM low-band RF power amplifier 200, a bias controller 300, and a WCDMA high-band integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention.
  • FIG. 2 is a diagram showing the configuration of an RF power amplifier 400 and a WCDMA low-band RF power amplifier 500.
  • FIG. 24 is a diagram showing the configuration of the semiconductor chip 1 of the semiconductor integrated circuit and the configuration of the RF power amplifier module PA_MD according to the third embodiment of the present invention.
  • a typical embodiment of the present invention is a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500).
  • the first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at right angles.
  • a first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier is formed along the second side.
  • second final stage amplifying elements (Q2) are formed.
  • Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor,
  • the planar shape of the active region is a rectangle.
  • the extending direction of the long sides of the plurality of rectangular regions of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
  • the direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2)
  • the direction of the repeated enlargement is selected in the length direction of the second side (see FIGS. 7 and 8).
  • the restriction on the arrangement direction of the amplifying element on the semiconductor chip surface can be eliminated.
  • the first RF power amplifier (100) includes a first first stage amplifying element (Q1), and includes a second first stage amplifying element (Q1) of the second RF power amplifier (500).
  • the amplifying elements of the first first stage amplifying element (Q1) and the second first stage amplifying element (Q1) are configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first first stage amplifying element (Q1) and the second first stage amplifying element (Q1) has an active region that determines the gain of each unit transistor, and The planar shape of the region is a rectangle.
  • the extending direction of each long side of the plurality of active regions of the plurality of unit transistors of the first first stage amplifying element (Q1) and the plurality of unit transistors of the second first stage amplifying element (Q1) is selected in the length direction of the second side.
  • the first first stage amplification element (Q1) and the first last stage amplification element (Q3) of the first RF power amplifier (100) are formed on the surface of the semiconductor chip along the first side. .
  • the second first stage amplification element (Q1) and the second last stage amplification element (Q3) of the second RF power amplifier (500) are formed on the surface of the semiconductor chip along the second side. (See FIG. 7).
  • the first RF power amplifier (100) includes a first interstage matching circuit (MN), and includes a second interstage matching circuit (MN) of the second RF power amplifier (500). .
  • the first inter-stage matching circuit (MN) of the first RF power amplifier (100) receives the amplified signal at the output terminal of the first first stage amplifying element (Q1) as the input terminal of the first last stage amplifying element (Q3). To communicate.
  • the second inter-stage matching circuit (MN) of the second RF power amplifier (500) receives the amplified signal at the output terminal of the second first stage amplifying element (Q1) as the input terminal of the second last stage amplifying element (Q2). To communicate.
  • the first first stage amplifying element (Q1), the first interstage matching circuit (MN), and the first last stage amplifying element (Q3) of the first RF power amplifier (100) are arranged along the first side. Formed on the surface of the semiconductor chip.
  • the second first stage amplifying element (Q1), the second interstage matching circuit (MN), and the second last stage amplifying element (Q3) of the second RF power amplifier (500) are along the second side. It is formed on the surface of the semiconductor chip (see FIG. 7).
  • a plurality of first output wires (DM1) are connected to a plurality of output electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3), so that the second final output A plurality of second output wirings (DM1) are connected to a plurality of output electrodes of the plurality of unit transistors of the stage amplifying element (Q2).
  • a plurality of first input wirings (GM1) are connected to a plurality of input electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3), and the plurality of the plurality of unit transistors of the second final stage amplifying element (Q2) are connected.
  • a plurality of second input wirings (GM1) are connected to the plurality of input electrodes of the unit transistor.
  • the extending direction of each wiring of the plurality of first output wirings (DM1) is selected in the length direction of the second side, and the extending direction of each wiring of the plurality of first input wirings (GM1) is the first side. Is selected in the length direction.
  • the extending direction of each wiring of the plurality of second output wirings (DM1) is selected in the length direction of the first side, and the extending direction of each wiring of the plurality of second input wirings (GM1) is the first side. Is selected in the length direction (see FIG. 8).
  • the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of unit transistors of the second final stage amplification element (Q2) are field effect transistors.
  • the field effect transistor has a gate electrode (G), a drain region (D), and a source region (S), and a length direction of the second side of the gate electrode between the drain region and the source region.
  • the rectangular short side of the active region is determined by the gate length (L) of the gate electrode, and the gate width (W) in the length direction of the first side of the gate electrode between the drain region and the source region is determined.
  • the long side of the rectangle of the active region is determined (see FIG. 8).
  • the plurality of first output wirings (DM1) are provided in the plurality of drain regions as the plurality of output electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3). Are connected, and the plurality of second output wirings (DM1) are connected to the plurality of drain regions as the plurality of output electrodes of the plurality of unit transistors of the second final stage amplifying element (Q2).
  • the plurality of first input wirings (GM1) are connected to the plurality of gate electrodes as the plurality of input electrodes of the plurality of unit transistors of the first final stage amplification element (Q3), and the second final stage amplification is performed.
  • the plurality of second input wirings (GM1) are connected to the plurality of gate electrodes as the plurality of input electrodes of the plurality of unit transistors of the element (Q2).
  • the extension direction of each wiring of the plurality of first output wirings (DM1) is selected in the length direction of the second side, and the extension direction of each wiring of the plurality of first input wirings (GM1) is It is selected in the length direction of the first side.
  • the extension direction of each wiring of the plurality of second output wirings (DM1) is selected in the length direction of the first side, and the extension direction of each wiring of the plurality of second input wirings (GM1) is The first side is selected in the length direction (see FIG. 8).
  • the plurality of gate electrodes which are the plurality of input electrodes of the plurality of unit transistors of the second final stage amplifying element (Q2) are the plurality of rectangles.
  • An active region is formed on the surface of the semiconductor chip extending in the length direction of the second side.
  • the plurality of gate electrodes (G) formed in the length direction of the second side and the plurality of second output wirings (DM1) formed in the length direction of the first side are formed on the semiconductor chip. Three-dimensionally intersect on the surface.
  • the source region (GND) connected to the ground voltage (GND) at a portion where the plurality of gate electrodes (G) and the plurality of second output wirings (DM1) intersect three-dimensionally on the surface of the semiconductor chip.
  • a plurality of source lines (24A) electrically connected to S) are formed between the plurality of gate electrodes (G) and the plurality of second output lines (DM1). Yes (see FIGS. 12 and 13).
  • the semiconductor chip is formed with a plurality of punched layers (4) reaching the back surface of the semiconductor chip from the front surface of the semiconductor chip.
  • the plurality of source lines (24A) are electrically connected to a source back surface electrode (36) formed on the back surface of the semiconductor chip through the plurality of punched layers (4). (See FIG. 13).
  • the plurality of unit transistors of the first final stage amplifying element (Q3) and the field effect transistors as the plurality of unit transistors of the second final stage amplifying element (Q2) are LDMOSFETs. (See FIGS. 7 and 8).
  • the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of unit transistors of the second final stage amplification element (Q2) are bipolar transistors. .
  • the bipolar transistor has a plurality of emitter regions, and the plurality of emitter regions are formed on the surface of the semiconductor chip as the plurality of rectangular active regions extending in the length direction of the second side. This is a feature (see FIG. 22).
  • the plurality of unit transistors of the first final stage amplification element (Q3) and the bipolar transistors as the plurality of unit transistors of the second final stage amplification element (Q2) are heterogeneous. It is a bipolar transistor (see FIG. 22).
  • the semiconductor integrated circuit further includes a third RF power amplifier (200).
  • the third side of the semiconductor chip of the semiconductor integrated circuit is arranged substantially parallel to the first side and intersects the second side substantially at a right angle.
  • a third final amplification element (Q3) of the third RF power amplifier (200) is formed on the surface of the semiconductor chip along the third side.
  • the third final stage amplifying element (Q3) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the third final stage amplifying element (Q3) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected in the length direction of the third side (see FIGS. 7 and 8). ).
  • the semiconductor integrated circuit further includes a fourth RF power amplifier (400).
  • the fourth side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the second side and intersects the third side substantially at a right angle.
  • a fourth final stage amplifying element (Q2) of the fourth RF power amplifier (400) is formed on the surface of the semiconductor chip along the fourth side.
  • the fourth final stage amplifying element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element (Q2) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected in the length direction of the fourth side (see FIGS. 7 and 8). ).
  • the third RF power amplifier (200), and the A bias controller (300) is formed at a position between the fourth RF power amplifier (400).
  • the bias control unit (300) is connected to the first first stage amplifying element (Q1) and the first last stage amplifying element (Q3) of the first RF power amplifier (100).
  • the second first stage amplifying element (Q1) and the second last stage amplifying element (Q2) are connected to the third first stage amplifying element (Q1) and the third last stage amplifying element (Q3) of the third RF power amplifier (200).
  • a bias voltage is supplied to each of the fourth first stage amplifying element (Q1) and the fourth last stage amplifying element (Q2) of the fourth RF power amplifier (400) (FIG. 7, FIG. 8).
  • a typical embodiment of another aspect of the present invention is a module in which a semiconductor chip of a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500) is mounted on a wiring board. It is.
  • the first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at a right angle.
  • a first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier is formed along the second side.
  • second final stage amplifying elements (Q2) are formed.
  • Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor,
  • the planar shape of the active region is a rectangle.
  • the extending directions of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3), and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
  • the direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2)
  • the direction of the repeated enlargement is selected in the length direction of the second side.
  • the semiconductor chip is mounted on the wiring board.
  • a first output matching circuit (100_OutMN) of the first RF power amplifier (100) is mounted on a first substrate portion of the wiring board that faces the one side of the semiconductor chip, and faces the two sides of the semiconductor chip.
  • a second output matching circuit (500_OutMN) of the second RF power amplifier (500) is mounted on the second substrate portion of the wiring board.
  • the amplified signal at the output terminal of the first final stage amplifying element (Q3) is supplied to the first output matching circuit (100_OutMN) via the one side of the semiconductor chip.
  • the amplified signal at the output terminal of the second final stage amplifying element (Q2) is supplied to the second output matching circuit (500_OutMN) via the two sides of the semiconductor chip. (See FIG. 24).
  • the restriction on the arrangement direction of the amplifying element on the semiconductor chip surface can be eliminated.
  • the semiconductor integrated circuit further includes a third RF power amplifier (200).
  • the third side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the first side and intersects the second side substantially at a right angle.
  • a third final amplification element (Q3) of the third RF power amplifier (200) is formed on the surface of the semiconductor chip along the third side.
  • the third final stage amplifying element (Q3) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the third final stage amplifying element (Q3) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected in the length direction of the third side.
  • a third output matching circuit (200_OutMN) of the third RF power amplifier (200) is mounted on the third substrate portion of the wiring board facing the three sides of the semiconductor chip.
  • the amplified signal at the output terminal of the third final stage amplifying element (Q3) is supplied to the third output matching circuit (200_OutMN) via the three sides of the semiconductor chip. (See FIG. 24).
  • the semiconductor integrated circuit further includes a fourth RF power amplifier (400).
  • the fourth side of the semiconductor chip of the semiconductor integrated circuit is arranged substantially parallel to the second side and intersects the third side substantially at a right angle.
  • a fourth final stage amplifying element (Q2) of the fourth RF power amplifier (400) is formed on the surface of the semiconductor chip along the fourth side.
  • the fourth final stage amplifying element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element (Q2) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected in the length direction of the fourth side.
  • a fourth output matching circuit (400_OutMN) of the fourth RF power amplifier (400) is mounted on the fourth substrate portion of the wiring board facing the four sides of the semiconductor chip.
  • the amplified signal at the output terminal of the fourth final stage amplification element (Q2) is supplied to the fourth output matching circuit (400_OutMN) through the four sides of the semiconductor chip. (See FIG. 24).
  • the plurality of unit transistors is a field effect transistor.
  • the first final stage amplification element (Q3), the second final stage amplification element (Q2), the third final stage amplification element (Q3), and the fourth final stage amplification element is an LDMOSFET.
  • the first final stage amplification element (Q3), the second final stage amplification element (Q2), the third final stage amplification element (Q3), and the fourth final stage amplification element ( The plurality of unit transistors of Q2) are bipolar transistors.
  • FIG. 1 is a diagram showing a planar structure of an LDMOSFET integrated on a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. Since the planar structure in FIG. 1 has been described at the beginning, description thereof will be omitted.
  • FIG. 2 is a diagram showing a cross-sectional structure of the LDMOSFET integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. Since the sectional structure of FIG. 2 has been described at the beginning, the description thereof will be omitted.
  • FIG. 3 is a diagram showing a configuration of the high-band RF power amplifier 100, the low-band RF power amplifier 200, and the bias control unit 300 that are integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention includes the high-band RF power amplifier and the low-band RF power amplifier shown in FIG. , Built-in. That is, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7 includes a plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier (GSM_HB) 100 and the GSM low band RF power.
  • GSM_HB GSM high band RF power amplifier
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7 includes a GSM high-band RF power amplifier (GSM_HB) 100, a GSM low-band RF power amplifier (GSM_LB) 200, and a WCDMA system.
  • GSM_HB GSM high-band RF power amplifier
  • GSM_LB GSM low-band RF power amplifier
  • WCDMA WCDMA system.
  • the input matching circuit InMN and the interstage matching circuit MN of each power amplifier of the high band RF power amplifier (WCDMA_HB) 400 and the WCDMA low band RF power amplifier (WCDMA_LB) 500 are integrated.
  • the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 respectively constituted by three-stage amplifiers are The rectangular semiconductor chip 1 is disposed on the upper long side and the lower long side, respectively. That is, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1. The plurality of LDMOSFETs Q 1, Q 2, Q 3 of the low-band RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 each constituted by a two-stage amplifier are used.
  • the rectangular semiconductor chip 1 is disposed on the left short side and the right short side, respectively.
  • the plurality of LDMOSFETs Q 1 and Q 2 of the WCDMA high-band RF power amplifier 400 are arranged on the short left side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1, and the WCDMA low-band
  • the plurality of LDMOSFETs Q1 and Q2 of the RF power amplifier 500 are arranged on the short right side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 are each constituted by a three-stage amplifier, and the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 are constituted by a two-stage amplifier. Each is configured because the transmission power of the GSM mobile communication terminal to the base station is relatively higher than that in the WCDMA system.
  • the extending direction of the long sides of the two gate electrodes is Y in the semiconductor chip 1.
  • the direction of the AA ′ line, which is the direction, is selected, while the unit transistor repeated enlargement for realizing a large element size is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 on the lower long side of the semiconductor chip 1 is extended in the Y direction of the semiconductor chip 1 in the extending direction of the long sides of the two gate electrodes. Is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size.
  • the final stage amplifying element Q2 which is a large element size of the WCDMA high band RF power amplifier 400 on the left short side of the semiconductor chip 1
  • the extending direction of the long sides of the two gate electrodes is the semiconductor chip 1.
  • Is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip, while repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip 1 Has been.
  • the extending direction of the long sides of the two gate electrodes is Y in the semiconductor chip 1. While the direction of the AA ′ line that is the direction is selected, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Yes.
  • the first stage amplifying element Q1 and the second stage amplifying element Q2 of each amplifier of the GSM type high band RF power amplifier 100 and the GSM type low band RF power amplifier 200 are also the final stage amplifying element Q3.
  • a plurality of unit transistors are connected in parallel.
  • a plurality of unit transistors constituting the second-stage amplifying element Q2 are repeated in the direction of the BB ′ line that is the X direction of the semiconductor chip 1
  • the enlargement amount is set smaller than the repeated enlargement amount of the final stage amplifying element Q3 that generates a large RF output.
  • the repeated enlargement amount in the direction of the BB ′ line which is the X direction of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplifying element Q1, gives an intermediate output. It is set to be smaller than the repetitive enlargement amount of the generated second-stage amplifying element Q2.
  • the first-stage amplifying element Q1 of each amplifier of the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 is also composed of a plurality of units similarly to the final-stage amplifying element Q2. It is configured by parallel connection of transistors. In order for the first stage amplifying element Q1 to generate a small RF output, the repeated enlargement amount in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplifying element Q1 generates a large output. It is set to be smaller than the repeated enlargement amount of the final stage amplifying element Q2.
  • FIG. 8 shows the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, which has a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1.
  • FIG. 2 is a diagram showing a state in which a final stage amplification element Q3 and a large stage size final stage amplification element Q2 of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 are configured.
  • FIG. 8 In the lower left of FIG. 8, two gate electrodes G formed in a rectangular shape, one drain region D formed in a rectangular shape in the center of the two gate electrodes G, and two gate electrodes G A planar structure of an LDMOSFET unit transistor Unit_MOS including two source regions S formed in a rectangular shape outside is shown.
  • the gate length L of the LDMOSFET is determined by the length of the gate electrode G between the drain region D and the source region S in the direction of the BB ′ line, and the gate electrode G between the drain region D and the source region S is determined.
  • the gate width W of the LDMOSFET is determined by the width in the direction of the AA ′ line. Since the two gate electrodes G of one unit transistor Unit_MOS are connected in common and the two source regions S are also connected in common, the two LDMOSFETs inside one unit transistor Unit_MOS operate in parallel.
  • the final stage amplifying element Q3 of the large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. Is repeatedly expanded for two rows in the X direction, and is repeatedly expanded for nine columns in the Y direction. That is, in the final stage amplifying element Q3, the substantial repeated enlargement of the unit transistor Unit_MOS for realizing a large element size is selected in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 disposed on the lower long side of the semiconductor chip 1 is also substantially repetitively enlarged by the unit transistor Unit_MOS for realizing a large element size.
  • the semiconductor chip 1 is selected in the direction of line BB ′, which is the X direction. Note that the repetition row in the X direction and the repetition column in the Y direction of the final stage amplifying element Q3 of the large element size of the GSM high band RF power amplifier 100 shown in FIG. As described, there are 3 rows and 12 columns. The reason why the repeated rows in the X direction and the repeated columns in the Y direction are made smaller than the actual size in FIG. 8 is to illustrate the gate electrode G and the drain region D omitted in FIG. 9 in FIG.
  • the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 disposed on the right short side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. Is repeatedly expanded for four rows in the X direction, and is repeatedly expanded for three columns in the Y direction. That is, in the final stage amplification element Q2, the substantial repeated enlargement of the unit transistor Unit_MOS for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the large-stage final-stage amplifying element Q2 of the WCDMA high-band RF power amplifier 400 arranged on the short left side of the semiconductor chip 1 is also a substantial repetition of the unit transistor Unit_MOS for realizing a large element size.
  • the enlargement is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the reason why the repeated rows in the X direction and the repeated columns in the Y direction are made smaller than the actual size in FIG. 8 is to illustrate the gate electrode G and the drain region D omitted in FIG. 12 in FIG.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are connected to the first gate wiring GM1,
  • the one gate wiring GM1 is connected to the gate pad GP through the second gate wiring GM2 having a large wiring width.
  • the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to the plurality of drain pads DP via the first drain wiring DM1.
  • the plurality of parallel first drain wirings DM1 are formed in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are connected to the first gate line GM1,
  • the one gate wiring GM1 is connected to the gate pad GP through the second gate wiring GM2 having a large wiring width.
  • the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to the plurality of drain pads DP via the first drain wiring DM1.
  • the plurality of parallel first drain wirings DM1 are formed in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
  • FIG. 9 is a diagram showing a specific state in which the large-amplifier final stage amplifying element Q3 of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention shown in FIG. 8 is configured.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are omitted. Furthermore, since the plurality of drain regions D of the plurality of unit transistors Unit_MOS exist below the first drain wiring DM1, they are omitted from the plan view of FIG. As shown in FIG. 9, the gate pad GP and the drain pad DP can be electrically connected to the outside of the semiconductor chip 1 by bonding wires BW or the like.
  • the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 is formed by connecting the unit transistor Unit_MOS shown in the lower left of FIG. It is configured by repeatedly enlarging 3 rows in the direction and repeatedly enlarging 12 columns in the Y direction. That is, the final stage amplifying element Q3 having a large element size is selected in the direction of the BB ′ line which is the X direction of the semiconductor chip 1 in order to substantially repeat the expansion of the unit transistor Unit_MOS for realizing the large element size. .
  • FIG. 10 is a diagram showing a main part of a specific configuration of the final stage amplifying element Q3 having a large element size of the GSM high band RF power amplifier 100 according to Embodiment 1 of the present invention shown in FIG.
  • a first drain wiring DM1 is formed on one drain region D formed in a rectangular shape at the center of the two gate electrodes G, and the two gate electrodes G serve as the first drain. They are commonly connected by a first gate line GM1 formed under the line DM1.
  • FIG. 11 is a diagram showing a specific state in which the large-amplifier final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 8 is configured.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are omitted. Further, the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to a plurality of first drain wirings DM1 formed in the direction of the BB ′ line that is the X direction.
  • the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 arranged on the right short side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. It is configured by iteratively enlarging for 12 rows in the direction and repeatedly enlarging for 5 columns in the Y direction. That is, the final stage amplifying element Q2 having a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1 in order to substantially repeat the enlargement of the unit transistor Unit_MOS for realizing the large element size. .
  • the large element size final stage amplifying element Q3 of the GSM high band RF power amplifier 100 shown in FIG. 9 and the large element size final stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 shown in FIG. R GSM (3 rows) ⁇ R WCDMA (12 rows), C GSM (12 columns)> C WCDMA (5 columns).
  • FIG. 12 is a diagram showing a main part of a specific configuration of the final stage amplifying element Q2 having a large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG.
  • the drain region D formed in a rectangular shape in the center portion of the two gate electrodes G is connected to the first drain wiring DM1 through the contact opening CNT, and the two gate electrodes G are connected to the first gate electrode G.
  • the first gate wiring GM1 formed in parallel with the one drain wiring DM1 is commonly connected.
  • DM1 crosses three-dimensionally. The cross-sectional distance between the gate electrode G and the first drain wiring DM1 is smaller than the planar distance between the first gate wiring GM1 and the first drain wiring DM1 formed in parallel in the plan view of FIG. Become.
  • the gate / drain feedback capacitance that determines the high-frequency characteristics of the LDMOSFET as the high-frequency amplifier is not the plane distance between the first gate wiring GM1 and the first drain wiring DM1, but the gate electrode G and the first drain wiring DM1.
  • the value of the gate-drain feedback capacitance increases, which is dominantly determined by the cross-sectional distance between the two.
  • the value of the gate-drain feedback capacitance increases, the high frequency characteristics of the LDMOSFET deteriorate.
  • the source wiring electrically connected to the source region S connected to the ground voltage GND is electrostatically connected at a portion where the gate electrode G of the LDMOSFET and the first drain wiring DM1 intersect three-dimensionally. Functions as a shield layer. That is, the source wiring functioning as an electrostatic shield layer is formed between the gate electrode G of the LDMOSFET and the first drain wiring DM1 at the three-dimensional intersection.
  • FIG. 13 shows a three-dimensional intersection of the gate electrode G of the LDMOSFET of the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 12 and the first drain wiring DM1.
  • FIG. 6 is a cross-sectional view showing a state where a source wiring electrically connected to a source region S connected to a ground voltage GND functions as an electrostatic shield layer in a portion to be operated.
  • the cross-sectional structure shown in FIG. 13 is obtained by forming a silicon nitride film 20 and a silicon oxide film 21 on top of the cross-sectional structure shown in FIG.
  • a plurality of contact holes 22 are formed in the silicon nitride film 20 and the silicon oxide film 21, and a first plug wiring 23 is formed inside the plurality of contact holes 22.
  • the N + type source region 16 and the P + type semiconductor region 17 of the source region S of the LDMOSFET are electrically connected to a source electrode 24A as a first source wiring via a plurality of first plug wirings 23. Further, the N + type drain region 15 of the drain region D of the LDMOSFET is electrically connected to the drain electrode 24B through the first plug wiring 23.
  • a first interlayer silicon oxide film 26 is formed on the source electrode 24A and the drain electrode 24B.
  • a through hole 27 is formed in the first interlayer silicon oxide film 26 above the drain electrode 24 B, and a second plug wiring 28 is formed inside the through hole 27.
  • a second drain electrode 29B is formed on the second plug wiring 28.
  • a second interlayer silicon oxide film 30 is formed on the second drain electrode 29B, and a through hole 31 (contact opening CNT) is formed in the second interlayer silicon oxide film 30 on the second drain electrode 29B.
  • a third plug wiring 32 is formed in the through hole 31. In the third plug wiring 32, a wiring layer 33 as the first drain wiring DM1 is formed.
  • the source electrode 24A overlaps the upper part of the gate electrode G (7) of the lower LDMOSFET, the gate electrode G (7) of the lower LDMOSFET and the upper first drain wiring DM1 (wiring layer 33). ) Is shielded so that the source electrode 24A effectively functions as an electrostatic shield layer. Further, a silicon oxide film 34 and a silicon nitride film 35 are formed as a final passivation film on the first drain wiring DM1 (wiring layer 33).
  • FIG. 14 shows the characteristics of the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 of FIG. 7 shown in FIG. 9 and FIG. And the characteristics of the large-amplifier final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 disposed on the short right side of the semiconductor chip 1 of FIG. 7 shown in FIG. 12 and the same gate width. It is the figure compared by gate length.
  • the final stage amplifying element Q3 of the GSM high-band RF power amplifier 100 and the final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 are shown. Have equivalent characteristics. However, regarding the feedback capacitance Crss, the final stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 is improved by 18% over the final stage amplifying element Q3 of the GSM high band RF power amplifier 100.
  • the last stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 has a smaller feedback capacity Crss than the last stage amplifying element Q3 of the GSM high-band RF power amplifier 100.
  • the source described in FIGS. The electrostatic shield effect between the first drain wiring DM and the gate electrode G (7) by the electrode 24A and the first gate wiring GM1 and the first drain wiring DM are arranged in parallel as apparent from FIG. This is because the first gate line GM1 and the first drain line DM1 do not intersect.
  • the final stage amplifying element Q3 of the GSM high band RF power amplifier 100 as is apparent from FIG. 9, the first gate wiring GM1 and the first drain wiring DM1 are arranged orthogonally, and the first gate wiring Since GM1 and the first drain wiring DM1 intersect, the feedback capacitance Crss increases.
  • the final stage amplification element Q2 of the WCDMA low-band RF power amplifier 500 has a smaller feedback capacity Crss than the final stage amplification element Q3 of the GSM high-band RF power amplifier 100, the final-stage amplification of the WCDMA low-band RF power amplifier 500 is performed.
  • the power added efficiency of the element Q2 is improved by about 3%.
  • the plurality of LDMOSFETs Q1 and Q2 of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1 are formed by the element structure described in FIGS. 11, 12, and 13 and function as an electrostatic shield layer.
  • the source electrode 24A can effectively shield between the gate electrode G (7) of the lower LDMOSFET and the upper first drain wiring DM1 (wiring layer 33).
  • FIG. 15 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15 is different from the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described in FIGS. 7 to 14 in the following points.
  • pads of the plurality of input terminals of the bias control unit 300 are provided on the upper long side of the rectangular semiconductor chip 1. Are arranged in the direction of the line BB ′, which is the X direction.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15 is the same as the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. Therefore, in the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM type low-band RF power amplifier 200 are the same as the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG.
  • the plurality of LDMOSFETs Q1 and Q2 of the WCDMA high-band RF power amplifier 400 are arranged in the direction of the BB ′ line which is the X direction on the lower long side of the A, and the A in the Y direction is on the left short side of the semiconductor chip 1.
  • a plurality of LDMOSFETs Q 1 and Q 2 of the WCDMA low-band RF power amplifier 500 are arranged in the direction of the AA line, and are arranged in the direction of the AA ′ line which is the Y direction on the short side of the right side of the semiconductor chip 1.
  • FIG. 16 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16 is different from the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. 7 to 14 in the following points.
  • the block of the bias control unit 300 is moved in the direction of the left short side of the semiconductor chip 1 to form a rectangular semiconductor chip.
  • a pad of a plurality of input terminals of the bias control unit 300 is arranged on the lower long side of 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16 is the same as the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. Therefore, in the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM type high-band RF power amplifier 100 are the same as the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. A plurality of LDMOSFETs Q1 and Q2 of the WCDMA low-band RF power amplifier 500 are arranged on the upper long side of the chip 1 in the direction of the BB ′ line which is the X direction. -A 'line direction.
  • FIG. 17 is a diagram showing a planar structure and a sectional structure of a unit transistor Unit_TRS of a planar bipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • a rectangular emitter electrode E is formed at the center, and a base electrode B is formed outside the emitter electrode E.
  • a collector electrode C is formed on the outside.
  • the broken line between the emitter electrode E and the base electrode B indicates the planar shape of the emitter-base junction
  • the broken line between the base electrode B and the collector electrode C indicates the planar shape of the base-collector junction.
  • the broken line outside the collector electrode C indicates the planar shape of the N-type collector region.
  • the emitter electrode E is electrically connected to the N + -type emitter region by ohmic contact
  • the base electrode B is electrically connected to the P-type base region by ohmic contact
  • the collector electrode C Are electrically connected to the N-type collector region by ohmic contact with the N + -type high impurity collector region.
  • a P-type substrate of a semiconductor integrated circuit is formed below the N-type collector region.
  • silicon is used for the N + -type emitter region, the P-type base region, the N-type collector region, and the P-type substrate.
  • the emitter current flows at a larger current density in the corner portion than in the flat portion of the cross-sectional structure of the emitter-base junction. This is well known as the edge effect of a transistor, and is caused by electric field concentration at the corner of the emitter-base junction.
  • the conductance of the amplification gain of the planar bipolar transistor shown in FIG. 17 is proportional to the emitter size of the transistor.
  • the emitter size of the planar bipolar transistor is determined more dominantly by the length of the peripheral distance in the planar structure of the emitter-base junction by the edge effect than the size of the emitter area.
  • the flat area of the useless emitter region is reduced by making the emitter region of the planar structure of the transistor rectangular. This increases the length of the peripheral distance in a useful emitter-base junction planar structure.
  • the unit transistor is repeatedly expanded in order to realize a large element size, and the repeated expansion is realized by parallel connection of a plurality of unit transistors.
  • FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3.
  • a plurality of unit transistors Unit_TRS of the planar bipolar transistor shown in FIG. 17 are repeatedly expanded in the direction of the BB ′ line which is the X direction.
  • the conductance of the amplification gain of the unit transistor Unit_TRS of the bipolar transistor shown in FIG. 17 also varies due to variations in the length of the peripheral distance in the planar structure of the emitter-base junction. The reason is that, in the photolithography for forming a rectangular emitter region having a planar structure in the manufacturing process of the semiconductor chip, the X direction and the Y direction have different dimensional deviations.
  • Q3 and WCDMA high-band RF power amplifier 400 transistors Q1 and Q2 and WCDMA low-band RF power amplifier 500 transistors Q1 and Q2 of all transistors in the planar structure of the emitter region of the rectangular long side extending direction is semiconductor The direction of the AA ′ line that is the Y direction of the chip 1 is unified.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM high-band RF power amplifier 100 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM low-band RF power amplifier 200 are a semiconductor chip. 1 is selected in the direction of the BB ′ line, which is the X direction.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA high-band RF power amplifier 400 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA low-band RF power amplifier 500 are the semiconductor chip 1 Is selected in the direction of the line AA ′, which is the Y direction.
  • FIG. 19 is a diagram showing a planar structure and a cross-sectional structure of a unit transistor Unit_TRS of a mesa type heterobipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • a rectangular emitter electrode E is formed in the center portion, and a base electrode B is formed outside the emitter electrode E.
  • a collector electrode C is formed on the outside.
  • the broken line between the emitter electrode E and the base electrode B indicates the planar shape of the emitter-base junction
  • the broken line between the base electrode B and the collector electrode C indicates the planar shape of the base-collector junction.
  • the broken line outside the collector electrode C indicates the planar shape of the N-type collector region.
  • the emitter electrode E is electrically connected to the N + -type emitter region which is the uppermost layer of the mesa structure by ohmic contact
  • the base electrode B is a P-type base which is an intermediate layer of the mesa structure.
  • the region is electrically connected to the region by ohmic contact
  • the collector electrode C is electrically connected to the N-type collector region which is the lowermost layer of the mesa structure by ohmic contact.
  • a semi-insulating substrate Sub having a high resistivity of the semiconductor integrated circuit is formed below the N-type collector region.
  • an N + -type emitter region that is the uppermost layer of the mesa structure, a P-type base region that is the intermediate layer, an N-type collector region that is the lowermost layer, and a semi-insulating substrate include a compound such as GaAs. A semiconductor is used.
  • the emitter current flows at a larger current density in the corner portion than in the flat portion of the cross-sectional structure of the emitter-base junction due to the edge effect described above.
  • the conductance of the amplification gain of the mesa heterobipolar transistor shown in FIG. 19 is also proportional to the emitter size of the transistor.
  • the emitter size of the mesa type heterobipolar transistor is determined more dominantly by the length of the peripheral distance in the planar structure of the emitter-base junction than the size of the emitter area due to the edge effect described above.
  • the flat area of the useless emitter region is reduced by making the emitter region of the planar structure of the transistor rectangular. This increases the length of the peripheral distance in a useful emitter-base junction planar structure.
  • the unit transistor is repeatedly expanded in order to realize a large element size, and the repeated expansion is realized by parallel connection of a plurality of unit transistors.
  • FIG. 20 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention, and the transistor Q1 of the GSM low-band RF power amplifier 200.
  • FIG. 3 is a diagram showing a planar structure of each RF power amplification mesa heterotransistor of Q2, Q2, and Q3.
  • one RF power amplification mesa type heterotransistor repeats a plurality of unit transistors Unit_TRS of the sa type heterobipolar transistor shown in FIG. 19 in the direction of the BB ′ line which is the X direction.
  • the conductance of the amplification gain of the unit transistor Unit_TRS of the mesa heterobipolar transistor shown in FIG. 19 also varies depending on the variation in the length of the peripheral distance in the planar structure of the emitter-base junction.
  • the reason for this is that not only does the X-direction and the Y-direction have different dimensional deviations in the photolithography for forming a rectangular emitter region having a planar structure in the manufacturing process of the semiconductor chip, but the mesa-type trapezoidal shape has a mesa-type emitter region. This is because there is a deviation due to the difference in the extending direction of the long side of the rectangle.
  • the mesa-type trapezoidal shape of the mesa-type emitter region has a deviation due to the difference in the extension direction of the long side due to the anisotropic etching at the time of chemical etching at the time of forming the mesa-type trapezoidal shape. It is. That is, the etching rates of chemical etching are different on a plurality of side surfaces of the mesa trapezoid.
  • FIG. 21 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region.
  • the mesa emitter region when the extension direction of the long side of the rectangle of the mesa emitter region is selected in the direction of the AA ′ line which is the Y direction (emitter length direction A), the mesa emitter region The case where the extension direction of the long side of the rectangle is selected in the direction of the BB ′ line which is the X direction (emitter length direction B) is shown.
  • the mesa trapezoidal shape in the cross section along the line aa ′ has a shorter lower side than the upper side, the length of the peripheral distance becomes longer as shown in the emitter length direction A in the upper part of FIG.
  • the conductance value of the amplification gain of the transistor increases.
  • the mesa type trapezoidal shape in the cross section along the line bb ′ has a lower side longer than the upper side, the length of the peripheral distance becomes shorter as shown in the emitter length direction B in the upper part of FIG.
  • the conductance value of the amplification gain of the transistor becomes small.
  • a shape having a long upper side of the trapezoidal shape is called an inverted mesa, and a shape having a short upper side of the trapezoidal shape is called a forward mesa.
  • Mesa heterobipolar transistors Q1, Q2, Q3 and all mesa types of mesa heterobipolar transistors Q1, Q2 of WCDMA high band RF power amplifier 400 and mesa heterobipolar transistors Q1, Q2 of WCDMA low band RF power amplifier 500 The extending direction of the long side of the rectangular emitter region of the planar structure of the heterobipolar transistor is unified with the direction of the AA ′ line which is the Y direction of the semiconductor chip 1.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM high-band RF power amplifier 100 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM low-band RF power amplifier 200 are a semiconductor chip. 1 is selected in the direction of the BB ′ line, which is the X direction.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA high-band RF power amplifier 400 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA low-band RF power amplifier 500 are the semiconductor chip 1 Is selected in the direction of the line AA ′, which is the Y direction.
  • FIG. 22 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention includes a high-band RF power amplifier and a low-band RF power amplifier shown in FIG. It is built-in. That is, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 22 includes a plurality of transistors Q1 and Q2 of the GSM high-band RF power amplifier (GSM_HB) 100 and a GSM low-band RF power amplifier.
  • GSM_HB GSM high-band RF power amplifier
  • GSM_LB A plurality of transistors Q1, Q2 of 200, and further a plurality of transistors Q1, Q2 of WCDMA high-band RF power amplifier (WCDMA_HB) 400 and a plurality of transistors Q1, Q2 of WCDMA low-band RF power amplifier (WCDMA_LB) 500 And the bias controller 300 are integrated.
  • all the transistors Q1 and Q2 integrated in the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22 are the planar bipolar transistors described with reference to FIGS. Or, it is the mesa type hetero bipolar transistor described in FIG. 19, FIG. 20, and FIG.
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22 includes a GSM high band RF power amplifier (GSM_HB) 100, a GSM low band RF power amplifier (GSM_LB) 200, and a WCDMA high
  • GSM_HB GSM high band RF power amplifier
  • GSM_LB GSM low band RF power amplifier
  • WCDMA WCDMA high
  • InMN and the interstage matching circuit MN of each power amplifier of the band RF power amplifier (WCDMA_HB) 400 and the WCDMA low-band RF power amplifier (WCDMA_LB) 500 are integrated.
  • the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 are the same as those of the rectangular semiconductor chip 1. They are arranged on the upper long side and the lower long side, respectively.
  • the plurality of transistors Q1 and Q2 of the GSM high-band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1, and the GSM low-band
  • the plurality of transistors Q1 and Q2 of the RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
  • the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 are the left of the rectangular semiconductor chip 1. It is arrange
  • the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. While selected in the direction of the AA ′ line, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the BB ′ line which is the X direction of the semiconductor chip 1. Further, in the final stage amplification transistor Q2 having a large element size of the GSM low band RF power amplifier 200 at the lower long side of the semiconductor chip 1, the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. On the other hand, the unit transistor is repeatedly expanded in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while being selected in the direction of the ⁇ A ′ line.
  • the extension direction of the long side of the emitter region is in the Y direction of the semiconductor chip 1. Is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size. .
  • the final stage amplification transistor Q2 which is a large element size of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1, the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. While selected in the direction of the AA ′ line, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1.
  • a plurality of unit transistors are connected in parallel as in the first stage amplification transistor Q1 and the last stage amplification transistor Q2 of each amplifier of the GSM high band RF power amplifier 100 and the GSM low band RF power amplifier 200. It is configured.
  • the amount of repetitive expansion in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplification transistor Q1 is the final stage amplification with a large gain. It is set smaller than the repetitive enlargement amount of the transistor Q2.
  • the first stage amplification transistor Q1 of each amplifier of the WCDMA high band RF power amplifier 400 and the WCDMA low band RF power amplifier 500 is also configured by parallel connection of a plurality of unit transistors, like the last stage amplification transistor Q2.
  • the amount of repetitive expansion in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplification transistor Q1 is the final stage amplification with a large gain. It is set smaller than the repetitive enlargement amount of the transistor Q2.
  • FIG. 23 shows a GSM high-band RF power amplifier 100, a GSM low-band RF power amplifier 200, a bias controller 300, and a WCDMA high-band integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention.
  • FIG. 2 is a diagram showing the configuration of an RF power amplifier 400 and a WCDMA low-band RF power amplifier 500.
  • Each RF power amplifier of the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 includes a first stage amplifying element Q1, a second stage amplifying element Q2, and a last stage amplifying element Q3.
  • the common electrodes of the plurality of amplification elements Q1 to Q3 are connected to the ground voltage GND, and the power supply voltage is connected to the output electrodes of the plurality of amplification elements Q1, Q2, and Q3 via load inductors L1, L2, and L3. Vdd is supplied.
  • the GSM high-band RF transmission input signal Pin_GSM_HB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is interstage.
  • the amplified signal of the amplifying element Q2 is supplied to the input electrode of the final stage amplifying element Q3 via the interstage matching circuit MN via the matching circuit MN.
  • the amplified signal of Q3 is output as a GSM high-band RF transmission output signal Pout_GSM_HB via the output matching circuit OutMN.
  • the GSM low-band RF transmission input signal Pin_GSM_LB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is the inter-stage matching circuit.
  • the amplified signal of the amplifying element Q2 is supplied to the input electrode of the final stage amplifying element Q3 via the interstage matching circuit MN and supplied to the input electrode of the amplifying element Q3.
  • the amplified signal is output as a GSM low-band RF transmission output signal Pout_GSM_LB via the output matching circuit OutMN.
  • Each RF power amplifier of the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 includes a first stage amplifying element Q1 and a last stage amplifying element Q2.
  • the common electrodes of the plurality of amplification elements Q1 and Q2 are connected to the ground voltage GND, and the power supply voltage Vdd is supplied to the output electrodes of the plurality of amplification elements Q1 and Q2 via the load inductors L1 and L2.
  • the WCDMA high-band RF transmission input signal Pin_WCDMA_HB is supplied to the input electrode of the first stage amplifying element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifying element Q1 is interstage.
  • the signal is supplied to the input electrode of the final stage amplifying element Q2 via the matching circuit MN, and the amplified signal of the amplifying element Q2 is output as the WCDMA high-band RF transmission output signal Pout_WCDMA_HB via the output matching circuit OutMN.
  • the WCDMA low-band RF transmission input signal Pin_WCDMA_LB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is the inter-stage matching circuit.
  • the signal is supplied to the input electrode of the final stage amplifying element Q2 via the MN, and the amplified signal of the amplifying element Q2 is output as the WCDMA low band RF transmission output signal Pout_WCDMA_LB via the output matching circuit OutMN.
  • the bias control unit 300 is supplied with the automatic power control signal Vapc and a plurality of control input signals Cont, so that the bias control unit 300 performs each RF of the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200.
  • Input electrode bias voltage supplied to the input electrodes of a plurality of amplifier elements Q 1, Q 2, Q 3 of the power amplifier and a plurality of amplifications of each RF power amplifier of WCDMA high-band RF power amplifier 400 and WCDMA low-band RF power amplifier 500 An input electrode bias voltage supplied to the input electrodes of the elements Q1 and Q2 is generated.
  • the plurality of amplifying elements Q1, Q2, Q3 of the GSM RF power amplifiers 100, 200 and the plurality of amplifying elements Q1, Q2 of the WCDMA RF power amplifiers 400, 500 are the LDMOSFETs described with reference to FIGS.
  • FIG. 24 is a diagram showing the configuration of the semiconductor chip 1 of the semiconductor integrated circuit and the configuration of the RF power amplifier module PA_MD according to the third embodiment of the present invention.
  • the GSM high band RF power amplifier 100 and the GSM low band RF power amplifier 200 are the same as those of the rectangular semiconductor chip 1. They are arranged on the upper long side and the lower long side, respectively. That is, the plurality of amplifying elements Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1. A plurality of amplifying elements Q 1, Q 2, Q 3 of the GSM low-band RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 each constituted by a two-stage amplifier are used.
  • the rectangular semiconductor chip 1 is disposed on the left short side and the right short side, respectively.
  • the plurality of amplifying elements Q1 and Q2 of the WCDMA high band RF power amplifier 400 are arranged on the short left side of the rectangular semiconductor chip 1 in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1,
  • the plurality of amplifying elements Q1 and Q2 of the WCDMA low-band RF power amplifier 500 are arranged on the short right side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 on the upper long side of the semiconductor chip 1 has an extending direction of the long side of the gate electrode or the emitter region in the Y direction of the semiconductor chip 1.
  • the direction of the AA ′ line, which is the direction, is selected, while the unit transistor repeated enlargement for realizing a large element size is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 on the lower long side of the semiconductor chip 1 has a longer side extending in the Y direction of the semiconductor chip 1 in the gate electrode or emitter region. Is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size.
  • the final stage amplifying element Q2 which has a large element size of the WCDMA high-band RF power amplifier 400 on the left short side of the semiconductor chip 1, has an extension direction of the long side of the gate electrode or emitter region of the semiconductor chip 1. While selected in the direction of the AA ′ line which is the Y direction, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1. ing.
  • the final stage amplifying element Q2 having a large element size of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1 has an extending direction of the long side of the gate electrode or the emitter region in the Y direction of the semiconductor chip 1. While the direction of the AA ′ line that is the direction is selected, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Yes.
  • the amplified output signal of the final stage amplifying element Q3 of the GSM high band RF power amplifier 100 is the same as that of the rectangular semiconductor chip 1.
  • the amplified output signal of the final stage amplifying element Q3 of the GSM low-band RF power amplifier 200 is derived from the lower long side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1
  • the amplified output signal of the final stage amplifying element Q2 of the WCDMAM high-band RF power amplifier 400 is derived from the short left side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1, and is amplified by the final stage of the WCDMAM low-band RF power amplifier 500.
  • the amplified output signal of the element Q2 is output from the right side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1.
  • the GSM high band RF power amplifier 100 is formed on the upper portion of the wiring board.
  • the output matching circuit 100_OutMN is arranged, the output matching circuit 200_OutMN of the GSM low-band RF power amplifier 200 is arranged in the lower part of the wiring board, and the output matching of the WCDMA high-band RF power amplifier 400 is arranged in the left part of the wiring board.
  • the output matching circuit 500_OutMN of the WCDMA low-band RF power amplifier 500 can be arranged at the right part of the wiring board.
  • the output signal of the final stage amplifying element is derived from the right short side and the left short side of the rectangular semiconductor chip 1, so that the rectangular Since the semiconductor chip 1 does not become long in the direction of the BB ′ line which is the X direction of the semiconductor chip 1, the chip size of the semiconductor chip 1 can be reduced. Further, since the RF signal output wiring of the wiring board of the RF power amplifier module PA_MD is also distributed in the upper part, the lower part, the right short side, and the left short side of the wiring board, there are less restrictions on the wiring layout and the wiring board. It is possible to reduce the area and cost.
  • an amplifying element integrated on a semiconductor chip of the semiconductor integrated circuit of the present invention an amplifying element other than an LDMOSFET, a planar bipolar transistor, a mesa type heterobipolar transistor, such as a MESFET, HEMT, or SiGe heterobipolar transistor is used. It is possible to use.

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Abstract

Le but de la présente invention est d'éliminer une restriction de direction de placement d'éléments d'un amplificateur sur une surface de puce de semi-conducteur. Un premier élément amplificateur d'étage final (Q3) d'un premier amplificateur de puissance RF (100) est formé sur la surface d'une puce de semi-conducteur et le long d'un premier bord de celle-ci, et un second élément amplificateur d'étage final (Q2) d'un second amplificateur de puissance RF (500) est formé le long d'un second bord perpendiculaire au premier bord. Les premier et second éléments d'étage final (Q3 et Q2) sont configurés à partir de multiples transistors unitaires. Les multiples transistors unitaires contiennent des régions actives (G) qui présentent une géométrie plane rectangulaire. La direction d'extension des bords plus longs des multiples rectangles dans les multiples transistors unitaires des premier et second éléments d'étage final (Q3 et Q2) est fixée dans la direction de la longueur du second bord. La direction de l'agrandissement itératif des multiples transistors unitaires dans le premier élément d'étage final (Q3) est fixée dans la direction de la longueur du premier bord, et la direction de l'agrandissement itératif des multiples transistors unitaires dans le second élément d'étage final (Q2) est fixée dans la direction de la longueur du second bord.
PCT/JP2012/065584 2011-07-14 2012-06-19 Circuit intégré à semi-conducteur et module sur lequel ce dernier est monté WO2013008587A1 (fr)

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JP2006313881A (ja) * 2005-04-05 2006-11-16 Matsushita Electric Ind Co Ltd バイポーラトランジスタおよび高周波増幅回路
JP2006352241A (ja) * 2005-06-13 2006-12-28 Renesas Technology Corp 高周波増幅回路および高周波電力増幅モジュール
JP2007173314A (ja) * 2005-12-19 2007-07-05 Renesas Technology Corp 半導体装置
JP2011091084A (ja) * 2009-10-20 2011-05-06 Nec Corp 半導体装置、およびインターフェースセルの配置方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006313881A (ja) * 2005-04-05 2006-11-16 Matsushita Electric Ind Co Ltd バイポーラトランジスタおよび高周波増幅回路
JP2006352241A (ja) * 2005-06-13 2006-12-28 Renesas Technology Corp 高周波増幅回路および高周波電力増幅モジュール
JP2007173314A (ja) * 2005-12-19 2007-07-05 Renesas Technology Corp 半導体装置
JP2011091084A (ja) * 2009-10-20 2011-05-06 Nec Corp 半導体装置、およびインターフェースセルの配置方法

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