WO2013008587A1 - Semiconductor integrated circuit and module mounting same - Google Patents

Semiconductor integrated circuit and module mounting same Download PDF

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Publication number
WO2013008587A1
WO2013008587A1 PCT/JP2012/065584 JP2012065584W WO2013008587A1 WO 2013008587 A1 WO2013008587 A1 WO 2013008587A1 JP 2012065584 W JP2012065584 W JP 2012065584W WO 2013008587 A1 WO2013008587 A1 WO 2013008587A1
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WIPO (PCT)
Prior art keywords
final stage
power amplifier
semiconductor chip
amplifying element
unit transistors
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PCT/JP2012/065584
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French (fr)
Japanese (ja)
Inventor
健一 那倉
雅志 岡野
靜城 中島
大部　功
Original Assignee
株式会社村田製作所
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Publication of WO2013008587A1 publication Critical patent/WO2013008587A1/en

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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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Definitions

  • the present invention relates to a semiconductor integrated circuit and a module on which the semiconductor integrated circuit is mounted, and particularly relates to a technique effective in eliminating the restriction on the arrangement direction of an amplification element on a semiconductor chip surface.
  • GSM Global System for Mobile Communication
  • GPRS General Packet Radio Service
  • EDGE is an abbreviation for Enhanced Data for GSM Evolution
  • Enhanced Data for GPRS is an abbreviation for Wideband, Code, Division, Multiple, Access.
  • Patent Document 1 describes an RF power amplification element called LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Filed Effect Transistor) integrated in a semiconductor integrated circuit built in an RF power amplifier.
  • LDMOSFET Layer Diffused Metal-Oxide-Semiconductor Filed Effect Transistor
  • one drain region formed in a rectangle is formed in the central portion between two gate electrodes formed in a rectangle.
  • Two source regions formed in a rectangular shape are formed in the outer part on the outside.
  • the source region and the source back electrode formed on the back surface of the single crystal silicon substrate are a low-resistance p-type polysilicon film doped with impurities at a high concentration or It is electrically connected by a punching layer formed of a low-resistance metal film.
  • a drain wiring of a multilayer wiring is formed in the drain region, and a plurality of source regions are connected to each other by a source wiring having a wiring layer smaller than the multilayer wiring of the drain wiring. Is electrically connected.
  • Multimode supports communication using multiple communication systems such as GSM and WCDMA
  • multiband supports transmission of multiple frequency bands such as GSM low band, GSM high band, WCDMA low band, and WCDMA high band.
  • GSM low band includes two frequency bands of GSM850 (824 to 849 MHz) and GSM900 (880 to 915 MHz)
  • GSM high band includes two frequency bands of DCS1800 (1710 to 1785 MHz) and PCS1900 (1850 to 1910 MHz). Is included.
  • DCS is an abbreviation for Digital Cellar System
  • PCS is an abbreviation for Personal Communication System.
  • the WCDMA low band includes band 5 (824 to 849 MHz) and band 8 (880 to 915 MHz)
  • the WCDMA high band includes band 1 (1920 to 1980 MHz), band 2 (1850 to 1910 MHz), and band 4 (1710 to 1755 MHz). ).
  • FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention.
  • one drain D region formed in a rectangular shape is formed in the central portion between the two gate electrodes G, and an outer portion outside the two gate electrodes G is formed in the outer portion.
  • Two source regions S formed in a rectangular shape are formed.
  • a contact 7 for connecting to the gate wiring for commonly connecting the gate electrodes of the plurality of LDMOSFETs is formed on the upper and lower portions of each gate electrode of the two gate electrodes G.
  • a plurality of punched layers 4 are formed in each source region of the two source regions S.
  • FIG. 2 is a diagram showing a cross-sectional structure of an RF power amplifying element called LDMOSFET, which was studied by the present inventors prior to the present invention.
  • 1 is a semiconductor chip (P-type single crystal silicon substrate), 2 is a P-type single crystal silicon epitaxial layer, 3 is a groove, 4 is a punched layer, 5 is a P-type well region, and 6 is a gate.
  • Insulating film 7 is a gate electrode, 8 is a cap insulating film, 9 is an N ⁇ type offset drain region, 10 is an N ⁇ type source region, 11 is a P type halo region, and 12 is a sidewall spacer.
  • 13 are N-type offset drain regions, 15 is an N + -type drain region, 16 is an N + -type source region, and 17 is a P + -type semiconductor region.
  • a P-type single crystal silicon epitaxial layer 2 is formed on the P-type single crystal silicon substrate 1.
  • a drain region D including an N-type offset drain region 13 and an N + -type drain region 15 is formed in the central portion between the two gate electrodes G.
  • a source region S including an N ⁇ -type source region 10, a P-type halo region 11, and an N + -type source region 16 is formed in an external portion outside the two gate electrodes G.
  • a P-type well region 5 is formed under the channel formation region, the N ⁇ -type source region 10, the P-type halo region 11, and the N + -type source region 16 immediately below the gate electrode G.
  • the plurality of N + type source regions 16 of the plurality of LDMOSFETs are electrically short-circuited to each other by the P + type semiconductor region 17.
  • a groove 3 is formed so as to penetrate the P-type well region 5 and the P-type single crystal silicon epitaxial layer 2 and reach the upper surface of the P-type single crystal silicon substrate 1.
  • a punching layer 4 made of a silicon film or a low resistance metal film is formed.
  • the N + type source regions 16 of the plurality of LDMOSFETs are electrically connected to the source back electrode 36 via the P + type semiconductor region 17, the punching layer 4, and the P type single crystal silicon substrate 1.
  • the source back electrode 36 is connected to the ground wiring of the RF power amplifier module, and this ground wiring is connected to the ground wiring of the mother board of the mobile communication terminal.
  • FIG. 3 is a diagram showing a configuration of the RF power amplifier module PA_MD studied by the present inventors prior to the present invention.
  • the RF power amplifier module PA_MD includes a high band RF power amplifier 100, a low band RF power amplifier 200, and a bias control unit 300.
  • Each of the RF power amplifiers of the high-band RF power amplifier 100 and the low-band RF power amplifier 200 includes an LDMOSFET Q1 as a first stage amplifying element, an LDMOSFET Q2 as a second stage amplifying element, and an LDMOSFET Q3 as a last stage amplifying element.
  • each RF power amplifier the sources of the plurality of LDMOSFETs Q1 to Q3 are connected to the ground voltage GND, and the power supply voltage Vdd is supplied to the drains of the plurality of LDMOSFETs Q1, Q2, and Q3 via the load inductors L1, L2, and L3.
  • the high-band RF transmission input signal Pin_HB is supplied to the gate of the FET Q1 of the first stage amplifying element via the input matching circuit InMN, and the amplified signal of the drain of the FET Q1 is passed through the inter-stage matching circuit MN.
  • the amplified signal of the FET Q2 is supplied to the gate of the FET Q3 of the final stage amplification element via the interstage matching circuit MN, and the amplified signal of the FET Q3 is supplied to the gate of the FET Q2 of the second stage amplification element via the output matching circuit OutMN. And output as a high-band RF transmission output signal Pout_HB.
  • the low-band RF transmission input signal Pin_LB is supplied to the gate of the FET Q1 of the first stage amplification element through the input matching circuit InMN, and the amplified signal at the drain of the FET Q1 is two-staged through the interstage matching circuit MN.
  • the amplified signal of the FET Q2 is supplied to the gate of the FET Q3 of the final stage amplification element through the interstage matching circuit MN, and the amplified signal of the FET Q3 is supplied to the low band through the output matching circuit OutMN.
  • An RF transmission output signal Pout_LB is output.
  • the bias control unit 300 is supplied with the automatic power control signal Vapc and a plurality of control input signals Cont, so that the bias control unit 300 includes a plurality of RF power amplifiers of the high-band RF power amplifier 100 and the low-band RF power amplifier 200.
  • the gate bias voltage supplied to the gates of the LDMOSFETs Q1, Q2, and Q3 is generated.
  • FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit built in the RF power amplifier module studied by the present inventors prior to the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit built in the RF power amplifier module includes a plurality of LDMOSFETs Q1, Q2, Q3 of the high-band RF power amplifier 100 and a plurality of LDMOSFETs Q1, of the low-band RF power amplifier 200.
  • Q2 and Q3 and the bias control unit 300 are integrated.
  • the extending direction of the long sides of the rectangles of the two gate electrodes of each of the plurality of LDMOSFETs Q1, Q2, and Q3 of the high-band RF power amplifier 100 is the Y direction of the semiconductor chip 1.
  • the direction of the line AA ′ is unified.
  • the extension direction of the long side of the two gate electrodes of the plurality of LDMOSFETs Q1, Q2, and Q3 of the low-band RF power amplifier 200 is also unified to the direction of the AA ′ line that is the Y direction of the semiconductor chip 1 Has been.
  • the conductance which is the amplification gain of the LDMOSFET
  • W / L the gate width W, which is the long side of the rectangle
  • the gate length L which is the short side of the rectangle
  • the gate electrode in the manufacturing process of the semiconductor chip 1
  • the formed photolithography has different dimensional deviations in the X direction and the Y direction of the semiconductor chip 1. Therefore, the extending direction of the long side of the rectangular electrode of one LDMOSFET is the AA ′ line which is the Y direction of the semiconductor chip 1, while the extending direction of the long side of the rectangular electrode of the gate electrode of the other LDMOSFET. Is a BB ′ line in the X direction of the semiconductor chip 1.
  • the gate length L of one LDMOSFET increases, while the gate width W of the other LDMOSFET increases.
  • the conductance of the amplification gain of one LDMOSFET decreases, while the conductance of the amplification gain of the other LDMOSFET increases.
  • the extension direction of the long side of the rectangular gate electrode of each of the LDMOSFETs Q1, Q2, Q3 integrated in the semiconductor chip 1 is the direction of the AA ′ line which is the Y direction of the semiconductor chip 1 To be unified.
  • the first stage amplifier element Q1 generates a relatively small RF output
  • the second stage amplifier element Q2 generates an intermediate RF output.
  • the final stage amplifying element Q3 generates a relatively large RF output. That is, in each RF power amplifier, in order to realize high power efficiency by amplifying a relatively small RF output in the first stage, the first stage amplifying element Q1 has a small element size. Further, in each RF power amplifier, in order to realize high power efficiency by amplification of the intermediate RF output at the second stage, the amplification element Q2 at the second stage has an intermediate element size. Further, in each RF power amplifier, in order to realize high power efficiency by amplification of a relatively large RF output at the final stage, the final stage amplifying element Q3 has a relatively large element size.
  • the plurality of LDMOSFETs Q1, Q2, and Q3 of the high-band RF power amplifier 100 are formed on the rectangular semiconductor chip 1 in the semiconductor integrated circuit studied by the inventors prior to the present invention shown in FIG.
  • a plurality of LDMOSFETs Q1, Q2, and Q3 of the low-band RF power amplifier 200 are arranged on the long side of the semiconductor chip 1 on the lower long side of the rectangular semiconductor chip 1 and arranged in the direction of the BB ′ line that is the X direction of the semiconductor chip 1 It is arranged in the direction of the BB ′ line, which is the X direction.
  • the LDMOSFET of the RF power amplifier is not arranged on the right short side and the left short side of the rectangular semiconductor chip 1, but only the pads of the plurality of input terminals of the bias control unit 300 are arranged. .
  • FIG. 5 is a diagram showing the configuration of another semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit built in the RF power amplifier module includes a plurality of LDMOSFETs Q1, Q2, and Q3 of a GSM type high band RF power amplifier (GSM_HB) 100 and a GSM type low band RF power amplifier.
  • GSM_LB 200 LDMOSFETs Q1, Q2, Q3, WCDMA high band RF power amplifier (WCDMA_HB) 400 LDMOSFETs Q1, Q2 and WCDMA low band RF power amplifier (WCDMA_LB) 500 LDMOSFETs Q1, Q2
  • a bias controller 300 is integrated.
  • the extending direction of the long sides of the rectangular gate electrodes of all the FETs Q1, Q2, and Q3 integrated on the semiconductor chip 1 for the reasons described above is The direction of the semiconductor chip 1 is unified in the direction of the AA ′ line which is the Y direction.
  • the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier (GSM_HB) 100 and the plurality of LDMOSFETs Q1 and Q2 of the WCDMA high band RF power amplifier (WCDMA_HB) 400 are the upper length of the rectangular semiconductor chip 1.
  • the plurality of 500 LDMOSFETs Q1 and Q2 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
  • the right short side and the left short side of the rectangular semiconductor chip 1 are not provided with the LDMOSFET of the RF power amplifier, but only the pads of the plurality of input terminals of the bias control unit 300 are provided. It was.
  • the drain output signal of the last stage amplifying element Q3 of the GSM high-band RF power amplifier 100 and the drain output signal of the last stage amplifying element Q2 of the WCDMA high-band RF power amplifier 400 are from the upper long side of the rectangular semiconductor chip 1. It must be derived to the output matching circuit OutMN outside the semiconductor chip 1. Exactly in the same way, the drain output signal of the last stage amplifying element Q3 of the GSM low band RF power amplifier 200 and the drain output signal of the last stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 are the lower long side of the rectangular semiconductor chip 1. To the output matching circuit OutMN outside the semiconductor chip 1.
  • FIG. 6 is a diagram showing a configuration of an RF power amplifier module studied by the present inventors prior to the present invention incorporating the semiconductor integrated circuit shown in FIG.
  • a semiconductor chip 1 of a semiconductor integrated circuit incorporating a system low-band RF power amplifier 200 and a WCDMA system low-band RF power amplifier 500 is mounted.
  • the drain output signal of the final stage amplifying element Q3 of the RF power amplifier 100 and the drain output signal of the final stage amplifying element Q2 of the RF power amplifier 400 are the external RF power of the semiconductor chip 1 from the upper long side of the rectangular semiconductor chip 1. It is necessary to be supplied to the passive component 44 of the output matching circuit in the upper part of the wiring board 42 of the amplifier module.
  • the drain output signal of the final stage amplifying element Q3 of the RF power amplifier 200 and the drain output signal of the final stage amplifying element Q2 of the RF power amplifier 500 are from the lower long side of the rectangular semiconductor chip 1 to the external RF of the semiconductor chip 1. It is necessary to be supplied to the passive component 44 of the output matching circuit in the lower part of the wiring board 42 of the power amplifier module. As described above, since the drain output signal of the final stage amplifying element is not derived from the right short side and the left short side of the rectangular semiconductor chip 1, the right side portion and the left side portion of the wiring board 42 of the RF power amplifier module are not provided. Only the wiring 43 connected to the pads of the plurality of input terminals of the bias control unit 300 is arranged.
  • the rectangular semiconductor chip 1 is in the X direction of the semiconductor chip 1. Since the length increases in the direction of the line BB ′, the chip size of the semiconductor chip 1 increases. Further, since the RF signal output wiring of the wiring board 42 of the RF power amplifier module incorporating the rectangular semiconductor chip 1 long in the X direction is concentrated only on the upper part and the lower part of the wiring board 42, the wiring layout is reduced. As a result of studies by the present inventors prior to the present invention, the problem that the area and cost of the wiring board 42 are increased due to many restrictions has been clarified.
  • the present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.
  • an object of the present invention is to eliminate restrictions on the arrangement direction of the amplifying element on the semiconductor chip surface.
  • a typical embodiment of the present invention is a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500).
  • the first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at right angles.
  • a first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier ( 500) of the second final stage amplification element (Q2).
  • Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor,
  • the planar shape of the active region is a rectangle.
  • the extending direction of the long sides of the plurality of rectangular regions of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
  • the direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2)
  • the direction of the repeated enlargement is selected in the length direction of the second side (see FIGS. 7 and 8).
  • FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention.
  • FIG. 1 shows a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. It is a figure which shows the planar structure of LDMOSFET integrated.
  • FIG. 2 is a diagram showing a cross-sectional structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention, and is shown in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. It is a figure which shows the cross-section of LDMOSFET integrated.
  • FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention.
  • FIG. 1 shows a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. It is a figure which shows the plan
  • FIG. 3 is a diagram showing a configuration of the RF power amplifier module PA_MD studied by the inventors prior to the present invention, and is integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing the configuration of a high band RF power amplifier 100, a low band RF power amplifier 200, and a bias control unit 300.
  • FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention.
  • FIG. 5 is a diagram showing the configuration of another semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention.
  • FIG. 6 is a diagram showing a configuration of an RF power amplifier module studied by the present inventors prior to the present invention incorporating the semiconductor integrated circuit shown in FIG.
  • FIG. 7 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 8 shows the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, which has a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1.
  • FIG. 2 is a diagram showing a state in which a final stage amplification element Q3 and a large stage size final stage amplification element Q2 of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 are configured.
  • FIG. 9 is a diagram showing a specific state in which the large-amplifier final stage amplification element Q3 of the GSM high-band RF power amplifier 100 according to the first embodiment of the present invention shown in FIG. 8 is configured.
  • FIG. 10 is a diagram illustrating a main part of a specific configuration of the final-stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention illustrated in FIG.
  • FIG. 11 is a diagram illustrating a specific state in which the large-amplifier final stage amplification element Q2 of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention illustrated in FIG. 8 is configured.
  • FIG. 10 is a diagram illustrating a main part of a specific configuration of the final-stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention illustrated in FIG.
  • FIG. 11 is a
  • FIG. 12 is a diagram showing a main part of a specific configuration of final-stage amplifying element Q2 having a large element size of WCDMA low-band RF power amplifier 500 according to Embodiment 1 of the present invention shown in FIG. 13 shows a three-dimensional intersection of the gate electrode G of the LDMOSFET of the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 12 and the first drain wiring DM1.
  • FIG. 6 is a cross-sectional view showing a state where a source wiring electrically connected to a source region S connected to a ground voltage GND functions as an electrostatic shield layer in a portion to be operated.
  • FIG. 14 shows the characteristics of the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 of FIG. 7 shown in FIG. 9 and
  • FIG. 13 is a diagram comparing characteristics of a final stage amplifying element Q2 having a large element size of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 of FIG. 7 shown in FIG.
  • FIG. 15 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 16 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 17 is a diagram showing a planar structure and a sectional structure of a unit transistor Unit_TRS of a planar bipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3.
  • FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3.
  • FIG. 19 is a diagram showing a planar structure and a cross-sectional structure of a unit transistor Unit_TRS of a mesa type heterobipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 20 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region.
  • FIG. 21 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region.
  • FIG. 22 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 23 shows a GSM high-band RF power amplifier 100, a GSM low-band RF power amplifier 200, a bias controller 300, and a WCDMA high-band integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention.
  • FIG. 2 is a diagram showing the configuration of an RF power amplifier 400 and a WCDMA low-band RF power amplifier 500.
  • FIG. 24 is a diagram showing the configuration of the semiconductor chip 1 of the semiconductor integrated circuit and the configuration of the RF power amplifier module PA_MD according to the third embodiment of the present invention.
  • a typical embodiment of the present invention is a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500).
  • the first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at right angles.
  • a first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier is formed along the second side.
  • second final stage amplifying elements (Q2) are formed.
  • Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor,
  • the planar shape of the active region is a rectangle.
  • the extending direction of the long sides of the plurality of rectangular regions of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
  • the direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2)
  • the direction of the repeated enlargement is selected in the length direction of the second side (see FIGS. 7 and 8).
  • the restriction on the arrangement direction of the amplifying element on the semiconductor chip surface can be eliminated.
  • the first RF power amplifier (100) includes a first first stage amplifying element (Q1), and includes a second first stage amplifying element (Q1) of the second RF power amplifier (500).
  • the amplifying elements of the first first stage amplifying element (Q1) and the second first stage amplifying element (Q1) are configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first first stage amplifying element (Q1) and the second first stage amplifying element (Q1) has an active region that determines the gain of each unit transistor, and The planar shape of the region is a rectangle.
  • the extending direction of each long side of the plurality of active regions of the plurality of unit transistors of the first first stage amplifying element (Q1) and the plurality of unit transistors of the second first stage amplifying element (Q1) is selected in the length direction of the second side.
  • the first first stage amplification element (Q1) and the first last stage amplification element (Q3) of the first RF power amplifier (100) are formed on the surface of the semiconductor chip along the first side. .
  • the second first stage amplification element (Q1) and the second last stage amplification element (Q3) of the second RF power amplifier (500) are formed on the surface of the semiconductor chip along the second side. (See FIG. 7).
  • the first RF power amplifier (100) includes a first interstage matching circuit (MN), and includes a second interstage matching circuit (MN) of the second RF power amplifier (500). .
  • the first inter-stage matching circuit (MN) of the first RF power amplifier (100) receives the amplified signal at the output terminal of the first first stage amplifying element (Q1) as the input terminal of the first last stage amplifying element (Q3). To communicate.
  • the second inter-stage matching circuit (MN) of the second RF power amplifier (500) receives the amplified signal at the output terminal of the second first stage amplifying element (Q1) as the input terminal of the second last stage amplifying element (Q2). To communicate.
  • the first first stage amplifying element (Q1), the first interstage matching circuit (MN), and the first last stage amplifying element (Q3) of the first RF power amplifier (100) are arranged along the first side. Formed on the surface of the semiconductor chip.
  • the second first stage amplifying element (Q1), the second interstage matching circuit (MN), and the second last stage amplifying element (Q3) of the second RF power amplifier (500) are along the second side. It is formed on the surface of the semiconductor chip (see FIG. 7).
  • a plurality of first output wires (DM1) are connected to a plurality of output electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3), so that the second final output A plurality of second output wirings (DM1) are connected to a plurality of output electrodes of the plurality of unit transistors of the stage amplifying element (Q2).
  • a plurality of first input wirings (GM1) are connected to a plurality of input electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3), and the plurality of the plurality of unit transistors of the second final stage amplifying element (Q2) are connected.
  • a plurality of second input wirings (GM1) are connected to the plurality of input electrodes of the unit transistor.
  • the extending direction of each wiring of the plurality of first output wirings (DM1) is selected in the length direction of the second side, and the extending direction of each wiring of the plurality of first input wirings (GM1) is the first side. Is selected in the length direction.
  • the extending direction of each wiring of the plurality of second output wirings (DM1) is selected in the length direction of the first side, and the extending direction of each wiring of the plurality of second input wirings (GM1) is the first side. Is selected in the length direction (see FIG. 8).
  • the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of unit transistors of the second final stage amplification element (Q2) are field effect transistors.
  • the field effect transistor has a gate electrode (G), a drain region (D), and a source region (S), and a length direction of the second side of the gate electrode between the drain region and the source region.
  • the rectangular short side of the active region is determined by the gate length (L) of the gate electrode, and the gate width (W) in the length direction of the first side of the gate electrode between the drain region and the source region is determined.
  • the long side of the rectangle of the active region is determined (see FIG. 8).
  • the plurality of first output wirings (DM1) are provided in the plurality of drain regions as the plurality of output electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3). Are connected, and the plurality of second output wirings (DM1) are connected to the plurality of drain regions as the plurality of output electrodes of the plurality of unit transistors of the second final stage amplifying element (Q2).
  • the plurality of first input wirings (GM1) are connected to the plurality of gate electrodes as the plurality of input electrodes of the plurality of unit transistors of the first final stage amplification element (Q3), and the second final stage amplification is performed.
  • the plurality of second input wirings (GM1) are connected to the plurality of gate electrodes as the plurality of input electrodes of the plurality of unit transistors of the element (Q2).
  • the extension direction of each wiring of the plurality of first output wirings (DM1) is selected in the length direction of the second side, and the extension direction of each wiring of the plurality of first input wirings (GM1) is It is selected in the length direction of the first side.
  • the extension direction of each wiring of the plurality of second output wirings (DM1) is selected in the length direction of the first side, and the extension direction of each wiring of the plurality of second input wirings (GM1) is The first side is selected in the length direction (see FIG. 8).
  • the plurality of gate electrodes which are the plurality of input electrodes of the plurality of unit transistors of the second final stage amplifying element (Q2) are the plurality of rectangles.
  • An active region is formed on the surface of the semiconductor chip extending in the length direction of the second side.
  • the plurality of gate electrodes (G) formed in the length direction of the second side and the plurality of second output wirings (DM1) formed in the length direction of the first side are formed on the semiconductor chip. Three-dimensionally intersect on the surface.
  • the source region (GND) connected to the ground voltage (GND) at a portion where the plurality of gate electrodes (G) and the plurality of second output wirings (DM1) intersect three-dimensionally on the surface of the semiconductor chip.
  • a plurality of source lines (24A) electrically connected to S) are formed between the plurality of gate electrodes (G) and the plurality of second output lines (DM1). Yes (see FIGS. 12 and 13).
  • the semiconductor chip is formed with a plurality of punched layers (4) reaching the back surface of the semiconductor chip from the front surface of the semiconductor chip.
  • the plurality of source lines (24A) are electrically connected to a source back surface electrode (36) formed on the back surface of the semiconductor chip through the plurality of punched layers (4). (See FIG. 13).
  • the plurality of unit transistors of the first final stage amplifying element (Q3) and the field effect transistors as the plurality of unit transistors of the second final stage amplifying element (Q2) are LDMOSFETs. (See FIGS. 7 and 8).
  • the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of unit transistors of the second final stage amplification element (Q2) are bipolar transistors. .
  • the bipolar transistor has a plurality of emitter regions, and the plurality of emitter regions are formed on the surface of the semiconductor chip as the plurality of rectangular active regions extending in the length direction of the second side. This is a feature (see FIG. 22).
  • the plurality of unit transistors of the first final stage amplification element (Q3) and the bipolar transistors as the plurality of unit transistors of the second final stage amplification element (Q2) are heterogeneous. It is a bipolar transistor (see FIG. 22).
  • the semiconductor integrated circuit further includes a third RF power amplifier (200).
  • the third side of the semiconductor chip of the semiconductor integrated circuit is arranged substantially parallel to the first side and intersects the second side substantially at a right angle.
  • a third final amplification element (Q3) of the third RF power amplifier (200) is formed on the surface of the semiconductor chip along the third side.
  • the third final stage amplifying element (Q3) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the third final stage amplifying element (Q3) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected in the length direction of the third side (see FIGS. 7 and 8). ).
  • the semiconductor integrated circuit further includes a fourth RF power amplifier (400).
  • the fourth side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the second side and intersects the third side substantially at a right angle.
  • a fourth final stage amplifying element (Q2) of the fourth RF power amplifier (400) is formed on the surface of the semiconductor chip along the fourth side.
  • the fourth final stage amplifying element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element (Q2) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected in the length direction of the fourth side (see FIGS. 7 and 8). ).
  • the third RF power amplifier (200), and the A bias controller (300) is formed at a position between the fourth RF power amplifier (400).
  • the bias control unit (300) is connected to the first first stage amplifying element (Q1) and the first last stage amplifying element (Q3) of the first RF power amplifier (100).
  • the second first stage amplifying element (Q1) and the second last stage amplifying element (Q2) are connected to the third first stage amplifying element (Q1) and the third last stage amplifying element (Q3) of the third RF power amplifier (200).
  • a bias voltage is supplied to each of the fourth first stage amplifying element (Q1) and the fourth last stage amplifying element (Q2) of the fourth RF power amplifier (400) (FIG. 7, FIG. 8).
  • a typical embodiment of another aspect of the present invention is a module in which a semiconductor chip of a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500) is mounted on a wiring board. It is.
  • the first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at a right angle.
  • a first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier is formed along the second side.
  • second final stage amplifying elements (Q2) are formed.
  • Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
  • Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor,
  • the planar shape of the active region is a rectangle.
  • the extending directions of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3), and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
  • the direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2)
  • the direction of the repeated enlargement is selected in the length direction of the second side.
  • the semiconductor chip is mounted on the wiring board.
  • a first output matching circuit (100_OutMN) of the first RF power amplifier (100) is mounted on a first substrate portion of the wiring board that faces the one side of the semiconductor chip, and faces the two sides of the semiconductor chip.
  • a second output matching circuit (500_OutMN) of the second RF power amplifier (500) is mounted on the second substrate portion of the wiring board.
  • the amplified signal at the output terminal of the first final stage amplifying element (Q3) is supplied to the first output matching circuit (100_OutMN) via the one side of the semiconductor chip.
  • the amplified signal at the output terminal of the second final stage amplifying element (Q2) is supplied to the second output matching circuit (500_OutMN) via the two sides of the semiconductor chip. (See FIG. 24).
  • the restriction on the arrangement direction of the amplifying element on the semiconductor chip surface can be eliminated.
  • the semiconductor integrated circuit further includes a third RF power amplifier (200).
  • the third side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the first side and intersects the second side substantially at a right angle.
  • a third final amplification element (Q3) of the third RF power amplifier (200) is formed on the surface of the semiconductor chip along the third side.
  • the third final stage amplifying element (Q3) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the third final stage amplifying element (Q3) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected in the length direction of the third side.
  • a third output matching circuit (200_OutMN) of the third RF power amplifier (200) is mounted on the third substrate portion of the wiring board facing the three sides of the semiconductor chip.
  • the amplified signal at the output terminal of the third final stage amplifying element (Q3) is supplied to the third output matching circuit (200_OutMN) via the three sides of the semiconductor chip. (See FIG. 24).
  • the semiconductor integrated circuit further includes a fourth RF power amplifier (400).
  • the fourth side of the semiconductor chip of the semiconductor integrated circuit is arranged substantially parallel to the second side and intersects the third side substantially at a right angle.
  • a fourth final stage amplifying element (Q2) of the fourth RF power amplifier (400) is formed on the surface of the semiconductor chip along the fourth side.
  • the fourth final stage amplifying element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element (Q2) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
  • the extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected as the length direction of the second side.
  • the direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected in the length direction of the fourth side.
  • a fourth output matching circuit (400_OutMN) of the fourth RF power amplifier (400) is mounted on the fourth substrate portion of the wiring board facing the four sides of the semiconductor chip.
  • the amplified signal at the output terminal of the fourth final stage amplification element (Q2) is supplied to the fourth output matching circuit (400_OutMN) through the four sides of the semiconductor chip. (See FIG. 24).
  • the plurality of unit transistors is a field effect transistor.
  • the first final stage amplification element (Q3), the second final stage amplification element (Q2), the third final stage amplification element (Q3), and the fourth final stage amplification element is an LDMOSFET.
  • the first final stage amplification element (Q3), the second final stage amplification element (Q2), the third final stage amplification element (Q3), and the fourth final stage amplification element ( The plurality of unit transistors of Q2) are bipolar transistors.
  • FIG. 1 is a diagram showing a planar structure of an LDMOSFET integrated on a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. Since the planar structure in FIG. 1 has been described at the beginning, description thereof will be omitted.
  • FIG. 2 is a diagram showing a cross-sectional structure of the LDMOSFET integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. Since the sectional structure of FIG. 2 has been described at the beginning, the description thereof will be omitted.
  • FIG. 3 is a diagram showing a configuration of the high-band RF power amplifier 100, the low-band RF power amplifier 200, and the bias control unit 300 that are integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • FIG. 7 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention includes the high-band RF power amplifier and the low-band RF power amplifier shown in FIG. , Built-in. That is, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7 includes a plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier (GSM_HB) 100 and the GSM low band RF power.
  • GSM_HB GSM high band RF power amplifier
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7 includes a GSM high-band RF power amplifier (GSM_HB) 100, a GSM low-band RF power amplifier (GSM_LB) 200, and a WCDMA system.
  • GSM_HB GSM high-band RF power amplifier
  • GSM_LB GSM low-band RF power amplifier
  • WCDMA WCDMA system.
  • the input matching circuit InMN and the interstage matching circuit MN of each power amplifier of the high band RF power amplifier (WCDMA_HB) 400 and the WCDMA low band RF power amplifier (WCDMA_LB) 500 are integrated.
  • the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 respectively constituted by three-stage amplifiers are The rectangular semiconductor chip 1 is disposed on the upper long side and the lower long side, respectively. That is, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1. The plurality of LDMOSFETs Q 1, Q 2, Q 3 of the low-band RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 each constituted by a two-stage amplifier are used.
  • the rectangular semiconductor chip 1 is disposed on the left short side and the right short side, respectively.
  • the plurality of LDMOSFETs Q 1 and Q 2 of the WCDMA high-band RF power amplifier 400 are arranged on the short left side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1, and the WCDMA low-band
  • the plurality of LDMOSFETs Q1 and Q2 of the RF power amplifier 500 are arranged on the short right side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 are each constituted by a three-stage amplifier, and the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 are constituted by a two-stage amplifier. Each is configured because the transmission power of the GSM mobile communication terminal to the base station is relatively higher than that in the WCDMA system.
  • the extending direction of the long sides of the two gate electrodes is Y in the semiconductor chip 1.
  • the direction of the AA ′ line, which is the direction, is selected, while the unit transistor repeated enlargement for realizing a large element size is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 on the lower long side of the semiconductor chip 1 is extended in the Y direction of the semiconductor chip 1 in the extending direction of the long sides of the two gate electrodes. Is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size.
  • the final stage amplifying element Q2 which is a large element size of the WCDMA high band RF power amplifier 400 on the left short side of the semiconductor chip 1
  • the extending direction of the long sides of the two gate electrodes is the semiconductor chip 1.
  • Is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip, while repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip 1 Has been.
  • the extending direction of the long sides of the two gate electrodes is Y in the semiconductor chip 1. While the direction of the AA ′ line that is the direction is selected, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Yes.
  • the first stage amplifying element Q1 and the second stage amplifying element Q2 of each amplifier of the GSM type high band RF power amplifier 100 and the GSM type low band RF power amplifier 200 are also the final stage amplifying element Q3.
  • a plurality of unit transistors are connected in parallel.
  • a plurality of unit transistors constituting the second-stage amplifying element Q2 are repeated in the direction of the BB ′ line that is the X direction of the semiconductor chip 1
  • the enlargement amount is set smaller than the repeated enlargement amount of the final stage amplifying element Q3 that generates a large RF output.
  • the repeated enlargement amount in the direction of the BB ′ line which is the X direction of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplifying element Q1, gives an intermediate output. It is set to be smaller than the repetitive enlargement amount of the generated second-stage amplifying element Q2.
  • the first-stage amplifying element Q1 of each amplifier of the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 is also composed of a plurality of units similarly to the final-stage amplifying element Q2. It is configured by parallel connection of transistors. In order for the first stage amplifying element Q1 to generate a small RF output, the repeated enlargement amount in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplifying element Q1 generates a large output. It is set to be smaller than the repeated enlargement amount of the final stage amplifying element Q2.
  • FIG. 8 shows the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, which has a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1.
  • FIG. 2 is a diagram showing a state in which a final stage amplification element Q3 and a large stage size final stage amplification element Q2 of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 are configured.
  • FIG. 8 In the lower left of FIG. 8, two gate electrodes G formed in a rectangular shape, one drain region D formed in a rectangular shape in the center of the two gate electrodes G, and two gate electrodes G A planar structure of an LDMOSFET unit transistor Unit_MOS including two source regions S formed in a rectangular shape outside is shown.
  • the gate length L of the LDMOSFET is determined by the length of the gate electrode G between the drain region D and the source region S in the direction of the BB ′ line, and the gate electrode G between the drain region D and the source region S is determined.
  • the gate width W of the LDMOSFET is determined by the width in the direction of the AA ′ line. Since the two gate electrodes G of one unit transistor Unit_MOS are connected in common and the two source regions S are also connected in common, the two LDMOSFETs inside one unit transistor Unit_MOS operate in parallel.
  • the final stage amplifying element Q3 of the large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. Is repeatedly expanded for two rows in the X direction, and is repeatedly expanded for nine columns in the Y direction. That is, in the final stage amplifying element Q3, the substantial repeated enlargement of the unit transistor Unit_MOS for realizing a large element size is selected in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 disposed on the lower long side of the semiconductor chip 1 is also substantially repetitively enlarged by the unit transistor Unit_MOS for realizing a large element size.
  • the semiconductor chip 1 is selected in the direction of line BB ′, which is the X direction. Note that the repetition row in the X direction and the repetition column in the Y direction of the final stage amplifying element Q3 of the large element size of the GSM high band RF power amplifier 100 shown in FIG. As described, there are 3 rows and 12 columns. The reason why the repeated rows in the X direction and the repeated columns in the Y direction are made smaller than the actual size in FIG. 8 is to illustrate the gate electrode G and the drain region D omitted in FIG. 9 in FIG.
  • the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 disposed on the right short side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. Is repeatedly expanded for four rows in the X direction, and is repeatedly expanded for three columns in the Y direction. That is, in the final stage amplification element Q2, the substantial repeated enlargement of the unit transistor Unit_MOS for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the large-stage final-stage amplifying element Q2 of the WCDMA high-band RF power amplifier 400 arranged on the short left side of the semiconductor chip 1 is also a substantial repetition of the unit transistor Unit_MOS for realizing a large element size.
  • the enlargement is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the reason why the repeated rows in the X direction and the repeated columns in the Y direction are made smaller than the actual size in FIG. 8 is to illustrate the gate electrode G and the drain region D omitted in FIG. 12 in FIG.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are connected to the first gate wiring GM1,
  • the one gate wiring GM1 is connected to the gate pad GP through the second gate wiring GM2 having a large wiring width.
  • the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to the plurality of drain pads DP via the first drain wiring DM1.
  • the plurality of parallel first drain wirings DM1 are formed in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are connected to the first gate line GM1,
  • the one gate wiring GM1 is connected to the gate pad GP through the second gate wiring GM2 having a large wiring width.
  • the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to the plurality of drain pads DP via the first drain wiring DM1.
  • the plurality of parallel first drain wirings DM1 are formed in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
  • FIG. 9 is a diagram showing a specific state in which the large-amplifier final stage amplifying element Q3 of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention shown in FIG. 8 is configured.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are omitted. Furthermore, since the plurality of drain regions D of the plurality of unit transistors Unit_MOS exist below the first drain wiring DM1, they are omitted from the plan view of FIG. As shown in FIG. 9, the gate pad GP and the drain pad DP can be electrically connected to the outside of the semiconductor chip 1 by bonding wires BW or the like.
  • the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 is formed by connecting the unit transistor Unit_MOS shown in the lower left of FIG. It is configured by repeatedly enlarging 3 rows in the direction and repeatedly enlarging 12 columns in the Y direction. That is, the final stage amplifying element Q3 having a large element size is selected in the direction of the BB ′ line which is the X direction of the semiconductor chip 1 in order to substantially repeat the expansion of the unit transistor Unit_MOS for realizing the large element size. .
  • FIG. 10 is a diagram showing a main part of a specific configuration of the final stage amplifying element Q3 having a large element size of the GSM high band RF power amplifier 100 according to Embodiment 1 of the present invention shown in FIG.
  • a first drain wiring DM1 is formed on one drain region D formed in a rectangular shape at the center of the two gate electrodes G, and the two gate electrodes G serve as the first drain. They are commonly connected by a first gate line GM1 formed under the line DM1.
  • FIG. 11 is a diagram showing a specific state in which the large-amplifier final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 8 is configured.
  • the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are omitted. Further, the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to a plurality of first drain wirings DM1 formed in the direction of the BB ′ line that is the X direction.
  • the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 arranged on the right short side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. It is configured by iteratively enlarging for 12 rows in the direction and repeatedly enlarging for 5 columns in the Y direction. That is, the final stage amplifying element Q2 having a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1 in order to substantially repeat the enlargement of the unit transistor Unit_MOS for realizing the large element size. .
  • the large element size final stage amplifying element Q3 of the GSM high band RF power amplifier 100 shown in FIG. 9 and the large element size final stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 shown in FIG. R GSM (3 rows) ⁇ R WCDMA (12 rows), C GSM (12 columns)> C WCDMA (5 columns).
  • FIG. 12 is a diagram showing a main part of a specific configuration of the final stage amplifying element Q2 having a large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG.
  • the drain region D formed in a rectangular shape in the center portion of the two gate electrodes G is connected to the first drain wiring DM1 through the contact opening CNT, and the two gate electrodes G are connected to the first gate electrode G.
  • the first gate wiring GM1 formed in parallel with the one drain wiring DM1 is commonly connected.
  • DM1 crosses three-dimensionally. The cross-sectional distance between the gate electrode G and the first drain wiring DM1 is smaller than the planar distance between the first gate wiring GM1 and the first drain wiring DM1 formed in parallel in the plan view of FIG. Become.
  • the gate / drain feedback capacitance that determines the high-frequency characteristics of the LDMOSFET as the high-frequency amplifier is not the plane distance between the first gate wiring GM1 and the first drain wiring DM1, but the gate electrode G and the first drain wiring DM1.
  • the value of the gate-drain feedback capacitance increases, which is dominantly determined by the cross-sectional distance between the two.
  • the value of the gate-drain feedback capacitance increases, the high frequency characteristics of the LDMOSFET deteriorate.
  • the source wiring electrically connected to the source region S connected to the ground voltage GND is electrostatically connected at a portion where the gate electrode G of the LDMOSFET and the first drain wiring DM1 intersect three-dimensionally. Functions as a shield layer. That is, the source wiring functioning as an electrostatic shield layer is formed between the gate electrode G of the LDMOSFET and the first drain wiring DM1 at the three-dimensional intersection.
  • FIG. 13 shows a three-dimensional intersection of the gate electrode G of the LDMOSFET of the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 12 and the first drain wiring DM1.
  • FIG. 6 is a cross-sectional view showing a state where a source wiring electrically connected to a source region S connected to a ground voltage GND functions as an electrostatic shield layer in a portion to be operated.
  • the cross-sectional structure shown in FIG. 13 is obtained by forming a silicon nitride film 20 and a silicon oxide film 21 on top of the cross-sectional structure shown in FIG.
  • a plurality of contact holes 22 are formed in the silicon nitride film 20 and the silicon oxide film 21, and a first plug wiring 23 is formed inside the plurality of contact holes 22.
  • the N + type source region 16 and the P + type semiconductor region 17 of the source region S of the LDMOSFET are electrically connected to a source electrode 24A as a first source wiring via a plurality of first plug wirings 23. Further, the N + type drain region 15 of the drain region D of the LDMOSFET is electrically connected to the drain electrode 24B through the first plug wiring 23.
  • a first interlayer silicon oxide film 26 is formed on the source electrode 24A and the drain electrode 24B.
  • a through hole 27 is formed in the first interlayer silicon oxide film 26 above the drain electrode 24 B, and a second plug wiring 28 is formed inside the through hole 27.
  • a second drain electrode 29B is formed on the second plug wiring 28.
  • a second interlayer silicon oxide film 30 is formed on the second drain electrode 29B, and a through hole 31 (contact opening CNT) is formed in the second interlayer silicon oxide film 30 on the second drain electrode 29B.
  • a third plug wiring 32 is formed in the through hole 31. In the third plug wiring 32, a wiring layer 33 as the first drain wiring DM1 is formed.
  • the source electrode 24A overlaps the upper part of the gate electrode G (7) of the lower LDMOSFET, the gate electrode G (7) of the lower LDMOSFET and the upper first drain wiring DM1 (wiring layer 33). ) Is shielded so that the source electrode 24A effectively functions as an electrostatic shield layer. Further, a silicon oxide film 34 and a silicon nitride film 35 are formed as a final passivation film on the first drain wiring DM1 (wiring layer 33).
  • FIG. 14 shows the characteristics of the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 of FIG. 7 shown in FIG. 9 and FIG. And the characteristics of the large-amplifier final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 disposed on the short right side of the semiconductor chip 1 of FIG. 7 shown in FIG. 12 and the same gate width. It is the figure compared by gate length.
  • the final stage amplifying element Q3 of the GSM high-band RF power amplifier 100 and the final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 are shown. Have equivalent characteristics. However, regarding the feedback capacitance Crss, the final stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 is improved by 18% over the final stage amplifying element Q3 of the GSM high band RF power amplifier 100.
  • the last stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 has a smaller feedback capacity Crss than the last stage amplifying element Q3 of the GSM high-band RF power amplifier 100.
  • the source described in FIGS. The electrostatic shield effect between the first drain wiring DM and the gate electrode G (7) by the electrode 24A and the first gate wiring GM1 and the first drain wiring DM are arranged in parallel as apparent from FIG. This is because the first gate line GM1 and the first drain line DM1 do not intersect.
  • the final stage amplifying element Q3 of the GSM high band RF power amplifier 100 as is apparent from FIG. 9, the first gate wiring GM1 and the first drain wiring DM1 are arranged orthogonally, and the first gate wiring Since GM1 and the first drain wiring DM1 intersect, the feedback capacitance Crss increases.
  • the final stage amplification element Q2 of the WCDMA low-band RF power amplifier 500 has a smaller feedback capacity Crss than the final stage amplification element Q3 of the GSM high-band RF power amplifier 100, the final-stage amplification of the WCDMA low-band RF power amplifier 500 is performed.
  • the power added efficiency of the element Q2 is improved by about 3%.
  • the plurality of LDMOSFETs Q1 and Q2 of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1 are formed by the element structure described in FIGS. 11, 12, and 13 and function as an electrostatic shield layer.
  • the source electrode 24A can effectively shield between the gate electrode G (7) of the lower LDMOSFET and the upper first drain wiring DM1 (wiring layer 33).
  • FIG. 15 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15 is different from the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described in FIGS. 7 to 14 in the following points.
  • pads of the plurality of input terminals of the bias control unit 300 are provided on the upper long side of the rectangular semiconductor chip 1. Are arranged in the direction of the line BB ′, which is the X direction.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15 is the same as the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. Therefore, in the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM type low-band RF power amplifier 200 are the same as the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG.
  • the plurality of LDMOSFETs Q1 and Q2 of the WCDMA high-band RF power amplifier 400 are arranged in the direction of the BB ′ line which is the X direction on the lower long side of the A, and the A in the Y direction is on the left short side of the semiconductor chip 1.
  • a plurality of LDMOSFETs Q 1 and Q 2 of the WCDMA low-band RF power amplifier 500 are arranged in the direction of the AA line, and are arranged in the direction of the AA ′ line which is the Y direction on the short side of the right side of the semiconductor chip 1.
  • FIG. 16 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16 is different from the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. 7 to 14 in the following points.
  • the block of the bias control unit 300 is moved in the direction of the left short side of the semiconductor chip 1 to form a rectangular semiconductor chip.
  • a pad of a plurality of input terminals of the bias control unit 300 is arranged on the lower long side of 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16 is the same as the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. Therefore, in the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM type high-band RF power amplifier 100 are the same as the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. A plurality of LDMOSFETs Q1 and Q2 of the WCDMA low-band RF power amplifier 500 are arranged on the upper long side of the chip 1 in the direction of the BB ′ line which is the X direction. -A 'line direction.
  • FIG. 17 is a diagram showing a planar structure and a sectional structure of a unit transistor Unit_TRS of a planar bipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • a rectangular emitter electrode E is formed at the center, and a base electrode B is formed outside the emitter electrode E.
  • a collector electrode C is formed on the outside.
  • the broken line between the emitter electrode E and the base electrode B indicates the planar shape of the emitter-base junction
  • the broken line between the base electrode B and the collector electrode C indicates the planar shape of the base-collector junction.
  • the broken line outside the collector electrode C indicates the planar shape of the N-type collector region.
  • the emitter electrode E is electrically connected to the N + -type emitter region by ohmic contact
  • the base electrode B is electrically connected to the P-type base region by ohmic contact
  • the collector electrode C Are electrically connected to the N-type collector region by ohmic contact with the N + -type high impurity collector region.
  • a P-type substrate of a semiconductor integrated circuit is formed below the N-type collector region.
  • silicon is used for the N + -type emitter region, the P-type base region, the N-type collector region, and the P-type substrate.
  • the emitter current flows at a larger current density in the corner portion than in the flat portion of the cross-sectional structure of the emitter-base junction. This is well known as the edge effect of a transistor, and is caused by electric field concentration at the corner of the emitter-base junction.
  • the conductance of the amplification gain of the planar bipolar transistor shown in FIG. 17 is proportional to the emitter size of the transistor.
  • the emitter size of the planar bipolar transistor is determined more dominantly by the length of the peripheral distance in the planar structure of the emitter-base junction by the edge effect than the size of the emitter area.
  • the flat area of the useless emitter region is reduced by making the emitter region of the planar structure of the transistor rectangular. This increases the length of the peripheral distance in a useful emitter-base junction planar structure.
  • the unit transistor is repeatedly expanded in order to realize a large element size, and the repeated expansion is realized by parallel connection of a plurality of unit transistors.
  • FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3.
  • a plurality of unit transistors Unit_TRS of the planar bipolar transistor shown in FIG. 17 are repeatedly expanded in the direction of the BB ′ line which is the X direction.
  • the conductance of the amplification gain of the unit transistor Unit_TRS of the bipolar transistor shown in FIG. 17 also varies due to variations in the length of the peripheral distance in the planar structure of the emitter-base junction. The reason is that, in the photolithography for forming a rectangular emitter region having a planar structure in the manufacturing process of the semiconductor chip, the X direction and the Y direction have different dimensional deviations.
  • Q3 and WCDMA high-band RF power amplifier 400 transistors Q1 and Q2 and WCDMA low-band RF power amplifier 500 transistors Q1 and Q2 of all transistors in the planar structure of the emitter region of the rectangular long side extending direction is semiconductor The direction of the AA ′ line that is the Y direction of the chip 1 is unified.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM high-band RF power amplifier 100 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM low-band RF power amplifier 200 are a semiconductor chip. 1 is selected in the direction of the BB ′ line, which is the X direction.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA high-band RF power amplifier 400 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA low-band RF power amplifier 500 are the semiconductor chip 1 Is selected in the direction of the line AA ′, which is the Y direction.
  • FIG. 19 is a diagram showing a planar structure and a cross-sectional structure of a unit transistor Unit_TRS of a mesa type heterobipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • a rectangular emitter electrode E is formed in the center portion, and a base electrode B is formed outside the emitter electrode E.
  • a collector electrode C is formed on the outside.
  • the broken line between the emitter electrode E and the base electrode B indicates the planar shape of the emitter-base junction
  • the broken line between the base electrode B and the collector electrode C indicates the planar shape of the base-collector junction.
  • the broken line outside the collector electrode C indicates the planar shape of the N-type collector region.
  • the emitter electrode E is electrically connected to the N + -type emitter region which is the uppermost layer of the mesa structure by ohmic contact
  • the base electrode B is a P-type base which is an intermediate layer of the mesa structure.
  • the region is electrically connected to the region by ohmic contact
  • the collector electrode C is electrically connected to the N-type collector region which is the lowermost layer of the mesa structure by ohmic contact.
  • a semi-insulating substrate Sub having a high resistivity of the semiconductor integrated circuit is formed below the N-type collector region.
  • an N + -type emitter region that is the uppermost layer of the mesa structure, a P-type base region that is the intermediate layer, an N-type collector region that is the lowermost layer, and a semi-insulating substrate include a compound such as GaAs. A semiconductor is used.
  • the emitter current flows at a larger current density in the corner portion than in the flat portion of the cross-sectional structure of the emitter-base junction due to the edge effect described above.
  • the conductance of the amplification gain of the mesa heterobipolar transistor shown in FIG. 19 is also proportional to the emitter size of the transistor.
  • the emitter size of the mesa type heterobipolar transistor is determined more dominantly by the length of the peripheral distance in the planar structure of the emitter-base junction than the size of the emitter area due to the edge effect described above.
  • the flat area of the useless emitter region is reduced by making the emitter region of the planar structure of the transistor rectangular. This increases the length of the peripheral distance in a useful emitter-base junction planar structure.
  • the unit transistor is repeatedly expanded in order to realize a large element size, and the repeated expansion is realized by parallel connection of a plurality of unit transistors.
  • FIG. 20 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention, and the transistor Q1 of the GSM low-band RF power amplifier 200.
  • FIG. 3 is a diagram showing a planar structure of each RF power amplification mesa heterotransistor of Q2, Q2, and Q3.
  • one RF power amplification mesa type heterotransistor repeats a plurality of unit transistors Unit_TRS of the sa type heterobipolar transistor shown in FIG. 19 in the direction of the BB ′ line which is the X direction.
  • the conductance of the amplification gain of the unit transistor Unit_TRS of the mesa heterobipolar transistor shown in FIG. 19 also varies depending on the variation in the length of the peripheral distance in the planar structure of the emitter-base junction.
  • the reason for this is that not only does the X-direction and the Y-direction have different dimensional deviations in the photolithography for forming a rectangular emitter region having a planar structure in the manufacturing process of the semiconductor chip, but the mesa-type trapezoidal shape has a mesa-type emitter region. This is because there is a deviation due to the difference in the extending direction of the long side of the rectangle.
  • the mesa-type trapezoidal shape of the mesa-type emitter region has a deviation due to the difference in the extension direction of the long side due to the anisotropic etching at the time of chemical etching at the time of forming the mesa-type trapezoidal shape. It is. That is, the etching rates of chemical etching are different on a plurality of side surfaces of the mesa trapezoid.
  • FIG. 21 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region.
  • the mesa emitter region when the extension direction of the long side of the rectangle of the mesa emitter region is selected in the direction of the AA ′ line which is the Y direction (emitter length direction A), the mesa emitter region The case where the extension direction of the long side of the rectangle is selected in the direction of the BB ′ line which is the X direction (emitter length direction B) is shown.
  • the mesa trapezoidal shape in the cross section along the line aa ′ has a shorter lower side than the upper side, the length of the peripheral distance becomes longer as shown in the emitter length direction A in the upper part of FIG.
  • the conductance value of the amplification gain of the transistor increases.
  • the mesa type trapezoidal shape in the cross section along the line bb ′ has a lower side longer than the upper side, the length of the peripheral distance becomes shorter as shown in the emitter length direction B in the upper part of FIG.
  • the conductance value of the amplification gain of the transistor becomes small.
  • a shape having a long upper side of the trapezoidal shape is called an inverted mesa, and a shape having a short upper side of the trapezoidal shape is called a forward mesa.
  • Mesa heterobipolar transistors Q1, Q2, Q3 and all mesa types of mesa heterobipolar transistors Q1, Q2 of WCDMA high band RF power amplifier 400 and mesa heterobipolar transistors Q1, Q2 of WCDMA low band RF power amplifier 500 The extending direction of the long side of the rectangular emitter region of the planar structure of the heterobipolar transistor is unified with the direction of the AA ′ line which is the Y direction of the semiconductor chip 1.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM high-band RF power amplifier 100 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM low-band RF power amplifier 200 are a semiconductor chip. 1 is selected in the direction of the BB ′ line, which is the X direction.
  • the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA high-band RF power amplifier 400 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA low-band RF power amplifier 500 are the semiconductor chip 1 Is selected in the direction of the line AA ′, which is the Y direction.
  • FIG. 22 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention includes a high-band RF power amplifier and a low-band RF power amplifier shown in FIG. It is built-in. That is, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 22 includes a plurality of transistors Q1 and Q2 of the GSM high-band RF power amplifier (GSM_HB) 100 and a GSM low-band RF power amplifier.
  • GSM_HB GSM high-band RF power amplifier
  • GSM_LB A plurality of transistors Q1, Q2 of 200, and further a plurality of transistors Q1, Q2 of WCDMA high-band RF power amplifier (WCDMA_HB) 400 and a plurality of transistors Q1, Q2 of WCDMA low-band RF power amplifier (WCDMA_LB) 500 And the bias controller 300 are integrated.
  • all the transistors Q1 and Q2 integrated in the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22 are the planar bipolar transistors described with reference to FIGS. Or, it is the mesa type hetero bipolar transistor described in FIG. 19, FIG. 20, and FIG.
  • the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22 includes a GSM high band RF power amplifier (GSM_HB) 100, a GSM low band RF power amplifier (GSM_LB) 200, and a WCDMA high
  • GSM_HB GSM high band RF power amplifier
  • GSM_LB GSM low band RF power amplifier
  • WCDMA WCDMA high
  • InMN and the interstage matching circuit MN of each power amplifier of the band RF power amplifier (WCDMA_HB) 400 and the WCDMA low-band RF power amplifier (WCDMA_LB) 500 are integrated.
  • the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 are the same as those of the rectangular semiconductor chip 1. They are arranged on the upper long side and the lower long side, respectively.
  • the plurality of transistors Q1 and Q2 of the GSM high-band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1, and the GSM low-band
  • the plurality of transistors Q1 and Q2 of the RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
  • the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 are the left of the rectangular semiconductor chip 1. It is arrange
  • the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. While selected in the direction of the AA ′ line, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the BB ′ line which is the X direction of the semiconductor chip 1. Further, in the final stage amplification transistor Q2 having a large element size of the GSM low band RF power amplifier 200 at the lower long side of the semiconductor chip 1, the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. On the other hand, the unit transistor is repeatedly expanded in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while being selected in the direction of the ⁇ A ′ line.
  • the extension direction of the long side of the emitter region is in the Y direction of the semiconductor chip 1. Is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size. .
  • the final stage amplification transistor Q2 which is a large element size of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1, the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. While selected in the direction of the AA ′ line, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1.
  • a plurality of unit transistors are connected in parallel as in the first stage amplification transistor Q1 and the last stage amplification transistor Q2 of each amplifier of the GSM high band RF power amplifier 100 and the GSM low band RF power amplifier 200. It is configured.
  • the amount of repetitive expansion in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplification transistor Q1 is the final stage amplification with a large gain. It is set smaller than the repetitive enlargement amount of the transistor Q2.
  • the first stage amplification transistor Q1 of each amplifier of the WCDMA high band RF power amplifier 400 and the WCDMA low band RF power amplifier 500 is also configured by parallel connection of a plurality of unit transistors, like the last stage amplification transistor Q2.
  • the amount of repetitive expansion in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplification transistor Q1 is the final stage amplification with a large gain. It is set smaller than the repetitive enlargement amount of the transistor Q2.
  • FIG. 23 shows a GSM high-band RF power amplifier 100, a GSM low-band RF power amplifier 200, a bias controller 300, and a WCDMA high-band integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention.
  • FIG. 2 is a diagram showing the configuration of an RF power amplifier 400 and a WCDMA low-band RF power amplifier 500.
  • Each RF power amplifier of the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 includes a first stage amplifying element Q1, a second stage amplifying element Q2, and a last stage amplifying element Q3.
  • the common electrodes of the plurality of amplification elements Q1 to Q3 are connected to the ground voltage GND, and the power supply voltage is connected to the output electrodes of the plurality of amplification elements Q1, Q2, and Q3 via load inductors L1, L2, and L3. Vdd is supplied.
  • the GSM high-band RF transmission input signal Pin_GSM_HB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is interstage.
  • the amplified signal of the amplifying element Q2 is supplied to the input electrode of the final stage amplifying element Q3 via the interstage matching circuit MN via the matching circuit MN.
  • the amplified signal of Q3 is output as a GSM high-band RF transmission output signal Pout_GSM_HB via the output matching circuit OutMN.
  • the GSM low-band RF transmission input signal Pin_GSM_LB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is the inter-stage matching circuit.
  • the amplified signal of the amplifying element Q2 is supplied to the input electrode of the final stage amplifying element Q3 via the interstage matching circuit MN and supplied to the input electrode of the amplifying element Q3.
  • the amplified signal is output as a GSM low-band RF transmission output signal Pout_GSM_LB via the output matching circuit OutMN.
  • Each RF power amplifier of the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 includes a first stage amplifying element Q1 and a last stage amplifying element Q2.
  • the common electrodes of the plurality of amplification elements Q1 and Q2 are connected to the ground voltage GND, and the power supply voltage Vdd is supplied to the output electrodes of the plurality of amplification elements Q1 and Q2 via the load inductors L1 and L2.
  • the WCDMA high-band RF transmission input signal Pin_WCDMA_HB is supplied to the input electrode of the first stage amplifying element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifying element Q1 is interstage.
  • the signal is supplied to the input electrode of the final stage amplifying element Q2 via the matching circuit MN, and the amplified signal of the amplifying element Q2 is output as the WCDMA high-band RF transmission output signal Pout_WCDMA_HB via the output matching circuit OutMN.
  • the WCDMA low-band RF transmission input signal Pin_WCDMA_LB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is the inter-stage matching circuit.
  • the signal is supplied to the input electrode of the final stage amplifying element Q2 via the MN, and the amplified signal of the amplifying element Q2 is output as the WCDMA low band RF transmission output signal Pout_WCDMA_LB via the output matching circuit OutMN.
  • the bias control unit 300 is supplied with the automatic power control signal Vapc and a plurality of control input signals Cont, so that the bias control unit 300 performs each RF of the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200.
  • Input electrode bias voltage supplied to the input electrodes of a plurality of amplifier elements Q 1, Q 2, Q 3 of the power amplifier and a plurality of amplifications of each RF power amplifier of WCDMA high-band RF power amplifier 400 and WCDMA low-band RF power amplifier 500 An input electrode bias voltage supplied to the input electrodes of the elements Q1 and Q2 is generated.
  • the plurality of amplifying elements Q1, Q2, Q3 of the GSM RF power amplifiers 100, 200 and the plurality of amplifying elements Q1, Q2 of the WCDMA RF power amplifiers 400, 500 are the LDMOSFETs described with reference to FIGS.
  • FIG. 24 is a diagram showing the configuration of the semiconductor chip 1 of the semiconductor integrated circuit and the configuration of the RF power amplifier module PA_MD according to the third embodiment of the present invention.
  • the GSM high band RF power amplifier 100 and the GSM low band RF power amplifier 200 are the same as those of the rectangular semiconductor chip 1. They are arranged on the upper long side and the lower long side, respectively. That is, the plurality of amplifying elements Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1. A plurality of amplifying elements Q 1, Q 2, Q 3 of the GSM low-band RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
  • the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 each constituted by a two-stage amplifier are used.
  • the rectangular semiconductor chip 1 is disposed on the left short side and the right short side, respectively.
  • the plurality of amplifying elements Q1 and Q2 of the WCDMA high band RF power amplifier 400 are arranged on the short left side of the rectangular semiconductor chip 1 in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1,
  • the plurality of amplifying elements Q1 and Q2 of the WCDMA low-band RF power amplifier 500 are arranged on the short right side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 on the upper long side of the semiconductor chip 1 has an extending direction of the long side of the gate electrode or the emitter region in the Y direction of the semiconductor chip 1.
  • the direction of the AA ′ line, which is the direction, is selected, while the unit transistor repeated enlargement for realizing a large element size is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1.
  • the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 on the lower long side of the semiconductor chip 1 has a longer side extending in the Y direction of the semiconductor chip 1 in the gate electrode or emitter region. Is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size.
  • the final stage amplifying element Q2 which has a large element size of the WCDMA high-band RF power amplifier 400 on the left short side of the semiconductor chip 1, has an extension direction of the long side of the gate electrode or emitter region of the semiconductor chip 1. While selected in the direction of the AA ′ line which is the Y direction, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1. ing.
  • the final stage amplifying element Q2 having a large element size of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1 has an extending direction of the long side of the gate electrode or the emitter region in the Y direction of the semiconductor chip 1. While the direction of the AA ′ line that is the direction is selected, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Yes.
  • the amplified output signal of the final stage amplifying element Q3 of the GSM high band RF power amplifier 100 is the same as that of the rectangular semiconductor chip 1.
  • the amplified output signal of the final stage amplifying element Q3 of the GSM low-band RF power amplifier 200 is derived from the lower long side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1
  • the amplified output signal of the final stage amplifying element Q2 of the WCDMAM high-band RF power amplifier 400 is derived from the short left side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1, and is amplified by the final stage of the WCDMAM low-band RF power amplifier 500.
  • the amplified output signal of the element Q2 is output from the right side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1.
  • the GSM high band RF power amplifier 100 is formed on the upper portion of the wiring board.
  • the output matching circuit 100_OutMN is arranged, the output matching circuit 200_OutMN of the GSM low-band RF power amplifier 200 is arranged in the lower part of the wiring board, and the output matching of the WCDMA high-band RF power amplifier 400 is arranged in the left part of the wiring board.
  • the output matching circuit 500_OutMN of the WCDMA low-band RF power amplifier 500 can be arranged at the right part of the wiring board.
  • the output signal of the final stage amplifying element is derived from the right short side and the left short side of the rectangular semiconductor chip 1, so that the rectangular Since the semiconductor chip 1 does not become long in the direction of the BB ′ line which is the X direction of the semiconductor chip 1, the chip size of the semiconductor chip 1 can be reduced. Further, since the RF signal output wiring of the wiring board of the RF power amplifier module PA_MD is also distributed in the upper part, the lower part, the right short side, and the left short side of the wiring board, there are less restrictions on the wiring layout and the wiring board. It is possible to reduce the area and cost.
  • an amplifying element integrated on a semiconductor chip of the semiconductor integrated circuit of the present invention an amplifying element other than an LDMOSFET, a planar bipolar transistor, a mesa type heterobipolar transistor, such as a MESFET, HEMT, or SiGe heterobipolar transistor is used. It is possible to use.

Abstract

The purpose of the present invention is to eliminate a placement direction restriction for amplifier elements on a semiconductor chip surface. A first final-stage amplifier element (Q3) of a first RF power amplifier (100) is formed on the surface of a semiconductor chip and along a first edge thereof, and a second final-stage amplifier element (Q2) of a second RF power amplifier (500) is formed along a second edge perpendicular to the first edge. The first and second final-stage elements (Q3 and Q2) are configured from multiple unit transistors. The multiple unit transistors contain active regions (G) having rectangular planar geometry. The extension direction of the longer edges of multiple rectangles in multiple unit transistors of the first and second final-stage elements (Q3 and Q2) is set in the length direction of the second edge. The direction of iterative enlargement for multiple unit transistors in the first final-stage element (Q3) is set in the length direction of the first edge, and the direction of iterative enlargement for multiple unit transistors in the second final-stage element (Q2) is set in the length direction of the second edge.

Description

半導体集積回路およびそれを搭載したモジュールSemiconductor integrated circuit and module equipped with the same
　本発明は、半導体集積回路およびそれを搭載したモジュールに関し、特に増幅素子の半導体チップ表面での配置方向の制約を解消するのに有効な技術に関するものである。 The present invention relates to a semiconductor integrated circuit and a module on which the semiconductor integrated circuit is mounted, and particularly relates to a technique effective in eliminating the restriction on the arrangement direction of an amplification element on a semiconductor chip surface.
　近年、ＧＳＭ（登録商標）方式、ＧＰＲＳ方式、ＥＤＧＥ方式、ＷＣＤＭＡ方式に代表される移動体通信機器が、世界的に普及している。移動体通信は、基地局と移動体通信端末の間の無線周波数(ＲＦ)信号の送受信によって実現される。移動体通信端末はバッテリーで動作して、移動体通信端末から基地局へのＲＦ送信信号の送信は移動体通信端末に搭載されるＲＦ電力増幅器によって実行される。バッテリーで動作する移動体通信端末で長時間の通話時間を可能とするためには、ＲＦ電力増幅器の電力効率を改善することが必要となる。尚、ＧＳＭは、Global System for Mobile Communicationの略である。また、ＧＰＲＳは、General Packet Radio Serviceの略である。更に、ＥＤＧＥは、Enhanced Data for GSM Evolution; Enhanced Data for GPRSの略である。また、ＷＣＤＭＡは、Wideband Code Division Multiple Accessの略である。 In recent years, mobile communication devices represented by the GSM (registered trademark) system, the GPRS system, the EDGE system, and the WCDMA system have spread worldwide. Mobile communication is realized by transmitting and receiving radio frequency (RF) signals between a base station and a mobile communication terminal. The mobile communication terminal operates on a battery, and transmission of an RF transmission signal from the mobile communication terminal to the base station is performed by an RF power amplifier mounted on the mobile communication terminal. In order to enable a long talk time in a mobile communication terminal operating on a battery, it is necessary to improve the power efficiency of the RF power amplifier. GSM is an abbreviation for Global System for Mobile Communication. GPRS is an abbreviation for General Packet Radio Service. Further, EDGE is an abbreviation for Enhanced Data for GSM Evolution; Enhanced Data for GPRS. WCDMA is an abbreviation for Wideband, Code, Division, Multiple, Access.
　一方、移動体通信端末に搭載されるＲＦ電力増幅器には小型化の要求が強くなっており、ＲＦ電力増幅器に内蔵される半導体集積回路のチップ面積の縮小と半導体集積回路に集積化されるＲＦ電力増幅素子の性能向上が求められている。 On the other hand, there is an increasing demand for miniaturization of an RF power amplifier mounted on a mobile communication terminal, and a reduction in the chip area of a semiconductor integrated circuit incorporated in the RF power amplifier and an RF integrated in the semiconductor integrated circuit. There is a demand for improved performance of power amplification elements.
　下記特許文献１には、ＲＦ電力増幅器に内蔵される半導体集積回路に集積化されるＬＤＭＯＳＦＥＴ(Laterally Diffused Metal-Oxide-Semiconductor Filed Effect Transistor)と呼ばれるＲＦ電力増幅素子が記載されている。ＬＤＭＯＳＦＥＴのＲＦ電力増幅素子の平面構造としては、長方形に形成された２本のゲート電極の間の中央部分に長方形に形成された１本のドレイン領域が形成されて、２本のゲート電極よりも外側の外部部分に長方形に形成された２本のソース領域が形成される。また、ＬＤＭＯＳＦＥＴのＲＦ電力増幅素子の断面構造としては、ソース領域と単結晶シリコン基板の裏面に形成されたソース裏面電極とは、不純物を高濃度でドープした低抵抗のｐ型多結晶シリコン膜または低抵抗の金属膜で形成した打ち抜き層によって電気的に接続され、ドレイン領域には多層配線のドレイン配線が形成され、ドレイン配線の多層配線よりも配線層の少ないソース配線によって複数のソース領域が相互に電気的に接続される。 Patent Document 1 below describes an RF power amplification element called LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Filed Effect Transistor) integrated in a semiconductor integrated circuit built in an RF power amplifier. As a planar structure of the RF power amplifying element of the LDMOSFET, one drain region formed in a rectangle is formed in the central portion between two gate electrodes formed in a rectangle. Two source regions formed in a rectangular shape are formed in the outer part on the outside. Further, as a cross-sectional structure of the RF power amplifying element of the LDMOSFET, the source region and the source back electrode formed on the back surface of the single crystal silicon substrate are a low-resistance p-type polysilicon film doped with impurities at a high concentration or It is electrically connected by a punching layer formed of a low-resistance metal film. A drain wiring of a multilayer wiring is formed in the drain region, and a plurality of source regions are connected to each other by a source wiring having a wiring layer smaller than the multilayer wiring of the drain wiring. Is electrically connected.
特開２００７－１７３３１４号　公報JP 2007-173314 A
　本発明者等は本発明に先立ち、マルチモード・マルチバンドの送信が可能なＲＦ電力増幅器に内蔵される半導体集積回路の開発に従事した。マルチモードはＧＳＭ方式やＷＣＤＭＡ方式等の複数の通信方式による通信をサポートするものであり、マルチバンドは例えばＧＳＭローバンドとＧＳＭハイバンドとＷＣＤＭＡローバンドとＷＣＤＭＡハイバンド等の複数の周波数バンドの送信をサポートするものである。すなわち、ＧＳＭローバンドはＧＳＭ８５０(８２４～８４９ＭＨｚ)とＧＳＭ９００(８８０～９１５ＭＨｚ)との２つの周波数バンドを含み、ＧＳＭハイバンドはＤＣＳ１８００(１７１０～１７８５ＭＨｚ)とＰＣＳ１９００(１８５０～１９１０ＭＨｚ)との２つの周波数バンドを含んでいる。尚、ＤＣＳはDigital Cellar Systemの略称、ＰＣＳはPersonal Communication Systemの略称である。また更にＷＣＤＭＡローバンドはバンド５(８２４～８４９ＭＨｚ)とバンド８(８８０～９１５ＭＨｚ)とを含み、ＷＣＤＭＡハイバンドはバンド１(１９２０～１９８０ＭＨｚ)とバンド２(１８５０～１９１０ＭＨｚ)とバンド４(１７１０～１７５５ＭＨｚ)とを含んでいる。 Prior to the present invention, the present inventors engaged in the development of a semiconductor integrated circuit built in an RF power amplifier capable of multimode / multiband transmission. Multimode supports communication using multiple communication systems such as GSM and WCDMA, and multiband supports transmission of multiple frequency bands such as GSM low band, GSM high band, WCDMA low band, and WCDMA high band. To do. That is, the GSM low band includes two frequency bands of GSM850 (824 to 849 MHz) and GSM900 (880 to 915 MHz), and the GSM high band includes two frequency bands of DCS1800 (1710 to 1785 MHz) and PCS1900 (1850 to 1910 MHz). Is included. DCS is an abbreviation for Digital Cellar System, and PCS is an abbreviation for Personal Communication System. Further, the WCDMA low band includes band 5 (824 to 849 MHz) and band 8 (880 to 915 MHz), and the WCDMA high band includes band 1 (1920 to 1980 MHz), band 2 (1850 to 1910 MHz), and band 4 (1710 to 1755 MHz). ).
　図１は、本発明に先立って本発明者等によって検討されたＬＤＭＯＳＦＥＴと呼ばれるＲＦ電力増幅素子の平面構造を示す図である。 FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention.
　図１に示したように、２本のゲート電極Ｇの間の中央部分に長方形に形成された１本のドレインＤ領域が形成されて、２本のゲート電極Ｇよりも外側の外部部分には長方形に形成された２本のソース領域Ｓが形成される。２本のゲート電極Ｇの各ゲート電極の上部と下部とには、複数のＬＤＭＯＳＦＥＴのゲート電極を共通接続するゲート配線と接続するためのコンタクト７が形成される。２本のソース領域Ｓの各ソース領域には、複数の打ち抜き層４が形成される。 As shown in FIG. 1, one drain D region formed in a rectangular shape is formed in the central portion between the two gate electrodes G, and an outer portion outside the two gate electrodes G is formed in the outer portion. Two source regions S formed in a rectangular shape are formed. A contact 7 for connecting to the gate wiring for commonly connecting the gate electrodes of the plurality of LDMOSFETs is formed on the upper and lower portions of each gate electrode of the two gate electrodes G. In each source region of the two source regions S, a plurality of punched layers 4 are formed.
　図２は、本発明に先立って本発明者等によって検討されたＬＤＭＯＳＦＥＴと呼ばれるＲＦ電力増幅素子の断面構造を示す図である。 FIG. 2 is a diagram showing a cross-sectional structure of an RF power amplifying element called LDMOSFET, which was studied by the present inventors prior to the present invention.
　図２において、１は半導体チップ(Ｐ型単結晶シリコン基板)で、２はＰ型単結晶シリコンエピタキシャル層、３は溝で、４は打ち抜き層で、５はＰ型ウェル領域で、６はゲート絶縁膜で、７はゲート電極で、８はキャップ絶縁膜で、９はＮ－型オフセットドレイン領域で、１０はＮ－型ソース領域で、１１はＰ型ハロー領域で、１２はサイドウォールスペーサで、１３はＮ型オフセットドレイン領域で、１５はＮ＋型ドレイン領域で、１６はＮ＋型ソース領域で、１７はＰ＋型半導体領域である。 In FIG. 2, 1 is a semiconductor chip (P-type single crystal silicon substrate), 2 is a P-type single crystal silicon epitaxial layer, 3 is a groove, 4 is a punched layer, 5 is a P-type well region, and 6 is a gate. Insulating film, 7 is a gate electrode, 8 is a cap insulating film, 9 is an N − type offset drain region, 10 is an N − type source region, 11 is a P type halo region, and 12 is a sidewall spacer. , 13 are N-type offset drain regions, 15 is an N + -type drain region, 16 is an N + -type source region, and 17 is a P + -type semiconductor region.
　図２に示したように、Ｐ型単結晶シリコン基板１の上部には、Ｐ型単結晶シリコンエピタキシャル層２が形成される。２本のゲート電極Ｇの間の中央部分には、Ｎ型オフセットドレイン領域１３とＮ＋型ドレイン領域１５とを含むドレイン領域Ｄが形成されている。２本のゲート電極Ｇよりも外側の外部部分には、Ｎ－型ソース領域１０とＰ型ハロー領域１１とＮ＋型ソース領域１６とを含むソース領域Ｓが形成されている。尚、Ｐ型ハロー領域１１を形成することによって、ソース領域からゲート電極Ｇの直下のチャネル形成領域への不純物の拡散が抑制され、更に短チャネル効果が抑制されて、しきい値電圧の低下も抑制されるものである。ゲート電極Ｇの直下のチャネル形成領域とＮ－型ソース領域１０とＰ型ハロー領域１１とＮ＋型ソース領域１６の下部には、Ｐ型ウェル領域５が形成される。複数のＬＤＭＯＳＦＥＴの複数のＮ＋型ソース領域１６はＰ＋型半導体領域１７によって相互に電気的に短絡される。Ｐ型ウェル領域５とＰ型単結晶シリコンエピタキシャル層２とを貫通してＰ型単結晶シリコン基板１の上部表面に到達するように溝３が形成され、溝３の内部にはＰ型多結晶シリコン膜または低抵抗の金属膜で形成した打ち抜き層４が形成される。従って、複数のＬＤＭＯＳＦＥＴのＮ＋型ソース領域１６は、Ｐ＋型半導体領域１７と打ち抜き層４とＰ型単結晶シリコン基板１とを介して、ソース裏面電極３６に電気的に接続される。ソース裏面電極３６はＲＦ電力増幅器モジュールの接地配線に接続され、この接地配線は移動体通信端末のマザーボートの接地配線に接続される。その結果、ＲＦ電力増幅器に内蔵される半導体集積回路に集積化される複数のＬＤＭＯＳＦＥＴは、極めて安定なソース接地増幅動作を実行することが可能となる。 As shown in FIG. 2, a P-type single crystal silicon epitaxial layer 2 is formed on the P-type single crystal silicon substrate 1. In the central portion between the two gate electrodes G, a drain region D including an N-type offset drain region 13 and an N + -type drain region 15 is formed. A source region S including an N − -type source region 10, a P-type halo region 11, and an N + -type source region 16 is formed in an external portion outside the two gate electrodes G. By forming the P-type halo region 11, the diffusion of impurities from the source region to the channel formation region immediately below the gate electrode G is suppressed, the short channel effect is further suppressed, and the threshold voltage is also reduced. It is suppressed. A P-type well region 5 is formed under the channel formation region, the N − -type source region 10, the P-type halo region 11, and the N + -type source region 16 immediately below the gate electrode G. The plurality of N + type source regions 16 of the plurality of LDMOSFETs are electrically short-circuited to each other by the P + type semiconductor region 17. A groove 3 is formed so as to penetrate the P-type well region 5 and the P-type single crystal silicon epitaxial layer 2 and reach the upper surface of the P-type single crystal silicon substrate 1. A punching layer 4 made of a silicon film or a low resistance metal film is formed. Therefore, the N + type source regions 16 of the plurality of LDMOSFETs are electrically connected to the source back electrode 36 via the P + type semiconductor region 17, the punching layer 4, and the P type single crystal silicon substrate 1. The source back electrode 36 is connected to the ground wiring of the RF power amplifier module, and this ground wiring is connected to the ground wiring of the mother board of the mobile communication terminal. As a result, the plurality of LDMOSFETs integrated in the semiconductor integrated circuit incorporated in the RF power amplifier can perform an extremely stable source ground amplification operation.
　図３は、本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールＰＡ＿ＭＤの構成を示す図である。 FIG. 3 is a diagram showing a configuration of the RF power amplifier module PA_MD studied by the present inventors prior to the present invention.
　図３に示したように、ＲＦ電力増幅器モジュールＰＡ＿ＭＤは、ハイバンドＲＦ電力増幅器１００とローバンドＲＦ電力増幅器２００とバイアス制御部３００とを含んでいる。ハイバンドＲＦ電力増幅器１００とローバンドＲＦ電力増幅器２００の各ＲＦ電力増幅器は、初段増幅素子としてのＬＤＭＯＳＦＥＴＱ１と２段目の増幅素子としてのＬＤＭＯＳＦＥＴＱ２と最終段増幅素子としてのＬＤＭＯＳＦＥＴＱ３とを含んでいる。各ＲＦ電力増幅器では、複数のＬＤＭＯＳＦＥＴＱ１～Ｑ３のソースは接地電圧ＧＮＤに接続され、複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３のドレインに負荷インダクタＬ１、Ｌ２、Ｌ３を介して電源電圧Ｖｄｄが供給される。 As shown in FIG. 3, the RF power amplifier module PA_MD includes a high band RF power amplifier 100, a low band RF power amplifier 200, and a bias control unit 300. Each of the RF power amplifiers of the high-band RF power amplifier 100 and the low-band RF power amplifier 200 includes an LDMOSFET Q1 as a first stage amplifying element, an LDMOSFET Q2 as a second stage amplifying element, and an LDMOSFET Q3 as a last stage amplifying element. In each RF power amplifier, the sources of the plurality of LDMOSFETs Q1 to Q3 are connected to the ground voltage GND, and the power supply voltage Vdd is supplied to the drains of the plurality of LDMOSFETs Q1, Q2, and Q3 via the load inductors L1, L2, and L3.
　ハイバンドＲＦ電力増幅器１００では、ハイバンドＲＦ送信入力信号Ｐｉｎ＿ＨＢが入力整合回路ＩｎＭＮを介して初段の増幅素子のＦＥＴＱ１のゲートに供給され、ＦＥＴＱ１のドレインの増幅信号は段間整合回路ＭＮを介して２段目の増幅素子のＦＥＴＱ２のゲートに供給され、ＦＥＴＱ２の増幅信号は段間整合回路ＭＮを介して最終段増幅素子のＦＥＴＱ３のゲートに供給され、ＦＥＴＱ３の増幅信号は出力整合回路ＯｕｔＭＮを介してハイバンドＲＦ送信出力信号Ｐｏｕｔ＿ＨＢとして出力される。 In the high-band RF power amplifier 100, the high-band RF transmission input signal Pin_HB is supplied to the gate of the FET Q1 of the first stage amplifying element via the input matching circuit InMN, and the amplified signal of the drain of the FET Q1 is passed through the inter-stage matching circuit MN. The amplified signal of the FET Q2 is supplied to the gate of the FET Q3 of the final stage amplification element via the interstage matching circuit MN, and the amplified signal of the FET Q3 is supplied to the gate of the FET Q2 of the second stage amplification element via the output matching circuit OutMN. And output as a high-band RF transmission output signal Pout_HB.
　ローバンドＲＦ電力増幅器２００では、ローバンドＲＦ送信入力信号Ｐｉｎ＿ＬＢが入力整合回路ＩｎＭＮを介して初段の増幅素子のＦＥＴＱ１のゲートに供給され、ＦＥＴＱ１のドレインの増幅信号は段間整合回路ＭＮを介して２段目の増幅素子のＦＥＴＱ２のゲートに供給され、ＦＥＴＱ２の増幅信号は段間整合回路ＭＮを介して最終段増幅素子のＦＥＴＱ３のゲートに供給され、ＦＥＴＱ３の増幅信号は出力整合回路ＯｕｔＭＮを介してローバンドＲＦ送信出力信号Ｐｏｕｔ＿ＬＢとして出力される。 In the low-band RF power amplifier 200, the low-band RF transmission input signal Pin_LB is supplied to the gate of the FET Q1 of the first stage amplification element through the input matching circuit InMN, and the amplified signal at the drain of the FET Q1 is two-staged through the interstage matching circuit MN. The amplified signal of the FET Q2 is supplied to the gate of the FET Q3 of the final stage amplification element through the interstage matching circuit MN, and the amplified signal of the FET Q3 is supplied to the low band through the output matching circuit OutMN. An RF transmission output signal Pout_LB is output.
　バイアス制御部３００には自動電力制御信号Ｖａｐｃと複数の制御入力信号Ｃｏｎｔが供給されることによって、バイアス制御部３００はハイバンドＲＦ電力増幅器１００とローバンドＲＦ電力増幅器２００との各ＲＦ電力増幅器の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３のゲートに供給されるゲートバイアス電圧を生成する。 The bias control unit 300 is supplied with the automatic power control signal Vapc and a plurality of control input signals Cont, so that the bias control unit 300 includes a plurality of RF power amplifiers of the high-band RF power amplifier 100 and the low-band RF power amplifier 200. The gate bias voltage supplied to the gates of the LDMOSFETs Q1, Q2, and Q3 is generated.
　図４は、本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールに内蔵される半導体集積回路の構成を示す図である。 FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit built in the RF power amplifier module studied by the present inventors prior to the present invention.
　図４に示したようにＲＦ電力増幅器モジュールに内蔵される半導体集積回路の半導体チップ１には、ハイバンドＲＦ電力増幅器１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３とローバンドＲＦ電力増幅器２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３とバイアス制御部３００とが集積化されている。 As shown in FIG. 4, the semiconductor chip 1 of the semiconductor integrated circuit built in the RF power amplifier module includes a plurality of LDMOSFETs Q1, Q2, Q3 of the high-band RF power amplifier 100 and a plurality of LDMOSFETs Q1, of the low-band RF power amplifier 200. Q2 and Q3 and the bias control unit 300 are integrated.
　特に図４に示したように、ハイバンドＲＦ電力増幅器１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３の各ＦＥＴの２本のゲート電極の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一されている。またローバンドＲＦ電力増幅器２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３の各ＦＥＴの２本のゲート電極の長方形の長辺の延長方向も、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一されている。 In particular, as shown in FIG. 4, the extending direction of the long sides of the rectangles of the two gate electrodes of each of the plurality of LDMOSFETs Q1, Q2, and Q3 of the high-band RF power amplifier 100 is the Y direction of the semiconductor chip 1. The direction of the line AA ′ is unified. In addition, the extension direction of the long side of the two gate electrodes of the plurality of LDMOSFETs Q1, Q2, and Q3 of the low-band RF power amplifier 200 is also unified to the direction of the AA ′ line that is the Y direction of the semiconductor chip 1 Has been.
　この理由は、ＬＤＭＯＳＦＥＴの増幅ゲインであるコンダクタンスが長方形の長辺であるゲート幅Ｗと長方形の短辺であるゲート長Ｌの比Ｗ／Ｌによって決定され、半導体チップ１の製造工程でのゲート電極形成のホトリソグラフィーで半導体チップ１のＸ方向とＹ方向とでそれぞれ異なった寸法偏差を持つためである。従って、１つのＬＤＭＯＳＦＥＴのゲート電極の長方形の長辺の延長方向を半導体チップ１のＹ方向であるＡ－Ａ´線とする一方、他の１つのＬＤＭＯＳＦＥＴのゲート電極の長方形の長辺の延長方向を半導体チップ１のＸ方向であるＢ－Ｂ´線としたとする。半導体チップ１の製造工程でのバラツキにより半導体チップ１のＸ方向の寸法が設計値よりも増加したとすると、１つのＬＤＭＯＳＦＥＴのゲート長Ｌが増加する一方、他の１つのＬＤＭＯＳＦＥＴのゲート幅Ｗが増加する。その結果、１つのＬＤＭＯＳＦＥＴの増幅ゲインのコンダクタンスが低下する一方、他の１つのＬＤＭＯＳＦＥＴの増幅ゲインのコンダクタンスが増加する。この理由によって、半導体チップ１に集積化される全てのＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３の各ＦＥＴのゲート電極の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一される。 This is because the conductance, which is the amplification gain of the LDMOSFET, is determined by the ratio W / L of the gate width W, which is the long side of the rectangle, and the gate length L, which is the short side of the rectangle, and the gate electrode in the manufacturing process of the semiconductor chip 1 This is because the formed photolithography has different dimensional deviations in the X direction and the Y direction of the semiconductor chip 1. Therefore, the extending direction of the long side of the rectangular electrode of one LDMOSFET is the AA ′ line which is the Y direction of the semiconductor chip 1, while the extending direction of the long side of the rectangular electrode of the gate electrode of the other LDMOSFET. Is a BB ′ line in the X direction of the semiconductor chip 1. If the dimension in the X direction of the semiconductor chip 1 has increased from the design value due to variations in the manufacturing process of the semiconductor chip 1, the gate length L of one LDMOSFET increases, while the gate width W of the other LDMOSFET increases. To increase. As a result, the conductance of the amplification gain of one LDMOSFET decreases, while the conductance of the amplification gain of the other LDMOSFET increases. For this reason, the extension direction of the long side of the rectangular gate electrode of each of the LDMOSFETs Q1, Q2, Q3 integrated in the semiconductor chip 1 is the direction of the AA ′ line which is the Y direction of the semiconductor chip 1 To be unified.
　一方、ハイバンドＲＦ電力増幅器１００とローバンドＲＦ電力増幅器２００の各ＲＦ電力増幅器で、初段増幅素子Ｑ１は比較的小さなＲＦ出力を発生して、２段目の増幅素子Ｑ２は中間のＲＦ出力を発生して、最終段増幅素子Ｑ３は比較的大きなＲＦ出力を発生する。すなわち、各ＲＦ電力増幅器では、初段の比較的小さなＲＦ出力の増幅で高い電力効率を実現するために、初段増幅素子Ｑ１は小さな素子サイズとされる。また、各ＲＦ電力増幅器では、２段目の中間のＲＦ出力の増幅で高い電力効率を実現するために、２段目の増幅素子Ｑ２は中間の素子サイズとされる。更に、各ＲＦ電力増幅器では、最終段の比較的大きなＲＦ出力の増幅で高い電力効率を実現するために、最終段増幅素子Ｑ３は比較的大きな素子サイズとされる。 On the other hand, in each of the RF power amplifiers of the high-band RF power amplifier 100 and the low-band RF power amplifier 200, the first stage amplifier element Q1 generates a relatively small RF output, and the second stage amplifier element Q2 generates an intermediate RF output. Thus, the final stage amplifying element Q3 generates a relatively large RF output. That is, in each RF power amplifier, in order to realize high power efficiency by amplifying a relatively small RF output in the first stage, the first stage amplifying element Q1 has a small element size. Further, in each RF power amplifier, in order to realize high power efficiency by amplification of the intermediate RF output at the second stage, the amplification element Q2 at the second stage has an intermediate element size. Further, in each RF power amplifier, in order to realize high power efficiency by amplification of a relatively large RF output at the final stage, the final stage amplifying element Q3 has a relatively large element size.
　このような理由によって図４に示した本発明に先立って本発明者等によって検討された半導体集積回路で、ハイバンドＲＦ電力増幅器１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３は長方形の半導体チップ１の上部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されて、ローバンドＲＦ電力増幅器２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３は長方形の半導体チップ１の下部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置される。その結果、長方形の半導体チップ１の右部短辺と左部短辺には、ＲＦ電力増幅器のＬＤＭＯＳＦＥＴは配置されず、バイアス制御部３００の複数の入力端子のパッドのみ配置されるものであった。 For this reason, the plurality of LDMOSFETs Q1, Q2, and Q3 of the high-band RF power amplifier 100 are formed on the rectangular semiconductor chip 1 in the semiconductor integrated circuit studied by the inventors prior to the present invention shown in FIG. A plurality of LDMOSFETs Q1, Q2, and Q3 of the low-band RF power amplifier 200 are arranged on the long side of the semiconductor chip 1 on the lower long side of the rectangular semiconductor chip 1 and arranged in the direction of the BB ′ line that is the X direction of the semiconductor chip 1 It is arranged in the direction of the BB ′ line, which is the X direction. As a result, the LDMOSFET of the RF power amplifier is not arranged on the right short side and the left short side of the rectangular semiconductor chip 1, but only the pads of the plurality of input terminals of the bias control unit 300 are arranged. .
　図５は、本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールに内蔵される他の半導体集積回路の構成を示す図である。 FIG. 5 is a diagram showing the configuration of another semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention.
　図５に示すようにＲＦ電力増幅器モジュールに内蔵される半導体集積回路の半導体チップ１には、ＧＳＭ方式ハイバンドＲＦ電力増幅器(ＧＳＭ＿ＨＢ)１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３とＧＳＭ方式ローバンドＲＦ電力増幅器(ＧＳＭ＿ＬＢ)２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３と、更にＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＨＢ)４００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＬＢ)５００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２とバイアス制御部３００とが集積化されている。 As shown in FIG. 5, the semiconductor chip 1 of the semiconductor integrated circuit built in the RF power amplifier module includes a plurality of LDMOSFETs Q1, Q2, and Q3 of a GSM type high band RF power amplifier (GSM_HB) 100 and a GSM type low band RF power amplifier. (GSM_LB) 200 LDMOSFETs Q1, Q2, Q3, WCDMA high band RF power amplifier (WCDMA_HB) 400 LDMOSFETs Q1, Q2 and WCDMA low band RF power amplifier (WCDMA_LB) 500 LDMOSFETs Q1, Q2 A bias controller 300 is integrated.
　図５に示した半導体集積回路の半導体チップ１においても、上述した理由によって半導体チップ１に集積化される全てのＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３の各ＦＥＴのゲート電極の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一される。その結果、ＧＳＭ方式ハイバンドＲＦ電力増幅器(ＧＳＭ＿ＨＢ)１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＨＢ)４００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２とは長方形の半導体チップ１の上部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されて、ＧＳＭ方式ローバンドＲＦ電力増幅器(ＧＳＭ＿ＬＢ)２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＬＢ)５００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２とは長方形の半導体チップ１の下部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置される。その結果、長方形の半導体チップ１の右部短辺と左部短辺には、ＲＦ電力増幅器のＬＤＭＯＳＦＥＴは配置されずに、バイアス制御部３００の複数の入力端子のパッドのみ配置されるものであった。 Also in the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 5, the extending direction of the long sides of the rectangular gate electrodes of all the FETs Q1, Q2, and Q3 integrated on the semiconductor chip 1 for the reasons described above is The direction of the semiconductor chip 1 is unified in the direction of the AA ′ line which is the Y direction. As a result, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier (GSM_HB) 100 and the plurality of LDMOSFETs Q1 and Q2 of the WCDMA high band RF power amplifier (WCDMA_HB) 400 are the upper length of the rectangular semiconductor chip 1. A plurality of LDMOSFETs Q1, Q2, and Q3 of a GSM low-band RF power amplifier (GSM_LB) 200 and a WCDMA low-band RF power amplifier (WCDMA_LB) that are arranged on the side in the direction of the BB ′ line that is the X direction of the semiconductor chip 1 The plurality of 500 LDMOSFETs Q1 and Q2 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line which is the X direction of the semiconductor chip 1. As a result, the right short side and the left short side of the rectangular semiconductor chip 1 are not provided with the LDMOSFET of the RF power amplifier, but only the pads of the plurality of input terminals of the bias control unit 300 are provided. It was.
　特にＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅素子Ｑ３のドレイン出力信号とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の最終段増幅素子Ｑ２のドレイン出力信号は、長方形の半導体チップ１の上部長辺から半導体チップ１の外部の出力整合回路ＯｕｔＭＮに導出されなければならない。全く同様にしてＧＳＭ方式ローバンドＲＦ電力増幅器２００の最終段増幅素子Ｑ３のドレイン出力信号とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅素子Ｑ２のドレイン出力信号は、長方形の半導体チップ１の下部長辺から半導体チップ１の外部の出力整合回路ＯｕｔＭＮに導出されなければならない。 In particular, the drain output signal of the last stage amplifying element Q3 of the GSM high-band RF power amplifier 100 and the drain output signal of the last stage amplifying element Q2 of the WCDMA high-band RF power amplifier 400 are from the upper long side of the rectangular semiconductor chip 1. It must be derived to the output matching circuit OutMN outside the semiconductor chip 1. Exactly in the same way, the drain output signal of the last stage amplifying element Q3 of the GSM low band RF power amplifier 200 and the drain output signal of the last stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 are the lower long side of the rectangular semiconductor chip 1. To the output matching circuit OutMN outside the semiconductor chip 1.
　図６は、図５に示した半導体集積回路を内蔵する本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールの構成を示す図である。 FIG. 6 is a diagram showing a configuration of an RF power amplifier module studied by the present inventors prior to the present invention incorporating the semiconductor integrated circuit shown in FIG.
　図６に示すように、ＲＦ電力増幅器モジュールの配線基板４２の中央部分には、図５に示したＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とバイアス制御部３００とＧＳＭ方式ローバンドＲＦ電力増幅器２００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００を内蔵した半導体集積回路の半導体チップ１が搭載される。しかし、ＲＦ電力増幅器１００の最終段増幅素子Ｑ３のドレイン出力信号とＲＦ電力増幅器４００の最終段増幅素子Ｑ２のドレイン出力信号は、長方形の半導体チップ１の上部長辺から半導体チップ１の外部ＲＦ電力増幅器モジュールの配線基板４２の上部部分の出力整合回路の受動部品４４に供給される必要がある。更に、ＲＦ電力増幅器２００の最終段増幅素子Ｑ３のドレイン出力信号とＲＦ電力増幅器５００の最終段増幅素子Ｑ２のドレイン出力信号とは、長方形の半導体チップ１の下部長辺から半導体チップ１の外部ＲＦ電力増幅器モジュールの配線基板４２の下部部分の出力整合回路の受動部品４４に供給される必要がある。このように、長方形の半導体チップ１の右部短辺と左部短辺からは最終段増幅素子のドレイン出力信号が導出されないので、ＲＦ電力増幅器モジュールの配線基板４２の右側部分と左側部分にはバイアス制御部３００の複数の入力端子のパッドと接続される配線４３のみ配置されるものであった。 As shown in FIG. 6, the GSM high band RF power amplifier 100, the WCDMA high band RF power amplifier 400, the bias controller 300, and the GSM shown in FIG. A semiconductor chip 1 of a semiconductor integrated circuit incorporating a system low-band RF power amplifier 200 and a WCDMA system low-band RF power amplifier 500 is mounted. However, the drain output signal of the final stage amplifying element Q3 of the RF power amplifier 100 and the drain output signal of the final stage amplifying element Q2 of the RF power amplifier 400 are the external RF power of the semiconductor chip 1 from the upper long side of the rectangular semiconductor chip 1. It is necessary to be supplied to the passive component 44 of the output matching circuit in the upper part of the wiring board 42 of the amplifier module. Further, the drain output signal of the final stage amplifying element Q3 of the RF power amplifier 200 and the drain output signal of the final stage amplifying element Q2 of the RF power amplifier 500 are from the lower long side of the rectangular semiconductor chip 1 to the external RF of the semiconductor chip 1. It is necessary to be supplied to the passive component 44 of the output matching circuit in the lower part of the wiring board 42 of the power amplifier module. As described above, since the drain output signal of the final stage amplifying element is not derived from the right short side and the left short side of the rectangular semiconductor chip 1, the right side portion and the left side portion of the wiring board 42 of the RF power amplifier module are not provided. Only the wiring 43 connected to the pads of the plurality of input terminals of the bias control unit 300 is arranged.
　図６から明らかなように、長方形の半導体チップ１の右部短辺と左部短辺から最終段増幅素子の出力信号が導出されないので、長方形の半導体チップ１が半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に長く大きくなるので、半導体チップ１のチップサイズが増大する。更に、このようにＸ方向に長い長方形の半導体チップ１を内蔵するＲＦ電力増幅器モジュールの配線基板４２のＲＦ信号出力配線も、配線基板４２の上部部分と下部部分にのみ集中するので、配線レイアウトに制約も多く、配線基板４２の面積とコストとが増大すると言う問題が本発明に先立った本発明者等による検討の結果、明らかとされた。 As apparent from FIG. 6, since the output signal of the final stage amplification element is not derived from the right short side and the left short side of the rectangular semiconductor chip 1, the rectangular semiconductor chip 1 is in the X direction of the semiconductor chip 1. Since the length increases in the direction of the line BB ′, the chip size of the semiconductor chip 1 increases. Further, since the RF signal output wiring of the wiring board 42 of the RF power amplifier module incorporating the rectangular semiconductor chip 1 long in the X direction is concentrated only on the upper part and the lower part of the wiring board 42, the wiring layout is reduced. As a result of studies by the present inventors prior to the present invention, the problem that the area and cost of the wiring board 42 are increased due to many restrictions has been clarified.
　本発明は、以上のような本発明に先立った本発明者等による検討の結果、なされたものである。 The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.
　従って、本発明の目的とするところは、増幅素子の半導体チップ表面での配置方向の制約を解消することにある。 Therefore, an object of the present invention is to eliminate restrictions on the arrangement direction of the amplifying element on the semiconductor chip surface.
　本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうちの代表的なものについて簡単に説明すれば下記のとおりである。 A typical one of the inventions disclosed in the present application will be briefly described as follows.
　すなわち、本発明の代表的な実施の形態は、第１ＲＦ電力増幅器(１００)と第２ＲＦ電力増幅器(５００)とを内蔵する半導体集積回路である。 That is, a typical embodiment of the present invention is a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500).
　前記半導体集積回路の半導体チップの第１辺と第２辺は、実質的に直角に交差する。 The first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at right angles.
　前記半導体チップの表面上に、前記第１辺に沿って前記第１ＲＦ電力増幅器(１００)の第１最終段増幅素子(Ｑ３)が形成され、前記第２辺に沿って前記第２ＲＦ電力増幅器(５００)の第２最終段増幅素子(Ｑ２)が形成される。 A first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier ( 500) of the second final stage amplification element (Q2).
　前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)の各増幅素子は、複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成される。 Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
　前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor, The planar shape of the active region is a rectangle.
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向と、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向とは、前記第２辺の長さ方向に選択される。 The extending direction of the long sides of the plurality of rectangular regions of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの反復拡大の方向は前記第１辺の長さ方向に選択され、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの反復拡大の方向は前記第２辺の長さ方向に選択されたことを特徴とする(図７、図８参照)。 The direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2) The direction of the repeated enlargement is selected in the length direction of the second side (see FIGS. 7 and 8).
　本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば下記の通りである。 The following is a brief description of the effects obtained by the representative inventions disclosed in the present application.
　すなわち、本発明によれば、増幅素子の半導体チップ表面での配置方向の制約を解消することができる。 That is, according to the present invention, it is possible to eliminate restrictions on the arrangement direction of the amplifying element on the semiconductor chip surface.
図１は、本発明に先立って本発明者等によって検討されたＬＤＭＯＳＦＥＴと呼ばれるＲＦ電力増幅素子の平面構造を示す図であり、また本発明の実施の形態１による半導体集積回路の半導体チップ１に集積化されるＬＤＭＯＳＦＥＴの平面構造を示す図である。FIG. 1 is a diagram showing a planar structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention. In addition, FIG. 1 shows a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. It is a figure which shows the planar structure of LDMOSFET integrated. 図２は、本発明に先立って本発明者等によって検討されたＬＤＭＯＳＦＥＴと呼ばれるＲＦ電力増幅素子の断面構造を示す図であり、また本発明の実施の形態１による半導体集積回路の半導体チップ１に集積化されるＬＤＭＯＳＦＥＴの断面構造を示す図である。FIG. 2 is a diagram showing a cross-sectional structure of an RF power amplifying element called LDMOSFET studied by the present inventors prior to the present invention, and is shown in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. It is a figure which shows the cross-section of LDMOSFET integrated. 図３は、本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールＰＡ＿ＭＤの構成を示す図であり、本発明の実施の形態１による半導体集積回路の半導体チップ１に集積化されるハイバンドＲＦ電力増幅器１００とローバンドＲＦ電力増幅器２００とバイアス制御部３００の構成を示す図である。FIG. 3 is a diagram showing a configuration of the RF power amplifier module PA_MD studied by the inventors prior to the present invention, and is integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a high band RF power amplifier 100, a low band RF power amplifier 200, and a bias control unit 300. 図４は、本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールに内蔵される半導体集積回路の構成を示す図である。FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention. 図５は、本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールに内蔵される他の半導体集積回路の構成を示す図である。FIG. 5 is a diagram showing the configuration of another semiconductor integrated circuit incorporated in the RF power amplifier module studied by the present inventors prior to the present invention. 図６は、図５に示した半導体集積回路を内蔵する本発明に先立って本発明者等によって検討されたＲＦ電力増幅器モジュールの構成を示す図である。FIG. 6 is a diagram showing a configuration of an RF power amplifier module studied by the present inventors prior to the present invention incorporating the semiconductor integrated circuit shown in FIG. 図７は、本発明の実施の形態１による半導体集積回路の半導体チップ１の構成を示す図である。FIG. 7 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. 図８は、図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１で、半導体チップ１の上部長辺に配置されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３と半導体チップ１の右部短辺に配置されるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２とが構成される様子を示す図である。FIG. 8 shows the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, which has a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1. FIG. 2 is a diagram showing a state in which a final stage amplification element Q3 and a large stage size final stage amplification element Q2 of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 are configured. 図９は、図８に示した本発明の実施の形態１によるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３が構成される具体的な様子を示す図である。FIG. 9 is a diagram showing a specific state in which the large-amplifier final stage amplification element Q3 of the GSM high-band RF power amplifier 100 according to the first embodiment of the present invention shown in FIG. 8 is configured. 図１０は、図９に示した本発明の実施の形態１によるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３の具体的な構成の主要部を示す図である。FIG. 10 is a diagram illustrating a main part of a specific configuration of the final-stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention illustrated in FIG. 図１１は、図８に示した本発明の実施の形態１によるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２が構成される具体的な様子を示す図である。FIG. 11 is a diagram illustrating a specific state in which the large-amplifier final stage amplification element Q2 of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention illustrated in FIG. 8 is configured. 図１２は、図１１に示した本発明の実施の形態１によるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２の具体的な構成の主要部を示す図である。FIG. 12 is a diagram showing a main part of a specific configuration of final-stage amplifying element Q2 having a large element size of WCDMA low-band RF power amplifier 500 according to Embodiment 1 of the present invention shown in FIG. 図１３は、図１２に示す本発明の実施の形態１によるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２のＬＤＭＯＳＦＥＴのゲート電極Ｇと第１ドレイン配線ＤＭ１が立体的に交差する部分において、接地電圧ＧＮＤに接続されるソース領域Ｓと電気的に接続されるソース配線が静電シールド層として機能する様子を示す断面図である。13 shows a three-dimensional intersection of the gate electrode G of the LDMOSFET of the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 12 and the first drain wiring DM1. FIG. 6 is a cross-sectional view showing a state where a source wiring electrically connected to a source region S connected to a ground voltage GND functions as an electrostatic shield layer in a portion to be operated. 図１４は、図９と図１０とに示した図７の半導体チップ１の上部長辺に配置されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３の特性と図１１と図１２とに示した図７の半導体チップ１の右部短辺に配置されるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２の特性とを比較した図である。14 shows the characteristics of the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 of FIG. 7 shown in FIG. 9 and FIG. 13 is a diagram comparing characteristics of a final stage amplifying element Q2 having a large element size of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 of FIG. 7 shown in FIG. 図１５は、本発明の実施の形態１による半導体集積回路の半導体チップ１の他の構成を示す図である。FIG. 15 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. 図１６は、本発明の実施の形態１による半導体集積回路の半導体チップ１の他の構成を示す図である。FIG. 16 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. 図１７は、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるプレーナ型バイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの平面構造と断面構造とを示す図である。FIG. 17 is a diagram showing a planar structure and a sectional structure of a unit transistor Unit_TRS of a planar bipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. 図１８は、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００のトランジスタＱ１、Ｑ２、Ｑ３とＧＳＭ方式ローバンドＲＦ電力増幅器２００のトランジスタＱ１、Ｑ２、Ｑ３の各ＲＦ電力増幅トランジスタの平面構造を示す図である。FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3. 図１９は、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるメサ型ヘテロバイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの平面構造と断面構造とを示す図である。FIG. 19 is a diagram showing a planar structure and a cross-sectional structure of a unit transistor Unit_TRS of a mesa type heterobipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. 図２０は、ＧａＡｓ化合物半導体基板の（１００）結晶面の上部に形成されるメサ型エミッタ領域のメサ型台形形状がメサ型エミッタ領域の長方形の長辺の延長方向の相違によって変化する様子を示す図である。FIG. 20 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region. FIG. 図２１は、ＧａＡｓ化合物半導体基板の（１００）結晶面の上部に形成されるメサ型エミッタ領域のメサ型台形形状がメサ型エミッタ領域の長方形の長辺の延長方向の相違によって変化する様子を示す図である。FIG. 21 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region. FIG. 図２２は、本発明の実施の形態２による半導体集積回路の半導体チップ１の構成を示す図である。FIG. 22 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. 図２３は、本発明の実施の形態３による半導体集積回路の半導体チップ１に集積化されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００とバイアス制御部３００とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００との構成を示す図である。FIG. 23 shows a GSM high-band RF power amplifier 100, a GSM low-band RF power amplifier 200, a bias controller 300, and a WCDMA high-band integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 2 is a diagram showing the configuration of an RF power amplifier 400 and a WCDMA low-band RF power amplifier 500. 図２４は、本発明の実施の形態３による半導体集積回路の半導体チップ１の構成とＲＦ電力増幅器モジュールＰＡ＿ＭＤの構成とを示す図である。FIG. 24 is a diagram showing the configuration of the semiconductor chip 1 of the semiconductor integrated circuit and the configuration of the RF power amplifier module PA_MD according to the third embodiment of the present invention.
１．実施の形態の概要
　まず、本願において開示される発明の代表的な実施の形態について概要を説明する。代表的な実施の形態についての概要説明で括弧を付して参照する図面の参照符号は、それが付された構成要素の概念に含まれるものを例示するに過ぎない。 1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.
　〔１〕本発明の代表的な実施の形態は、第１ＲＦ電力増幅器(１００)と第２ＲＦ電力増幅器(５００)とを内蔵する半導体集積回路である。 [1] A typical embodiment of the present invention is a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500).
　前記半導体集積回路の半導体チップの第１辺と第２辺とは、実質的に直角に交差するものである。 The first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at right angles.
　前記半導体チップの表面上には、前記第１辺に沿って前記第１ＲＦ電力増幅器(１００)の第１最終段増幅素子(Ｑ３)が形成され、前記第２辺に沿って前記第２ＲＦ電力増幅器(５００)の第２最終段増幅素子(Ｑ２)が形成される。 A first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier is formed along the second side. (500) second final stage amplifying elements (Q2) are formed.
　前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)の各増幅素子は、複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成される。 Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
　前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor, The planar shape of the active region is a rectangle.
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向と、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向とは、前記第２辺の長さ方向に選択される。 The extending direction of the long sides of the plurality of rectangular regions of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの反復拡大の方向は前記第１辺の長さ方向に選択され、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの反復拡大の方向は前記第２辺の長さ方向に選択されたことを特徴とするものである(図７、図８参照)。 The direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2) The direction of the repeated enlargement is selected in the length direction of the second side (see FIGS. 7 and 8).
　前記実施の形態によれば、増幅素子の半導体チップ表面での配置方向の制約を解消することができる。 According to the embodiment, the restriction on the arrangement direction of the amplifying element on the semiconductor chip surface can be eliminated.
　好適な実施の形態では、前記第１ＲＦ電力増幅器(１００)は第１初段増幅素子(Ｑ１)を含み、前記第２ＲＦ電力増幅器(５００)の第２初段増幅素子(Ｑ１)を含む。 In a preferred embodiment, the first RF power amplifier (100) includes a first first stage amplifying element (Q1), and includes a second first stage amplifying element (Q1) of the second RF power amplifier (500).
　前記第１初段増幅素子(Ｑ１)と前記第２初段増幅素子(Ｑ１)の各増幅素子は、複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成される。 The amplifying elements of the first first stage amplifying element (Q1) and the second first stage amplifying element (Q1) are configured by parallel connection of a plurality of unit transistors (Unit_MOS).
　前記第１初段増幅素子(Ｑ１)と前記第２初段増幅素子(Ｑ１)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 Each unit transistor of the plurality of unit transistors of the first first stage amplifying element (Q1) and the second first stage amplifying element (Q1) has an active region that determines the gain of each unit transistor, and The planar shape of the region is a rectangle.
　前記第１初段増幅素子(Ｑ１)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向と、前記第２初段増幅素子(Ｑ１)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向とは、前記第２辺の長さ方向に選択される。 The extending direction of each long side of the plurality of active regions of the plurality of unit transistors of the first first stage amplifying element (Q1) and the plurality of unit transistors of the second first stage amplifying element (Q1) The extending direction of each long side of the plurality of rectangles of the plurality of active regions is selected in the length direction of the second side.
　前記第１ＲＦ電力増幅器(１００)の前記第１初段増幅素子(Ｑ１)と前記第１最終段増幅素子(Ｑ３)とは、前記第１辺に沿って前記半導体チップの前記表面上に形成される。 The first first stage amplification element (Q1) and the first last stage amplification element (Q3) of the first RF power amplifier (100) are formed on the surface of the semiconductor chip along the first side. .
　前記第２ＲＦ電力増幅器(５００)の前記第２初段増幅素子(Ｑ１)と前記第２最終段増幅素子(Ｑ３)とは、前記第２辺に沿って前記半導体チップの前記表面上に形成されたことを特徴とするものである(図７参照)。 The second first stage amplification element (Q1) and the second last stage amplification element (Q3) of the second RF power amplifier (500) are formed on the surface of the semiconductor chip along the second side. (See FIG. 7).
　他の好適な実施の形態では、前記第１ＲＦ電力増幅器(１００)は第１段間整合回路(ＭＮ)を含み、前記第２ＲＦ電力増幅器(５００)の第２段間整合回路(ＭＮ)を含む。 In another preferred embodiment, the first RF power amplifier (100) includes a first interstage matching circuit (MN), and includes a second interstage matching circuit (MN) of the second RF power amplifier (500). .
　前記第１ＲＦ電力増幅器(１００)の前記第１段間整合回路(ＭＮ)は、前記第１初段増幅素子(Ｑ１)の出力端子の増幅信号を前記第１最終段増幅素子(Ｑ３)の入力端子に伝達する。 The first inter-stage matching circuit (MN) of the first RF power amplifier (100) receives the amplified signal at the output terminal of the first first stage amplifying element (Q1) as the input terminal of the first last stage amplifying element (Q3). To communicate.
　前記第２ＲＦ電力増幅器(５００)の前記第２段間整合回路(ＭＮ)は、前記第２初段増幅素子(Ｑ１)の出力端子の増幅信号を前記第２最終段増幅素子(Ｑ２)の入力端子に伝達する。 The second inter-stage matching circuit (MN) of the second RF power amplifier (500) receives the amplified signal at the output terminal of the second first stage amplifying element (Q1) as the input terminal of the second last stage amplifying element (Q2). To communicate.
　前記第１ＲＦ電力増幅器(１００)の前記第１初段増幅素子(Ｑ１)と前記第１段間整合回路(ＭＮ)と前記第１最終段増幅素子(Ｑ３)とは、前記第１辺に沿って前記半導体チップの前記表面上に形成される。 The first first stage amplifying element (Q1), the first interstage matching circuit (MN), and the first last stage amplifying element (Q3) of the first RF power amplifier (100) are arranged along the first side. Formed on the surface of the semiconductor chip.
　前記第２ＲＦ電力増幅器(５００)の前記第２初段増幅素子(Ｑ１)と前記第２段間整合回路(ＭＮ)と前記第２最終段増幅素子(Ｑ３)とは、前記第２辺に沿って前記半導体チップの前記表面上に形成されたことを特徴とするものである(図７参照)。 The second first stage amplifying element (Q1), the second interstage matching circuit (MN), and the second last stage amplifying element (Q3) of the second RF power amplifier (500) are along the second side. It is formed on the surface of the semiconductor chip (see FIG. 7).
　更に他の好適な実施の形態では、前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの複数の出力電極には複数の第１出力配線(ＤＭ１)が接続され、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの複数の出力電極には複数の第２出力配線(ＤＭ１)が接続される。 In still another preferred embodiment, a plurality of first output wires (DM1) are connected to a plurality of output electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3), so that the second final output A plurality of second output wirings (DM1) are connected to a plurality of output electrodes of the plurality of unit transistors of the stage amplifying element (Q2).
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの複数の入力電極には複数の第１入力配線(ＧＭ１)が接続され、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの複数の入力電極には複数の第２入力配線(ＧＭ１)が接続される。 A plurality of first input wirings (GM1) are connected to a plurality of input electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3), and the plurality of the plurality of unit transistors of the second final stage amplifying element (Q2) are connected. A plurality of second input wirings (GM1) are connected to the plurality of input electrodes of the unit transistor.
　前記複数の第１出力配線(ＤＭ１)の各配線の延長方向は前記第２辺の長さ方向に選択され、前記複数の第１入力配線(ＧＭ１)の各配線の延長方向は前記第１辺の長さ方向に選択される。 The extending direction of each wiring of the plurality of first output wirings (DM1) is selected in the length direction of the second side, and the extending direction of each wiring of the plurality of first input wirings (GM1) is the first side. Is selected in the length direction.
　前記複数の第２出力配線(ＤＭ１)の各配線の延長方向は前記第１辺の長さ方向に選択され、前記複数の第２入力配線(ＧＭ１)の各配線の延長方向は前記第１辺の長さ方向に選択されたことを特徴とするものである(図８参照)。 The extending direction of each wiring of the plurality of second output wirings (DM1) is selected in the length direction of the first side, and the extending direction of each wiring of the plurality of second input wirings (GM1) is the first side. Is selected in the length direction (see FIG. 8).
　より好適な実施の形態では、前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタと前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタとは、電界効果トランジスタである。 In a more preferred embodiment, the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of unit transistors of the second final stage amplification element (Q2) are field effect transistors.
　前記電界効果トランジスタはゲート電極(Ｇ)とドレイン領域(Ｄ)とソース領域(Ｓ)とを有し、前記ドレイン領域と前記ソース領域との間の前記ゲート電極の前記第２辺の長さ方向のゲート長(Ｌ)によって前記活性領域の前記長方形の短辺が決定され、前記ドレイン領域と前記ソース領域との間の前記ゲート電極の前記第１辺の長さ方向のゲート幅(Ｗ)によって前記活性領域の前記長方形の前記長辺が決定されることを特徴とするものである(図８参照)。 The field effect transistor has a gate electrode (G), a drain region (D), and a source region (S), and a length direction of the second side of the gate electrode between the drain region and the source region. The rectangular short side of the active region is determined by the gate length (L) of the gate electrode, and the gate width (W) in the length direction of the first side of the gate electrode between the drain region and the source region is determined. The long side of the rectangle of the active region is determined (see FIG. 8).
　他のより好適な実施の形態では、前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの前記複数の出力電極としての複数のドレイン領域には前記複数の第１出力配線(ＤＭ１)が接続され、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の出力電極としての複数のドレイン領域には前記複数の第２出力配線(ＤＭ１)が接続される。 In another more preferred embodiment, the plurality of first output wirings (DM1) are provided in the plurality of drain regions as the plurality of output electrodes of the plurality of unit transistors of the first final stage amplifying element (Q3). Are connected, and the plurality of second output wirings (DM1) are connected to the plurality of drain regions as the plurality of output electrodes of the plurality of unit transistors of the second final stage amplifying element (Q2).
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの前記複数の入力電極としての複数のゲート電極には前記複数の第１入力配線(ＧＭ１)が接続され、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の入力電極としての複数のゲート電極には前記複数の第２入力配線(ＧＭ１)が接続される。 The plurality of first input wirings (GM1) are connected to the plurality of gate electrodes as the plurality of input electrodes of the plurality of unit transistors of the first final stage amplification element (Q3), and the second final stage amplification is performed. The plurality of second input wirings (GM1) are connected to the plurality of gate electrodes as the plurality of input electrodes of the plurality of unit transistors of the element (Q2).
　前記複数の第１出力配線(ＤＭ１)の前記各配線の前記延長方向は前記第２辺の長さ方向に選択され、前記複数の第１入力配線(ＧＭ１)の前記各配線の前記延長方向は前記第１辺の長さ方向に選択される。 The extension direction of each wiring of the plurality of first output wirings (DM1) is selected in the length direction of the second side, and the extension direction of each wiring of the plurality of first input wirings (GM1) is It is selected in the length direction of the first side.
　前記複数の第２出力配線(ＤＭ１)の前記各配線の前記延長方向は前記第１辺の長さ方向に選択され、前記複数の第２入力配線(ＧＭ１)の前記各配線の前記延長方向は前記第１辺の長さ方向に選択されたことを特徴とするものである(図８参照)。 The extension direction of each wiring of the plurality of second output wirings (DM1) is selected in the length direction of the first side, and the extension direction of each wiring of the plurality of second input wirings (GM1) is The first side is selected in the length direction (see FIG. 8).
　更に他のより好適な実施の形態では、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の入力電極である前記複数のゲート電極は、前記複数の長方形の前記複数の活性領域として前記第２辺の長さ方向に延長して前記半導体チップの前記表面上に形成される。 In still another more preferred embodiment, the plurality of gate electrodes which are the plurality of input electrodes of the plurality of unit transistors of the second final stage amplifying element (Q2) are the plurality of rectangles. An active region is formed on the surface of the semiconductor chip extending in the length direction of the second side.
　前記第２辺の長さ方向に形成された前記複数のゲート電極(Ｇ)と前記第１辺の長さ方向に形成された前記複数の第２出力配線(ＤＭ１)とは、前記半導体チップの前記表面上で立体的に交差する。 The plurality of gate electrodes (G) formed in the length direction of the second side and the plurality of second output wirings (DM1) formed in the length direction of the first side are formed on the semiconductor chip. Three-dimensionally intersect on the surface.
　前記半導体チップの前記表面上で前記複数のゲート電極(Ｇ)と前記複数の第２出力配線(ＤＭ１)とが立体的に交差する部分において、接地電圧(ＧＮＤ)に接続される前記ソース領域(Ｓ)と電気的に接続される複数のソース配線(２４Ａ)が前記複数のゲート電極(Ｇ)と前記複数の第２出力配線(ＤＭ１)との間に形成されたことを特徴とするものである(図１２、図１３参照)。 The source region (GND) connected to the ground voltage (GND) at a portion where the plurality of gate electrodes (G) and the plurality of second output wirings (DM1) intersect three-dimensionally on the surface of the semiconductor chip. A plurality of source lines (24A) electrically connected to S) are formed between the plurality of gate electrodes (G) and the plurality of second output lines (DM1). Yes (see FIGS. 12 and 13).
　別のより好適な実施の形態では、前記半導体チップには、前記半導体チップの前記表面から前記半導体チップの裏面に到達する複数の打ち抜き層(４)が形成される。 In another more preferred embodiment, the semiconductor chip is formed with a plurality of punched layers (4) reaching the back surface of the semiconductor chip from the front surface of the semiconductor chip.
　前記複数のソース配線(２４Ａ)は、前記複数の打ち抜き層(４)を介して前記半導体チップの前記裏面に形成されたソース裏面電極(３６)に電気的に接続されたことを特徴とするものである(図１３参照)。 The plurality of source lines (24A) are electrically connected to a source back surface electrode (36) formed on the back surface of the semiconductor chip through the plurality of punched layers (4). (See FIG. 13).
　具体的な実施の形態では、前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタと前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタとしての前記電界効果トランジスタは、ＬＤＭＯＳＦＥＴであることを特徴とするものである(図７、図８参照)。 In a specific embodiment, the plurality of unit transistors of the first final stage amplifying element (Q3) and the field effect transistors as the plurality of unit transistors of the second final stage amplifying element (Q2) are LDMOSFETs. (See FIGS. 7 and 8).
　他の具体的な実施の形態では、前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタと前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタとは、バイポーラトランジスタである。 In another specific embodiment, the plurality of unit transistors of the first final stage amplification element (Q3) and the plurality of unit transistors of the second final stage amplification element (Q2) are bipolar transistors. .
　前記バイポーラトランジスタは複数のエミッタ領域を有し、前記複数のエミッタ領域は前記複数の長方形の前記複数の活性領域として前記第２辺の長さ方向に延長して前記半導体チップの前記表面上に形成されたことを特徴とするものである(図２２参照)。 The bipolar transistor has a plurality of emitter regions, and the plurality of emitter regions are formed on the surface of the semiconductor chip as the plurality of rectangular active regions extending in the length direction of the second side. This is a feature (see FIG. 22).
　より具体的な実施の形態では、前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタと前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタとしての前記バイポーラトランジスタは、ヘテロバイポーラトランジスタであることを特徴とするものである(図２２参照)。 In a more specific embodiment, the plurality of unit transistors of the first final stage amplification element (Q3) and the bipolar transistors as the plurality of unit transistors of the second final stage amplification element (Q2) are heterogeneous. It is a bipolar transistor (see FIG. 22).
　他のより具体的な実施の形態では、前記半導体集積回路は、第３ＲＦ電力増幅器(２００)を更に内蔵する。 In another more specific embodiment, the semiconductor integrated circuit further includes a third RF power amplifier (200).
　前記半導体集積回路の前記半導体チップの第３辺は前記第１辺と実質的に平行に配置されて前記第２辺と実質的に直角に交差するものである。 The third side of the semiconductor chip of the semiconductor integrated circuit is arranged substantially parallel to the first side and intersects the second side substantially at a right angle.
　前記半導体チップの前記表面上には、前記第３辺に沿って前記第３ＲＦ電力増幅器(２００)の第３最終段増幅素子(Ｑ３)が形成される。 A third final amplification element (Q3) of the third RF power amplifier (200) is formed on the surface of the semiconductor chip along the third side.
　前記第３最終段増幅素子(Ｑ３)は複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成され、前記第３最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 The third final stage amplifying element (Q3) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the third final stage amplifying element (Q3) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
　前記第３最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択される。 The extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected as the length direction of the second side.
　前記第３最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの反復拡大の方向は、前記第３辺の長さ方向に選択されたことを特徴とするものである(図７、図８参照)。 The direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected in the length direction of the third side (see FIGS. 7 and 8). ).
　更に他のより具体的な実施の形態では、前記半導体集積回路は、第４ＲＦ電力増幅器(４００)を更に内蔵する。 In still another more specific embodiment, the semiconductor integrated circuit further includes a fourth RF power amplifier (400).
　前記半導体集積回路の前記半導体チップの第４辺は前記第２辺と実質的に平行に配置されて前記第３辺と実質的に直角に交差するものである。 The fourth side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the second side and intersects the third side substantially at a right angle.
　前記半導体チップの前記表面上には、前記第４辺に沿って前記第４ＲＦ電力増幅器(４００)の第４最終段増幅素子(Ｑ２)が形成される。 A fourth final stage amplifying element (Q2) of the fourth RF power amplifier (400) is formed on the surface of the semiconductor chip along the fourth side.
　前記第４最終段増幅素子(Ｑ２)は複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成され、前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 The fourth final stage amplifying element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element (Q2) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
　前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択される。 The extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected as the length direction of the second side.
　前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの反復拡大の方向は、前記第４辺の長さ方向に選択されたことを特徴とするものである(図７、図８参照)。 The direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected in the length direction of the fourth side (see FIGS. 7 and 8). ).
　最も具体的な実施の形態では、前記半導体チップの前記表面上には、前記第１ＲＦ電力増幅器(１００)と前記第２ＲＦ電力増幅器(５００)との間と前記第３ＲＦ電力増幅器(２００)と前記第４ＲＦ電力増幅器(４００)との間の位置に、バイアス制御部(３００)が形成される。 In a most specific embodiment, on the surface of the semiconductor chip, between the first RF power amplifier (100) and the second RF power amplifier (500), the third RF power amplifier (200), and the A bias controller (300) is formed at a position between the fourth RF power amplifier (400).
　前記バイアス制御部(３００)は、前記第１ＲＦ電力増幅器(１００)の前記第１初段増幅素子(Ｑ１)と前記第１最終段増幅素子(Ｑ３)に、前記第２ＲＦ電力増幅器(５００)の前記第２初段増幅素子(Ｑ１)と前記第２最終段増幅素子(Ｑ２)に、前記第３ＲＦ電力増幅器(２００)の第３初段増幅素子(Ｑ１)と前記第３最終段増幅素子(Ｑ３)に、前記第４ＲＦ電力増幅器(４００)の第４初段増幅素子(Ｑ１)と前記第４最終段増幅素子(Ｑ２)に、それぞれバイアス電圧を供給することを特徴とするものである(図７、図８参照)。 The bias control unit (300) is connected to the first first stage amplifying element (Q1) and the first last stage amplifying element (Q3) of the first RF power amplifier (100). The second first stage amplifying element (Q1) and the second last stage amplifying element (Q2) are connected to the third first stage amplifying element (Q1) and the third last stage amplifying element (Q3) of the third RF power amplifier (200). A bias voltage is supplied to each of the fourth first stage amplifying element (Q1) and the fourth last stage amplifying element (Q2) of the fourth RF power amplifier (400) (FIG. 7, FIG. 8).
　〔２〕本発明の別の観点の代表的な実施の形態は、第１ＲＦ電力増幅器(１００)と第２ＲＦ電力増幅器(５００)とを内蔵する半導体集積回路の半導体チップを配線基板に搭載するモジュールである。 [2] A typical embodiment of another aspect of the present invention is a module in which a semiconductor chip of a semiconductor integrated circuit incorporating a first RF power amplifier (100) and a second RF power amplifier (500) is mounted on a wiring board. It is.
　前記半導体集積回路の前記半導体チップの第１辺と第２辺とは、実質的に直角に交差するものである。 The first side and the second side of the semiconductor chip of the semiconductor integrated circuit substantially intersect at a right angle.
　前記半導体チップの表面上には、前記第１辺に沿って前記第１ＲＦ電力増幅器(１００)の第１最終段増幅素子(Ｑ３)が形成され、前記第２辺に沿って前記第２ＲＦ電力増幅器(５００)の第２最終段増幅素子(Ｑ２)が形成される。 A first final stage amplifying element (Q3) of the first RF power amplifier (100) is formed on the surface of the semiconductor chip along the first side, and the second RF power amplifier is formed along the second side. (500) second final stage amplifying elements (Q2) are formed.
　前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)の各増幅素子は、複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成される。 Each amplification element of the first final stage amplification element (Q3) and the second final stage amplification element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS).
　前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 Each unit transistor of the plurality of unit transistors of the first final stage amplifying element (Q3) and the second final stage amplifying element (Q2) has an active region that determines the gain of each unit transistor, The planar shape of the active region is a rectangle.
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向と、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向とは、前記第２辺の長さ方向に選択される。 The extending directions of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element (Q3), and the plurality of the plurality of unit areas of the second final stage amplification element (Q2) The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the unit transistor is selected in the length direction of the second side.
　前記第１最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの反復拡大の方向は前記第１辺の長さ方向に選択され、前記第２最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの反復拡大の方向は前記第２辺の長さ方向に選択される。 The direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element (Q3) is selected in the length direction of the first side, and the plurality of unit transistors of the second final stage amplification element (Q2) The direction of the repeated enlargement is selected in the length direction of the second side.
　前記配線基板に、前記半導体チップが搭載される。 The semiconductor chip is mounted on the wiring board.
　前記半導体チップの前記１辺と対向する前記配線基板の第１基板部分に前記第１ＲＦ電力増幅器(１００)の第１出力整合回路(１００＿ＯｕｔＭＮ)が搭載され、前記半導体チップの前記２辺と対向する前記配線基板の第２基板部分に前記第２ＲＦ電力増幅器(５００)の第２出力整合回路(５００＿ＯｕｔＭＮ)が搭載される。 A first output matching circuit (100_OutMN) of the first RF power amplifier (100) is mounted on a first substrate portion of the wiring board that faces the one side of the semiconductor chip, and faces the two sides of the semiconductor chip. A second output matching circuit (500_OutMN) of the second RF power amplifier (500) is mounted on the second substrate portion of the wiring board.
　前記第１最終段増幅素子(Ｑ３)の出力端子の増幅信号は、前記半導体チップの前記１辺を介して、前記第１出力整合回路(１００＿ＯｕｔＭＮ)に供給される。 The amplified signal at the output terminal of the first final stage amplifying element (Q3) is supplied to the first output matching circuit (100_OutMN) via the one side of the semiconductor chip.
　前記第２最終段増幅素子(Ｑ２)の出力端子の増幅信号は、前記半導体チップの前記２辺を介して、前記第２出力整合回路(５００＿ＯｕｔＭＮ)に供給されたことを特徴とするものである(図２４参照)。 The amplified signal at the output terminal of the second final stage amplifying element (Q2) is supplied to the second output matching circuit (500_OutMN) via the two sides of the semiconductor chip. (See FIG. 24).
　前記実施の形態によれば、増幅素子の半導体チップ表面での配置方向の制約を解消することができる。 According to the embodiment, the restriction on the arrangement direction of the amplifying element on the semiconductor chip surface can be eliminated.
　好適な実施の形態では、前記半導体集積回路は、第３ＲＦ電力増幅器(２００)を更に内蔵する。 In a preferred embodiment, the semiconductor integrated circuit further includes a third RF power amplifier (200).
　前記半導体集積回路の前記半導体チップの第３辺は、前記第１辺と実質的に平行に配置されて前記第２辺と実質的に直角に交差するものである。 The third side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the first side and intersects the second side substantially at a right angle.
　前記半導体チップの前記表面上には、前記第３辺に沿って前記第３ＲＦ電力増幅器(２００)の第３最終段増幅素子(Ｑ３)が形成される。 A third final amplification element (Q3) of the third RF power amplifier (200) is formed on the surface of the semiconductor chip along the third side.
　前記第３最終段増幅素子(Ｑ３)は複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成され、前記第３最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 The third final stage amplifying element (Q3) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the third final stage amplifying element (Q3) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
　前記第３最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択される。 The extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected as the length direction of the second side.
　前記第３最終段増幅素子(Ｑ３)の前記複数の単位トランジスタの反復拡大の方向は、前記第３辺の長さ方向に選択される。 The direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element (Q3) is selected in the length direction of the third side.
　前記半導体チップの前記３辺と対向する前記配線基板の第３基板部分に、前記第３ＲＦ電力増幅器(２００)の第３出力整合回路(２００＿ＯｕｔＭＮ)が搭載される。 A third output matching circuit (200_OutMN) of the third RF power amplifier (200) is mounted on the third substrate portion of the wiring board facing the three sides of the semiconductor chip.
　前記第３最終段増幅素子(Ｑ３)の出力端子の増幅信号は、前記半導体チップの前記３辺を介して、前記第３出力整合回路(２００＿ＯｕｔＭＮ)に供給されたことを特徴とするものである(図２４参照)。 The amplified signal at the output terminal of the third final stage amplifying element (Q3) is supplied to the third output matching circuit (200_OutMN) via the three sides of the semiconductor chip. (See FIG. 24).
　他の好適な実施の形態では、前記半導体集積回路は、第４ＲＦ電力増幅器(４００)を更に内蔵する。 In another preferred embodiment, the semiconductor integrated circuit further includes a fourth RF power amplifier (400).
　前記半導体集積回路の前記半導体チップの第４辺は、前記第２辺と実質的に平行に配置されて前記第３辺と実質的に直角に交差するものである。 The fourth side of the semiconductor chip of the semiconductor integrated circuit is arranged substantially parallel to the second side and intersects the third side substantially at a right angle.
　前記半導体チップの前記表面上には、前記第４辺に沿って前記第４ＲＦ電力増幅器(４００)の第４最終段増幅素子(Ｑ２)が形成される。 A fourth final stage amplifying element (Q2) of the fourth RF power amplifier (400) is formed on the surface of the semiconductor chip along the fourth side.
　前記第４最終段増幅素子(Ｑ２)は複数の単位トランジスタ(Ｕｎｉｔ＿ＭＯＳ)の並列接続によって構成され、前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形である。 The fourth final stage amplifying element (Q2) is configured by parallel connection of a plurality of unit transistors (Unit_MOS), and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element (Q2) It has an active region that determines the gain of the transistor, and the planar shape of the active region is rectangular.
　前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択される。 The extending direction of the long sides of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected as the length direction of the second side.
　前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタの反復拡大の方向は、前記第４辺の長さ方向に選択される。 The direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element (Q2) is selected in the length direction of the fourth side.
　前記半導体チップの前記４辺と対向する前記配線基板の第４基板部分に、前記第４ＲＦ電力増幅器(４００)の第４出力整合回路(４００＿ＯｕｔＭＮ)が搭載される。 A fourth output matching circuit (400_OutMN) of the fourth RF power amplifier (400) is mounted on the fourth substrate portion of the wiring board facing the four sides of the semiconductor chip.
　前記第４最終段増幅素子(Ｑ２)の出力端子の増幅信号は、前記半導体チップの前記４辺を介して、前記第４出力整合回路(４００＿ＯｕｔＭＮ)に供給されたことを特徴とするものである(図２４参照)。 The amplified signal at the output terminal of the fourth final stage amplification element (Q2) is supplied to the fourth output matching circuit (400_OutMN) through the four sides of the semiconductor chip. (See FIG. 24).
　具体的な実施の形態では、前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)と前記第３最終段増幅素子(Ｑ３)と前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタは、電界効果トランジスタであることを特徴とするものである。 In a specific embodiment, the first final stage amplification element (Q3), the second final stage amplification element (Q2), the third final stage amplification element (Q3), and the fourth final stage amplification element (Q2). The plurality of unit transistors is a field effect transistor.
　他の具体的な実施の形態では、前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)と前記第３最終段増幅素子(Ｑ３)と前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタとしての前記電界効果トランジスタは、ＬＤＭＯＳＦＥＴであることを特徴とするものである。 In another specific embodiment, the first final stage amplification element (Q3), the second final stage amplification element (Q2), the third final stage amplification element (Q3), and the fourth final stage amplification element. The field effect transistor as the plurality of unit transistors in (Q2) is an LDMOSFET.
　最も具体的な実施の形態では、前記第１最終段増幅素子(Ｑ３)と前記第２最終段増幅素子(Ｑ２)と前記第３最終段増幅素子(Ｑ３)と前記第４最終段増幅素子(Ｑ２)の前記複数の単位トランジスタは、バイポーラトランジスタであることを特徴とするものである。 In the most specific embodiment, the first final stage amplification element (Q3), the second final stage amplification element (Q2), the third final stage amplification element (Q3), and the fourth final stage amplification element ( The plurality of unit transistors of Q2) are bipolar transistors.
　２．実施の形態の詳細
　次に、実施の形態について更に詳述する。尚、発明を実施するための最良の形態を説明するための全図において、前記の図と同一の機能を有する部品には同一の符号を付して、その繰り返しの説明は省略する。 2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.
　［実施の形態１］
　《ＬＤＭＯＳＦＥＴの平面構造および断面構造》
　図１は、本発明の実施の形態１による半導体集積回路の半導体チップ１に集積化されるＬＤＭＯＳＦＥＴの平面構造を示す図である。図１の平面構造は、冒頭で説明したので、説明を省略する。 [Embodiment 1]
<< Planar structure and sectional structure of LDMOSFET >>
FIG. 1 is a diagram showing a planar structure of an LDMOSFET integrated on a semiconductor chip 1 of a semiconductor integrated circuit according to Embodiment 1 of the present invention. Since the planar structure in FIG. 1 has been described at the beginning, description thereof will be omitted.
　図２は、本発明の実施の形態１による半導体集積回路の半導体チップ１に集積化されるＬＤＭＯＳＦＥＴの断面構造を示す図である。図２の断面構造は、冒頭で説明したので、説明を省略する。 FIG. 2 is a diagram showing a cross-sectional structure of the LDMOSFET integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention. Since the sectional structure of FIG. 2 has been described at the beginning, the description thereof will be omitted.
　《ＲＦ電力増幅器とバイアス制御部》
　図３は、本発明の実施の形態１による半導体集積回路の半導体チップ１に集積化されるハイバンドＲＦ電力増幅器１００とローバンドＲＦ電力増幅器２００とバイアス制御部３００の構成を示す図である。 << RF power amplifier and bias control section >>
FIG. 3 is a diagram showing a configuration of the high-band RF power amplifier 100, the low-band RF power amplifier 200, and the bias control unit 300 that are integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
　ハイバンドＲＦ電力増幅器１００とローバンドＲＦ電力増幅器２００とバイアス制御部３００に関しては、冒頭で説明をしたので、説明を省略する。 Since the high-band RF power amplifier 100, the low-band RF power amplifier 200, and the bias control unit 300 have been described at the beginning, description thereof will be omitted.
　《半導体チップの構成》
　図７は、本発明の実施の形態１による半導体集積回路の半導体チップ１の構成を示す図である。 <Structure of semiconductor chip>
FIG. 7 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
　図７に示すように、本発明の実施の形態１による半導体集積回路の半導体チップ１は、図３に示したハイバンドＲＦ電力増幅器とローバンドＲＦ電力増幅器とを、ＧＳＭ方式とＷＣＤＭＡ方式の２系統、内蔵するものである。すなわち、図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１には、ＧＳＭ方式ハイバンドＲＦ電力増幅器(ＧＳＭ＿ＨＢ)１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３とＧＳＭ方式ローバンドＲＦ電力増幅器(ＧＳＭ＿ＬＢ)２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３と、更にＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＨＢ)４００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＬＢ)５００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２とバイアス制御部３００とが集積化されている。 As shown in FIG. 7, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention includes the high-band RF power amplifier and the low-band RF power amplifier shown in FIG. , Built-in. That is, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7 includes a plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier (GSM_HB) 100 and the GSM low band RF power. A plurality of LDMOSFETs Q1, Q2, and Q3 of the amplifier (GSM_LB) 200, a plurality of LDMOSFETs Q1 and Q2 of the WCDMA high-band RF power amplifier (WCDMA_HB) 400, and a plurality of LDMOSFETs Q1 and Q2 of the WCDMA low-band RF power amplifier (WCDMA_LB) 500 And the bias controller 300 are integrated.
　更に、図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１には、ＧＳＭ方式ハイバンドＲＦ電力増幅器(ＧＳＭ＿ＨＢ)１００とＧＳＭ方式ローバンドＲＦ電力増幅器(ＧＳＭ＿ＬＢ)２００とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＨＢ)４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＬＢ)５００の各電力増幅器の入力整合回路ＩｎＭＮと段間整合回路ＭＮとが集積化されている。 Further, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7 includes a GSM high-band RF power amplifier (GSM_HB) 100, a GSM low-band RF power amplifier (GSM_LB) 200, and a WCDMA system. The input matching circuit InMN and the interstage matching circuit MN of each power amplifier of the high band RF power amplifier (WCDMA_HB) 400 and the WCDMA low band RF power amplifier (WCDMA_LB) 500 are integrated.
　図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１においては、ＲＦ電力増幅器１００とＲＦ電力増幅器２００とＲＦ電力増幅器４００とＲＦ電力増幅器５００の全てのＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３の各ＦＥＴの２本のゲート電極の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一されている。従って、半導体チップ１の製造工程のバラツキに依存する４系統のＲＦ電力増幅器１００、２００、４００、５００の全てのＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３の各ＦＥＴの増幅ゲインのコンダクタンスの相対的なバラツキを、低減することが可能となる。 In the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, all the LDMOSFETs Q1, Q2, Q3 of the RF power amplifier 100, the RF power amplifier 200, the RF power amplifier 400, and the RF power amplifier 500 are shown. The extending directions of the long sides of the two gate electrodes of each FET are unified in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1. Therefore, the relative variation in the conductance of the amplification gain of all the LDMOSFETs Q1, Q2, and Q3 of the four RF power amplifiers 100, 200, 400, and 500 depending on the variation in the manufacturing process of the semiconductor chip 1 is reduced. It becomes possible to do.
　また図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１においては、３段増幅器によってそれぞれ構成されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００とは、長方形の半導体チップ１の上部長辺と下部長辺とにそれぞれ配置されている。すなわち、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３は長方形の半導体チップ１の上部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置され、ＧＳＭ方式ローバンドＲＦ電力増幅器２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３は長方形の半導体チップ１の下部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されている。 Further, in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 respectively constituted by three-stage amplifiers are The rectangular semiconductor chip 1 is disposed on the upper long side and the lower long side, respectively. That is, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM high band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1. The plurality of LDMOSFETs Q 1, Q 2, Q 3 of the low-band RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
　更に図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１においては、２段増幅器によってそれぞれ構成されるＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００とは、長方形の半導体チップ１の左部短辺と右部短辺とにそれぞれ配置されている。すなわち、ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２は長方形の半導体チップ１の左部短辺に半導体チップ１のＹ方向であるＡ－Ａ´線の方向に配置され、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２は長方形の半導体チップ１の右部短辺に半導体チップ１のＹ方向であるＡ－Ａ´線の方向に配置されている。尚、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００とが３段増幅器によってそれぞれ構成され、ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００とが２段増幅器によってそれぞれ構成されているのは、ＧＳＭ方式の移動体通信端末の基地局への送信電力がＷＣＤＭＡ方式の場合よりも相対的に大きいためである。 Further, in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 each constituted by a two-stage amplifier are used. The rectangular semiconductor chip 1 is disposed on the left short side and the right short side, respectively. That is, the plurality of LDMOSFETs Q 1 and Q 2 of the WCDMA high-band RF power amplifier 400 are arranged on the short left side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1, and the WCDMA low-band The plurality of LDMOSFETs Q1 and Q2 of the RF power amplifier 500 are arranged on the short right side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. The GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 are each constituted by a three-stage amplifier, and the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 are constituted by a two-stage amplifier. Each is configured because the transmission power of the GSM mobile communication terminal to the base station is relatively higher than that in the WCDMA system.
　従って、半導体チップ１の上部長辺でＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大きな素子サイズとされた最終段増幅素子Ｑ３は、その２本のゲート電極の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択されている。また更に半導体チップ１の下部長辺でＧＳＭ方式ローバンドＲＦ電力増幅器２００の大きな素子サイズとされた最終段増幅素子Ｑ３は、その２本のゲート電極の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択されている。 Therefore, in the final stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 on the upper long side of the semiconductor chip 1, the extending direction of the long sides of the two gate electrodes is Y in the semiconductor chip 1. The direction of the AA ′ line, which is the direction, is selected, while the unit transistor repeated enlargement for realizing a large element size is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1. . Further, the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 on the lower long side of the semiconductor chip 1 is extended in the Y direction of the semiconductor chip 1 in the extending direction of the long sides of the two gate electrodes. Is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size.
　それに対して半導体チップ１の左部短辺でＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の大きな素子サイズとされた最終段増幅素子Ｑ２は、その２本のゲート電極の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方で、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択されている。また更に半導体チップ１の右部短辺でＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大きな素子サイズとされた最終段増幅素子Ｑ２は、その２本のゲート電極の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方で、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択されている。 On the other hand, in the final stage amplifying element Q2, which is a large element size of the WCDMA high band RF power amplifier 400 on the left short side of the semiconductor chip 1, the extending direction of the long sides of the two gate electrodes is the semiconductor chip 1. Is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip, while repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip 1 Has been. Furthermore, in the final stage amplifying element Q2, which is a large element size of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1, the extending direction of the long sides of the two gate electrodes is Y in the semiconductor chip 1. While the direction of the AA ′ line that is the direction is selected, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Yes.
　図７には示されてはいないが、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００の各増幅器の初段増幅素子Ｑ１と２段目の増幅素子Ｑ２も、最終段増幅素子Ｑ３と同様に、複数の単位トランジスタの並列接続によって構成されている。２段目の増幅素子Ｑ２が中間的なＲＦ出力を発生するために２段目の増幅素子Ｑ２を構成する複数の単位トランジスタの半導体チップ１のＸ方向であるＢ－Ｂ´線の方向の反復拡大量は、大きなＲＦ出力を発生する最終段増幅素子Ｑ３の反復拡大量よりも小さく設定される。初段増幅素子Ｑ１が小さな出力を発生するために初段増幅素子Ｑ１を構成する複数の単位トランジスタの半導体チップ１のＸ方向であるＢ－Ｂ´線の方向の反復拡大量は、中間的な出力を発生する２段目の増幅素子Ｑ２の反復拡大量よりも小さく設定される。 Although not shown in FIG. 7, the first stage amplifying element Q1 and the second stage amplifying element Q2 of each amplifier of the GSM type high band RF power amplifier 100 and the GSM type low band RF power amplifier 200 are also the final stage amplifying element Q3. In the same manner as described above, a plurality of unit transistors are connected in parallel. In order for the second-stage amplifying element Q2 to generate an intermediate RF output, a plurality of unit transistors constituting the second-stage amplifying element Q2 are repeated in the direction of the BB ′ line that is the X direction of the semiconductor chip 1 The enlargement amount is set smaller than the repeated enlargement amount of the final stage amplifying element Q3 that generates a large RF output. In order for the first stage amplifying element Q1 to generate a small output, the repeated enlargement amount in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplifying element Q1, gives an intermediate output. It is set to be smaller than the repetitive enlargement amount of the generated second-stage amplifying element Q2.
　やはり図７には示されてはいないが、ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の各増幅器の初段増幅素子Ｑ１も、最終段増幅素子Ｑ２と同様に、複数の単位トランジスタの並列接続によって構成されている。初段増幅素子Ｑ１が小さいＲＦ出力を発生させるために初段増幅素子Ｑ１を構成する複数の単位トランジスタの半導体チップ１のＹ方向であるＡ－Ａ´線の方向の反復拡大量は、大きな出力を発生する最終段増幅素子Ｑ２の反復拡大量よりも小さく設定される。 Although not shown in FIG. 7, the first-stage amplifying element Q1 of each amplifier of the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 is also composed of a plurality of units similarly to the final-stage amplifying element Q2. It is configured by parallel connection of transistors. In order for the first stage amplifying element Q1 to generate a small RF output, the repeated enlargement amount in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplifying element Q1 generates a large output. It is set to be smaller than the repeated enlargement amount of the final stage amplifying element Q2.
　《大素子サイズの最終段増幅素子の構成》
　図８は、図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１で、半導体チップ１の上部長辺に配置されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３と半導体チップ１の右部短辺に配置されるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２とが構成される様子を示す図である。 <Large-amplifier configuration of the last stage amplifier>
FIG. 8 shows the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, which has a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1. FIG. 2 is a diagram showing a state in which a final stage amplification element Q3 and a large stage size final stage amplification element Q2 of a WCDMA low-band RF power amplifier 500 arranged on the short right side of the semiconductor chip 1 are configured.
　図８の左下には、長方形に形成された２本のゲート電極Ｇと、２本のゲート電極Ｇの中央部分に長方形に形成された１本のドレイン領域Ｄと、２本のゲート電極Ｇの外部に長方形に形成された２本のソース領域Ｓとを含むＬＤＭＯＳＦＥＴの単位トランジスタＵｎｉｔ＿ＭＯＳの平面構造が示されている。ドレイン領域Ｄとソース領域Ｓとの間のゲート電極ＧのＢ－Ｂ´線の方向の長さによってＬＤＭＯＳＦＥＴのゲート長Ｌが決定されて、ドレイン領域Ｄとソース領域Ｓとの間のゲート電極ＧのＡ－Ａ´線の方向の幅によってＬＤＭＯＳＦＥＴのゲート幅Ｗが決定される。１個の単位トランジスタＵｎｉｔ＿ＭＯＳの２本のゲート電極Ｇは共通接続され、２本のソース領域Ｓも共通接続されるので、１個の単位トランジスタＵｎｉｔ＿ＭＯＳの内部の２個のＬＤＭＯＳＦＥＴは並列動作する。 In the lower left of FIG. 8, two gate electrodes G formed in a rectangular shape, one drain region D formed in a rectangular shape in the center of the two gate electrodes G, and two gate electrodes G A planar structure of an LDMOSFET unit transistor Unit_MOS including two source regions S formed in a rectangular shape outside is shown. The gate length L of the LDMOSFET is determined by the length of the gate electrode G between the drain region D and the source region S in the direction of the BB ′ line, and the gate electrode G between the drain region D and the source region S is determined. The gate width W of the LDMOSFET is determined by the width in the direction of the AA ′ line. Since the two gate electrodes G of one unit transistor Unit_MOS are connected in common and the two source regions S are also connected in common, the two LDMOSFETs inside one unit transistor Unit_MOS operate in parallel.
　図８の上部に示すように、半導体チップ１の上部長辺に配置されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３は、図８の左下に示した単位トランジスタＵｎｉｔ＿ＭＯＳをＸ方向の２行分反復拡大して、Ｙ方向の９列分反復拡大することによって構成されている。すなわち、最終段増幅素子Ｑ３では、大きな素子サイズの実現のための単位トランジスタＵｎｉｔ＿ＭＯＳの実質的な反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択されている。従って、半導体チップ１の下部長辺に配置されるＧＳＭ方式ローバンドＲＦ電力増幅器２００の大素子サイズの最終段増幅素子Ｑ３も、大きな素子サイズの実現のための単位トランジスタＵｎｉｔ＿ＭＯＳの実質的な反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択される。尚、図８に示したＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３のＸ方向の反復行とＹ方向の反復列とは２行・９列ではなく実際は図９で説明するように３行・１２列である。図８でＸ方向の反復行とＹ方向の反復列とを実際よりも小さくしたのは、図９で省略されたゲート電極Ｇとドレイン領域Ｄとを図８で図示するためである。 As shown in the upper part of FIG. 8, the final stage amplifying element Q3 of the large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. Is repeatedly expanded for two rows in the X direction, and is repeatedly expanded for nine columns in the Y direction. That is, in the final stage amplifying element Q3, the substantial repeated enlargement of the unit transistor Unit_MOS for realizing a large element size is selected in the direction of the BB ′ line that is the X direction of the semiconductor chip 1. Accordingly, the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 disposed on the lower long side of the semiconductor chip 1 is also substantially repetitively enlarged by the unit transistor Unit_MOS for realizing a large element size. The semiconductor chip 1 is selected in the direction of line BB ′, which is the X direction. Note that the repetition row in the X direction and the repetition column in the Y direction of the final stage amplifying element Q3 of the large element size of the GSM high band RF power amplifier 100 shown in FIG. As described, there are 3 rows and 12 columns. The reason why the repeated rows in the X direction and the repeated columns in the Y direction are made smaller than the actual size in FIG. 8 is to illustrate the gate electrode G and the drain region D omitted in FIG. 9 in FIG.
　図８の右下に示すように半導体チップ１の右部短辺に配置されるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２は、図８の左下に示した単位トランジスタＵｎｉｔ＿ＭＯＳをＸ方向の４行分反復拡大して、Ｙ方向の３列分反復拡大することによって構成されている。すなわち、最終段増幅素子Ｑ２では、大きな素子サイズの実現のための単位トランジスタＵｎｉｔ＿ＭＯＳの実質的な反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択されている。従って、半導体チップ１の左部短辺に配置されるＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の大素子サイズの最終段増幅素子Ｑ２も、大きな素子サイズの実現のための単位トランジスタＵｎｉｔ＿ＭＯＳの実質的な反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される。尚、図８に示したＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２のＸ方向の反復行とＹ方向の反復列とは４行・３列ではなく実際は図１１で説明するように１２行・５列である。図８でＸ方向の反復行とＹ方向の反復列とを実際よりも小さくしたのは、図１２で省略されたゲート電極Ｇとドレイン領域Ｄとを図８で図示するためである。 As shown in the lower right of FIG. 8, the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 disposed on the right short side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. Is repeatedly expanded for four rows in the X direction, and is repeatedly expanded for three columns in the Y direction. That is, in the final stage amplification element Q2, the substantial repeated enlargement of the unit transistor Unit_MOS for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Accordingly, the large-stage final-stage amplifying element Q2 of the WCDMA high-band RF power amplifier 400 arranged on the short left side of the semiconductor chip 1 is also a substantial repetition of the unit transistor Unit_MOS for realizing a large element size. The enlargement is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Note that the repetition row in the X direction and the repetition column in the Y direction of the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 shown in FIG. It is 12 rows and 5 columns. The reason why the repeated rows in the X direction and the repeated columns in the Y direction are made smaller than the actual size in FIG. 8 is to illustrate the gate electrode G and the drain region D omitted in FIG. 12 in FIG.
　図８の上部に示すＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３では、複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のゲート電極Ｇは第１ゲート配線ＧＭ１に接続され、複数の第１ゲート配線ＧＭ１は配線幅の大きな第２ゲート配線ＧＭ２を介してゲートパッドＧＰに接続されている。更に複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のドレイン領域Ｄは、第１ドレイン配線ＤＭ１を介して複数のドレインパッドＤＰに接続されている。また複数の平行な第１ドレイン配線ＤＭ１は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に形成されている。 In the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 shown in the upper part of FIG. 8, the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are connected to the first gate wiring GM1, The one gate wiring GM1 is connected to the gate pad GP through the second gate wiring GM2 having a large wiring width. Further, the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to the plurality of drain pads DP via the first drain wiring DM1. The plurality of parallel first drain wirings DM1 are formed in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
　図８の右下に示すＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２では、複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のゲート電極Ｇは第１ゲート配線ＧＭ１に接続され、複数の第１ゲート配線ＧＭ１は配線幅の大きな第２ゲート配線ＧＭ２を介してゲートパッドＧＰに接続されている。更に複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のドレイン領域Ｄは、第１ドレイン配線ＤＭ１を介して複数のドレインパッドＤＰに接続されている。また複数の平行な第１ドレイン配線ＤＭ１は、半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に形成されている。 In the large-amplifier final-stage amplifier element Q2 of the WCDMA low-band RF power amplifier 500 shown in the lower right of FIG. 8, the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are connected to the first gate line GM1, The one gate wiring GM1 is connected to the gate pad GP through the second gate wiring GM2 having a large wiring width. Further, the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to the plurality of drain pads DP via the first drain wiring DM1. The plurality of parallel first drain wirings DM1 are formed in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
　図８の上部に示したＲＦ電力増幅器１００の最終段増幅素子Ｑ３の単位トランジスタＵｎｉｔ＿ＭＯＳの反復拡大の行本数ＲＧＳＭと列本数ＣＧＳＭと図８の右下に示したＲＦ電力増幅器５００の最終段増幅素子Ｑ２の単位トランジスタＵｎｉｔ＿ＭＯＳの反復拡大の行本数ＲＷＣＤＭＡと列本数ＣＷＣＤＭＡとの間には、ＲＧＳＭ＜ＲＷＣＤＭＡ、ＣＧＳＭ＞ＣＷＣＤＭＡの関係が成立する。 The number of rows R GSM and the number of columns C GSM of the unit transistor Unit_MOS of the final stage amplifying element Q3 of the RF power amplifier 100 shown in the upper part of FIG. 8 and the final stage of the RF power amplifier 500 shown in the lower right of FIG. A relationship of R GSM <R WCDMA and C GSM > C WCDMA is established between the number of rows R WCDMA and the number of columns C WCDMA of the repeated expansion of the unit transistor Unit_MOS of the amplifying element Q2.
　図９は、図８に示した本発明の実施の形態１によるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３が構成される具体的な様子を示す図である。 FIG. 9 is a diagram showing a specific state in which the large-amplifier final stage amplifying element Q3 of the GSM high-band RF power amplifier 100 according to Embodiment 1 of the present invention shown in FIG. 8 is configured.
　図９においては、簡素化のために、複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のゲート電極Ｇは、省略されている。更に複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のドレイン領域Ｄは、第１ドレイン配線ＤＭ１の下に存在しているので、図９の平面図から省略されている。図９に示すように、ゲートパッドＧＰ、ドレインパッドＤＰは、ボンディングワイヤＢＷ等によって半導体チップ１の外部と電気的に接続可能とされている。 In FIG. 9, for simplification, the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are omitted. Furthermore, since the plurality of drain regions D of the plurality of unit transistors Unit_MOS exist below the first drain wiring DM1, they are omitted from the plan view of FIG. As shown in FIG. 9, the gate pad GP and the drain pad DP can be electrically connected to the outside of the semiconductor chip 1 by bonding wires BW or the like.
　図９に示すように、半導体チップ１の上部長辺に配置されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３は、図８の左下に示した単位トランジスタＵｎｉｔ＿ＭＯＳをＸ方向の３行分反復拡大して、Ｙ方向の１２列分反復拡大することによって構成されている。すなわち、大素子サイズの最終段増幅素子Ｑ３は、大素子サイズの実現のための単位トランジスタＵｎｉｔ＿ＭＯＳの実質的な反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択される。 As shown in FIG. 9, the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 is formed by connecting the unit transistor Unit_MOS shown in the lower left of FIG. It is configured by repeatedly enlarging 3 rows in the direction and repeatedly enlarging 12 columns in the Y direction. That is, the final stage amplifying element Q3 having a large element size is selected in the direction of the BB ′ line which is the X direction of the semiconductor chip 1 in order to substantially repeat the expansion of the unit transistor Unit_MOS for realizing the large element size. .
　図１０は、図９に示した本発明の実施の形態１によるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３の具体的な構成の主要部を示す図である。 FIG. 10 is a diagram showing a main part of a specific configuration of the final stage amplifying element Q3 having a large element size of the GSM high band RF power amplifier 100 according to Embodiment 1 of the present invention shown in FIG.
　図１０に示すように、２本のゲート電極Ｇの中央部分に長方形に形成された１本のドレイン領域Ｄの上部に第１ドレイン配線ＤＭ１が形成され、２本のゲート電極Ｇは第１ドレイン配線ＤＭ１の下部に形成された第１ゲート配線ＧＭ１によって共通接続されている。 As shown in FIG. 10, a first drain wiring DM1 is formed on one drain region D formed in a rectangular shape at the center of the two gate electrodes G, and the two gate electrodes G serve as the first drain. They are commonly connected by a first gate line GM1 formed under the line DM1.
　図１１は、図８に示した本発明の実施の形態１によるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２が構成される具体的な様子を示す図である。 FIG. 11 is a diagram showing a specific state in which the large-amplifier final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 8 is configured.
　図１１においては、簡素化のために、複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のゲート電極Ｇは、省略されている。更に複数の単位トランジスタＵｎｉｔ＿ＭＯＳの複数のドレイン領域Ｄは、Ｘ方向であるＢ－Ｂ´線の方向に形成された複数の第１ドレイン配線ＤＭ１に接続されている。 In FIG. 11, for simplification, the plurality of gate electrodes G of the plurality of unit transistors Unit_MOS are omitted. Further, the plurality of drain regions D of the plurality of unit transistors Unit_MOS are connected to a plurality of first drain wirings DM1 formed in the direction of the BB ′ line that is the X direction.
　図１１に示すように、半導体チップ１の右部短辺に配置されるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２は、図８の左下に示した単位トランジスタＵｎｉｔ＿ＭＯＳをＸ方向の１２行分反復拡大して、Ｙ方向の５列分反復拡大することによって構成されている。すなわち、大素子サイズの最終段増幅素子Ｑ２は、大素子サイズの実現のための単位トランジスタＵｎｉｔ＿ＭＯＳの実質的な反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される。 As shown in FIG. 11, the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 arranged on the right short side of the semiconductor chip 1 is the unit transistor Unit_MOS shown in the lower left of FIG. It is configured by iteratively enlarging for 12 rows in the direction and repeatedly enlarging for 5 columns in the Y direction. That is, the final stage amplifying element Q2 having a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1 in order to substantially repeat the enlargement of the unit transistor Unit_MOS for realizing the large element size. .
　また、図９に示したＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３と図１１に示したＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２とでも、ＲＧＳＭ(３行)＜ＲＷＣＤＭＡ(１２行)、ＣＧＳＭ(１２列)＞ＣＷＣＤＭＡ(５列)の関係が成立することが理解される。 Also, the large element size final stage amplifying element Q3 of the GSM high band RF power amplifier 100 shown in FIG. 9 and the large element size final stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 shown in FIG. , R GSM (3 rows) <R WCDMA (12 rows), C GSM (12 columns)> C WCDMA (5 columns).
　図１２は、図１１に示した本発明の実施の形態１によるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２の具体的な構成の主要部を示す図である。 FIG. 12 is a diagram showing a main part of a specific configuration of the final stage amplifying element Q2 having a large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG.
　図１２に示すように２本のゲート電極Ｇの中央部分に長方形に形成されたドレイン領域Ｄは、コンタクト開口部ＣＮＴを介して第１ドレイン配線ＤＭ１に接続され、２本のゲート電極Ｇは第１ドレイン配線ＤＭ１と平行に形成された第１ゲート配線ＧＭ１によって共通接続されている。 As shown in FIG. 12, the drain region D formed in a rectangular shape in the center portion of the two gate electrodes G is connected to the first drain wiring DM1 through the contact opening CNT, and the two gate electrodes G are connected to the first gate electrode G. The first gate wiring GM1 formed in parallel with the one drain wiring DM1 is commonly connected.
　図１２から明らかなように、Ｙ方向であるＡ－Ａ´線の方向に形成されるＬＤＭＯＳＦＥＴのゲート電極ＧとＸ方向であるＢ－Ｂ´線の方向に形成された複数の第１ドレイン配線ＤＭ１とは、立体的に交差する。図１２の平面図で平行に形成された第１ゲート配線ＧＭ１と第１ドレイン配線ＤＭ１との間の平面距離よりも、ゲート電極Ｇと第１ドレイン配線ＤＭ１との間の断面距離の方が小さくなる。 As is apparent from FIG. 12, the gate electrode G of the LDMOSFET formed in the direction of the AA ′ line which is the Y direction and a plurality of first drain wirings formed in the direction of the BB ′ line which is the X direction. DM1 crosses three-dimensionally. The cross-sectional distance between the gate electrode G and the first drain wiring DM1 is smaller than the planar distance between the first gate wiring GM1 and the first drain wiring DM1 formed in parallel in the plan view of FIG. Become.
　従って、高周波増幅素子としてのＬＤＭＯＳＦＥＴの高周波特性を決定するゲート・ドレイン帰還容量が第１ゲート配線ＧＭ１と第１ドレイン配線ＤＭ１との間の平面距離ではなく、ゲート電極Ｇと第１ドレイン配線ＤＭ１との間の断面距離によって支配的に決定され、ゲート・ドレイン帰還容量の値が増大する危険性がある。良く知られているようにゲート・ドレイン帰還容量の値が増大すると、ＬＤＭＯＳＦＥＴの高周波特性は劣化する。 Therefore, the gate / drain feedback capacitance that determines the high-frequency characteristics of the LDMOSFET as the high-frequency amplifier is not the plane distance between the first gate wiring GM1 and the first drain wiring DM1, but the gate electrode G and the first drain wiring DM1. There is a risk that the value of the gate-drain feedback capacitance increases, which is dominantly determined by the cross-sectional distance between the two. As is well known, when the value of the gate-drain feedback capacitance increases, the high frequency characteristics of the LDMOSFET deteriorate.
　この問題を解消するために、ＬＤＭＯＳＦＥＴのゲート電極Ｇと第１ドレイン配線ＤＭ１が立体的に交差する部分において、接地電圧ＧＮＤに接続されるソース領域Ｓと電気的に接続されるソース配線が静電シールド層として機能する。すなわち、静電シールド層として機能するソース配線が、立体交差の部分においてＬＤＭＯＳＦＥＴのゲート電極Ｇと第１ドレイン配線ＤＭ１との間に形成される。 In order to solve this problem, the source wiring electrically connected to the source region S connected to the ground voltage GND is electrostatically connected at a portion where the gate electrode G of the LDMOSFET and the first drain wiring DM1 intersect three-dimensionally. Functions as a shield layer. That is, the source wiring functioning as an electrostatic shield layer is formed between the gate electrode G of the LDMOSFET and the first drain wiring DM1 at the three-dimensional intersection.
　図１３は、図１２に示す本発明の実施の形態１によるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２のＬＤＭＯＳＦＥＴのゲート電極Ｇと第１ドレイン配線ＤＭ１が立体的に交差する部分において、接地電圧ＧＮＤに接続されるソース領域Ｓと電気的に接続されるソース配線が静電シールド層として機能する様子を示す断面図である。 13 shows a three-dimensional intersection of the gate electrode G of the LDMOSFET of the final stage amplifying element Q2 of the large element size of the WCDMA low-band RF power amplifier 500 according to the first embodiment of the present invention shown in FIG. 12 and the first drain wiring DM1. FIG. 6 is a cross-sectional view showing a state where a source wiring electrically connected to a source region S connected to a ground voltage GND functions as an electrostatic shield layer in a portion to be operated.
　図１３に示す断面構造は、図２に示した断面構造の上部に窒化シリコン膜２０と酸化シリコン膜２１とが形成されたものである。窒化シリコン膜２０と酸化シリコン膜２１には複数のコンタクトホール２２が形成され、複数のコンタクトホール２２の内部に第１プラグ配線２３が形成される。 The cross-sectional structure shown in FIG. 13 is obtained by forming a silicon nitride film 20 and a silicon oxide film 21 on top of the cross-sectional structure shown in FIG. A plurality of contact holes 22 are formed in the silicon nitride film 20 and the silicon oxide film 21, and a first plug wiring 23 is formed inside the plurality of contact holes 22.
　ＬＤＭＯＳＦＥＴのソース領域ＳのＮ＋型ソース領域１６とＰ＋型半導体領域１７は、複数の第１プラグ配線２３を介して、第１ソース配線としてのソース電極２４Ａに電気的に接続される。またＬＤＭＯＳＦＥＴのドレイン領域ＤのＮ＋型ドレイン領域１５は、第１プラグ配線２３を介して、ドレイン電極２４Ｂに電気的に接続される。 The N + type source region 16 and the P + type semiconductor region 17 of the source region S of the LDMOSFET are electrically connected to a source electrode 24A as a first source wiring via a plurality of first plug wirings 23. Further, the N + type drain region 15 of the drain region D of the LDMOSFET is electrically connected to the drain electrode 24B through the first plug wiring 23.
　ソース電極２４Ａとドレイン電極２４Ｂの上部に、第１層間シリコン酸化膜２６が形成される。ドレイン電極２４Ｂの上部の第１層間シリコン酸化膜２６には、スルーホール２７が形成され、スルーホール２７の内部に第２プラグ配線２８が形成される。第２プラグ配線２８の上部には、第２ドレイン電極２９Ｂが形成される。第２ドレイン電極２９Ｂの上部に第２層間シリコン酸化膜３０が形成され、第２ドレイン電極２９Ｂの上部の第２層間シリコン酸化膜３０には、スルーホール３１(コンタクト開口部ＣＮＴ)が形成されて、スルーホール３１の内部に第３プラグ配線３２が形成される。第３プラグ配線３２には、第１ドレイン配線ＤＭ１としての配線層３３が形成される。このように、下部のＬＤＭＯＳＦＥＴのゲート電極Ｇ(７)の上部をソース電極２４Ａがオーバーラップしているので、下部のＬＤＭＯＳＦＥＴのゲート電極Ｇ(７)と上部の第１ドレイン配線ＤＭ１(配線層３３)との間をソース電極２４Ａが静電シールド層として効果的に機能するシールドするものである。更に、第１ドレイン配線ＤＭ１(配線層３３)の上部には、酸化シリコン膜３４と窒化シリコン膜３５とがファイナルパッシベーション膜として形成される。 A first interlayer silicon oxide film 26 is formed on the source electrode 24A and the drain electrode 24B. A through hole 27 is formed in the first interlayer silicon oxide film 26 above the drain electrode 24 B, and a second plug wiring 28 is formed inside the through hole 27. A second drain electrode 29B is formed on the second plug wiring 28. A second interlayer silicon oxide film 30 is formed on the second drain electrode 29B, and a through hole 31 (contact opening CNT) is formed in the second interlayer silicon oxide film 30 on the second drain electrode 29B. A third plug wiring 32 is formed in the through hole 31. In the third plug wiring 32, a wiring layer 33 as the first drain wiring DM1 is formed. Thus, since the source electrode 24A overlaps the upper part of the gate electrode G (7) of the lower LDMOSFET, the gate electrode G (7) of the lower LDMOSFET and the upper first drain wiring DM1 (wiring layer 33). ) Is shielded so that the source electrode 24A effectively functions as an electrostatic shield layer. Further, a silicon oxide film 34 and a silicon nitride film 35 are formed as a final passivation film on the first drain wiring DM1 (wiring layer 33).
　図１４は、図９と図１０とに示した図７の半導体チップ１の上部長辺に配置されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大素子サイズの最終段増幅素子Ｑ３の特性と図１１と図１２とに示した図７の半導体チップ１の右部短辺に配置されるＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大素子サイズの最終段増幅素子Ｑ２の特性とを同一のゲート幅と同一のゲート長とで比較した図である。 14 shows the characteristics of the final stage amplifying element Q3 having a large element size of the GSM type high band RF power amplifier 100 arranged on the upper long side of the semiconductor chip 1 of FIG. 7 shown in FIG. 9 and FIG. And the characteristics of the large-amplifier final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 disposed on the short right side of the semiconductor chip 1 of FIG. 7 shown in FIG. 12 and the same gate width. It is the figure compared by gate length.
　図１４に示すように、オン抵抗Ｒｏｎと入力容量Cｉｓｓと出力容量Ｃｏｓｓとに関しては、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅素子Ｑ３とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅素子Ｑ２は同等の特性となっている。しかし、帰還容量Ｃｒｓｓに関しては、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅素子Ｑ３よりＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅素子Ｑ２の方が１８％改善されている。ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅素子Ｑ２の方がＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅素子Ｑ３よりも帰還容量Ｃｒｓｓが小さいのは、図１１と図１２とで説明したソース電極２４Ａによる第１ドレイン配線ＤＭとゲート電極Ｇ(７)との間の静電シールド効果と、図１１から明らかなように第１ゲート配線ＧＭ１と第１ドレイン配線ＤＭとが平行に配置され、第１ゲート配線ＧＭ１と第１ドレイン配線ＤＭ１とが交差しないためである。それに対して、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅素子Ｑ３では、図９から明らかなように第１ゲート配線ＧＭ１と第１ドレイン配線ＤＭ１とが直交して配置され、第１ゲート配線ＧＭ１と第１ドレイン配線ＤＭ１とが交差しているため、帰還容量Ｃｒｓｓが増加するものである。 As shown in FIG. 14, regarding the on-resistance Ron, the input capacitance Ciss, and the output capacitance Coss, the final stage amplifying element Q3 of the GSM high-band RF power amplifier 100 and the final stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 are shown. Have equivalent characteristics. However, regarding the feedback capacitance Crss, the final stage amplifying element Q2 of the WCDMA low band RF power amplifier 500 is improved by 18% over the final stage amplifying element Q3 of the GSM high band RF power amplifier 100. The last stage amplifying element Q2 of the WCDMA low-band RF power amplifier 500 has a smaller feedback capacity Crss than the last stage amplifying element Q3 of the GSM high-band RF power amplifier 100. The source described in FIGS. The electrostatic shield effect between the first drain wiring DM and the gate electrode G (7) by the electrode 24A and the first gate wiring GM1 and the first drain wiring DM are arranged in parallel as apparent from FIG. This is because the first gate line GM1 and the first drain line DM1 do not intersect. On the other hand, in the final stage amplifying element Q3 of the GSM high band RF power amplifier 100, as is apparent from FIG. 9, the first gate wiring GM1 and the first drain wiring DM1 are arranged orthogonally, and the first gate wiring Since GM1 and the first drain wiring DM1 intersect, the feedback capacitance Crss increases.
　従って、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅素子Ｑ２がＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅素子Ｑ３よりも帰還容量Ｃｒｓｓが小さいので、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅素子Ｑ２の電力付加効率が３％程度改善されるものとなる。 Therefore, since the final stage amplification element Q2 of the WCDMA low-band RF power amplifier 500 has a smaller feedback capacity Crss than the final stage amplification element Q3 of the GSM high-band RF power amplifier 100, the final-stage amplification of the WCDMA low-band RF power amplifier 500 is performed. The power added efficiency of the element Q2 is improved by about 3%.
　更に、図７に示した本発明の実施の形態１による半導体集積回路の半導体チップ１では、半導体チップ１の左部短辺に配置されたＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２と、半導体チップ１の右部短辺にＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２とは、図１１と図１２と図１３で説明した素子構造によって形成され、静電シールド層として機能するソース電極２４Ａが、下部のＬＤＭＯＳＦＥＴのゲート電極Ｇ(７)と上部の第１ドレイン配線ＤＭ１(配線層３３)との間を効果的にシールドすることが可能となる。 Furthermore, in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 7, the plurality of LDMOSFETs Q1, Q2 of the WCDMA high-band RF power amplifier 400 disposed on the left short side of the semiconductor chip 1 The plurality of LDMOSFETs Q1 and Q2 of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1 are formed by the element structure described in FIGS. 11, 12, and 13 and function as an electrostatic shield layer. Thus, the source electrode 24A can effectively shield between the gate electrode G (7) of the lower LDMOSFET and the upper first drain wiring DM1 (wiring layer 33).
　《半導体チップの他の構成》
　図１５は、本発明の実施の形態１による半導体集積回路の半導体チップ１の他の構成を示す図である。 <Other configuration of semiconductor chip>
FIG. 15 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
　図１５に示した半導体集積回路の半導体チップ１が、図７から図１４まで説明した本発明の実施の形態１による半導体集積回路の半導体チップ１と相違するのは、下記の点である。 The semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15 is different from the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described in FIGS. 7 to 14 in the following points.
　すなわち、図１５に示した本発明の実施の形態１による半導体集積回路の半導体チップ１では、長方形の半導体チップ１の上部長辺にはバイアス制御部３００の複数の入力端子のパッドが半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されている。 That is, in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 15, pads of the plurality of input terminals of the bias control unit 300 are provided on the upper long side of the rectangular semiconductor chip 1. Are arranged in the direction of the line BB ′, which is the X direction.
　その他に関しては、図１５に示した半導体集積回路の半導体チップ１は、図７から図１４まで説明した本発明の実施の形態１による半導体集積回路の半導体チップ１と同一である。従って、図１５に示した半導体集積回路の半導体チップ１では、図７に示した半導体集積回路の半導体チップ１と同様に、ＧＳＭ方式ローバンドＲＦ電力増幅器２００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３は半導体チップ１の下部長辺にＸ方向であるＢ－Ｂ´線の方向に配置され、ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２は半導体チップ１の左部短辺にＹ方向であるＡ－Ａ´線の方向に配置され、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２は半導体チップ１の右部短辺にＹ方向であるＡ－Ａ´線の方向に配置されている。 In other respects, the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15 is the same as the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. Therefore, in the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 15, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM type low-band RF power amplifier 200 are the same as the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. The plurality of LDMOSFETs Q1 and Q2 of the WCDMA high-band RF power amplifier 400 are arranged in the direction of the BB ′ line which is the X direction on the lower long side of the A, and the A in the Y direction is on the left short side of the semiconductor chip 1. A plurality of LDMOSFETs Q 1 and Q 2 of the WCDMA low-band RF power amplifier 500 are arranged in the direction of the AA line, and are arranged in the direction of the AA ′ line which is the Y direction on the short side of the right side of the semiconductor chip 1.
　図１６は、本発明の実施の形態１による半導体集積回路の半導体チップ１の他の構成を示す図である。 FIG. 16 is a diagram showing another configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention.
　図１６に示した半導体集積回路の半導体チップ１が、図７から図１４まで説明した本発明の実施の形態１による半導体集積回路の半導体チップ１と相違するのは、下記の点である。 The semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16 is different from the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. 7 to 14 in the following points.
　すなわち、図１６に示した本発明の実施の形態１による半導体集積回路の半導体チップ１では、バイアス制御部３００のブロックは半導体チップ１の左部短辺の方向に移動されて、長方形の半導体チップ１の下部長辺にはバイアス制御部３００の複数の入力端子のパッドが半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されている。 That is, in the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 16, the block of the bias control unit 300 is moved in the direction of the left short side of the semiconductor chip 1 to form a rectangular semiconductor chip. A pad of a plurality of input terminals of the bias control unit 300 is arranged on the lower long side of 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
　その他に関しては、図１６に示した半導体集積回路の半導体チップ１は、図７から図１４まで説明した本発明の実施の形態１による半導体集積回路の半導体チップ１と同一である。従って、図１６に示した半導体集積回路の半導体チップ１では、図７に示した半導体集積回路の半導体チップ１と同様に、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２、Ｑ３は半導体チップ１の上部長辺にＸ方向であるＢ－Ｂ´線の方向に配置され、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の複数のＬＤＭＯＳＦＥＴＱ１、Ｑ２は半導体チップ１の右部短辺にＹ方向であるＡ－Ａ´線の方向に配置されている。 In other respects, the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16 is the same as the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention described with reference to FIGS. Therefore, in the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. 16, the plurality of LDMOSFETs Q1, Q2, and Q3 of the GSM type high-band RF power amplifier 100 are the same as the semiconductor chip 1 of the semiconductor integrated circuit shown in FIG. A plurality of LDMOSFETs Q1 and Q2 of the WCDMA low-band RF power amplifier 500 are arranged on the upper long side of the chip 1 in the direction of the BB ′ line which is the X direction. -A 'line direction.
　［実施の形態２］
　《バイポーラトランジスタの平面構造および断面構造》
　図１７は、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるプレーナ型バイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの平面構造と断面構造とを示す図である。 [Embodiment 2]
<< Planar structure and sectional structure of bipolar transistor >>
FIG. 17 is a diagram showing a planar structure and a sectional structure of a unit transistor Unit_TRS of a planar bipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
　図１７の平面構造に示すようにプレーナ型バイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳでは、中央部分に長方形のエミッタ電極Ｅが形成されて、エミッタ電極Ｅの外部にはベース電極Ｂが形成されて、ベース電極Ｂの外部にはコレクタ電極Ｃが形成されている。図１７の平面構造において、エミッタ電極Ｅとベース電極Ｂの間の破線はエミッタ・ベース接合の平面形状を示し、ベース電極Ｂとコレクタ電極Ｃの間の破線はベース・コレクタ接合の平面形状を示し、コレクタ電極Ｃの外部の破線はＮ型コレクタ領域の平面形状を示している。 As shown in the planar structure of FIG. 17, in the unit transistor Unit_TRS of the planar bipolar transistor, a rectangular emitter electrode E is formed at the center, and a base electrode B is formed outside the emitter electrode E. A collector electrode C is formed on the outside. In the planar structure of FIG. 17, the broken line between the emitter electrode E and the base electrode B indicates the planar shape of the emitter-base junction, and the broken line between the base electrode B and the collector electrode C indicates the planar shape of the base-collector junction. The broken line outside the collector electrode C indicates the planar shape of the N-type collector region.
　図１７の断面構造に示すように、エミッタ電極ＥはＮ＋型エミッタ領域とオーミック接触によって電気的に接続され、ベース電極ＢはＰ型ベース領域とオーミック接触によって電気的に接続され、コレクタ電極ＣはＮ＋型高不純物コレクタ領域とのオーミック接触によってＮ型コレクタ領域と電気的に接続される。尚、Ｎ型コレクタ領域の下部には、半導体集積回路のＰ型サブストレートが形成されている。図１７の断面構造において、Ｎ＋型エミッタ領域とＰ型ベース領域とＮ型コレクタ領域とＰ型サブストレートには、シリコンが使用されている。 As shown in the cross-sectional structure of FIG. 17, the emitter electrode E is electrically connected to the N + -type emitter region by ohmic contact, the base electrode B is electrically connected to the P-type base region by ohmic contact, and the collector electrode C Are electrically connected to the N-type collector region by ohmic contact with the N + -type high impurity collector region. A P-type substrate of a semiconductor integrated circuit is formed below the N-type collector region. In the cross-sectional structure of FIG. 17, silicon is used for the N + -type emitter region, the P-type base region, the N-type collector region, and the P-type substrate.
　図１７に示すプレーナ型バイポーラトランジスタでは、エミッタ電流はエミッタ・ベース接合の断面構造の平坦部分よりも角部分に大きな電流密度で流れる。これは、トランジスタのエッジ効果として良く知られ、エミッタ・ベース接合の角部分における電界集中に起因するものである。 In the planar bipolar transistor shown in FIG. 17, the emitter current flows at a larger current density in the corner portion than in the flat portion of the cross-sectional structure of the emitter-base junction. This is well known as the edge effect of a transistor, and is caused by electric field concentration at the corner of the emitter-base junction.
　図１７に示すプレーナ型バイポーラトランジスタの増幅ゲインのコンダクタンスは、トランジスタのエミッタサイズに比例することも良く知られている。プレーナ型バイポーラトランジスタのエミッタサイズは、エミッタ面積の大きさよりも上述したエッジ効果によってエミッタ・ベース接合の平面構造での周辺距離の長さによって支配的に決定される。 It is well known that the conductance of the amplification gain of the planar bipolar transistor shown in FIG. 17 is proportional to the emitter size of the transistor. The emitter size of the planar bipolar transistor is determined more dominantly by the length of the peripheral distance in the planar structure of the emitter-base junction by the edge effect than the size of the emitter area.
　従って、図１７に示したプレーナ型バイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの増幅ゲインのコンダクタンスを大きくするために、トランジスタの平面構造のエミッタ領域を長方形とすることによって無駄なエミッタ領域の平坦部分を低減する一方、有益なエミッタ・ベース接合の平面構造での周辺距離の長さを増大するものである。一方、バイポーラトランジスタでは、大きな素子サイズの実現のために単位トランジスタの反復拡大がなされ、反復拡大は複数の単位トランジスタの並列接続によって実現される。 Therefore, in order to increase the conductance of the amplification gain of the unit transistor Unit_TRS of the planar bipolar transistor shown in FIG. 17, the flat area of the useless emitter region is reduced by making the emitter region of the planar structure of the transistor rectangular. This increases the length of the peripheral distance in a useful emitter-base junction planar structure. On the other hand, in the bipolar transistor, the unit transistor is repeatedly expanded in order to realize a large element size, and the repeated expansion is realized by parallel connection of a plurality of unit transistors.
　図１８は、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００のトランジスタＱ１、Ｑ２、Ｑ３とＧＳＭ方式ローバンドＲＦ電力増幅器２００のトランジスタＱ１、Ｑ２、Ｑ３の各ＲＦ電力増幅トランジスタの平面構造を示す図である。 FIG. 18 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 and transistor Q1 of the GSM low-band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a figure which shows the planar structure of each RF power amplification transistor of Q2, Q2, and Q3.
　図１８に示すように、１個のＲＦ電力増幅トランジスタは、図１７に示したプレーナ型バイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳを複数個、Ｘ方向であるＢ－Ｂ´線の方向に反復拡大される。 As shown in FIG. 18, in one RF power amplification transistor, a plurality of unit transistors Unit_TRS of the planar bipolar transistor shown in FIG. 17 are repeatedly expanded in the direction of the BB ′ line which is the X direction.
　一方、図１７に示したバイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの増幅ゲインのコンダクタンスも、エミッタ・ベース接合の平面構造での周辺距離の長さのバラツキにより変動する。その理由は、半導体チップの製造工程での平面構造の長方形のエミッタ領域形成のホトリソグラフィーで、Ｘ方向とＹ方向とでそれぞれ異なった寸法偏差を持つからである。 On the other hand, the conductance of the amplification gain of the unit transistor Unit_TRS of the bipolar transistor shown in FIG. 17 also varies due to variations in the length of the peripheral distance in the planar structure of the emitter-base junction. The reason is that, in the photolithography for forming a rectangular emitter region having a planar structure in the manufacturing process of the semiconductor chip, the X direction and the Y direction have different dimensional deviations.
　従って、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００のトランジスタＱ１、Ｑ２、Ｑ３とＧＳＭ方式ローバンドＲＦ電力増幅器２００のトランジスタＱ１、Ｑ２、Ｑ３とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００のトランジスタＱ１、Ｑ２とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００のトランジスタＱ１、Ｑ２の全てのトランジスタの平面構造のエミッタ領域の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一される。従って、半導体チップ１の製造工程のバラツキに依存する４系統のＲＦ電力増幅器１００、２００、４００、５００の全てのバイポーラトランジスタＱ１、Ｑ２、Ｑ３の各増幅ゲインのコンダクタンスの相対的なバラツキを、低減することが可能となる。 Therefore, the transistors Q1, Q2, Q3 of the GSM high band RF power amplifier 100 and the transistors Q1, Q2 of the GSM low band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. , Q3 and WCDMA high-band RF power amplifier 400 transistors Q1 and Q2 and WCDMA low-band RF power amplifier 500 transistors Q1 and Q2 of all transistors in the planar structure of the emitter region of the rectangular long side extending direction is semiconductor The direction of the AA ′ line that is the Y direction of the chip 1 is unified. Therefore, the relative variation in the conductance of each amplification gain of all the bipolar transistors Q1, Q2, Q3 of the four RF power amplifiers 100, 200, 400, 500 depending on the variation in the manufacturing process of the semiconductor chip 1 is reduced. It becomes possible to do.
　一方、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅トランジスタＱ３の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大と、ＧＳＭ方式ローバンドＲＦ電力増幅器２００の最終段増幅トランジスタＱ３の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大とは、半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択される。更にＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の最終段増幅トランジスタＱ２の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大と、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅トランジスタＱ２の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大とは、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される。 On the other hand, the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM high-band RF power amplifier 100 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM low-band RF power amplifier 200 are a semiconductor chip. 1 is selected in the direction of the BB ′ line, which is the X direction. Further, the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA high-band RF power amplifier 400 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA low-band RF power amplifier 500 are the semiconductor chip 1 Is selected in the direction of the line AA ′, which is the Y direction.
　《ヘテロバイポーラトランジスタの平面構造および断面構造》
　図１９は、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるメサ型ヘテロバイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの平面構造と断面構造とを示す図である。 << Planar structure and cross-sectional structure of heterobipolar transistor >>
FIG. 19 is a diagram showing a planar structure and a cross-sectional structure of a unit transistor Unit_TRS of a mesa type heterobipolar transistor integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
　図１９の平面構造に示すようにメサ型ヘテロバイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳでは、中央部分に長方形のエミッタ電極Ｅが形成され、エミッタ電極Ｅの外部にはベース電極Ｂが形成されて、ベース電極Ｂの外部にはコレクタ電極Ｃが形成されている。図１９の平面構造において、エミッタ電極Ｅとベース電極Ｂの間の破線はエミッタ・ベース接合の平面形状を示し、ベース電極Ｂとコレクタ電極Ｃの間の破線はベース・コレクタ接合の平面形状を示し、コレクタ電極Ｃの外部の破線はＮ型コレクタ領域の平面形状を示している。 As shown in the planar structure of FIG. 19, in the unit transistor Unit_TRS of the mesa type heterobipolar transistor, a rectangular emitter electrode E is formed in the center portion, and a base electrode B is formed outside the emitter electrode E. A collector electrode C is formed on the outside. In the planar structure of FIG. 19, the broken line between the emitter electrode E and the base electrode B indicates the planar shape of the emitter-base junction, and the broken line between the base electrode B and the collector electrode C indicates the planar shape of the base-collector junction. The broken line outside the collector electrode C indicates the planar shape of the N-type collector region.
　図１９の断面構造に示すように、エミッタ電極Ｅはメサ構造の最上層であるＮ＋型エミッタ領域とオーミック接触によって電気的に接続され、ベース電極Ｂはメサ構造の中間層であるＰ型ベース領域とオーミック接触によって電気的に接続され、コレクタ電極Ｃはメサ構造の最下層であるＮ型コレクタ領域とオーミック接触によって電気的に接続される。尚、Ｎ型コレクタ領域の下部には、半導体集積回路の高抵抗率の半絶縁性基板Ｓｕｂが形成されている。図１９の断面構造において、メサ構造の最上層であるＮ＋型エミッタ領域と中間層であるＰ型ベース領域と最下層であるＮ型コレクタ領域と半絶縁性基板には、例えばＧａＡｓ等の化合物半導体が使用される。 As shown in the cross-sectional structure of FIG. 19, the emitter electrode E is electrically connected to the N + -type emitter region which is the uppermost layer of the mesa structure by ohmic contact, and the base electrode B is a P-type base which is an intermediate layer of the mesa structure. The region is electrically connected to the region by ohmic contact, and the collector electrode C is electrically connected to the N-type collector region which is the lowermost layer of the mesa structure by ohmic contact. Note that a semi-insulating substrate Sub having a high resistivity of the semiconductor integrated circuit is formed below the N-type collector region. In the cross-sectional structure of FIG. 19, an N + -type emitter region that is the uppermost layer of the mesa structure, a P-type base region that is the intermediate layer, an N-type collector region that is the lowermost layer, and a semi-insulating substrate include a compound such as GaAs. A semiconductor is used.
　図１９に示したメサ型ヘテロバイポーラトランジスタでも、上述したエッジ効果によってエミッタ電流はエミッタ・ベース接合の断面構造の平坦部分よりも角部分に大きな電流密度で流れる。また図１９に示したメサ型ヘテロバイポーラトランジスタの増幅ゲインのコンダクタンスも、トランジスタのエミッタサイズに比例する。メサ型ヘテロバイポーラトランジスタのエミッタサイズは、エミッタ面積の大きさよりも上述したエッジ効果によってエミッタ・ベース接合の平面構造での周辺距離の長さによって支配的に決定される。 In the mesa type hetero bipolar transistor shown in FIG. 19, the emitter current flows at a larger current density in the corner portion than in the flat portion of the cross-sectional structure of the emitter-base junction due to the edge effect described above. Further, the conductance of the amplification gain of the mesa heterobipolar transistor shown in FIG. 19 is also proportional to the emitter size of the transistor. The emitter size of the mesa type heterobipolar transistor is determined more dominantly by the length of the peripheral distance in the planar structure of the emitter-base junction than the size of the emitter area due to the edge effect described above.
　従って、図１９に示すメサ型ヘテロバイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの増幅ゲインのコンダクタンスを大きくするために、トランジスタの平面構造のエミッタ領域を長方形とすることによって無駄なエミッタ領域の平坦部分を低減する一方、有益なエミッタ・ベース接合の平面構造での周辺距離の長さを増大するものである。一方、バイポーラトランジスタでは、大きな素子サイズの実現のために単位トランジスタの反復拡大がなされ、反復拡大は複数の単位トランジスタの並列接続によって実現される。 Accordingly, in order to increase the conductance of the amplification gain of the unit transistor Unit_TRS of the mesa type heterobipolar transistor shown in FIG. 19, the flat area of the useless emitter region is reduced by making the emitter region of the planar structure of the transistor rectangular. This increases the length of the peripheral distance in a useful emitter-base junction planar structure. On the other hand, in the bipolar transistor, the unit transistor is repeatedly expanded in order to realize a large element size, and the repeated expansion is realized by parallel connection of a plurality of unit transistors.
　図２０は、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００のトランジスタＱ１、Ｑ２、Ｑ３とＧＳＭ方式ローバンドＲＦ電力増幅器２００のトランジスタＱ１、Ｑ２、Ｑ３の各ＲＦ電力増幅メサ型ヘテロトランジスタの平面構造を示す図である。 FIG. 20 shows transistors Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention, and the transistor Q1 of the GSM low-band RF power amplifier 200. FIG. 3 is a diagram showing a planar structure of each RF power amplification mesa heterotransistor of Q2, Q2, and Q3.
　図２０に示すように、１個のＲＦ電力増幅メサ型ヘテロトランジスタは、図１９に示したサ型ヘテロバイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳを複数個、Ｘ方向であるＢ－Ｂ´線の方向に反復拡大される
　一方、図１９に示したメサ型ヘテロバイポーラトランジスタの単位トランジスタＵｎｉｔ＿ＴＲＳの増幅ゲインのコンダクタンスも、エミッタ・ベース接合の平面構造での周辺距離の長さのバラツキにより変動する。その理由は、半導体チップの製造工程での平面構造の長方形のエミッタ領域形成のホトリソグラフィーでＸ方向とＹ方向とでそれぞれ異なった寸法偏差を持つだけではなく、メサ型台形形状がメサ型エミッタ領域の長方形の長辺の延長方向の相違によって偏差を持つからである。このように、メサ型エミッタ領域のメサ型台形形状が長辺の延長方向の相違によって偏差を持つのは、メサ型台形形状の形成の際の化学エッチングの際の異方性エッチングに起因するものである。すなわち、メサ型台形の複数の側面にて、化学エッチングのエッチ速度が相違するものである。 As shown in FIG. 20, one RF power amplification mesa type heterotransistor repeats a plurality of unit transistors Unit_TRS of the sa type heterobipolar transistor shown in FIG. 19 in the direction of the BB ′ line which is the X direction. On the other hand, the conductance of the amplification gain of the unit transistor Unit_TRS of the mesa heterobipolar transistor shown in FIG. 19 also varies depending on the variation in the length of the peripheral distance in the planar structure of the emitter-base junction. The reason for this is that not only does the X-direction and the Y-direction have different dimensional deviations in the photolithography for forming a rectangular emitter region having a planar structure in the manufacturing process of the semiconductor chip, but the mesa-type trapezoidal shape has a mesa-type emitter region. This is because there is a deviation due to the difference in the extending direction of the long side of the rectangle. As described above, the mesa-type trapezoidal shape of the mesa-type emitter region has a deviation due to the difference in the extension direction of the long side due to the anisotropic etching at the time of chemical etching at the time of forming the mesa-type trapezoidal shape. It is. That is, the etching rates of chemical etching are different on a plurality of side surfaces of the mesa trapezoid.
　図２１は、ＧａＡｓ化合物半導体基板の（１００）結晶面の上部に形成されるメサ型エミッタ領域のメサ型台形形状がメサ型エミッタ領域の長方形の長辺の延長方向の相違によって変化する様子を示す図である。 FIG. 21 shows how the mesa-type trapezoidal shape of the mesa-type emitter region formed above the (100) crystal plane of the GaAs compound semiconductor substrate changes depending on the extension direction of the long side of the rectangle of the mesa-type emitter region. FIG.
　図２１の上部には、メサ型エミッタ領域の長方形の長辺の延長方向がＹ方向であるＡ－Ａ´線の方向に選択された場合(エミッタ長さ方位Ａ)と、メサ型エミッタ領域の長方形の長辺の延長方向がＸ方向であるＢ－Ｂ´線の方向に選択された場合(エミッタ長さ方位Ｂ)とが示されている。 In the upper part of FIG. 21, when the extension direction of the long side of the rectangle of the mesa emitter region is selected in the direction of the AA ′ line which is the Y direction (emitter length direction A), the mesa emitter region The case where the extension direction of the long side of the rectangle is selected in the direction of the BB ′ line which is the X direction (emitter length direction B) is shown.
　図２１の下部には、メサ型エミッタ領域の長方形の長辺の延長方向がＹ方向であるＡ－Ａ´線の方向に選択された場合(エミッタ長さ方位Ａ)のａ－ａ´線での断面と、サ型エミッタ領域の長方形の長辺の延長方向がＸ方向であるＢ－Ｂ´線の方向に選択された場合(エミッタ長さ方位Ｂ)のｂ－ｂ´線での断面とが示されている。 In the lower part of FIG. 21, when the extension direction of the long side of the rectangle of the mesa emitter region is selected in the direction of the AA ′ line which is the Y direction (emitter length azimuth A), the aa ′ line And a cross section taken along the line bb ′ when the extension direction of the long side of the rectangular shape of the sub-emitter region is selected in the direction of the BB ′ line which is the X direction (emitter length direction B) It is shown.
　ａ－ａ´線での断面でのメサ型台形形状は上辺よりも下辺が短いので、図２１の上部のエミッタ長さ方位Ａに示すように周辺距離の長さが長くなり、メサ型ヘテロバイポーラトランジスタの増幅ゲインのコンダクタンスの値は大きくなる。ｂ－ｂ´線での断面でのメサ型台形形状は上辺よりも下辺が長いので、図２０の上部のエミッタ長さ方位Ｂに示すように周辺距離の長さが短くなり、メサ型ヘテロバイポーラトランジスタの増幅ゲインのコンダクタンスの値は小さくなる。尚、台形形状の上辺が長い形状は逆メサと呼ばれ、台形形状の上辺が短い形状は順メサと呼ばれている。 Since the mesa trapezoidal shape in the cross section along the line aa ′ has a shorter lower side than the upper side, the length of the peripheral distance becomes longer as shown in the emitter length direction A in the upper part of FIG. The conductance value of the amplification gain of the transistor increases. Since the mesa type trapezoidal shape in the cross section along the line bb ′ has a lower side longer than the upper side, the length of the peripheral distance becomes shorter as shown in the emitter length direction B in the upper part of FIG. The conductance value of the amplification gain of the transistor becomes small. A shape having a long upper side of the trapezoidal shape is called an inverted mesa, and a shape having a short upper side of the trapezoidal shape is called a forward mesa.
　従って、本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００のメサ型ヘテロバイポーラトランジスタＱ１、Ｑ２、Ｑ３とＧＳＭ方式ローバンドＲＦ電力増幅器２００のメサ型ヘテロバイポーラトランジスタＱ１、Ｑ２、Ｑ３とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００のメサ型ヘテロバイポーラトランジスタＱ１、Ｑ２とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００のメサ型ヘテロバイポーラトランジスタＱ１、Ｑ２の全てのメサ型ヘテロバイポーラトランジスタの平面構造のエミッタ領域の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一される。従って、半導体チップ１の製造工程のバラツキに依存する４系統のＲＦ電力増幅器１００、２００、４００、５００の全てのバイポーラトランジスタＱ１、Ｑ２、Ｑ３の各増幅ゲインのコンダクタンスの相対的なバラツキを、低減することが可能となる。 Therefore, the mesa type heterobipolar transistors Q1, Q2, Q3 of the GSM type high band RF power amplifier 100 and the GSM type low band RF power amplifier 200 integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention. Mesa heterobipolar transistors Q1, Q2, Q3 and all mesa types of mesa heterobipolar transistors Q1, Q2 of WCDMA high band RF power amplifier 400 and mesa heterobipolar transistors Q1, Q2 of WCDMA low band RF power amplifier 500 The extending direction of the long side of the rectangular emitter region of the planar structure of the heterobipolar transistor is unified with the direction of the AA ′ line which is the Y direction of the semiconductor chip 1. Therefore, the relative variation in the conductance of each amplification gain of all the bipolar transistors Q1, Q2, Q3 of the four RF power amplifiers 100, 200, 400, 500 depending on the variation in the manufacturing process of the semiconductor chip 1 is reduced. It becomes possible to do.
　一方、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅トランジスタＱ３の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大と、ＧＳＭ方式ローバンドＲＦ電力増幅器２００の最終段増幅トランジスタＱ３の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大とは、半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択される。更にＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の最終段増幅トランジスタＱ２の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大と、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の最終段増幅トランジスタＱ２の単位トランジスタＵｎｉｔ＿ＴＲＳの反復拡大とは、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される。 On the other hand, the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM high-band RF power amplifier 100 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q3 of the GSM low-band RF power amplifier 200 are a semiconductor chip. 1 is selected in the direction of the BB ′ line, which is the X direction. Further, the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA high-band RF power amplifier 400 and the repeated expansion of the unit transistor Unit_TRS of the final stage amplification transistor Q2 of the WCDMA low-band RF power amplifier 500 are the semiconductor chip 1 Is selected in the direction of the line AA ′, which is the Y direction.
　《半導体チップの構成》
　図２２は、本発明の実施の形態２による半導体集積回路の半導体チップ１の構成を示す図である。 <Structure of semiconductor chip>
FIG. 22 is a diagram showing a configuration of the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention.
　図２２に示すように本発明の実施の形態２による半導体集積回路の半導体チップ１は、図３に示したハイバンドＲＦ電力増幅器とローバンドＲＦ電力増幅器とを、ＧＳＭ方式とＷＣＤＭＡ方式の２系統、内蔵するものである。すなわち、図２２に示した本発明の実施の形態１による半導体集積回路の半導体チップ１には、ＧＳＭ方式ハイバンドＲＦ電力増幅器(ＧＳＭ＿ＨＢ)１００の複数のトランジスタＱ１、Ｑ２とＧＳＭ方式ローバンドＲＦ電力増幅器(ＧＳＭ＿ＬＢ)２００の複数のトランジスタＱ１、Ｑ２と、更にＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＨＢ)４００の複数のトランジスタＱ１、Ｑ２とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＬＢ)５００の複数のトランジスタＱ１、Ｑ２とバイアス制御部３００とが集積化されている。尚、図２２に示した本発明の実施の形態２による半導体集積回路の半導体チップ１に集積化された全てのトランジスタＱ１、Ｑ２は、図１７と図１８とで説明したプレーナ型バイポーラトランジスタであるか、もしくは図１９と図２０と図２１で説明したメサ型ヘテロバイポーラトランジスタである。 As shown in FIG. 22, the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention includes a high-band RF power amplifier and a low-band RF power amplifier shown in FIG. It is built-in. That is, the semiconductor chip 1 of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 22 includes a plurality of transistors Q1 and Q2 of the GSM high-band RF power amplifier (GSM_HB) 100 and a GSM low-band RF power amplifier. (GSM_LB) A plurality of transistors Q1, Q2 of 200, and further a plurality of transistors Q1, Q2 of WCDMA high-band RF power amplifier (WCDMA_HB) 400 and a plurality of transistors Q1, Q2 of WCDMA low-band RF power amplifier (WCDMA_LB) 500 And the bias controller 300 are integrated. Note that all the transistors Q1 and Q2 integrated in the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22 are the planar bipolar transistors described with reference to FIGS. Or, it is the mesa type hetero bipolar transistor described in FIG. 19, FIG. 20, and FIG.
　更に図２２に示した本発明の実施の形態２による半導体集積回路の半導体チップ１には、ＧＳＭ方式ハイバンドＲＦ電力増幅器(ＧＳＭ＿ＨＢ)１００とＧＳＭ方式ローバンドＲＦ電力増幅器(ＧＳＭ＿ＬＢ)２００とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＨＢ)４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器(ＷＣＤＭＡ＿ＬＢ)５００の各電力増幅器の入力整合回路ＩｎＭＮと段間整合回路ＭＮとが集積化されている。 Furthermore, the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22 includes a GSM high band RF power amplifier (GSM_HB) 100, a GSM low band RF power amplifier (GSM_LB) 200, and a WCDMA high The input matching circuit InMN and the interstage matching circuit MN of each power amplifier of the band RF power amplifier (WCDMA_HB) 400 and the WCDMA low-band RF power amplifier (WCDMA_LB) 500 are integrated.
　図２２に示した本発明の実施の形態２による半導体集積回路の半導体チップ１においては、ＲＦ電力増幅器１００とＲＦ電力増幅器２００とＲＦ電力増幅器４００とＲＦ電力増幅器５００の全てのトランジスタＱ１、Ｑ２のエミッタ領域の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一されている。従って、半導体チップ１の製造工程のバラツキに依存する４系統のＲＦ電力増幅器１００、２００、４００、５００の全てのトランジスタＱ１、Ｑ２の増幅ゲインのコンダクタンスの相対的なバラツキを、低減することが可能となる。 In the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22, all of the transistors Q1 and Q2 of the RF power amplifier 100, the RF power amplifier 200, the RF power amplifier 400, and the RF power amplifier 500 are included. The extending direction of the long side of the rectangle of the emitter region is unified with the direction of the AA ′ line which is the Y direction of the semiconductor chip 1. Accordingly, it is possible to reduce the relative variation in the conductance of the amplification gains of all the transistors Q1 and Q2 of the four RF power amplifiers 100, 200, 400, and 500 depending on the variation in the manufacturing process of the semiconductor chip 1. It becomes.
　また、図２２に示した本発明の実施の形態２による半導体集積回路の半導体チップ１においては、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００とは、長方形の半導体チップ１の上部長辺と下部長辺とにそれぞれ配置されている。すなわち、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の複数のトランジスタＱ１、Ｑ２は長方形の半導体チップ１の上部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置され、ＧＳＭ方式ローバンドＲＦ電力増幅器２００の複数のトランジスタＱ１、Ｑ２は長方形の半導体チップ１の下部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されている。 Further, in the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22, the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 are the same as those of the rectangular semiconductor chip 1. They are arranged on the upper long side and the lower long side, respectively. That is, the plurality of transistors Q1 and Q2 of the GSM high-band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1, and the GSM low-band The plurality of transistors Q1 and Q2 of the RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line which is the X direction of the semiconductor chip 1.
　更に図２２に示した本発明の実施の形態２による半導体集積回路の半導体チップ１においては、ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００とは、長方形の半導体チップ１の左部短辺と右部短辺とにそれぞれ配置されている。すなわち、ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の複数のトランジスタＱ１、Ｑ２は長方形の半導体チップ１の左部短辺に半導体チップ１のＹ方向であるＡ－Ａ´線の方向に配置され、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の複数のトランジスタＱ１、Ｑ２は長方形の半導体チップ１の右部短辺に半導体チップ１のＹ方向であるＡ－Ａ´線の方向に配置されている。 Furthermore, in the semiconductor chip 1 of the semiconductor integrated circuit according to the second embodiment of the present invention shown in FIG. 22, the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 are the left of the rectangular semiconductor chip 1. It is arrange | positioned at the part short side and the right part short side, respectively. That is, the plurality of transistors Q1 and Q2 of the WCDMA high-band RF power amplifier 400 are arranged on the short side of the left side of the rectangular semiconductor chip 1 in the direction of the AA ′ line, which is the Y direction of the semiconductor chip 1. The plurality of transistors Q1 and Q2 of the low-band RF power amplifier 500 are disposed on the short right side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
　従って、半導体チップ１の上部長辺でＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大きな素子サイズとされた最終段増幅トランジスタＱ２は、そのエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択されている。また更に半導体チップ１の下部長辺でＧＳＭ方式ローバンドＲＦ電力増幅器２００の大きな素子サイズとされた最終段増幅トランジスタＱ２は、そのエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択されている。 Therefore, in the final stage amplification transistor Q2 having a large element size of the GSM high-band RF power amplifier 100 on the upper long side of the semiconductor chip 1, the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. While selected in the direction of the AA ′ line, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the BB ′ line which is the X direction of the semiconductor chip 1. Further, in the final stage amplification transistor Q2 having a large element size of the GSM low band RF power amplifier 200 at the lower long side of the semiconductor chip 1, the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. On the other hand, the unit transistor is repeatedly expanded in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while being selected in the direction of the −A ′ line.
　それに対して半導体チップ１の左部短辺でＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の大きな素子サイズとされた最終段増幅トランジスタＱ２は、そのエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方で、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択されている。また更に半導体チップ１の右部短辺でＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大きな素子サイズとされた最終段増幅トランジスタＱ２は、そのエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方で、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択されている。 On the other hand, in the final stage amplification transistor Q2, which has a large element size of the WCDMA high-band RF power amplifier 400 on the short left side of the semiconductor chip 1, the extension direction of the long side of the emitter region is in the Y direction of the semiconductor chip 1. Is selected in the direction of the AA ′ line, which is the Y direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size. . Further, in the final stage amplification transistor Q2, which is a large element size of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1, the extending direction of the long side of the emitter region is the Y direction of the semiconductor chip 1. While selected in the direction of the AA ′ line, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1.
　図２２に示す半導体チップ１では、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００の各増幅器の初段増幅トランジスタＱ１と最終段増幅トランジスタＱ２と同様に複数の単位トランジスタの並列接続によって構成されている。初段増幅トランジスタＱ１を小ゲインとするために初段増幅トランジスタＱ１を構成する複数の単位トランジスタの半導体チップ１のＹ方向であるＡ－Ａ´線の方向の反復拡大量は、大ゲインの最終段増幅トランジスタＱ２の反復拡大量よりも小さく設定される。更にＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の各増幅器の初段増幅トランジスタＱ１も、最終段増幅トランジスタＱ２と同様に、複数の単位トランジスタの並列接続によって構成されている。初段増幅トランジスタＱ１を小ゲインとするために初段増幅トランジスタＱ１を構成する複数の単位トランジスタの半導体チップ１のＹ方向であるＡ－Ａ´線の方向の反復拡大量は、大ゲインの最終段増幅トランジスタＱ２の反復拡大量よりも小さく設定される。 In the semiconductor chip 1 shown in FIG. 22, a plurality of unit transistors are connected in parallel as in the first stage amplification transistor Q1 and the last stage amplification transistor Q2 of each amplifier of the GSM high band RF power amplifier 100 and the GSM low band RF power amplifier 200. It is configured. In order to make the first stage amplification transistor Q1 have a small gain, the amount of repetitive expansion in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplification transistor Q1 is the final stage amplification with a large gain. It is set smaller than the repetitive enlargement amount of the transistor Q2. Further, the first stage amplification transistor Q1 of each amplifier of the WCDMA high band RF power amplifier 400 and the WCDMA low band RF power amplifier 500 is also configured by parallel connection of a plurality of unit transistors, like the last stage amplification transistor Q2. In order to make the first stage amplification transistor Q1 have a small gain, the amount of repetitive expansion in the direction of the AA ′ line of the semiconductor chip 1 of the plurality of unit transistors constituting the first stage amplification transistor Q1 is the final stage amplification with a large gain. It is set smaller than the repetitive enlargement amount of the transistor Q2.
　［実施の形態３］
　《ＲＦ電力増幅器とバイアス制御部》
　図２３は、本発明の実施の形態３による半導体集積回路の半導体チップ１に集積化されるＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００とバイアス制御部３００とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００との構成を示す図である。 [Embodiment 3]
<< RF power amplifier and bias control section >>
FIG. 23 shows a GSM high-band RF power amplifier 100, a GSM low-band RF power amplifier 200, a bias controller 300, and a WCDMA high-band integrated on the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention. FIG. 2 is a diagram showing the configuration of an RF power amplifier 400 and a WCDMA low-band RF power amplifier 500.
　ＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００の各ＲＦ電力増幅器は、初段増幅素子Ｑ１と２段目の増幅素子Ｑ２と最終段増幅素子Ｑ３とを含んでいる。各ＲＦ電力増幅器では、複数の増幅素子Ｑ１～Ｑ３の共通電極は接地電圧ＧＮＤに接続されて、複数の増幅素子Ｑ１、Ｑ２、Ｑ３の出力電極に負荷インダクタＬ１、Ｌ２、Ｌ３を介して電源電圧Ｖｄｄが供給される。 Each RF power amplifier of the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200 includes a first stage amplifying element Q1, a second stage amplifying element Q2, and a last stage amplifying element Q3. In each RF power amplifier, the common electrodes of the plurality of amplification elements Q1 to Q3 are connected to the ground voltage GND, and the power supply voltage is connected to the output electrodes of the plurality of amplification elements Q1, Q2, and Q3 via load inductors L1, L2, and L3. Vdd is supplied.
　ＧＳＭ方式ハイバンドＲＦ電力増幅器１００では、ＧＳＭハイバンドＲＦ送信入力信号Ｐｉｎ＿ＧＳＭ＿ＨＢが入力整合回路ＩｎＭＮを介して初段の増幅素子Ｑ１の入力電極に供給され、増幅素子Ｑ１の出力電極の増幅信号は段間整合回路ＭＮを介して２段目の増幅素子Ｑ２の入力電極に供給され、増幅素子Ｑ２の増幅信号は段間整合回路ＭＮを介して最終段増幅素子Ｑ３の入力電極に供給されて、増幅素子Ｑ３の増幅信号は出力整合回路ＯｕｔＭＮを介してＧＳＭハイバンドＲＦ送信出力信号Ｐｏｕｔ＿ＧＳＭ＿ＨＢとして出力される。 In the GSM high-band RF power amplifier 100, the GSM high-band RF transmission input signal Pin_GSM_HB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is interstage. The amplified signal of the amplifying element Q2 is supplied to the input electrode of the final stage amplifying element Q3 via the interstage matching circuit MN via the matching circuit MN. The amplified signal of Q3 is output as a GSM high-band RF transmission output signal Pout_GSM_HB via the output matching circuit OutMN.
　ＧＳＭ方式ローバンドＲＦ電力増幅器２００では、ＧＳＭローバンドＲＦ送信入力信号Ｐｉｎ＿ＧＳＭ＿ＬＢが入力整合回路ＩｎＭＮを介して初段の増幅素子Ｑ１の入力電極に供給され、増幅素子Ｑ１の出力電極の増幅信号は段間整合回路ＭＮを介して２段目の増幅素子Ｑ２の入力電極に供給され、増幅素子Ｑ２の増幅信号は段間整合回路ＭＮを介して最終段増幅素子Ｑ３の入力電極に供給されて、増幅素子Ｑ３の増幅信号は出力整合回路ＯｕｔＭＮを介してＧＳＭローバンドＲＦ送信出力信号Ｐｏｕｔ＿ＧＳＭ＿ＬＢとして出力される。 In the GSM low-band RF power amplifier 200, the GSM low-band RF transmission input signal Pin_GSM_LB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is the inter-stage matching circuit. The amplified signal of the amplifying element Q2 is supplied to the input electrode of the final stage amplifying element Q3 via the interstage matching circuit MN and supplied to the input electrode of the amplifying element Q3. The amplified signal is output as a GSM low-band RF transmission output signal Pout_GSM_LB via the output matching circuit OutMN.
　ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の各ＲＦ電力増幅器は、初段増幅素子Ｑ１と最終段増幅素子Ｑ２とを含んでいる。各ＲＦ電力増幅器では、複数の増幅素子Ｑ１、Ｑ２の共通電極は接地電圧ＧＮＤに接続されて、複数の増幅素子Ｑ１、Ｑ２の出力電極に負荷インダクタＬ１、Ｌ２を介して電源電圧Ｖｄｄが供給される。 Each RF power amplifier of the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 includes a first stage amplifying element Q1 and a last stage amplifying element Q2. In each RF power amplifier, the common electrodes of the plurality of amplification elements Q1 and Q2 are connected to the ground voltage GND, and the power supply voltage Vdd is supplied to the output electrodes of the plurality of amplification elements Q1 and Q2 via the load inductors L1 and L2. The
　ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００では、ＷＣＤＭＡハイバンドＲＦ送信入力信号Ｐｉｎ＿ＷＣＤＭＡ＿ＨＢが入力整合回路ＩｎＭＮを介して初段の増幅素子Ｑ１の入力電極に供給され、増幅素子Ｑ１の出力電極の増幅信号は段間整合回路ＭＮを介して最終段増幅素子Ｑ２の入力電極に供給され、増幅素子Ｑ２の増幅信号は出力整合回路ＯｕｔＭＮを介してＷＣＤＭＡハイバンドＲＦ送信出力信号Ｐｏｕｔ＿ＷＣＤＭＡ＿ＨＢとして出力される。 In the WCDMA high-band RF power amplifier 400, the WCDMA high-band RF transmission input signal Pin_WCDMA_HB is supplied to the input electrode of the first stage amplifying element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifying element Q1 is interstage. The signal is supplied to the input electrode of the final stage amplifying element Q2 via the matching circuit MN, and the amplified signal of the amplifying element Q2 is output as the WCDMA high-band RF transmission output signal Pout_WCDMA_HB via the output matching circuit OutMN.
　ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００では、ＷＣＤＭＡローバンドＲＦ送信入力信号Ｐｉｎ＿ＷＣＤＭＡ＿ＬＢが入力整合回路ＩｎＭＮを介して初段の増幅素子Ｑ１の入力電極に供給され、増幅素子Ｑ１の出力電極の増幅信号は段間整合回路ＭＮを介して最終段増幅素子Ｑ２の入力電極に供給されて、増幅素子Ｑ２の増幅信号は出力整合回路ＯｕｔＭＮを介してＷＣＤＭＡローバンドＲＦ送信出力信号Ｐｏｕｔ＿ＷＣＤＭＡ＿ＬＢとして出力される。 In the WCDMA low-band RF power amplifier 500, the WCDMA low-band RF transmission input signal Pin_WCDMA_LB is supplied to the input electrode of the first-stage amplifier element Q1 via the input matching circuit InMN, and the amplified signal at the output electrode of the amplifier element Q1 is the inter-stage matching circuit. The signal is supplied to the input electrode of the final stage amplifying element Q2 via the MN, and the amplified signal of the amplifying element Q2 is output as the WCDMA low band RF transmission output signal Pout_WCDMA_LB via the output matching circuit OutMN.
　バイアス制御部３００には自動電力制御信号Ｖａｐｃと複数の制御入力信号Ｃｏｎｔが供給されることによって、バイアス制御部３００はＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００との各ＲＦ電力増幅器の複数の増幅素子Ｑ１、Ｑ２、Ｑ３の入力電極に供給される入力電極バイアス電圧とＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００との各ＲＦ電力増幅器の複数の増幅素子Ｑ１、Ｑ２の入力電極に供給される入力電極バイアス電圧とを生成する。 The bias control unit 300 is supplied with the automatic power control signal Vapc and a plurality of control input signals Cont, so that the bias control unit 300 performs each RF of the GSM high-band RF power amplifier 100 and the GSM low-band RF power amplifier 200. Input electrode bias voltage supplied to the input electrodes of a plurality of amplifier elements Q 1, Q 2, Q 3 of the power amplifier and a plurality of amplifications of each RF power amplifier of WCDMA high-band RF power amplifier 400 and WCDMA low-band RF power amplifier 500 An input electrode bias voltage supplied to the input electrodes of the elements Q1 and Q2 is generated.
　ＧＳＭ方式ＲＦ電力増幅器１００、２００の複数の増幅素子Ｑ１、Ｑ２、Ｑ３とＷＣＤＭＡ方式ＲＦ電力増幅器４００、５００の複数の増幅素子Ｑ１、Ｑ２とは、図７から図１３までに説明したＬＤＭＯＳＦＥＴもしくは図１７と図１８とで説明したプレーナ型バイポーラトランジスタもしくは図１９と図２０と図２１で説明したメサ型ヘテロバイポーラトランジスタである。 The plurality of amplifying elements Q1, Q2, Q3 of the GSM RF power amplifiers 100, 200 and the plurality of amplifying elements Q1, Q2 of the WCDMA RF power amplifiers 400, 500 are the LDMOSFETs described with reference to FIGS. The planar bipolar transistor described with reference to FIGS. 17 and 18 or the mesa-type hetero bipolar transistor described with reference to FIGS.
　《半導体集積回路とＲＦ電力増幅器モジュール》
　図２４は、本発明の実施の形態３による半導体集積回路の半導体チップ１の構成とＲＦ電力増幅器モジュールＰＡ＿ＭＤの構成とを示す図である。 << Semiconductor integrated circuit and RF power amplifier module >>
FIG. 24 is a diagram showing the configuration of the semiconductor chip 1 of the semiconductor integrated circuit and the configuration of the RF power amplifier module PA_MD according to the third embodiment of the present invention.
　図２４に示した本発明の実施の形態３による半導体集積回路の半導体チップ１においては、ＲＦ電力増幅器１００とＲＦ電力増幅器２００とＲＦ電力増幅器４００とＲＦ電力増幅器５００の全ての増幅素子Ｑ１、Ｑ２、Ｑ３のゲート電極またはエミッタ領域の長方形の長辺の延長方向は、半導体チップ１のＹ方向であるＡ－Ａ´線の方向に統一されている。従って、半導体チップ１の製造工程のバラツキに依存する４系統のＲＦ電力増幅器１００、２００、４００、５００の全ての増幅素子Ｑ１、Ｑ２、Ｑ３の各ＦＥＴの増幅ゲインのコンダクタンスの相対的なバラツキを、低減することが可能となる。 In the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 24, all the amplifying elements Q1, Q2 of the RF power amplifier 100, the RF power amplifier 200, the RF power amplifier 400, and the RF power amplifier 500 are illustrated. The extension direction of the long side of the rectangle of the gate electrode or emitter region of Q3 is unified with the direction of the AA ′ line which is the Y direction of the semiconductor chip 1. Accordingly, the relative variation of the conductance of the amplification gain of each of the amplifying elements Q1, Q2, and Q3 of the four RF power amplifiers 100, 200, 400, and 500 depending on the variation of the manufacturing process of the semiconductor chip 1 is reduced. Can be reduced.
　また、図２４に示した本発明の実施の形態３による半導体集積回路の半導体チップ１においては、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００とＧＳＭ方式ローバンドＲＦ電力増幅器２００とは、長方形の半導体チップ１の上部長辺と下部長辺とにそれぞれ配置されている。すなわち、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の複数の増幅素子Ｑ１、Ｑ２、Ｑ３は長方形の半導体チップ１の上部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されて、ＧＳＭ方式ローバンドＲＦ電力増幅器２００の複数の増幅素子Ｑ１、Ｑ２、Ｑ３は長方形の半導体チップ１の下部長辺に半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に配置されている。 Also, in the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 24, the GSM high band RF power amplifier 100 and the GSM low band RF power amplifier 200 are the same as those of the rectangular semiconductor chip 1. They are arranged on the upper long side and the lower long side, respectively. That is, the plurality of amplifying elements Q1, Q2, and Q3 of the GSM high-band RF power amplifier 100 are arranged on the upper long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1. A plurality of amplifying elements Q 1, Q 2, Q 3 of the GSM low-band RF power amplifier 200 are arranged on the lower long side of the rectangular semiconductor chip 1 in the direction of the BB ′ line that is the X direction of the semiconductor chip 1.
　更に図２４に示した本発明の実施の形態３による半導体集積回路の半導体チップ１においては、２段増幅器によってそれぞれ構成されるＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００とＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００とは、長方形の半導体チップ１の左部短辺と右部短辺とにそれぞれ配置されている。すなわち、ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の複数の増幅素子Ｑ１、Ｑ２は長方形の半導体チップ１の左部短辺に半導体チップ１のＹ方向であるＡ－Ａ´線の方向に配置されて、ＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の複数の増幅素子Ｑ１、Ｑ２は長方形の半導体チップ１の右部短辺に半導体チップ１のＹ方向であるＡ－Ａ´線の方向に配置されている。 Furthermore, in the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 24, the WCDMA high-band RF power amplifier 400 and the WCDMA low-band RF power amplifier 500 each constituted by a two-stage amplifier are used. The rectangular semiconductor chip 1 is disposed on the left short side and the right short side, respectively. That is, the plurality of amplifying elements Q1 and Q2 of the WCDMA high band RF power amplifier 400 are arranged on the short left side of the rectangular semiconductor chip 1 in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1, The plurality of amplifying elements Q1 and Q2 of the WCDMA low-band RF power amplifier 500 are arranged on the short right side of the rectangular semiconductor chip 1 in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1.
　従って、半導体チップ１の上部長辺でＧＳＭ方式ハイバンドＲＦ電力増幅器１００の大きな素子サイズとされた最終段増幅素子Ｑ３は、そのゲート電極またはエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択されている。また更に半導体チップ１の下部長辺でＧＳＭ方式ローバンドＲＦ電力増幅器２００の大きな素子サイズとされた最終段増幅素子Ｑ３は、そのゲート電極またはエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に選択されている。 Therefore, the final stage amplifying element Q3 having a large element size of the GSM high-band RF power amplifier 100 on the upper long side of the semiconductor chip 1 has an extending direction of the long side of the gate electrode or the emitter region in the Y direction of the semiconductor chip 1. The direction of the AA ′ line, which is the direction, is selected, while the unit transistor repeated enlargement for realizing a large element size is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1. . Further, the final stage amplifying element Q3 having a large element size of the GSM low-band RF power amplifier 200 on the lower long side of the semiconductor chip 1 has a longer side extending in the Y direction of the semiconductor chip 1 in the gate electrode or emitter region. Is selected in the direction of the BB ′ line, which is the X direction of the semiconductor chip 1, while the unit transistor is repeatedly expanded for realizing a large element size.
　それに対して半導体チップ１の左部短辺でＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の大きな素子サイズとされた最終段増幅素子Ｑ２は、ゲート電極またはエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方で、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択されている。また更に半導体チップ１の右部短辺でＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の大きな素子サイズとされた最終段増幅素子Ｑ２は、そのゲート電極またはエミッタ領域の長辺の延長方向は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択される一方で、大きな素子サイズの実現のための単位トランジスタの反復拡大は半導体チップ１のＹ方向であるＡ－Ａ´線の方向に選択されている。 On the other hand, the final stage amplifying element Q2, which has a large element size of the WCDMA high-band RF power amplifier 400 on the left short side of the semiconductor chip 1, has an extension direction of the long side of the gate electrode or emitter region of the semiconductor chip 1. While selected in the direction of the AA ′ line which is the Y direction, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line which is the Y direction of the semiconductor chip 1. ing. Further, the final stage amplifying element Q2 having a large element size of the WCDMA low-band RF power amplifier 500 on the right short side of the semiconductor chip 1 has an extending direction of the long side of the gate electrode or the emitter region in the Y direction of the semiconductor chip 1. While the direction of the AA ′ line that is the direction is selected, the repeated enlargement of the unit transistor for realizing a large element size is selected in the direction of the AA ′ line that is the Y direction of the semiconductor chip 1. Yes.
　また更に図２４に示した本発明の実施の形態３による半導体集積回路の半導体チップ１においては、ＧＳＭ方式ハイバンドＲＦ電力増幅器１００の最終段増幅素子Ｑ３の増幅出力信号は長方形の半導体チップ１の上部長辺から半導体チップ１の外部に導出され、ＧＳＭ方式ローバンドＲＦ電力増幅器２００の最終段増幅素子Ｑ３の増幅出力信号は長方形の半導体チップ１の下部長辺から半導体チップ１の外部に導出され、ＷＣＤＭＡＭ方式ハイバンドＲＦ電力増幅器４００の最終段増幅素子Ｑ２の増幅出力信号は長方形の半導体チップ１の左部短辺から半導体チップ１の外部に導出され、ＷＣＤＭＡＭ方式ローバンドＲＦ電力増幅器５００の最終段増幅素子Ｑ２の増幅出力信号は長方形の半導体チップ１の右部短辺から半導体チップ１の外部に導出されている。 Furthermore, in the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 24, the amplified output signal of the final stage amplifying element Q3 of the GSM high band RF power amplifier 100 is the same as that of the rectangular semiconductor chip 1. Derived from the upper long side to the outside of the semiconductor chip 1, the amplified output signal of the final stage amplifying element Q3 of the GSM low-band RF power amplifier 200 is derived from the lower long side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1, The amplified output signal of the final stage amplifying element Q2 of the WCDMAM high-band RF power amplifier 400 is derived from the short left side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1, and is amplified by the final stage of the WCDMAM low-band RF power amplifier 500. The amplified output signal of the element Q2 is output from the right side of the rectangular semiconductor chip 1 to the outside of the semiconductor chip 1. We are led to.
　その結果、図２４に示した本発明の実施の形態３による半導体集積回路の半導体チップ１を搭載するＲＦ電力増幅器モジュールＰＡ＿ＭＤによれば、配線基板の上部部分にＧＳＭ方式ハイバンドＲＦ電力増幅器１００の出力整合回路１００＿ＯｕｔＭＮを配置して、配線基板の下部部分にＧＳＭ方式ローバンドＲＦ電力増幅器２００の出力整合回路２００＿ＯｕｔＭＮを配置して、配線基板の左部部分にＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器４００の出力整合回路４００＿ＯｕｔＭＮを配置して、配線基板の右部部分にＷＣＤＭＡ方式ローバンドＲＦ電力増幅器５００の出力整合回路５００＿ＯｕｔＭＮを配置することが可能となる。 As a result, according to the RF power amplifier module PA_MD on which the semiconductor chip 1 of the semiconductor integrated circuit according to the third embodiment of the present invention shown in FIG. 24 is mounted, the GSM high band RF power amplifier 100 is formed on the upper portion of the wiring board. The output matching circuit 100_OutMN is arranged, the output matching circuit 200_OutMN of the GSM low-band RF power amplifier 200 is arranged in the lower part of the wiring board, and the output matching of the WCDMA high-band RF power amplifier 400 is arranged in the left part of the wiring board. By arranging the circuit 400_OutMN, the output matching circuit 500_OutMN of the WCDMA low-band RF power amplifier 500 can be arranged at the right part of the wiring board.
　図２４から明らかなように、本発明の実施の形態３によれば、長方形の半導体チップ１の右部短辺と左部短辺から最終段増幅素子の出力信号が導出されるので、長方形の半導体チップ１が半導体チップ１のＸ方向であるＢ－Ｂ´線の方向に長く大きくならないので、半導体チップ１のチップサイズを縮小できる。更に、ＲＦ電力増幅器モジュールＰＡ＿ＭＤの配線基板のＲＦ信号出力配線も、配線基板の上部部分と下部部分と右部短辺と左部短辺に分散するので、配線レイアウトに制約も少なくなり、配線基板の面積とコストを低減することが可能となる。 As is clear from FIG. 24, according to the third embodiment of the present invention, the output signal of the final stage amplifying element is derived from the right short side and the left short side of the rectangular semiconductor chip 1, so that the rectangular Since the semiconductor chip 1 does not become long in the direction of the BB ′ line which is the X direction of the semiconductor chip 1, the chip size of the semiconductor chip 1 can be reduced. Further, since the RF signal output wiring of the wiring board of the RF power amplifier module PA_MD is also distributed in the upper part, the lower part, the right short side, and the left short side of the wiring board, there are less restrictions on the wiring layout and the wiring board. It is possible to reduce the area and cost.
　以上、本発明者によってなされた発明を種々の実施の形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.
　例えば、本発明の半導体集積回路の半導体チップに集積化される増幅素子としては、ＬＤＭＯＳＦＥＴやプレーナ型バイポーラトランジスタやメサ型へテロバイポーラトランジスタ以外の増幅素子、例えばＭＥＳＦＥＴやＨＥＭＴやＳｉＧｅへテロバイポーラトランジスタを使用することが可能である。 For example, as an amplifying element integrated on a semiconductor chip of the semiconductor integrated circuit of the present invention, an amplifying element other than an LDMOSFET, a planar bipolar transistor, a mesa type heterobipolar transistor, such as a MESFET, HEMT, or SiGe heterobipolar transistor is used. It is possible to use.
　１…半導体チップ(Ｐ型単結晶シリコン基板)
　２…Ｐ型単結晶シリコンエピタキシャル層
　３…溝
　４…打ち抜き層
　５…Ｐ型ウェル領域
　６…ゲート絶縁膜
　７…ゲート電極
　８…キャップ絶縁膜
　９…Ｎ－型オフセットドレイン領域
　１０…Ｎ－型ソース領域
　１１…Ｐ型ハロー領域
　１２…サイドウォールスペーサ
　１３…Ｎ型オフセットドレイン領域
　１５…Ｎ＋型ドレイン領域
　１６…Ｎ＋型ソース領域
　１７…Ｐ＋型半導体領域
　２０…窒化シリコン膜
　２１…酸化シリコン膜
　２２…コンタクトホール
　２３…第１プラグ配線
　２４Ａ…ソース電極
　２４Ｂ…ドレイン電極
　２６…第１層間シリコン酸化膜
　２７…スルーホール
　２８…第２プラグ配線
　２９Ｂ…第ドレイン電極
　３０…第２層間シリコン酸化膜
　３１…スルーホール
　３２…第３プラグ配線
　３３…配線(第１ドレイン配線)
　３４…酸化シリコン膜
　３５…窒化シリコン膜
　Ｇ…ゲート電極
　Ｄ…ドレイン領域
　Ｓ…ソース領域
　１００…ＧＳＭ方式ハイバンドＲＦ電力増幅器
　２００…ＧＳＭ方式ローイバンドＲＦ電力増幅器
　３００…バイアス制御部
　４００…ＷＣＤＭＡ方式ハイバンドＲＦ電力増幅器
　５００…ＷＣＤＭＡ方式ローイバンドＲＦ電力増幅器
　Ｑ１、Ｑ２、Ｑ３…増幅素子
　ＩｎＭＮ…入力整合回路
　ＭＮ…段間整合回路
　ＯｕｔＭＮ…出力整合回路
　Ｕｎｉｔ＿ＭＯＳ…単位トランジスタ
　ＧＭ１…第１ゲート配線
　ＧＭ２…第２ゲート配線
　ＤＭ１…第１ドレイン配線
　Ｅ…エミッタ電極
　Ｂ…ベース電極
　Ｃ…コレクタ電極
　Ｕｎｉｔ＿ＴＲＳ…単位トランジスタ
　ＰＡ＿ＭＤ…ＲＦ電力増幅器モジュール 1 ... Semiconductor chip (P-type single crystal silicon substrate)
DESCRIPTION OF SYMBOLS 2 ... P-type single crystal silicon epitaxial layer 3 ... Groove 4 ... Punching layer 5 ... P-type well region 6 ... Gate insulating film 7 ... Gate electrode 8 ... Cap insulating film 9 ... N - type offset drain region 10 ... N - type source region 11 ... P-type halo regions 12 ... sidewall spacer 13 ... N-type offset drain region 15 ... N + -type drain region 16 ... N + -type source region 17 ... P + -type semiconductor region 20 ... silicon film 21 ... silicon oxide nitride film DESCRIPTION OF SYMBOLS 22 ... Contact hole 23 ... 1st plug wiring 24A ... Source electrode 24B ... Drain electrode 26 ... 1st interlayer silicon oxide film 27 ... Through hole 28 ... 2nd plug wiring 29B ... 2nd drain electrode 30 ... 2nd interlayer silicon oxide film 31 ... Through hole 32 ... Third plug wiring 33 ... Wiring (first drain wiring)
34 ... Silicon oxide film 35 ... Silicon nitride film G ... Gate electrode D ... Drain region S ... Source region 100 ... GSM high band RF power amplifier 200 ... GSM low band RF power amplifier 300 ... Bias controller 400 ... WCDMA high band RF power amplifier 500... WCDMA low-band RF power amplifier Q1, Q2, Q3... Amplifying element InMN... Input matching circuit MN... Interstage matching circuit OutMN. Wiring DM1 ... First drain wiring E ... Emitter electrode B ... Base electrode C ... Collector electrode Unit_TRS ... Unit transistor PA_MD ... RF power amplifier module

Claims (20)

  1. 　第１ＲＦ電力増幅器と第２ＲＦ電力増幅器とを内蔵する半導体集積回路であって、
    　前記半導体集積回路の半導体チップの第１辺と第２辺とは、実質的に直角に交差するものであり、
    　前記半導体チップの表面上には、前記第１辺に沿って前記第１ＲＦ電力増幅器の第１最終段増幅素子が形成され、前記第２辺に沿って前記第２ＲＦ電力増幅器の第２最終段増幅素子が形成され、
    　前記第１最終段増幅素子と前記第２最終段増幅素子の各増幅素子は、複数の単位トランジスタの並列接続によって構成され、
    　前記第１最終段増幅素子と前記第２最終段増幅素子の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形であり、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向と、前記第２最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向とは、前記第２辺の長さ方向に選択され、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は前記第１辺の長さ方向に選択され、前記第２最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は前記第２辺の長さ方向に選択された
    ことを特徴とする半導体集積回路。     A semiconductor integrated circuit including a first RF power amplifier and a second RF power amplifier,
    The first side and the second side of the semiconductor chip of the semiconductor integrated circuit intersect substantially at right angles;
    A first final stage amplification element of the first RF power amplifier is formed along the first side on the surface of the semiconductor chip, and a second final stage amplification of the second RF power amplifier is formed along the second side. An element is formed,
    Each amplification element of the first final stage amplification element and the second final stage amplification element is configured by a parallel connection of a plurality of unit transistors,
    Each unit transistor of the plurality of unit transistors of the first final stage amplification element and the second final stage amplification element has an active region that determines the gain of each unit transistor, and the planar shape of the active region Is a rectangle,
    The extending directions of the long sides of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element, and the plurality of unit transistors of the second final stage amplification element The extension direction of each long side of the plurality of rectangles of the active region is selected in the length direction of the second side,
    The direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element is selected in the length direction of the first side, and the direction of repetitive expansion of the plurality of unit transistors of the second final stage amplification element is A semiconductor integrated circuit selected in the length direction of the second side.
  2. 　請求項１において、
    　前記第１ＲＦ電力増幅器は第１初段増幅素子を含み、前記第２ＲＦ電力増幅器の第２初段増幅素子を含み、
    　前記第１初段増幅素子と前記第２初段増幅素子の各増幅素子は、複数の単位トランジスタの並列接続によって構成され、
    　前記第１初段増幅素子と前記第２初段増幅素子の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形であり、
    　前記第１初段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向と、前記第２初段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向とは、前記第２辺の長さ方向に選択され、
    　前記第１ＲＦ電力増幅器の前記第１初段増幅素子と前記第１最終段増幅素子とは、前記第１辺に沿って前記半導体チップの前記表面上に形成され、
    　前記第２ＲＦ電力増幅器の前記第２初段増幅素子と前記第２最終段増幅素子とは、前記第２辺に沿って前記半導体チップの前記表面上に形成された
    ことを特徴とする半導体集積回路。     In claim 1,
    The first RF power amplifier includes a first first stage amplifying element, and includes a second first stage amplifying element of the second RF power amplifier,
    Each amplification element of the first first stage amplification element and the second first stage amplification element is configured by a parallel connection of a plurality of unit transistors,
    Each unit transistor of the plurality of unit transistors of the first first stage amplification element and the second first stage amplification element has an active region that determines the gain of each unit transistor, and the planar shape of the active region is rectangular. And
    The extending directions of the long sides of the plurality of active regions of the plurality of unit transistors of the first first stage amplification element, and the plurality of active regions of the plurality of unit transistors of the second first stage amplification element The extending direction of each long side of the plurality of rectangles is selected in the length direction of the second side,
    The first first stage amplification element and the first last stage amplification element of the first RF power amplifier are formed on the surface of the semiconductor chip along the first side,
    2. The semiconductor integrated circuit according to claim 1, wherein the second first stage amplification element and the second last stage amplification element of the second RF power amplifier are formed on the surface of the semiconductor chip along the second side.
  3. 　請求項２において、
    　前記第１ＲＦ電力増幅器は第１段間整合回路を含み、前記第２ＲＦ電力増幅器の第２段間整合回路を含み、
    　前記第１ＲＦ電力増幅器の前記第１段間整合回路は、前記第１初段増幅素子の出力端子の増幅信号を前記第１最終段増幅素子の入力端子に伝達して、
    　前記第２ＲＦ電力増幅器の前記第２段間整合回路は、前記第２初段増幅素子の出力端子の増幅信号を前記第２最終段増幅素子の入力端子に伝達して、
    　前記第１ＲＦ電力増幅器の前記第１初段増幅素子と前記第１段間整合回路と前記第１最終段増幅素子とは、前記第１辺に沿って前記半導体チップの前記表面上に形成され、
    　前記第２ＲＦ電力増幅器の前記第２初段増幅素子と前記第２段間整合回路と前記第２最終段増幅素子とは、前記第２辺に沿って前記半導体チップの前記表面上に形成された
    ことを特徴とする半導体集積回路。     In claim 2,
    The first RF power amplifier includes a first interstage matching circuit, and includes a second interstage matching circuit of the second RF power amplifier;
    The first interstage matching circuit of the first RF power amplifier transmits the amplified signal of the output terminal of the first first stage amplifying element to the input terminal of the first last stage amplifying element,
    The second interstage matching circuit of the second RF power amplifier transmits the amplified signal of the output terminal of the second first stage amplifying element to the input terminal of the second last stage amplifying element,
    The first first stage amplifying element, the first interstage matching circuit, and the first last stage amplifying element of the first RF power amplifier are formed on the surface of the semiconductor chip along the first side,
    The second first stage amplifying element, the second interstage matching circuit, and the second last stage amplifying element of the second RF power amplifier are formed on the surface of the semiconductor chip along the second side. A semiconductor integrated circuit.
  4. 　請求項２において、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの複数の出力電極には複数の第１出力配線が接続され、前記第２最終段増幅素子の前記複数の単位トランジスタの複数の出力電極には複数の第２出力配線が接続され、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの複数の入力電極には複数の第１入力配線が接続され、前記第２最終段増幅素子の前記複数の単位トランジスタの複数の入力電極には複数の第２入力配線が接続され、
    　前記複数の第１出力配線の各配線の延長方向は前記第２辺の長さ方向に選択され、前記複数の第１入力配線の各配線の延長方向は前記第１辺の長さ方向に選択され、
    　前記複数の第２出力配線の各配線の延長方向は前記第１辺の長さ方向に選択され、前記複数の第２入力配線の各配線の延長方向は前記第１辺の長さ方向に選択された
    ことを特徴とする半導体集積回路。     In claim 2,
    A plurality of first output wires are connected to a plurality of output electrodes of the plurality of unit transistors of the first final stage amplifying element, and a plurality of output electrodes of the plurality of unit transistors of the second final stage amplifying element are connected to A plurality of second output wires are connected,
    A plurality of first input lines are connected to a plurality of input electrodes of the plurality of unit transistors of the first final stage amplification element, and a plurality of input electrodes of the plurality of unit transistors of the second final stage amplification element are connected to A plurality of second input wires are connected,
    The extending direction of each of the plurality of first output wirings is selected in the length direction of the second side, and the extending direction of each of the plurality of first input wirings is selected in the length direction of the first side. And
    The extension direction of each wiring of the plurality of second output wirings is selected in the length direction of the first side, and the extension direction of each wiring of the plurality of second input wirings is selected in the length direction of the first side. A semiconductor integrated circuit characterized by the above.
  5. 　請求項４において、
    　前記第１最終段増幅素子の前記複数の単位トランジスタと前記第２最終段増幅素子の前記複数の単位トランジスタとは、電界効果トランジスタであり、
    　前記電界効果トランジスタはゲート電極とドレイン領域とソース領域とを有し、前記ドレイン領域と前記ソース領域との間の前記ゲート電極の前記第２辺の長さ方向のゲート長によって前記活性領域の前記長方形の短辺が決定され、前記ドレイン領域と前記ソース領域との間の前記ゲート電極の前記第１辺の長さ方向のゲート幅によって前記活性領域の前記長方形の前記長辺が決定される
    ことを特徴とする半導体集積回路。     In claim 4,
    The plurality of unit transistors of the first final stage amplifying element and the plurality of unit transistors of the second final stage amplifying element are field effect transistors,
    The field effect transistor has a gate electrode, a drain region, and a source region, and the active region has the gate length in the length direction of the second side of the gate electrode between the drain region and the source region. The short side of the rectangle is determined, and the long side of the rectangle of the active region is determined by the gate width in the length direction of the first side of the gate electrode between the drain region and the source region. A semiconductor integrated circuit.
  6. 　請求項５において、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの前記複数の出力電極としての複数のドレイン領域には前記複数の第１出力配線が接続され、前記第２最終段増幅素子の前記複数の単位トランジスタの前記複数の出力電極としての複数のドレイン領域には前記複数の第２出力配線が接続され、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの前記複数の入力電極としての複数のゲート電極には前記複数の第１入力配線が接続され、前記第２最終段増幅素子の前記複数の単位トランジスタの前記複数の入力電極としての複数のゲート電極には前記複数の第２入力配線が接続され、
    　前記複数の第１出力配線の前記各配線の前記延長方向は前記第２辺の長さ方向に選択され、前記複数の第１入力配線の前記各配線の前記延長方向は前記第１辺の長さ方向に選択され、
    　前記複数の第２出力配線の前記各配線の前記延長方向は前記第１辺の長さ方向に選択され、前記複数の第２入力配線の前記各配線の前記延長方向は前記第１辺の長さ方向に選択された
    ことを特徴とする半導体集積回路。     In claim 5,
    The plurality of first output wirings are connected to the plurality of drain regions as the plurality of output electrodes of the plurality of unit transistors of the first final stage amplification element, and the plurality of units of the second final stage amplification element are connected. The plurality of second output wirings are connected to a plurality of drain regions as the plurality of output electrodes of the transistor,
    The plurality of first input lines are connected to the plurality of gate electrodes as the plurality of input electrodes of the plurality of unit transistors of the first final stage amplifying element, and the plurality of units of the second final stage amplifying element are connected. The plurality of second input wirings are connected to a plurality of gate electrodes as the plurality of input electrodes of the transistor,
    The extending direction of the wirings of the plurality of first output wirings is selected in the length direction of the second side, and the extending direction of the wirings of the plurality of first input wirings is the length of the first side. Selected in the direction,
    The extending direction of the wirings of the plurality of second output wirings is selected in the length direction of the first side, and the extending direction of the wirings of the plurality of second input wirings is the length of the first side. A semiconductor integrated circuit characterized by being selected in the vertical direction.
  7. 　請求項６において、
    　前記第２最終段増幅素子の前記複数の単位トランジスタの前記複数の入力電極である前記複数のゲート電極は、前記複数の長方形の前記複数の活性領域として前記第２辺の長さ方向に延長して前記半導体チップの前記表面上に形成され、
    　前記第２辺の長さ方向に形成された前記複数のゲート電極と前記第１辺の長さ方向に形成された前記複数の第２出力配線とは、前記半導体チップの前記表面上で立体的に交差して、
    　前記半導体チップの前記表面上で前記複数のゲート電極と前記複数の第２出力配線とが立体的に交差する部分において、接地電圧に接続される前記ソース領域と電気的に接続される複数のソース配線が前記複数のゲート電極と前記複数の第２出力配線との間に形成された
    ことを特徴とする半導体集積回路。     In claim 6,
    The plurality of gate electrodes which are the plurality of input electrodes of the plurality of unit transistors of the second final stage amplification element extend in the length direction of the second side as the plurality of rectangular active regions. Formed on the surface of the semiconductor chip,
    The plurality of gate electrodes formed in the length direction of the second side and the plurality of second output wirings formed in the length direction of the first side are three-dimensional on the surface of the semiconductor chip. Cross
    A plurality of sources electrically connected to the source region connected to a ground voltage at a portion where the plurality of gate electrodes and the plurality of second output wirings three-dimensionally intersect on the surface of the semiconductor chip A semiconductor integrated circuit, wherein a wiring is formed between the plurality of gate electrodes and the plurality of second output wirings.
  8. 　請求項７において、
    　前記半導体チップには、前記半導体チップの前記表面から前記半導体チップの裏面に到達する複数の打ち抜き層が形成され、
    　前記複数のソース配線は、前記複数の打ち抜き層を介して前記半導体チップの前記裏面に形成されたソース裏面電極に電気的に接続された
    ことを特徴とする半導体集積回路。     In claim 7,
    The semiconductor chip is formed with a plurality of punched layers reaching the back surface of the semiconductor chip from the front surface of the semiconductor chip,
    The semiconductor integrated circuit, wherein the plurality of source wirings are electrically connected to a source back surface electrode formed on the back surface of the semiconductor chip through the plurality of punched layers.
  9. 　請求項２において、
    　前記第１最終段増幅素子の前記複数の単位トランジスタと前記第２最終段増幅素子の前記複数の単位トランジスタとしての前記電界効果トランジスタは、ＬＤＭＯＳＦＥＴである
    ことを特徴とする半導体集積回路。     In claim 2,
    The semiconductor integrated circuit, wherein the plurality of unit transistors of the first final stage amplification element and the field effect transistors as the plurality of unit transistors of the second final stage amplification element are LDMOSFETs.
  10. 　請求項２において、
    　前記第１最終段増幅素子の前記複数の単位トランジスタと前記第２最終段増幅素子の前記複数の単位トランジスタとは、バイポーラトランジスタであり、
    　前記バイポーラトランジスタは複数のエミッタ領域を有し、前記複数のエミッタ領域は前記複数の長方形の前記複数の活性領域として前記第２辺の長さ方向に延長して前記半導体チップの前記表面上に形成された
    ことを特徴とする半導体集積回路。     In claim 2,
    The plurality of unit transistors of the first final stage amplification element and the plurality of unit transistors of the second final stage amplification element are bipolar transistors,
    The bipolar transistor has a plurality of emitter regions, and the plurality of emitter regions are formed on the surface of the semiconductor chip as the plurality of rectangular active regions extending in the length direction of the second side. A semiconductor integrated circuit characterized by the above.
  11. 　請求項１０において、
    　前記第１最終段増幅素子の前記複数の単位トランジスタと前記第２最終段増幅素子の前記複数の単位トランジスタとしての前記バイポーラトランジスタは、ヘテロバイポーラトランジスタである
    ことを特徴とする半導体集積回路。     In claim 10,
    The semiconductor integrated circuit, wherein the plurality of unit transistors of the first final stage amplifying element and the bipolar transistors as the plurality of unit transistors of the second final stage amplifying element are heterobipolar transistors.
  12. 　請求項２において、
    　前記半導体集積回路は、第３ＲＦ電力増幅器を更に内蔵して、
    　前記半導体集積回路の前記半導体チップの第３辺は前記第１辺と実質的に平行に配置されて前記第２辺と実質的に直角に交差するものであり、
    　前記半導体チップの前記表面上には、前記第３辺に沿って前記第３ＲＦ電力増幅器の第３最終段増幅素子が形成され、
    　前記第３最終段増幅素子は複数の単位トランジスタの並列接続によって構成され、前記第３最終段増幅素子の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形であり、
    　前記第３最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択され、
    　前記第３最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は、前記第３辺の長さ方向に選択された
    ことを特徴とする半導体集積回路。     In claim 2,
    The semiconductor integrated circuit further includes a third RF power amplifier,
    A third side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the first side and intersects the second side substantially at a right angle;
    A third final stage amplification element of the third RF power amplifier is formed along the third side on the surface of the semiconductor chip.
    The third final stage amplifying element is configured by parallel connection of a plurality of unit transistors, and each unit transistor of the plurality of unit transistors of the third final stage amplifying element has an active region that determines the gain of each unit transistor. The active region has a rectangular planar shape,
    An extending direction of each long side of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element is selected as a length direction of the second side,
    The semiconductor integrated circuit according to claim 3, wherein the direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element is selected in the length direction of the third side.
  13. 　請求項１２において、
    　前記半導体集積回路は、第４ＲＦ電力増幅器を更に内蔵して、
    　前記半導体集積回路の前記半導体チップの第４辺は前記第２辺と実質的に平行に配置されて前記第３辺と実質的に直角に交差するものであり、
    　前記半導体チップの前記表面上には、前記第４辺に沿って前記第４ＲＦ電力増幅器の第４最終段増幅素子が形成され、
    　前記第４最終段増幅素子は複数の単位トランジスタの並列接続によって構成され、前記第４最終段増幅素子の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形であり、
    　前記第４最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択され、
    　前記第４最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は、前記第４辺の長さ方向に選択された
    ことを特徴とする半導体集積回路。     In claim 12,
    The semiconductor integrated circuit further includes a fourth RF power amplifier,
    A fourth side of the semiconductor chip of the semiconductor integrated circuit is arranged substantially parallel to the second side and intersects the third side substantially at right angles;
    On the surface of the semiconductor chip, a fourth final stage amplification element of the fourth RF power amplifier is formed along the fourth side,
    The fourth final stage amplifying element is configured by parallel connection of a plurality of unit transistors, and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element has an active region that determines the gain of each unit transistor. The active region has a rectangular planar shape,
    The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplification element is selected in the length direction of the second side,
    The semiconductor integrated circuit according to claim 4, wherein the direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element is selected in the length direction of the fourth side.
  14. 　請求項１３において、
    　前記半導体チップの前記表面上には、前記第１ＲＦ電力増幅器と前記第２ＲＦ電力増幅器との間と前記第３ＲＦ電力増幅器と前記第４ＲＦ電力増幅器との間の位置に、バイアス制御部が形成され、
    　前記バイアス制御部は、前記第１ＲＦ電力増幅器の前記第１初段増幅素子と前記第１最終段増幅素子に、前記第２ＲＦ電力増幅器の前記第２初段増幅素子と前記第２最終段増幅素子に、前記第３ＲＦ電力増幅器の第３初段増幅素子と前記第３最終段増幅素子に、前記第４ＲＦ電力増幅器の第４初段増幅素子と前記第４最終段増幅素子に、それぞれバイアス電圧を供給する
    ことを特徴とする半導体集積回路。     In claim 13,
    A bias controller is formed on the surface of the semiconductor chip at a position between the first RF power amplifier and the second RF power amplifier and between the third RF power amplifier and the fourth RF power amplifier.
    The bias control unit is connected to the first first stage amplification element and the first last stage amplification element of the first RF power amplifier, to the second first stage amplification element and the second last stage amplification element of the second RF power amplifier, Bias voltage is supplied to the third first stage amplifying element and the third last stage amplifying element of the third RF power amplifier, and to the fourth first stage amplifying element and the fourth last stage amplifying element of the fourth RF power amplifier, respectively. A semiconductor integrated circuit.
  15. 　第１ＲＦ電力増幅器と第２ＲＦ電力増幅器とを内蔵する半導体集積回路の半導体チップを配線基板に搭載するモジュールであって、
    　前記半導体集積回路の前記半導体チップの第１辺と第２辺とは、実質的に直角に交差するものであり、
    　前記半導体チップの表面上には、前記第１辺に沿って前記第１ＲＦ電力増幅器の第１最終段増幅素子が形成され、前記第２辺に沿って前記第２ＲＦ電力増幅器の第２最終段増幅素子が形成され、
    　前記第１最終段増幅素子と前記第２最終段増幅素子の各増幅素子は、複数の単位トランジスタの並列接続によって構成され、
    　前記第１最終段増幅素子と前記第２最終段増幅素子の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形であり、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向と、前記第２最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向とは、前記第２辺の長さ方向に選択され、
    　前記第１最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は前記第１辺の長さ方向に選択され、前記第２最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は前記第２辺の長さ方向に選択され、
    　前記配線基板に、前記半導体チップが搭載され、
    　前記半導体チップの前記１辺と対向する前記配線基板の第１基板部分に前記第１ＲＦ電力増幅器の第１出力整合回路が搭載され、前記半導体チップの前記２辺と対向する前記配線基板の第２基板部分に前記第２ＲＦ電力増幅器の第２出力整合回路が搭載され、
    　前記第１最終段増幅素子の出力端子の増幅信号は、前記半導体チップの前記１辺を介して、前記第１出力整合回路に供給され、
    　前記第２最終段増幅素子の出力端子の増幅信号は、前記半導体チップの前記２辺を介して、前記第２出力整合回路に供給された
    ことを特徴とするモジュール。     A module for mounting a semiconductor chip of a semiconductor integrated circuit including a first RF power amplifier and a second RF power amplifier on a wiring board,
    The first side and the second side of the semiconductor chip of the semiconductor integrated circuit intersect substantially at right angles,
    A first final stage amplification element of the first RF power amplifier is formed along the first side on the surface of the semiconductor chip, and a second final stage amplification of the second RF power amplifier is formed along the second side. An element is formed,
    Each amplification element of the first final stage amplification element and the second final stage amplification element is configured by a parallel connection of a plurality of unit transistors,
    Each unit transistor of the plurality of unit transistors of the first final stage amplification element and the second final stage amplification element has an active region that determines the gain of each unit transistor, and the planar shape of the active region Is a rectangle,
    The extending directions of the long sides of the plurality of active regions of the plurality of unit transistors of the first final stage amplification element, and the plurality of unit transistors of the second final stage amplification element The extension direction of each long side of the plurality of rectangles of the active region is selected in the length direction of the second side,
    The direction of repetitive expansion of the plurality of unit transistors of the first final stage amplification element is selected in the length direction of the first side, and the direction of repetitive expansion of the plurality of unit transistors of the second final stage amplification element is Selected in the length direction of the second side;
    The semiconductor chip is mounted on the wiring board,
    A first output matching circuit of the first RF power amplifier is mounted on a first substrate portion of the wiring board facing the one side of the semiconductor chip, and a second of the wiring board facing the two sides of the semiconductor chip. A second output matching circuit of the second RF power amplifier is mounted on the substrate portion;
    The amplified signal at the output terminal of the first final stage amplification element is supplied to the first output matching circuit through the one side of the semiconductor chip,
    The module, wherein the amplified signal at the output terminal of the second final stage amplifying element is supplied to the second output matching circuit via the two sides of the semiconductor chip.
  16. 　請求項１５において、
    　前記半導体集積回路は、第３ＲＦ電力増幅器を更に内蔵して、
    　前記半導体集積回路の前記半導体チップの第３辺は、前記第１辺と実質的に平行に配置されて前記第２辺と実質的に直角に交差するものであり、
    　前記半導体チップの前記表面上には、前記第３辺に沿って前記第３ＲＦ電力増幅器の第３最終段増幅素子が形成され、
    　前記第３最終段増幅素子は複数の単位トランジスタの並列接続によって構成され、前記第３最終段増幅素子の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形であり、
    　前記第３最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択され、
    　前記第３最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は、前記第３辺の長さ方向に選択され、
    　前記半導体チップの前記３辺と対向する前記配線基板の第３基板部分に、前記第３ＲＦ電力増幅器の第３出力整合回路が搭載され、
    　前記第３最終段増幅素子の出力端子の増幅信号は、前記半導体チップの前記３辺を介して、前記第３出力整合回路に供給された
    ことを特徴とするモジュール。     In claim 15,
    The semiconductor integrated circuit further includes a third RF power amplifier,
    A third side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the first side and intersects the second side substantially at a right angle;
    A third final stage amplification element of the third RF power amplifier is formed along the third side on the surface of the semiconductor chip.
    The third final stage amplifying element is configured by parallel connection of a plurality of unit transistors, and each unit transistor of the plurality of unit transistors of the third final stage amplifying element has an active region that determines the gain of each unit transistor. The active region has a rectangular planar shape,
    An extending direction of each long side of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the third final stage amplifying element is selected as a length direction of the second side,
    The direction of repeated expansion of the plurality of unit transistors of the third final stage amplifying element is selected in the length direction of the third side,
    A third output matching circuit of the third RF power amplifier is mounted on a third substrate portion of the wiring substrate facing the three sides of the semiconductor chip;
    The module, wherein the amplified signal at the output terminal of the third final stage amplifier is supplied to the third output matching circuit via the three sides of the semiconductor chip.
  17. 　請求項１６において、
    　前記半導体集積回路は、第４ＲＦ電力増幅器を更に内蔵して、
    　前記半導体集積回路の前記半導体チップの第４辺は、前記第２辺と実質的に平行に配置されて前記第３辺と実質的に直角に交差するものであり、
    　前記半導体チップの前記表面上には、前記第４辺に沿って前記第４ＲＦ電力増幅器の第４最終段増幅素子が形成され、
    　前記第４最終段増幅素子は複数の単位トランジスタの並列接続によって構成され、前記第４最終段増幅素子の前記複数の単位トランジスタの各単位トランジスタは、当該各単位トランジスタのゲインを決定する活性領域を有するものであり、当該活性領域の平面形状は長方形であり、
    　前記第４最終段増幅素子の前記複数の単位トランジスタの前記複数の活性領域の前記複数の長方形の各長辺の延長方向は、前記第２辺の長さ方向に選択され、
    　前記第４最終段増幅素子の前記複数の単位トランジスタの反復拡大の方向は、前記第４辺の長さ方向に選択され、
    　前記半導体チップの前記４辺と対向する前記配線基板の第４基板部分に、前記第４ＲＦ電力増幅器の第４出力整合回路が搭載され、
    　前記第４最終段増幅素子の出力端子の増幅信号は、前記半導体チップの前記４辺を介して、前記第４出力整合回路に供給された
    ことを特徴とするモジュール。     In claim 16,
    The semiconductor integrated circuit further includes a fourth RF power amplifier,
    A fourth side of the semiconductor chip of the semiconductor integrated circuit is disposed substantially parallel to the second side and intersects the third side substantially at a right angle;
    On the surface of the semiconductor chip, a fourth final stage amplification element of the fourth RF power amplifier is formed along the fourth side,
    The fourth final stage amplifying element is configured by parallel connection of a plurality of unit transistors, and each unit transistor of the plurality of unit transistors of the fourth final stage amplifying element has an active region that determines the gain of each unit transistor. The active region has a rectangular planar shape,
    The extending direction of each long side of the plurality of rectangles of the plurality of active regions of the plurality of unit transistors of the fourth final stage amplification element is selected in the length direction of the second side,
    The direction of repeated expansion of the plurality of unit transistors of the fourth final stage amplifying element is selected in the length direction of the fourth side,
    A fourth output matching circuit of the fourth RF power amplifier is mounted on a fourth substrate portion of the wiring substrate facing the four sides of the semiconductor chip;
    The module, wherein the amplified signal at the output terminal of the fourth final stage amplifier is supplied to the fourth output matching circuit via the four sides of the semiconductor chip.
  18. 　請求項１７において、
    　前記第１最終段増幅素子と前記第２最終段増幅素子と前記第３最終段増幅素子と前記第４最終段増幅素子の前記複数の単位トランジスタは、電界効果トランジスタである
    ことを特徴とするモジュール。     In claim 17,
    The plurality of unit transistors of the first final stage amplifying element, the second final stage amplifying element, the third final stage amplifying element, and the fourth final stage amplifying element are field effect transistors. .
  19. 　請求項１８において、
    　前記第１最終段増幅素子と前記第２最終段増幅素子と前記第３最終段増幅素子と前記第４最終段増幅素子の前記複数の単位トランジスタとしての前記電界効果トランジスタは、ＬＤＭＯＳＦＥＴである
    ことを特徴とするモジュール。     In claim 18,
    The field effect transistors as the plurality of unit transistors of the first final stage amplifying element, the second final stage amplifying element, the third final stage amplifying element, and the fourth final stage amplifying element are LDMOSFETs. Feature module.
  20. 　請求項１７において、
    　前記第１最終段増幅素子と前記第２最終段増幅素子と前記第３最終段増幅素子と前記第４最終段増幅素子の前記複数の単位トランジスタは、バイポーラトランジスタである
    ことを特徴とするモジュール。     In claim 17,
    The module, wherein the plurality of unit transistors of the first final stage amplification element, the second final stage amplification element, the third final stage amplification element, and the fourth final stage amplification element are bipolar transistors.
PCT/JP2012/065584 2011-07-14 2012-06-19 Semiconductor integrated circuit and module mounting same WO2013008587A1 (en)

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JP2006313881A (en) * 2005-04-05 2006-11-16 Matsushita Electric Ind Co Ltd Bipolar transistor and radio frequency amplifier circuit
JP2006352241A (en) * 2005-06-13 2006-12-28 Renesas Technology Corp High frequency amplifier circuit and high frequency power amplification module
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JP2011091084A (en) * 2009-10-20 2011-05-06 Nec Corp Semiconductor device and arrangement method of interface cell

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