WO2012172991A1 - 半導体ユニットおよびそれを用いた半導体装置 - Google Patents

半導体ユニットおよびそれを用いた半導体装置 Download PDF

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Publication number
WO2012172991A1
WO2012172991A1 PCT/JP2012/064145 JP2012064145W WO2012172991A1 WO 2012172991 A1 WO2012172991 A1 WO 2012172991A1 JP 2012064145 W JP2012064145 W JP 2012064145W WO 2012172991 A1 WO2012172991 A1 WO 2012172991A1
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Prior art keywords
main surface
semiconductor
sic
conductive plate
electrode
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PCT/JP2012/064145
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English (en)
French (fr)
Inventor
俊之 三柳
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富士電機株式会社
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Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP2013520502A priority Critical patent/JP5692377B2/ja
Priority to CN201280023833.9A priority patent/CN103563075B/zh
Priority to EP12800609.5A priority patent/EP2722879B1/en
Priority to KR1020137030448A priority patent/KR101887199B1/ko
Publication of WO2012172991A1 publication Critical patent/WO2012172991A1/ja
Priority to US14/078,727 priority patent/US9165871B2/en

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Definitions

  • the present invention relates to a semiconductor unit in which a plurality of semiconductor chips are sandwiched between upper and lower conductive plates and a semiconductor device using the semiconductor unit.
  • Si-IGBT insulated gate bipolar transistor manufactured using a Si semiconductor substrate
  • SiC-Di SiC semiconductor substrate
  • FWD free wheeling diode
  • a semiconductor device having a structure using a diode) has been developed.
  • This SiC-Di is a Schottky barrier diode, which can have a higher breakdown voltage than a Schottky barrier diode manufactured from a Si semiconductor substrate, and can have a smaller switching loss than a pn diode.
  • Si is silicon and SiC is silicon carbide (silicon carbide).
  • FIG. 5A and 5B are configuration diagrams of a conventional semiconductor device, in which FIG. 5A is a layout diagram in a case, and FIG.
  • the semiconductor device 500 is a semiconductor module including two Si-IGBT chips 66 and eight SiC-Di chips (SiC-diode chips) 68 that are freewheeling diodes. This semiconductor device 500 can constitute one upper arm or lower arm of an inverter.
  • an insulating substrate 62 with a conductive pattern is bonded on a copper base plate 61, and a first conductive pattern 63, a second conductive pattern 64, and a third conductive pattern 65 are formed on the insulating substrate 62 with a conductive pattern.
  • the first conductive pattern 63, the collector electrode 67 of the Si-IGBT chip 66, and the cathode electrode 69 of the SiC-Di chip 68 are joined to the second conductive pattern 64 by solder or Ag paste (not shown).
  • the emitter electrode 70 of the Si-IGBT chip 66 and the anode electrode 71 of the SiC-Di chip 68 are connected to the second conductive pattern 64 by an aluminum wire 72.
  • the gate pad 73 of the Si-IGBT chip 66 is connected to the third conductive pattern 65 by an aluminum wire 74.
  • the first conductive pattern 63 and the second conductive pattern 64 join the collector terminal C, the emitter terminal E, and the gate terminal G to the third conductive pattern 65, respectively.
  • a case 75 that accommodates each chip is joined to a copper base plate 61 that is a heat radiator, and the terminals (collector terminal C, emitter terminal E, gate terminal G) are exposed on the case 75, For example, a gel (not shown) is filled.
  • two Si-IGBT chips 66 and eight SiC-Di chips 68 are housed in a case 75. Since the crystallinity of the SiC semiconductor substrate is not always good, the size of one SiC-Di chip 68 is limited and is about several mm square. Therefore, the semiconductor device 500 requires, for example, four SiC-Di chips 68 for one Si-IGBT chip 66. In some cases, it is necessary to increase the number of SiC-Di chips 68 further.
  • Patent Document 1 dissimilar elements connected in parallel are connected by a conductive plate and resin-sealed to form a semiconductor unit (also referred to as a unit package), and a semiconductor module is configured using a plurality of the semiconductor units (unit packages). Is disclosed.
  • the size of the SiC-Di chip 68 using the SiC semiconductor substrate uses Si. Smaller than the size of the Di chip. Therefore, in the semiconductor module (semiconductor device 500) using the SiC-Di chip 68 as shown in FIG. 5, it is necessary to connect a large number of SiC-Di chips 68 in parallel.
  • the semiconductor module semiconductor device 500
  • the number of wires 72 used for connection increases, the man-hour increases and the cost increases.
  • the semiconductor module (semiconductor device 500) due to the variation in the length of the wire 72, the parallel operation between the respective chips may cause variation, and the chip that causes current concentration may be destroyed. 500).
  • the semiconductor module (semiconductor device 500) has a high thermal resistance due to the single-sided cooling structure.
  • Patent Document 1 a semiconductor unit (unit package) is formed by connecting a plurality of elements of the same type (for example, SiC-Di chips) in parallel, and a semiconductor device is assembled using the semiconductor unit. Not listed.
  • An object of the present invention is to solve the above-described problems, a semiconductor unit that performs uniform parallel operation between chips, and a low-cost and high-reliability semiconductor device that uses the semiconductor unit and has a small thermal resistance. Is to provide.
  • the semiconductor unit is a semiconductor unit in which a large number of semiconductor chips formed using a wide gap semiconductor substrate are connected in parallel, and the plurality of semiconductor chips of the same type are arranged on the first main surface of the first common conductive plate.
  • One main surface is bonded, a conductive block is bonded to the other main surface of the semiconductor chip, a first main surface of a second common conductive plate is bonded onto the plurality of conductive blocks, and the first The second main surface of the common conductive plate and the second main surface of the second common conductive plate are exposed, and the first main surface of the first common conductive plate and the second common conductive plate
  • An insulating resin is filled between and integrated with the first main surface.
  • the semiconductor unit is provided as follows.
  • the semiconductor chip is a SiC-diode chip, a cathode electrode is formed on the one main surface, an anode electrode is formed on the other main surface, and the cathode electrode is formed on the first common conductive plate.
  • the anode electrode is bonded to the first main surface of the second common conductive plate via the conductive block.
  • the anode electrode is bonded to the first main surface.
  • the semiconductor unit is provided as follows.
  • the semiconductor chip is a SiC switching device, wherein a first main electrode is formed on the one main surface, a second main electrode and a gate electrode are formed on the other main surface, and the second common conductivity is formed.
  • a third conductive plate that is insulated from the plate and led out to the second main surface side of the second common conductive plate, wherein the first main electrode is the first common conductive plate of the first common conductive plate.
  • the second main electrode is bonded to the main surface via the conductive block, and the gate electrode is bonded to the third conductive plate to the first main surface of the second common conductive plate.
  • a semiconductor device in which a first semiconductor unit and a second semiconductor unit are mounted on a common insulating substrate and connected.
  • the first semiconductor unit is the semiconductor unit containing a SiC-diode chip as the semiconductor chip
  • the second semiconductor unit is the semiconductor unit containing a SiC switching device as the semiconductor chip
  • the SiC- In the diode chip a cathode electrode is formed on the one main surface, an anode electrode is formed on the other main surface, and the cathode electrode is bonded to the first main surface of the first common conductive plate.
  • the anode electrode is bonded to the first main surface of the second common conductive plate through the conductive block, and the SiC switching device has a first main electrode formed on the one main surface.
  • a second main electrode and a gate electrode are formed on the other main surface, and the second common conductive plate is insulated from the second common conductive plate.
  • a third conductive plate led out to the second main surface side, wherein the first main electrode is on the first main surface of the first common conductive plate, and the second main electrode is on the conductive block.
  • the gate electrode is joined to the third conductive plate on the first main surface of the second common conductive plate.
  • a semiconductor device in which a first semiconductor unit and an IGBT chip formed on a silicon semiconductor substrate are mounted and connected to a common insulating substrate.
  • the first semiconductor unit is the semiconductor unit including a SiC-diode chip as the semiconductor chip, and the SiC-diode chip has a cathode electrode formed on the one main surface and the other main surface.
  • Has an anode electrode the cathode electrode is joined to the first main surface of the first common conductive plate, and the anode electrode is connected to the first common conductive plate through the conductive block. It is joined to the main surface.
  • a semiconductor unit is formed by sandwiching a plurality of identical small semiconductor chips formed of a SiC semiconductor substrate or a GaN semiconductor substrate, which are wide gap semiconductor substrates, between two conductive plates (common copper plates) and connecting them in parallel.
  • a semiconductor unit is formed by sandwiching a plurality of identical small semiconductor chips formed of a SiC semiconductor substrate or a GaN semiconductor substrate, which are wide gap semiconductor substrates, between two conductive plates (common copper plates) and connecting them in parallel.
  • an Si-IGBT chip By connecting an Si-IGBT chip and a semiconductor unit composed of a SiC-Di chip that serves as a freewheeling diode in antiparallel, a semiconductor device that forms, for example, an upper arm or a lower arm of an inverter is formed. A small and low-cost and highly reliable semiconductor device can be obtained.
  • the semiconductor unit constituted by the SiC-MOSFET chip and the semiconductor unit constituted by the SiC-Di chip are connected in reverse parallel to form a semiconductor device which becomes the upper arm or the lower arm of the inverter, thereby enabling heat generation.
  • a highly reliable semiconductor device with low resistance and low cost can be obtained.
  • FIG. 4 is a configuration diagram of a semiconductor unit according to a second embodiment of the present invention, in which (a) is a plan view of the main part and (b) is a cross-sectional view of the main part taken along line X3-X3 of (a).
  • FIG. 4 is a configuration diagram of a semiconductor unit according to a second embodiment of the present invention, in which (a) is a plan view of the main part and (b) is a cross-sectional view of the main part taken along line X3-X3 of (a).
  • FIG. 7 is a configuration diagram of a semiconductor device according to a third embodiment of the present invention, in which (a) is a plan view of the main part and (b) is a cross-sectional view of the main part taken along line X5-X5 of (a).
  • FIG. 7 is a configuration diagram of a semiconductor device according to a fourth embodiment of the present invention, in which (a) is a plan view of the main part and (b) is a cross-sectional view of the main part taken along line X6-X6 of (a).
  • FIG. 1 is a configuration diagram of a semiconductor unit according to a first embodiment of the present invention.
  • FIG. 1 (a) is a plan view of the main part, and FIG. 1 (b) is cut along line X1-X1 in FIG. 1 (a). It is principal part sectional drawing.
  • FIG. 1A is a schematic plan view of a main part viewed in the direction of an arrow from a plane cut along line X2-X2 in FIG.
  • the semiconductor unit 100 is a semiconductor module having a structure in which a plurality of diode chips (hereinafter referred to as SiC-Di chips) 2 formed on a silicon carbide semiconductor substrate (SiC semiconductor substrate) 2 are connected in parallel.
  • SiC-Di chips silicon carbide semiconductor substrate
  • the SiC-Di chip 2 is an element in which a cathode electrode 3 is formed on one main surface and an anode electrode 5 is formed on the other main surface.
  • cathode electrodes 3 of four SiC-Di chips 2 are joined on a first common copper plate (first common electrode plate) 1 with solder 4, and anode electrodes 5 of four SiC-Di chips 2.
  • a copper block 6 as a heat spreader is joined to the top with solder 7.
  • One second common copper plate (second common electrode plate) 8 is joined to each copper block 6 by solder 9.
  • the high heat resistant resin 10 that covers at least the end 2a of the SiC-Di chip 2 is capable of sealing performance such as insulation and adhesion even when the temperature during operation of the SiC-Di chip 2 (for example, 150 ° C.) is reached. Must not deteriorate, and the heat-resistant temperature is about 175 ° C.
  • the semiconductor unit 100 configured by connecting these four small SiC-Di chips 2 in parallel has an equivalent element structure of a large area and is made into one element. For this reason, if the semiconductor unit 100 is used, for example, a plurality of small SiC-Di chips of several mm square can be handled as one element (for example, one element whose side is less than 1 cm). By preparing such a semiconductor unit 100 in advance, handling of the SiC-Di chip 2 becomes easy even when a semiconductor device described later is assembled.
  • the semiconductor unit 100 since the semiconductor unit 100 has a structure in which four small SiC-Di chips 2 are sandwiched between the first common copper plate 1 and the second common copper plate 8 and has no wire bonding, the four SiC-Di chips 2 Between each other, there is no influence of the inductance component existing in the bonding wire, and uniform parallel operation is performed. Therefore, current does not concentrate on one specific SiC-Di chip 2, so that element destruction can be prevented and high reliability can be achieved.
  • FIGS. 2A and 2B are configuration diagrams of a semiconductor unit according to a second embodiment of the present invention.
  • FIG. 2A is a plan view of the main part, and FIG. 2B is cut along the line X3-X3 in FIG. It is principal part sectional drawing.
  • FIG. 2A is a schematic plan view of a main part viewed in the direction of the arrow from the plane cut along line X4-X4 in FIG. 2B.
  • the semiconductor unit 200 is a semiconductor module having a structure in which a plurality of SiC-MOSFET chips 12 formed on a SiC semiconductor substrate are connected in parallel.
  • the SiC-MOSFET chip 12 is an example of an SiC switching device, and an SiC-JFET (Junction Field Effect Transistor: Junction Field Effect Transistor), SiC-IGBT, etc. can be applied to the SiC switching device. It is.
  • the SiC-MOSFET chip 12 will be described as an example.
  • the SiC-MOSFET chip 12 is an element in which a drain electrode 13 is formed on one main surface and a source electrode 15 and a gate pad 24 are formed on the other main surface.
  • the difference between the semiconductor unit 200 of FIG. 2 and the semiconductor unit 100 of FIG. 1 is that the SiC-Di chip 2 is replaced with a SiC-MOSFET chip 12 as a semiconductor chip.
  • the insulating substrate 11 with the auxiliary conductive pattern is formed with a back surface metal film 20 on the back surface and a first conductive pattern 21 to which the MOSFET is bonded on the front surface.
  • the back surface metal film 20 is insulated.
  • the first conductive pattern 21 is connected by a connection conductor 23 penetrating the substrate 22. Further, the first conductive pattern 21 and the back surface metal film 20 may be connected by a wire or the like without providing the connection conductor 23.
  • the drain electrodes 13 of the four small SiC-MOSFET chips 12 are joined with the solder 14 on the first conductive pattern 21 of the insulating substrate 11 with the auxiliary conductive pattern, and the gate pads 24 of the respective SiC-MOSFET chips 12 are independent of each other.
  • the second conductive pattern 25 is connected via a wire 26.
  • the copper block 16 is joined to the source electrode 15 of each of the four SiC-MOSFET chips 12 by solder 17.
  • One common copper plate 18 is joined to each copper block 16 by solder 19.
  • a gate conductor 27 that is insulated from the common copper plate 18 passes through the common copper plate 18.
  • the gate conductor 27 is connected to the gate pad 24 of the SiC-MOSFET chip 12 through the second conductive pattern 25.
  • the surface opposite to the bonding surface between the back surface metal film 20 of the insulating substrate 11 and the copper block 16 of the common copper plate 18 is exposed, and the region sandwiched between the insulating substrate 11 and the common copper plate 18, at least the SiC-MOSFET chip.
  • the region covering the 12 end portions 12a is molded with a high heat resistant resin 28 such as silicone rubber or epoxy resin.
  • the heat-resistant resin 28 covering at least the end portion 12a of the SiC-MOSFET chip 12 has a sealing performance such as insulation and adhesion even when the temperature of the SiC-MOSFET chip 12 is reached (for example, 150 ° C.). Must not deteriorate, and the heat-resistant temperature is about 175 ° C.
  • the insulating substrate 11 with the auxiliary conductive pattern serves as the first common copper plate 1 in FIG.
  • this semiconductor unit 200 substantially the same effect as the semiconductor unit 100 can be obtained.
  • the thermal resistance becomes higher than that radiated from the first common copper plate 1 in FIG.
  • the cross-sectional area of the connection conductor 23 is increased, the thermal resistance can be lowered.
  • the semiconductor unit 200 configured by connecting the four small SiC-MOSFET chips 12 in parallel has an equivalent element structure of a large area and is integrated into one element. For this reason, if the semiconductor unit 200 is used, for example, a plurality of minute (several mm square) SiC-MOSFET chips 12 can be collectively handled as one element (for example, one element whose side is less than 1 cm). . By preparing such a semiconductor unit 200 in advance, handling of the SiC-MOSFET chip 12 becomes easy even when a semiconductor device described later is assembled.
  • the semiconductor units 100 and 200 each including the small SiC-Di chip 2 and the small SiC-MOSFET chip 12 are given as examples.
  • the chip is not limited to the SiC-Di chip 2 or the SiC-MOSFET chip 12.
  • this structure in which a plurality of small chips are operated in parallel is useful. is there.
  • the present invention can be applied to SiC-IGBT chips, GaN-Di chips, GaN-MOSFET chips, GaN-IGBT chips, and the like.
  • FIG. 3 is a block diagram of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 3 (a) is a plan view of the main part, and FIG. 3 (b) is cut along line X5-X5 in FIG. 3 (a). It is principal part sectional drawing.
  • FIG. 3A is a schematic layout diagram in the case 44.
  • This semiconductor device 300 has a structure in which a semiconductor unit 100 composed of a SiC-Di chip 2 as a freewheeling diode is connected in reverse parallel to two Si-IGBT chips 35, and one upper arm or one of an inverter This is a semiconductor module constituting the lower arm.
  • the number is not limited to this.
  • a back metal film 33 of an insulating substrate 32 with a conductive pattern is bonded to the copper base plate 31 with solder (not shown), and the collector electrode 36 of the two Si-IGBT chips 35 and the SiC-Di chip 2 are connected to the third conductive pattern 34.
  • the first common copper plates 1 of the two semiconductor units 100 configured in the above are joined by solder (not shown).
  • the emitter electrode 37 of the Si-IGBT chip 35 and the fourth conductive pattern 38 are connected by a wire 39. Further, the gate pad 40 of the Si-IGBT chip 35 and the fifth conductive pattern 41 are connected by a wire 42. The second common copper plate 8 of the semiconductor unit 100 and the fourth conductive pattern 38 are connected by a flexible flat ribbon wire 43.
  • a collector terminal C is connected to the third conductive pattern 34, an emitter terminal E is connected to the fourth conductive pattern 38, and a gate terminal G is connected to the fifth conductive pattern 41.
  • a conductor such as a plurality of copper wires, aluminum wires, or a simple thin copper plate may be used.
  • the case 44 is covered from above so that the Si-IGBT chip 35 and the semiconductor unit 100 composed of the SiC-Di chip 2 are accommodated, and the emitter terminal E, the collector terminal C, and the gate terminal G are placed on the upper surface of the case 44. Expose. Further, the lower part of the case 44 is joined to the copper base plate 31 and a gel (not shown) is filled in the case 44 to complete the semiconductor device 300.
  • the semiconductor device 300 can be more easily assembled than the conventional semiconductor device 500, and the cost of the semiconductor device 300 can be reduced. Further, since the anode electrodes 5 of the four SiC-Di chips 2 are connected to the second common copper plate 8 via the copper block 6, the variation in inductance between the four SiC-Di chips 2 is reduced. The four SiC-Di chips 2 can perform a uniform parallel operation. As a result, the semiconductor unit 100 is less likely to be destroyed due to current concentration, and the reliability of the semiconductor device 300 is improved.
  • FIG. 4A and 4B are configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 4A is a plan view of an essential part
  • FIG. 4B is a cross-sectional view taken along line X6-X6 in FIG. It is principal part sectional drawing.
  • FIG. 4A is a schematic layout diagram in the case 57.
  • This semiconductor device 400 has a structure in which a semiconductor unit 200 composed of a SiC-Di chip 2 as a freewheeling diode is connected in reverse parallel to a semiconductor unit 200 composed of a SiC-MOSFET chip 12, and is located above one of the inverters. It is a semiconductor module constituting an arm or one lower arm.
  • a semiconductor unit 200 composed of a SiC-Di chip 2 as a freewheeling diode
  • a semiconductor unit 200 composed of a SiC-MOSFET chip 12
  • It is a semiconductor module constituting an arm or one lower arm.
  • two examples of the semiconductor units 100 and 200 are given, but the number is not limited to this.
  • An insulating substrate 52 with a conductive pattern is bonded to the copper base plate 51 with solder (not shown), and the insulating substrate 11 with an auxiliary conductive pattern of the semiconductor unit 200 constituted by two SiC-MOSFET chips 12 on the sixth conductive pattern 53. Are joined with solder (not shown).
  • first common copper plate 1 of the semiconductor unit 100 constituted by the two SiC-Di chips 2 is joined to the sixth conductive pattern 53 by solder (not shown).
  • the common copper plate 18 of the semiconductor unit 200 and the seventh conductive pattern 54 are connected by a flexible flat ribbon wire 55.
  • second common copper plate 8 of the semiconductor unit 100 and the seventh conductive pattern 54 are connected by a flexible flat ribbon wire 55.
  • the gate conductor 27 of the semiconductor unit 200 is connected to the eighth conductive pattern 56 with a wire 58.
  • the gate conductor 27 and the common copper plate 18 are electrically insulated by a high heat resistant resin 28.
  • the collector terminal C is joined to the sixth conductive pattern 53
  • the emitter terminal E is joined to the seventh conductive pattern 54
  • the gate terminal G is joined to the eighth conductive pattern 56, respectively.
  • a plurality of copper wires, aluminum wires, or a conductor such as a simple thin copper plate may be used.
  • a case 57 is covered from above so that the semiconductor unit 200 composed of the SiC-MOSFET chip 12 and the semiconductor unit 100 composed of the SiC-Di chip 2 are accommodated, and the collector terminal C and the emitter terminal E are covered from the upper surface of the case 57. And the gate terminal G are exposed.
  • the lower part of the case 57 is joined to the copper base plate 51 to complete the semiconductor device 400.
  • the use of the semiconductor units 100 and 200 improves the assemblability, and the semiconductor The cost of the device 400 can be reduced.
  • the thermal resistance of the semiconductor device 400 can be reduced. Further, by using the semiconductor units 100 and 200, the variation in inductance between the chips is reduced, and a uniform parallel operation can be performed between the chips. As a result, the semiconductor units 100 and 200 are not easily destroyed due to current concentration, and the reliability of the semiconductor device 400 is improved.
  • the semiconductor device 400 in which the semiconductor units 100 and 200 including the SiC-MOSFET chip 12 and the SiC-Di chip 2 are combined has been described as an example. As described above, as the semiconductor chip to be used, The present invention is not limited to the SiC-MOSFET chip 12 or the SiC-Di chip 2.

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Abstract

　各チップ間で均一な並列動作をする半導体ユニットと、この半導体ユニットを用いて製作される熱抵抗が小さな低コストで高信頼性の半導体装置を提供することにある。　ワイドギャップ基板であるＳｉＣ基板で形成された同一で複数の小さな半導体チップ（ＳｉＣ－Ｄｉチップ（２））を２枚の導電板（共通銅板（１），（８））で挟みこみ、並列接続して半導体ユニット（１００）を形成する。こうすることで、複数の半導体チップ（ＳｉＣ－Ｄｉチップ（２））の並列動作が均一化し、電流集中による破壊が防止できる高信頼性の半導体ユニット（１００）とすることができる。

Description

半導体ユニットおよびそれを用いた半導体装置
　この発明は、複数の半導体チップを上下の導電板で挟んだ半導体ユニットと、この半導体ユニットを用いた半導体装置に関する。
　近年、インバータ装置などを構成する半導体モジュールとして、Ｓｉ－ＩＧＢＴ（Ｓｉ半導体基板を用いて製作した絶縁ゲートバイポーラトランジスタ）とＦＷＤ（フリーホイーリングダイオード）としてＳｉＣ－Ｄｉ（ＳｉＣ半導体基板を用いて製作したダイオード）を用いる構造の半導体装置が開発されている。このＳｉＣ－Ｄｉはショットキーバリアダイオードであり、Ｓｉ半導体基板で製作するショットキーバリアダイオードより高耐圧化でき、またｐｎダイオードよりスイッチング損失を小さくできる。尚、ＳｉはシリコンでありＳｉＣは炭化シリコン（炭化珪素）である。
　図５は、従来の半導体装置の構成図であり、同図（ａ）はケース内の配置図、同図（ｂ）は要部断面図である。この半導体装置５００は、２個のＳｉ－ＩＧＢＴチップ６６と、フリーホイーリングダイオードである８個のＳｉＣ－Ｄｉチップ（ＳｉＣ－ダイオードチップ）６８とからなる半導体モジュールである。この半導体装置５００は、インバータの１つの上アーム、または下アームを構成できる。
　半導体装置５００は、銅ベース板６１上に導電パターン付き絶縁基板６２を接合し、導電パターン付き絶縁基板６２上に第１導電パターン６３、第２導電パターン６４、および第３導電パターン６５が形成されている。この第１導電パターン６３と、Ｓｉ－ＩＧＢＴチップ６６のコレクタ電極６７、第２導電パターン６４にＳｉＣ－Ｄｉチップ６８のカソード電極６９がそれぞれ図示しない半田やＡｇペーストで接合されている。Ｓｉ－ＩＧＢＴチップ６６のエミッタ電極７０と、ＳｉＣ－Ｄｉチップ６８のアノード電極７１は、アルミニウムのワイヤ７２で第２導電パターン６４に接続する。また、Ｓｉ－ＩＧＢＴチップ６６のゲートパッド７３は、アルミニウムのワイヤ７４で第３導電パターン６５に接続する。
　第１導電パターン６３、第２導電パターン６４は、第３導電パターン６５にコレクタ端子Ｃ、エミッタ端子Ｅおよびゲート端子Ｇをそれぞれ接合する。
　各チップを収納するケース７５は、放熱体である銅ベース板６１に接合し、このケース７５上に前記の各端子（コレクタ端子Ｃ、エミッタ端子Ｅ、ゲート端子Ｇ）を露出させ、ケース７５内には例えば図示しないゲルが充填されている。
　図５では、２個のＳｉ－ＩＧＢＴチップ６６と８個のＳｉＣ－Ｄｉチップ６８がケース７５に収納されている。ＳｉＣ半導体基板の結晶性が必ずしも良くないため、１つのＳｉＣ－Ｄｉチップ６８の大きさには制約があり、数ｍｍ角程度である。そのため、半導体装置５００は、１つのＳｉ－ＩＧＢＴチップ６６に対して、例えば、４個のＳｉＣ－Ｄｉチップ６８が必要となる。場合によっては、さらにＳｉＣ－Ｄｉチップ６８を多くする必要がある。
　特許文献１では、並列接続する異種の素子を導電板で接続して樹脂封止して半導体ユニット（単位パッケージともいう）とし、この半導体ユニット（単位パッケージ）を複数用いて半導体モジュールを構成することが開示されている。
特許第４２５４５２７号公報
　前記したように、ＳｉＣ半導体基板は大面積になると結晶欠陥を多数含むため、ＳｉＣ半導体基板を用いたＳｉＣ－Ｄｉチップ６８の大きさ（前記したように数ｍｍ角程度）は、Ｓｉを用いたＤｉチップの大きさに比べて小さくなる。そのため、図５に示すようなＳｉＣ－Ｄｉチップ６８を用いる半導体モジュール（半導体装置５００）では、多数のＳｉＣ－Ｄｉチップ６８を並列接続させて用いる必要がある。
　そのため、半導体モジュール（半導体装置５００）は、接続に用いるワイヤ７２の本数が多くなり、工数が増大しコストが増大する。また、半導体モジュール（半導体装置５００）は、ワイヤ７２の長さのばらつきにより、各チップ間の並列動作にばらつきが生じて電流集中を起こすチップが破壊する場合が出てきて、半導体モジュール（半導体装置５００）の信頼性が低下する。また、半導体モジュール（半導体装置５００）は、片面冷却構造のため、熱抵抗が高い。
　また、特許文献１では、同一種の素子（例えば、ＳｉＣ－Ｄｉチップなど）を複数並列に接続して半導体ユニット（単位パッケージ）を形成し、この半導体ユニットを用いて半導体装置を組み立てることについては記載されていない。
　この発明の目的は、前記の課題を解決して、各チップ間で均一な並列動作をする半導体ユニットと、この半導体ユニットを用いて製作される熱抵抗が小さな低コストで高信頼性の半導体装置を提供することにある。
　上記目的を達成するために、以下に示すような、半導体ユニットが提供される。半導体ユニットは、ワイドギャップ半導体基板を用いて形成される半導体チップを多数並列接続してなる半導体ユニットにおいて、第１の共通導電板の第１の主面上に同一種の複数の前記半導体チップの一方の主面を接合し、前記半導体チップの他方の主面に導電ブロックをそれぞれ接合し、該複数の導電ブロック上に第２の共通導電板の第１の主面を接合し、前記第１の共通導電板の第２の主面と前記第２の共通導電板の第２の主面とを露出させ、前記第１の共通導電板の第１の主面と前記第２の共通導電板の第１の主面との間に絶縁樹脂を充填して一体化する。
　また、上記半導体ユニットは、次のようにして提供される。前記半導体チップは、ＳｉＣ－ダイオードチップであり、前記一方の主面にはカソード電極が形成され、前記他方の主面にはアノード電極が形成され、前記カソード電極が前記第１の共通導電板の前記第１の主面に接合され、前記アノード電極が前記導電ブロックを介して前記第２の共通導電板の前記第１の主面に接合される。
　また、上記半導体ユニットは、次のようにして提供される。前記半導体チップは、ＳｉＣスイッチングデバイスであり、前記一方の主面には第１主電極が形成され、前記他方の主面には第２主電極とゲート電極が形成され、前記第２の共通導電板とは絶縁されて前記第２の共通導電板の第２の主面側に導出される第３の導電板を備え、前記第１主電極が前記第１の共通導電板の前記第１の主面に、前記第２主電極が前記導電ブロックを介して接合され、前記第２の共通導電板の前記第１の主面に、前記ゲート電極が前記第３の導電板に接合される。
　また、上記目的を達成するために、第１の半導体ユニットと、第２の半導体ユニットと、を共通の絶縁基板に搭載して接続する半導体装置が提供される。第１の半導体ユニットは、前記半導体チップとしてＳｉＣ－ダイオードチップを内蔵する上記半導体ユニットであり、第２の半導体ユニットは、前記半導体チップとしてＳｉＣスイッチングデバイスを内蔵する上記半導体ユニットであり、前記ＳｉＣ－ダイオードチップは、前記一方の主面にはカソード電極が形成され、前記他方の主面にはアノード電極が形成され、前記カソード電極が前記第１の共通導電板の前記第１の主面に接合され、前記アノード電極が前記導電ブロックを介して前記第２の共通導電板の前記第１の主面に接合され、前記ＳｉＣスイッチングデバイスは、前記一方の主面には第１主電極が形成され、前記他方の主面には第２主電極とゲート電極が形成され、前記第２の共通導電板とは絶縁されて前記第２の共通導電板の第２の主面側に導出される第３の導電板を備え、前記第１主電極が前記第１の共通導電板の前記第１の主面に、前記第２主電極が前記導電ブロックを介して接合され、前記第２の共通導電板の前記第１の主面に、前記ゲート電極が前記第３の導電板に接合される。
　また、上記目的を達成するために、第１の半導体ユニットと、シリコン半導体基板に形成されたＩＧＢＴチップと、を共通の絶縁基板に搭載して接続する半導体装置が提供される。第１の半導体ユニットは、前記半導体チップとしてＳｉＣ－ダイオードチップを内蔵する上記半導体ユニットであり、前記ＳｉＣ－ダイオードチップは、前記一方の主面にはカソード電極が形成され、前記他方の主面にはアノード電極が形成され、前記カソード電極が前記第１の共通導電板の前記第１の主面に接合され、前記アノード電極が前記導電ブロックを介して前記第２の共通導電板の前記第１の主面に接合される。
　この発明によれば、ワイドギャップ半導体基板であるＳｉＣ半導体基板やＧａＮ半導体基板で形成された同一で複数の小さな半導体チップを２枚の導電板（共通銅板）で挟みこみ、並列接続して半導体ユニットを形成する。こうすることで、複数の半導体チップの並列動作が均一化し、電流集中による破壊が防止できる高信頼性の半導体ユニットとすることができる。
　Ｓｉ－ＩＧＢＴチップとフリーホイーリングダイオードとなるＳｉＣ－Ｄｉチップで構成された半導体ユニットとを逆並列接続して、例えばインバータの上アームもしくは下アームとなる半導体装置を形成することで、熱抵抗が小さな低コストで高信頼性の半導体装置とすることができる。
　また、ＳｉＣ－ＭＯＳＦＥＴチップで構成される半導体ユニットと、ＳｉＣ－Ｄｉチップで構成される半導体ユニットとを逆並列接続して、インバータの上アームもしくは下アームとなる半導体装置を形成することで、熱抵抗が小さな低コストで高信頼性の半導体装置とすることができる。
　本発明の上記および他の目的、特徴および利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
この発明の第１実施例の半導体ユニットの構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ１－Ｘ１線で切断した要部断面図である。 この発明の第２実施例の半導体ユニットの構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ３－Ｘ３線で切断した要部断面図である。 この発明の第３実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ５－Ｘ５線で切断した要部断面図である。 この発明の第４実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ６－Ｘ６線で切断した要部断面図である。 従来の半導体装置の構成図であり、（ａ）はケース内の配置図、（ｂ）は要部断面図である。
　実施の形態を以下の実施例で説明する。
＜実施例１＞
　図１は、この発明の第１実施例の半導体ユニットの構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ１－Ｘ１線で切断した要部断面図である。図１（ａ）は、図１（ｂ）のＸ２－Ｘ２線で切断した平面から矢印方向に見た模式的な要部平面図である。この半導体ユニット１００は、炭化珪素半導体基板（ＳｉＣ半導体基板）に形成されたダイオードチップ（以下、ＳｉＣ－Ｄｉチップという）２を複数個、を並列接続した構造の半導体モジュールである。
　ＳｉＣ－Ｄｉチップ２は、一方の主面にカソード電極３が形成され、他方の主面にアノード電極５が形成された素子である。
　この例では、第１共通銅板（第１の共通電極板）１上に４個のＳｉＣ－Ｄｉチップ２のカソード電極３を半田４で接合し、４個のＳｉＣ－Ｄｉチップ２のアノード電極５上にそれぞれヒートスプレッダとしての銅ブロック６を半田７で接合する。それぞれの銅ブロック６上に１つの第２共通銅板（第２の共通電極板）８を半田９で接合する。そして、第１共通銅板１のＳｉＣ－Ｄｉチップ２との接合面とは反対側の主面と、同じく第２共通銅板８の銅ブロック６との接合面とは反対側の面を露出させ、第１共通銅板１と第２共通銅板８で挟まれた領域、少なくともＳｉＣ－Ｄｉチップ２の端部２ａを覆う領域をシリコーンゴムやエポキシ樹脂などの高耐熱樹脂１０でモールドする。
　ここで、少なくともＳｉＣ－Ｄｉチップ２の端部２ａを覆う高耐熱樹脂１０は、ＳｉＣ－Ｄｉチップ２の動作時の温度（例えば１５０℃）に至っても、絶縁性や密着性などの封止性能が劣化しない必要があり、耐熱温度は１７５℃程度である。
　この４個の小さなＳｉＣ－Ｄｉチップ２が並列接続されて構成される半導体ユニット１００は、等価的に大面積の素子構造になり、１素子化される。このため、半導体ユニット１００を用いれば、例えば数ｍｍ角の微小なＳｉＣ－Ｄｉチップ２複数個をあたかも１素子（例えば１辺が１ｃｍ弱の１素子）として一括して取り扱うことができる。このような半導体ユニット１００を予め作成しておくことで、後述する半導体装置を組み立てる際にも、ＳｉＣ－Ｄｉチップ２の取り扱いが容易となる。
　また、半導体ユニット１００は、４個の小さなＳｉＣ－Ｄｉチップ２が第１共通銅板１と第２共通銅板８で挟まれ、ワイヤボンディングレスの構造であるため、４個のＳｉＣ－Ｄｉチップ２の相互間では、ボンディングワイヤに存在するインダクタンス成分による影響がなく均一な並列動作をする。そのため、特定の１個のＳｉＣ－Ｄｉチップ２に電流が集中することがなくなるため、素子破壊が防止できて高信頼性化できる。
　また、この半導体ユニット１００は、第１共通銅板１と第２共通銅板８との両面冷却構造となり、ＳｉＣ－Ｄｉチップ２で発生した熱は第１共通銅板１と第２共通銅板８の両方から放熱されるため、熱抵抗は小さくなる。
＜実施例２＞
　図２は、この発明の第２実施例の半導体ユニットの構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ３－Ｘ３線で切断した要部断面図である。図２（ａ）は、図２（ｂ）のＸ４－Ｘ４線で切断した平面から矢印方向に見た模式的な要部平面図である。この半導体ユニット２００は、ＳｉＣ半導体基板に形成されたＳｉＣ－ＭＯＳＦＥＴチップ１２を複数個、並列接続した構造の半導体モジュールである。
　ここで、ＳｉＣ－ＭＯＳＦＥＴチップ１２は、ＳｉＣ製のスイッチングデバイスの一例であり、ＳｉＣ製のスイッチングデバイスは、ＳｉＣ－ＪＦＥＴ（Junction Field Effect Transistor：接合型電界効果トランジスタ），ＳｉＣ－ＩＧＢＴなども適用可能である。ここでは、ＳｉＣ－ＭＯＳＦＥＴチップ１２を例示して説明する。
　ＳｉＣ－ＭＯＳＦＥＴチップ１２は、一方の主面にドレイン電極１３が形成され、他方の主面にソース電極１５とゲートパッド２４が形成された素子である。
　図２の半導体ユニット２００と図１の半導体ユニット１００の違いは、半導体チップとしてＳｉＣ－Ｄｉチップ２をＳｉＣ－ＭＯＳＦＥＴチップ１２に置き換えた点である。また、第１共通銅板１の代わりに、図２に示すような補助導電パターン付き絶縁基板１１を用いた点である。
　補助導電パターン付き絶縁基板１１は、図２に示すように裏面に裏面金属膜２０を形成し、おもて面にＭＯＳＦＥＴが接合する第１導電パターン２１を形成し、この裏面金属膜２０は絶縁基板２２を貫通した接続導体２３で第１導電パターン２１に接続する。また、接続導体２３を設けずに、第１導電パターン２１と裏面金属膜２０をワイヤなどで接続してもよい。
　補助導電パターン付き絶縁基板１１の第１導電パターン２１上に４個の小さなＳｉＣ－ＭＯＳＦＥＴチップ１２の各ドレイン電極１３を半田１４で接合し、各ＳｉＣ－ＭＯＳＦＥＴチップ１２のゲートパッド２４をそれぞれ独立した第２導電パターン２５にワイヤ２６を介して接続する。
　４個のＳｉＣ－ＭＯＳＦＥＴチップ１２のソース電極１５にそれぞれ銅ブロック１６を半田１７で接合する。それぞれの銅ブロック１６上に１つの共通銅板１８を半田１９で接合する。
　共通銅板１８には、共通銅板１８とは絶縁されたゲート導体２７が貫通している。ゲート導体２７は、第２導電パターン２５を介してＳｉＣ－ＭＯＳＦＥＴチップ１２のゲートパッド２４に接続されている。
　そして、絶縁基板１１の裏面金属膜２０と共通銅板１８の銅ブロック１６との接合面とは反対側の面を露出させ、絶縁基板１１と共通銅板１８で挟まれた領域、少なくともＳｉＣ－ＭＯＳＦＥＴチップ１２の端部１２ａを覆う領域をシリコーンゴムやエポキシ樹脂などの高耐熱樹脂２８でモールドする。
　ここで、少なくともＳｉＣ－ＭＯＳＦＥＴチップ１２の端部１２ａを覆う高耐熱樹脂２８は、ＳｉＣ－ＭＯＳＦＥＴチップ１２の動作時の温度（例えば１５０℃）に至っても、絶縁性や密着性などの封止性能が劣化しない必要があり、耐熱温度は１７５℃程度である。
　前記の補助導電パターン付き絶縁基板１１が図１の第１共通銅板１の役割をする。この半導体ユニット２００の場合も前記の半導体ユニット１００とほぼ同様の効果が得られる。但し、ＳｉＣ－ＭＯＳＦＥＴチップ１２で発生した熱は下方側では補助導電パターン付き絶縁基板１１から放熱されるので、図１の第１共通銅板１から放熱される場合より熱抵抗は高くなる。しかし、接続導体２３の断面積を大きくすれば熱抵抗を下げることができる。
　この４個の小さなＳｉＣ－ＭＯＳＦＥＴチップ１２が並列接続されて構成される半導体ユニット２００は、等価的に大面積の素子構造になり、１素子化される。このため、半導体ユニット２００を用いれば、例えば、複数個の微小（数ｍｍ角）なＳｉＣ－ＭＯＳＦＥＴチップ１２をあたかも１素子（例えば１辺が１ｃｍ弱の１素子）として一括して取り扱うことができる。このような半導体ユニット２００を予め作成しておくことで、後述する半導体装置を組み立てる際にも、ＳｉＣ－ＭＯＳＦＥＴチップ１２の取り扱いが容易となる。
　尚、実施例１および実施例２では、小さなＳｉＣ－Ｄｉチップ２および小さなＳｉＣ－ＭＯＳＦＥＴチップ１２で構成された半導体ユニット１００，２００をそれぞれ例として挙げた。しかし、チップとしてはＳｉＣ－Ｄｉチップ２やＳｉＣ－ＭＯＳＦＥＴチップ１２に限るものではない。また、例えば、ＧａＮ（窒化ガリウム）半導体基板などバンドギャップの広い半導体基板を用いて形成された素子で面積の大きいチップの製作が困難な場合、複数の小さなチップを並列動作させる本構造が有用である。また、将来的には、ＳｉＣ－ＩＧＢＴチップおよびＧａＮ－Ｄｉチップ、ＧａＮ－ＭＯＳＦＥＴチップ，ＧａＮ－ＩＧＢＴチップなどにも本発明を適用することができる。
　また、半導体ユニット１００，２００は４個の同一の小さなＳｉＣ－Ｄｉチップ２あるいはＳｉＣ－ＭＯＳＦＥＴチップ１２で構成された例を示したが、個数についてはこれに限るものではない。所望の電流容量となるように、半導体ユニット１００，２００に格納するＳｉＣ－Ｄｉチップ２，ＳｉＣ－ＭＯＳＦＥＴチップ１２の個数（並列数）を適宜変更すればよい。
＜実施例３＞
　図３は、この発明の第３実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ５－Ｘ５線で切断した要部断面図である。図３（ａ）はケース４４内の模式的な配置図である。
　この半導体装置３００は、２個のＳｉ－ＩＧＢＴチップ３５にフリーホイーリングダイオードとしてＳｉＣ－Ｄｉチップ２で構成される半導体ユニット１００を逆並列接続した構造であり、インバータの１つの上アームもしくは１つの下アームを構成する半導体モジュールである。個数についてはこれに限るものではない。
　銅ベース板３１上に導電パターン付き絶縁基板３２の裏面金属膜３３を図示しない半田で接合し、第３導電パターン３４上に２個のＳｉ－ＩＧＢＴチップ３５のコレクタ電極３６とＳｉＣ－Ｄｉチップ２で構成された２個の半導体ユニット１００の第１共通銅板１を図示しない半田で接合する。
　Ｓｉ－ＩＧＢＴチップ３５のエミッタ電極３７と第４導電パターン３８をワイヤ３９で接続する。また、Ｓｉ－ＩＧＢＴチップ３５のゲートパッド４０と第５導電パターン４１をワイヤ４２で接続する。半導体ユニット１００の第２共通銅板８と第４導電パターン３８をフリキシブルな平板のリボンワイヤ４３で接続する。
　前記の第３導電パターン３４にコレクタ端子Ｃ、第４導電パターン３８にエミッタ端子Ｅ、第５導電パターン４１にゲート端子Ｇを接続する。
　尚、このリボンワイヤ４３の代わりに複数の銅線やアルミニウム線、あるいは単なる薄い銅板などの導体を用いても構わない。
　Ｓｉ－ＩＧＢＴチップ３５と、ＳｉＣ－Ｄｉチップ２で構成された半導体ユニット１００とが収納されるように上方からケース４４を被せ、エミッタ端子Ｅ、コレクタ端子Ｃおよびゲート端子Ｇをケース４４の上面に露出させる。また、ケース４４の下部を銅ベース板３１に接合し、図示しないゲルをケース４４内に充填して半導体装置３００が完成する。
　半導体装置３００は、半導体ユニット１００を用いることで、従来の半導体装置５００に比べると、組立性が向上し、半導体装置３００の低コスト化を図ることができる。
　また、４個のＳｉＣ－Ｄｉチップ２のアノード電極５が銅ブロック６を介して第２共通銅板８に接続する構造であるため、４個のＳｉＣ－Ｄｉチップ２間のインダクタンスのばらつきは小さくなり、この４個のＳｉＣ－Ｄｉチップ２は均一な並列動作ができる。その結果、電流集中による半導体ユニット１００の破壊が生じ難くなり、半導体装置３００の信頼性が向上する。
　また、半導体ユニット１００は両面から冷却されるため、半導体装置３００の熱抵抗を小さくできる。
＜実施例４＞
　図４は、この発明の第４実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ６－Ｘ６線で切断した要部断面図である。図４（ａ）はケース５７内の模式的な配置図である。
　この半導体装置４００は、ＳｉＣ－ＭＯＳＦＥＴチップ１２で構成される半導体ユニット２００にフリーホイーリングダイオードとしてＳｉＣ－Ｄｉチップ２で構成される半導体ユニット１００を逆並列接続した構造であり、インバータの１つの上アームもしくは１つの下アームを構成する半導体モジュールである。ここでは、半導体ユニット１００，２００は共に２個の例を挙げたが、個数はこれに限るものではない。
　銅ベース板５１上に導電パターン付き絶縁基板５２を図示しない半田で接合し、第６導電パターン５３上に２個のＳｉＣ－ＭＯＳＦＥＴチップ１２で構成された半導体ユニット２００の補助導電パターン付き絶縁基板１１を図示しない半田で接合する。
　また、第６の導電パターン５３上に２個のＳｉＣ－Ｄｉチップ２で構成された半導体ユニット１００の第１共通銅板１を図示しない半田で接合する。
　半導体ユニット２００の共通銅板１８と第７導電パターン５４をフリキシブルな平板のリボンワイヤ５５で接続する。また、半導体ユニット１００の第２共通銅板８と第７導電パターン５４をフリキシブルな平板のリボンワイヤ５５で接続する。また、半導体ユニット２００のゲート導体２７を第８導電パターン５６にワイヤ５８で接続する。このゲート導体２７と共通銅板１８は、高耐熱樹脂２８で電気的に絶縁されている。
　また、前記の第６導電パターン５３にコレクタ端子Ｃ、第７導電パターン５４にエミッタ端子Ｅおよび第８導電パターン５６にゲート端子Ｇをそれぞれ接合する。
　尚、このリボンワイヤ５５の代わりに複数の銅線やアルミニウム線、あるいは単なる薄い銅板などの導体を用いても構わない。
　ＳｉＣ－ＭＯＳＦＥＴチップ１２で構成された半導体ユニット２００とＳｉＣ－Ｄｉチップ２で構成された半導体ユニット１００が収納されるように上方からケース５７を被せ、ケース５７の上面からコレクタ端子Ｃ、エミッタ端子Ｅおよびゲート端子Ｇをそれぞれ露出させる。ケース５７の下部を銅ベース板５１に接合して半導体装置４００が完成する。
　ＳｉＣ－ＭＯＳＦＥＴチップ１２とＳｉＣ－Ｄｉチップ２をそれぞれ１個毎にワイヤを介して導電パターンに接続する従来の場合に比べると、半導体ユニット１００，２００を用いることで、組立性が向上し、半導体装置４００の低コスト化を図ることができる。
　また、両面冷却できる半導体ユニット１００，２００を用いることで、半導体装置４００の熱抵抗を小さくできる。
　また、半導体ユニット１００，２００を用いることで、各チップ間でのインダクタンスのばらつきは小さくなり、各チップ間で均一な並列動作ができる。その結果、電流集中による半導体ユニット１００，２００の破壊が生じ難くなり半導体装置４００の信頼性が向上する。
　尚、実施例４において、ＳｉＣ－ＭＯＳＦＥＴチップ１２とＳｉＣ－Ｄｉチップ２からなる半導体ユニット１００，２００を組み合わせた半導体装置４００を例に挙げたが、用いられる半導体チップとしては、前記したように、ＳｉＣ－ＭＯＳＦＥＴチップ１２やＳｉＣ－Ｄｉチップ２に限るものではない。
　上記については単に本発明の原理を示すものである。
　さらに、多数の変形、変更が当業者にとって可能であり、本発明は上記に示し、説明した正確な構成および応用例に限定されるものではなく、対応するすべての変形例および均等物は、添付の請求項およびその均等物による本発明の範囲とみなされる。
　１　第１共通銅板
　２　ＳｉＣ－Ｄｉチップ
　２ａ，１２ａ　端部
　３　カソード電極
　４，７，９，１４，１７，１９　半田
　５　アノード電極
　６，１６　銅ブロック
　８　第２共通銅板
　１０，２８　高耐熱樹脂
　１１　補助導電パターン付き絶縁基板
　１２　ＳｉＣ－ＭＯＳＦＥＴチップ
　１３　ドレイン電極
　１５　ソース電極
　１８　共通銅板
　２０，３３　裏面金属膜
　２１　第１導電パターン
　２２　絶縁基板
　２３　接続導体
　２４，４０　ゲートパッド
　２５　第２導電パターン
　２６，３９，４２，５８　ワイヤ
　２７　ゲート導体
　３１，５１　銅ベース板
　３２，５２　導電パターン付き絶縁基板
　３４　第３導電パターン
　３５　Ｓｉ－ＩＧＢＴチップ
　３６　コレクタ電極
　３７　エミッタ電極
　３８　第４導電パターン
　４１　第５導電パターン
　４３，５５　リボンワイヤ
　４４，５７　ケース
　５３　第６導電パターン
　５４　第７導電パターン
　５６　第８導電パターン
　１００，２００　半導体ユニット
　３００，４００　半導体装置
　Ｃ　コレクタ端子
　Ｅ　エミッタ端子
　Ｇ　ゲート端子

Claims (5)

  1. 　ワイドギャップ半導体基板を用いて形成される半導体チップを多数並列接続してなる半導体ユニットにおいて、
    　第１の共通導電板の第１の主面上に同一種の複数の前記半導体チップの一方の主面を接合し、前記半導体チップの他方の主面に導電ブロックをそれぞれ接合し、該複数の導電ブロック上に第２の共通導電板の第１の主面を接合し、前記第１の共通導電板の第２の主面と前記第２の共通導電板の第２の主面とを露出させ、前記第１の共通導電板の第１の主面と前記第２の共通導電板の第１の主面との間に絶縁樹脂を充填して一体化することを特徴とする半導体ユニット。
  2. 　前記半導体チップは、ＳｉＣ－ダイオードチップであり、前記一方の主面にはカソード電極が形成され、前記他方の主面にはアノード電極が形成され、
    　前記カソード電極が前記第１の共通導電板の前記第１の主面に接合され、
    　前記アノード電極が前記導電ブロックを介して前記第２の共通導電板の前記第１の主面に接合される、
    　ことを特徴とする請求の範囲第１項記載の半導体ユニット。
  3. 　前記半導体チップは、ＳｉＣスイッチングデバイスであり、前記一方の主面には第１主電極が形成され、前記他方の主面には第２主電極とゲート電極が形成され、前記第２の共通導電板とは絶縁されて前記第２の共通導電板の第２の主面側に導出される第３の導電板を備え、
    　前記第１主電極が前記第１の共通導電板の前記第１の主面に、前記第２主電極が前記導電ブロックを介して接合され、
    　前記第２の共通導電板の前記第１の主面に、前記ゲート電極が前記第３の導電板に接合される、
    　ことを特徴とする請求の範囲第１項記載の半導体ユニット。
  4. 　前記半導体チップとしてＳｉＣ－ダイオードチップを内蔵する請求の範囲第１項記載の第１の半導体ユニットと、
    　前記半導体チップとしてＳｉＣスイッチングデバイスを内蔵する請求の範囲第１項記載の第２の半導体ユニットと、
    　を共通の絶縁基板に搭載して接続する半導体装置であって、
    　前記ＳｉＣ－ダイオードチップは、
    　前記一方の主面にはカソード電極が形成され、前記他方の主面にはアノード電極が形成され、
    　前記カソード電極が前記第１の共通導電板の前記第１の主面に接合され、
    　前記アノード電極が前記導電ブロックを介して前記第２の共通導電板の前記第１の主面に接合され、
    　前記ＳｉＣスイッチングデバイスは、前記一方の主面には第１主電極が形成され、前記他方の主面には第２主電極とゲート電極が形成され、前記第２の共通導電板とは絶縁されて前記第２の共通導電板の第２の主面側に導出される第３の導電板を備え、
    　前記第１主電極が前記第１の共通導電板の前記第１の主面に、前記第２主電極が前記導電ブロックを介して接合され、
    　前記第２の共通導電板の前記第１の主面に、前記ゲート電極が前記第３の導電板に接合される、
    　ことを特徴とする半導体装置。
  5. 　前記半導体チップとしてＳｉＣ－ダイオードチップを内蔵する請求の範囲第１項記載の第１の半導体ユニットと、
    　シリコン半導体基板に形成されたＩＧＢＴチップと、
    　を共通の絶縁基板に搭載して接続する半導体装置であって、
    　前記ＳｉＣ－ダイオードチップは、
    　前記一方の主面にはカソード電極が形成され、前記他方の主面にはアノード電極が形成され、
    　前記カソード電極が前記第１の共通導電板の前記第１の主面に接合され、
    　前記アノード電極が前記導電ブロックを介して前記第２の共通導電板の前記第１の主面に接合される、
    　ことを特徴とする半導体装置。
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