WO2012166749A2 - Implantation d'ion et recuit pour des cellules solaires à rendement élevé à jonction arrière et contact arrière - Google Patents

Implantation d'ion et recuit pour des cellules solaires à rendement élevé à jonction arrière et contact arrière Download PDF

Info

Publication number
WO2012166749A2
WO2012166749A2 PCT/US2012/039901 US2012039901W WO2012166749A2 WO 2012166749 A2 WO2012166749 A2 WO 2012166749A2 US 2012039901 W US2012039901 W US 2012039901W WO 2012166749 A2 WO2012166749 A2 WO 2012166749A2
Authority
WO
WIPO (PCT)
Prior art keywords
thin
silicon
base
silicon substrate
laser
Prior art date
Application number
PCT/US2012/039901
Other languages
English (en)
Other versions
WO2012166749A3 (fr
Inventor
Mehrdad M. Moslehi
Virendra V. Rana
Pawan Kapur
Original Assignee
Solexel, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solexel, Inc. filed Critical Solexel, Inc.
Priority to KR1020137034723A priority Critical patent/KR101396027B1/ko
Priority to EP12793962.7A priority patent/EP2715797A4/fr
Publication of WO2012166749A2 publication Critical patent/WO2012166749A2/fr
Publication of WO2012166749A3 publication Critical patent/WO2012166749A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/035281—Shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This disclosure relates in general to the field of photovoltaics and solar cells, and more particularly to methods for manufacturing thin-film solar cells (TFSCs). More particularly, the present disclosure provides ion implantation applications for manufacturing Thin-Film Crystalline Silicon Solar Cells (TFSC).
  • TFSC Thin-Film Crystalline Silicon Solar Cells
  • Ion implantation involves implantation of ions of certain elements into a solid and is a standard technique used in the fabrication of semiconductor devices.
  • the implantation of dopant atoms such as phosphorous (P), arsenic (As), and boron (B) may be used to form semiconductor junctions, while the implantation of oxygen may be used in silicon-on-oxide (SOI) devices.
  • SOI silicon-on-oxide
  • c-Si crystalline silicon
  • the p-n junctions are often formed by either POC13-based doping, or a phosphorous compound deposition or spray-on followed by annealing.
  • C-Si Thin-Film Solar Cells may be advantageously made by depositing a thin layer of c-Si on a suitable substrate or by slicing a c-Si ingot into thin wafers using advanced wire sawing or other known techniques such as hydrogen implantation followed by annealing to cause thin wafer separation.
  • TFSS thin-film silicon substrates
  • CVD chemical vapor deposition
  • Solar cells created in this epitaxial silicon deposition method may be planar or have a well defined structure.
  • any three-dimensional surface structure is possible for 3-D cells, various performance limitations make certain 3-D structures more advantageous - such as pyramidal or prism based three-dimensional surface features.
  • the current standard technique for the formation of selective emitters involves several steps. Usually, the full front surface of a p-type wafer is lightly doped using the POC13 based process or a process involving spraying a phosphorous-compound followed by anneal. Then a passivating dielectric is deposited on the front surface of the silicon substrate. The regions that are desired to be metallization contacts are then selectively opened in this dielectric, usually by a laser ablation or an etch gel process. A second doping process is then carried out to selectively dope these localized regions with a high concentration of phosphorous. However, this process is often lengthy, costly, and inefficient.
  • the emitter characteristics are solely determined by the temperature and time used for the doping anneal.
  • the lifetime of minority charge carriers is greatly reduced at concentrations above lE18cm-3. For maximum blue response this would appear to be the upper limit of the dopant concentration in the emitter. However, this would lead to very high emitter sheet resistance and high series resistance and low fill factor (FF) and low current density (Jsc).
  • the method must include improved methods for forming emitter regions, base regions, and back/front surface fields in surface regions of thin-film solar cells.
  • Yet another technical advantage includes the utilization of the field effect to enhance passivation - this may be achieved by suitably charging the overlying dielectric using ion implantation.
  • FIGUREs 1A and IB show a top and cross-sectional view, respectively, of an example of a pyramidal three-dimensional thin-film silicon substrate (TFSS),;
  • TFSS pyramidal three-dimensional thin-film silicon substrate
  • FIGUREs 2A and 2B show a top and cross-sectional view, respectively, of an example of a three-dimensional thin-film silicon substrate (TFSS) with prism surface features;
  • TFSS thin-film silicon substrate
  • FIGURE 3 illustrates a pyramidal three-dimensional thin-film solar cell with a standard configuration of frontside and backside contacts
  • FIGURE 4 illustrates a prism three-dimensional thin-film solar cell with a standard configuration of frontside and backside contacts
  • FIGURE 5 is a graph representing an idealized dopant profile for homogeneous emitters
  • FIGURE 6 shows an ion implantation process for variable doping on pyramidal three-dimensional TFSS
  • FIGURE 7 shows an angled ion implantation process on pyramidal three- dimensional TFSS
  • FIGURE 8 illustrates a pyramidal three-dimensional thin-film solar cell with selective frontside emitters
  • FIGURE 9 illustrates a pyramidal three-dimensional thin-film solar cell with all backside contacts
  • FIGURE 10 illustrates a planar thin-film solar cell with all backside contacts
  • FIGUREs 11A through 11B show a process flow for the formation of a reusable template for forming a crystalline thin-film silicon solar cell
  • FIGUREs 12A through 13D show the process flow for the formation of a front contact crystalline thin-film silicon solar cell in accordance with the disclosed subject matter
  • FIGUREs 14A through 15D show the process flow for the formation of a back contact crystalline thin-film silicon solar cell in accordance with the disclosed subject matter;
  • FIGUREs 16A through 16H show the process flow for the formation of a back contact planar crystalline thin-film silicon solar cell in accordance with the disclosed subject matter;
  • FIGURE 17 is a process flow for commercially manufacturing an all back contact back-junction solar cell using planar thin films
  • FIGURE 18 is a cross section of a back contact/back junction solar cell structure
  • FIGURE 19 is a modified process flow for the formation of islands (discrete) of isolated base contacts
  • FIGURES 20 to 24 are diagrams of a solar cell after key fabrication steps of FIGURE 19;
  • FIGURE 25 is a process flow embodiment for forming a selective emitter
  • FIGURE 26 shows a cell pattern with discrete isolated base and emitter
  • FIGURE 27 shows an alternative cell pattern embodiment
  • FIGURE 28 are graphs showing simulation results of FSF dopant concentration
  • FIGURES 29A-C are cross sections of a solar cell after FSF formation process steps
  • FIGURE 30 is process flow to form a solar cell with an FSF layer
  • FIGURE 31 is a combined process flow in accordance with the disclosed subject matter
  • FIGURE 32 is a process flow in accordance with the disclosed subject matter.
  • FIGURE 33 is a diagram of a cross section of the solar cell formed in accordance with the disclosed subject matter.
  • a preferred semiconductor material for the 3-D TFSS is crystalline silicon (c-Si), although other
  • semiconductor materials may also be used.
  • One embodiment uses monocrystalline silicon as the thin film semiconductor material.
  • Other embodiments use multicrystalline silicon,
  • polycrystalline silicon polycrystalline silicon, microcrystalline silicon, amorphous silicon, porous silicon, and/or a combination thereof.
  • the designs here are also applicable to other semiconductor materials including but not limited to germanium, silicon germanium, silicon carbide, a crystalline compound semiconductor, or a combination thereof. Additional applications include copper indium gallium selenide (CIGS) and cadmium telluride semiconductor thin films.
  • CGS copper indium gallium selenide
  • cadmium telluride semiconductor thin films include copper indium gallium selenide (CIGS) and cadmium telluride semiconductor thin films.
  • front and back are used to refer to the position of the metal contacts on the solar cell.
  • a front contact solar cell, or frontside contact is one which positioned on the solar cell side facing towards the light.
  • a back contact solar cell, or backside contact is one which is positioned on the solar cell side facing away from the light.
  • the present disclosure describes the use of ion implantation technique in the manufacture of 3-dimensional thin-film crystalline silicon solar cells (TFSC), including those with pyramidal and prism unit cell structures.
  • the present disclosure also describes the use of ion implantation technique in the manufacture of planar thin film crystalline silicon (c-Si) solar cells (TFSC).
  • TFSC planar thin film crystalline silicon
  • the present disclosure describes the use of ion implantation to form emitter regions, selective emitter regions, base regions, selective base regions, back surface fields, and front surface fields in a TFSC and the application of ion implantation methods to form the p-n junction for TFSC.
  • the present disclosure enables the use of ion implantation to independently control the dopant concentration and the emitter depth.
  • the dopant profile control sometimes referred to as profile engineering of emitters, is used to maximize the solar cell performance including but not limited to blue response, Voc, and current collection.
  • FIGUREs 1A and IB show a top and cross-sectional view, respectively, of an example of a pyramidal three-dimensional thin-film silicon substrate (TFSS), which also may be referred to as a wafer.
  • FIGURE 1A is a top view of an embodiment of a pyramidal TFSS comprised of large pyramidal cavities 10 and small pyramidal cavities 12 on a silicon substrate.
  • FIGURE IB is a cross-section of the substrate shown in FIGURE 1A, substrate 14, showing small pyramidal cavities 16 and large pyramidal cavities 18. It should be noted that the pyramidal structures may have flat top and bottom regions or may end in an angled apex/tips (as shown in FIGURE IB).
  • FIGUREs 2A and 2B show a top and cross-sectional view, respectively, of an example of a three-dimensional thin-film silicon substrate (TFSS) with prism surface features.
  • FIGURE 2A is a top view of an embodiment of a prism TFSS comprised of hexagonal prism structures 20 on a silicon substrate.
  • FIGURE 2B is a cross-section of the substrate shown in FIGURE 2A, substrate 22, showing hexagonal prism cavities 24.
  • One method for forming planar or three-dimensional TFSSs involves using an initial thick wafer as a substrate.
  • the substrate may be mono- or multi-crystalline.
  • the substrate surface may be patterned using techniques such as lithography.
  • a porous silicon structure is created on the surface.
  • CVD chemical vapor deposition
  • the epitaxial silicon layer is then dislodged from the porous silicon layer by mechanical or chemical means. This results in a wafer with a desired thickness and a planar or 3-D structure.
  • the example thin-film silicon substrates shown in FIGURESs 1 and 2 may be formed using this method.
  • the present disclosure employs thin film solar cells that have a three-dimensional structure where a desired structural pattern has been formed using MEMS type processing.
  • FIGURE 3 illustrates a pyramidal three-dimensional thin-film solar cell with a standard configuration of frontside (the solar cell side facing the light) and backside contacts positioned on the surface of the cell.
  • P-type (P+) base 30 often an epitaxial silicon layer, has been doped according to an ion implantation process to create N-type (N+) emitter layer 32 and p-type (P++) back surface field 34.
  • Emitter metal 38 and base metal 40 is an electroplated or electroless plated single or multilayer high-conductivity metallized regions (silver, aluminum, nickel, titanium, cobalt, or tantalum) - shown, emitter metal 38 is silver and base metal 40 is aluminum. Alternatively, the metal layer could be inkjet dispensed.
  • Anti-reflection coating 36 may also serve as a frontside passivation layer given a controlled thickness.
  • the emitter metal contacts are formed in continuous metal lines, i.e. fingers and busbars on the 3- D TFSC top surface.
  • the base metal contacts have been formed on the inverted pyramidal apex regions on the backside of the 3-D TFSS, the base metal contacts are isolated regions.
  • N+ emitter for a p-type base c-Si TFSC material The same procedures may be used to make P+ emitter for an n-type base c-Si TFSC material.
  • the dopant species may be P, As, and Sb, while B, Al, Ga, and In may be used to form P+ emitter in an n-type silicon TFSC substrate.
  • the ion implantation methods for forming a homogenous emitter layer 32 and back surface field 34 include forming a homogeneous phosphorous doped emitter in the front surface of the substrate by using ion implantation after manufacturing a 3-D thin-film c- Si p- type wafer.
  • the back surface field is created by implanting a P-type dopant such as boron.
  • the cell is then completed using standard passivation and metallization techniques.
  • FIGURE 4 illustrates a prism three-dimensional thin-film solar cell with a standard configuration of frontside (light side) and backside contacts positioned on the surface of the cell.
  • P-type (P+) base 50 often an epitaxial silicon layer, has been doped according to an ion implantation process to create N-type (N+) emitter layer 52.
  • Back surface dielectric 54 acts as a passivation layer.
  • emitter metal 58 is silver and base metal 60 is aluminum.
  • Anti- reflection coating 56 is an optical coating is an optical coating applied to the surface of the TFSC to reduce reflection.
  • emitter layer 52 may be created using phosphorous implantation and back surface dielectric 54 may be created using boron implantation.
  • the TFSC depicted in FIGURE 4 shows the metal to contact the back surface through a number of localized contacts opened in the back surface dielectric. The contact resistance of these contacts may be lowered using boron implantation. Alternatively, instead of these localized contacts a back surface field may be created using boron implantation.
  • ion implantation provides the ability to make shallow junctions of desired dopant concentrations by the control of ion dose and energy.
  • the use of the disclosed ion implantation process thus makes it possible to obtain emitters with the desired surface dopant concentration, profile, and depth.
  • Implanted emitters also eliminate the phosphorus dead layer and other complications commonly associated with POCl 3 - doped emitters.
  • FIGURE 5 is a graph representing an idealized dopant profile for homogeneous emitters in dopant concentration (atoms/cm ) over junction depth.
  • a precise control of the dopant profile may be only possible using a precision technology such as ion implantation.
  • a very thin layer ⁇ 0.1 um near the surface of the wafer has a high dopant concentration (up to Ie21/cm3) while the rest of the emitter has a dopant concentration close to 1E18 atoms/cm3.
  • FIGURE 6 shows an ion implantation process for variable doping on pyramidal three-dimensional TFSS 62.
  • pyramidal three-dimensional TFSS 62 has inverted pyramidal cavity walls aligned along the (111) crystallographic plane - thus ⁇ is about 54.7°.
  • the relative angular orientation of the implanted surface with respect to the incoming ion beam makes it possible to obtain a desired, variable doping by using an ion implantation process for doping the pyramidal three-dimensional TFSS 62.
  • the regions on the 3-D TFSS which have surfaces perpendicular to the incident ion beam are heavily doped, such as Region A, thus, creating a lower sheet resistance junction.
  • regions on the 3-D TFSS which receive ions at an angle such as the (111) inverted pyramidal cavity wall surfaces, shown as Region B, are doped effectively at a lighter dose, thus, creating a higher sheet resistance junction. Since the (111) surface (or any oblique orientation surface) is inclined at angle ⁇ (which is the angle with respect to the flat horizontal surfaces - shown these flat surfaces are aligned along the (100) crystallographic plane making ⁇ about 54.7°), the dopant concentration is reduced to cos6 of the horizontal surface.
  • a passivating dielectric such as SiN:H
  • metal for emitter contact metallization This may be carried out by using one the several techniques such: as an Ag paste that etches through the passivating dielectric; by making openings using laser ablation of the passivating dielectric: by removal using etch paste, followed by plating-based and/or PVD metal deposition.
  • the ion implantation process for variable doping to form selective emitters on the 3-D structure shown facilitates one step selective doping and the formation of dual-doped emitter junctions without a need for a more complex process flow using lithography or screen printing patterning.
  • FIGURE 7 shows an angled ion implantation process on pyramidal three- dimensional TFSS 64.
  • This ion implantation process may be used to selectively dope the regions around the tips/ledges of the three-dimensional surface features (shown as Region A) of TFSS 64.
  • the low doped emitter is first uniformly formed using an implantation direction normal to the plane of the TFSS 64 or by standard industrial techniques.
  • angled ion implantation is used to selectively heavily dope the tips of the structure (Region A in FIGURE 7) which are then selectively contacted by the metal.
  • the present disclosure also describes implantation of B and P ions to produce suitable back surface field (BSF) in thin-film planar and three dimensional solar cells in p-type or n-type silicon, respectively.
  • BSF back surface field
  • the current industrial practice of making the back surface field (BSF) using Al-paste firing and forming the Al-Si alloy to provide the P+ layer has severe limitations.
  • the p/p+ interface is not sharp but is instead diffused - resulting in low reflectivity for minority carrier electrons.
  • the Si/ Al-Si interface is also diffused, resulting in low optical reflectivity for long wavelength photons. Additionally, there are manufacturing problems such as the low
  • the wafer may be rotated during implantation so that all sides or faces of the structure are uniformly doped.
  • any desired profile of BSF may be obtained.
  • the structure of 3-D TFSC may be used to obtain selective doping for the BSF.
  • the heavily doped tips are then selectively contacted by a back metal, such as aluminum.
  • a back metal such as aluminum.
  • an angled ion implantation of the 3-D TFSC may be also used to obtain selective doping for the BSF.
  • the heavily doped tips are then selectively contacted by back metal.
  • the implant anneal process may be combined with oxidation to produce high quality front and back passivation of cells.
  • the passivation on N+ surfaces is enhanced when the passivating dielectric has extra positive charge.
  • the SiN:H typically used in the solar industry has a surplus positive charge which, when controlled properly, can help provide superior passivation of N+ surfaces.
  • the dielectric layer passivating the back surface field may be implanted with a negatively charged ion to further reduce the surface recombination due to the field effect.
  • the ion implantation methods of the present disclosure may also be used to obtain localized openings in the dielectric layer for metal contacts.
  • the tips or ledges of the 3-D TFSC are selectively implanted with an ion species, such as nitrogen, that retards/slows the growth of oxide during a subsequent thermal oxidation process.
  • an ion species such as nitrogen
  • passivating oxide grows everywhere except for these high, tip regions which have been selectively implanted.
  • the small amount of SiN formation due the implantation of N is easily removed in a cleaning sequence involving dilute HF followed by phosphoric acid etch.
  • These regions are then selectively contacted by metal.
  • the selectively opened regions can be selectively contacted with metal using plating, ink-jet or other techniques. This facilitates the optimization of front metal pattern to improve the cell performance.
  • On the back side these regions can be selectively plated or contacted upon the blanket deposition of aluminum using PVD or evaporation schemes.
  • Such localized contact scheme leads to the well know PERL type of cell structure and with it well known performance benefits.
  • FIGURE 8 illustrates a pyramidal three-dimensional thin-film solar cell with selective frontside emitters.
  • P-type (P+) base 70 an epitaxial silicon layer, has been doped according to an ion implantation process to create N-type (N+) emitter layer 72 and p-type (P++) back surface field 74.
  • Selective emitter 82 is formed through an angled ion implantation process.
  • the cell is then completed using standard passivation and metallization techniques to form emitter metal contacts 78 (silver) and base metal contacts 80 (aluminum).
  • Anti-reflection coating 76 is an optical coating is an optical coating applied to the surface of the TFSC to reduce reflection.
  • FIGURES 12A - 13D depict a detailed process flow describing the formation of the three-dimensional thin-film solar cell shown in FIGURE 8.
  • FIGURE 9 illustrates a pyramidal three-dimensional thin-film solar cell with all backside contacts.
  • N-type (N+) base 90 an epitaxial silicon layer, has been doped according to an ion implantation process to create N-type (N+) front side field 92 and p-type (P+) emitter layer 94.
  • Selective emitter 104 and selective base 102 are formed through angled ion
  • Anti-reflection coating 96 is an optical coating is an optical coating applied to the surface of the TFSC to reduce reflection.
  • Selective emitter 104 is conveniently obtained during the blanket implantation of emitter layer 94.
  • the n-type wafer with a pyramidal 3-D structure is implanted with boron to form emitter layer 94 - lower doped on the side walls but highly doped on the flat surface.
  • Front side field 92 is obtained by blanket implantation of phosphorous.
  • FIGURES 14A - 15D depict a detailed process flow describing the formation of the three-dimensional thin-film solar cell shown in FIGURE 9.
  • FIGURE 10 illustrates a planar thin-film solar cell with all backside contacts.
  • N- type (N+) base 110 an epitaxial silicon layer, has been doped according to an ion implantation process to create N-type (N+) front side field 112 and p-type (P+) emitter layer 114.
  • Selective emitter 124 and base 122 are formed through angled ion implantation processes and use plated metals, such as nickel and copper, as contacts.
  • the cell is then completed using standard passivation and metallization techniques to form base and emitter contact metals and backside passivation dielectric layer 118.
  • Anti-reflection coating 116 and reflective insulator 120 help to increase the light trapping capabilities of the planar TFSC.
  • the planar back contact TFSC in FIGURE 10 may be made from planar thin-film c- Si wafers.
  • N-type material is advantageous to when forming planar backside TFSC with methods of the present disclosure.
  • P-type (P+) emitter layer 114 is first made using a blanket implantation of the back surface of the wafer with boron.
  • backside passivation dielectric layer 118 is grown or deposited.
  • Base 122 is made by opening contacts in this dielectric and then implanting with phosphorous.
  • Selective emitter 124 is made next by passivating with a dielectric layer and opening contacts and implanting with boron.
  • Front surface field 112 is then obtained using the blanket implantation of phosphorous.
  • FIGURES 16A - 16H depict a detailed process flow describing the formation of the planar thin-film solar cell shown in FIGURE 10.
  • FIGURE 11A is a process flow showing the formation of a reusable template for forming a crystalline thin-film silicon solar cell (such as that shown in FIGURES 8 and 9).
  • FIGURE 11B is a corresponding illustrative depiction of the process steps in FIGURE 11A.
  • FIGURE 11A is an embodiment of a process flow depicting major fabrication process steps for manufacturing an inverted pyramidal silicon template and three-dimensional thin-film silicon substrate for use in forming a thin-film silicon solar cell in accordance with the ion implantation methods of the present disclosure.
  • a template for manufacturing inverted pyramidal solar cells is formed.
  • the silicon template making process starts with a mono-crystalline (100) silicon wafer (142).
  • the starting wafer may be in circular or square shapes.
  • Step 160 involves forming a thin hard masking layer (144) on the exposed wafer surfaces.
  • the hard masking layer is used to mask the silicon surface areas that do not need to be etched in the later steps - the surface areas that will become the top surface of the template.
  • the proper hard masking layer includes, but is not limited to, thermally grown silicon oxide and low-pressure vapor phase deposited (LPCVD) silicon nitride.
  • Steps 162 and 164 involve a photolithography step, which consists of photoresist coating, baking, UV light exposure over a photomask, post baking, photoresist developing, wafer cleaning and drying.
  • the pattern on the photomask (146) depicting an array or a staggered pattern of inverted pyramidal base openings, will be transferred to the photoresist layer.
  • the patterned photoresist layer is used as a soft masking layer for the hard masking layer etching of step 166.
  • Step 166 involves further transferring the photoresist pattern to the hard masking layer layered underneath by chemical etching, such as etching a thin silicon oxide layer with buffered HF solution. Other wet etching methods and dry etching methods as known in semiconductor and MEMS wafer processing may also be used.
  • step 168 the remaining soft masking layer, i.e. the photoresist layer (150), is removed and the wafer (148) is cleaned.
  • photoresist removal process examples include wet methods, such as using acetone or piranha solution (a mixture of sulfuric acid and hydrogen peroxide), or dry methods such as oxygen plasma ashing.
  • the wafers are batch loaded in an anisotropic silicon wet etchant such as KOH solution.
  • KOH anisotropic silicon wet etchant
  • the typical etch temperature is in the range of 50°C to 80°C and etch rate is about 0.2um/min to lum/min.
  • TMAH tetramethylammonium hydroxide
  • the KOH or TMAH silicon etch rate depends upon the orientations to crystalline silicon planes.
  • the (111) family of crystallographic planes are etched at a very slow rate and are normally "stop" planes for the anisotropic etching of a (100) silicon wafer with patterned hard mask.
  • the intersection of two (111) planes or a (111) plane with a bottom (100) plane produce anisotropic etching structures for (100) silicon wafers after a time-controlled etch. Examples of these structures include V-grooves and pyramidal cavities with sharp tip cavity bottom (where (111) planes meet) or a small flat cavity bottom (a remaining (100) plane).
  • silicon template 154 is ready for processing.
  • FIGURE 12A is a process flow showing the formation of a epitaxial silicon cell used for forming a crystalline thin-film front contact silicon solar cell (such as that shown in FIGURE 8).
  • FIGURE 12B is a corresponding illustrative depiction of the process steps in FIGURE 12A.
  • step 180 the remaining hard masking layer is removed, by HF solution in the case the hard masking layer is silicon dioxide.
  • the wafer may be cleaned in standard SCI (mixture of NH 4 OH and H 2 0 2 ) and SC2 (mixture of HCL and H 2 0 2 ) wafer wet cleaning solutions followed by a thorough deionized wafer rinsing and hot N 2 drying.
  • SCI mixture of NH 4 OH and H 2 0 2
  • SC2 mixture of HCL and H 2 0 2
  • Step 180 marks the beginning of a silicon template re-use cycle.
  • a porous silicon layer (192) is formed by electrochemical HF etching on the silicon template front surfaces.
  • the porous silicon layer is to be used as a sacrificial layer for epitaxial silicon layer release.
  • the porous silicon layer preferably consists of two thin layers with different porosities.
  • the first thin porous silicon layer is a top layer and is formed first from the bulk silicon wafer.
  • the first thin layer preferably has a lower porosity of 10% ⁇ 35%.
  • the second thin porous silicon layer is directly grown from the bulk silicon and is underneath the first thin layer of porous silicon.
  • the 2 nd thin porous silicon layer preferably has a higher porosity in the range of 40% ⁇ 80%.
  • the top porous silicon layer is used as a crystalline seed layer for high quality epitaxial silicon growth and the bottom underneath higher porosity porous silicon layer is used for facilitating TFSS release due to its less dense physical connections between the epitaxial and bulk silicon interfaces and its weak mechanical strength.
  • a single porous silicon layer with a progressively increased or graded porosity from top to bottom may also be used.
  • the top portion of the porous silicon layer has a low porosity of 10% to 35% and the lower portion of the porous silicon layer has a high porosity of 40% to 80%.
  • the wafer Before step 184, the epitaxial silicon growth, the wafer may be baked in a high temperature (at 950°C to 1150°C) hydrogen environment within the epitaxial silicon deposition reactor in order to form coalesced structures with relatively large voids within the higher-porosity porous silicon layer (or portion of a single layer) while forming a continuous surface seed layer of crystalline silicon on the lower-porosity porous silicon layer (or portion of a single layer).
  • a mono-crystalline silicon epitaxial layer with n-type base (194) is deposited on the front side only.
  • the bulk base of the epitaxial layer is p-type, boron (B 2 H6) doped.
  • the thickness of the epitaxial layer is preferably in the range of 5um to 60um.
  • an encompassing border trench may be made on the peripheral of the active wafer area to facilitate the release of the TFSS.
  • the encompassing trenches may be formed by controlled laser cutting and their depths are preferably in the range of 5um to lOOum.
  • the trenches define the boundary of the 3-D TFSS to be released and allow initiation of the release from the trenched region.
  • the remaining epitaxial silicon layer may be removed by mechanical grinding or polishing of the template edges.
  • the epitaxial layer of silicon (200) is released and separated from the silicon template.
  • the released epitaxial silicon layer is referred to as a 3-D thin film silicon substrate (3-D TFSS).
  • the epitaxial layer release methods disclosed in U.S. Patent Application No. 12/473,811 entitled, SUBSTRATE RELEASE METHODS AND APPARATUS are hereby incorporated by reference.
  • the 3-D TFSS may be released in an ultrasonic Dl-water bath.
  • the 3-D TFSS may be released by direct pulling with wafer backside and top epitaxial vacuum chucked.
  • the epitaxial layer is released by direct pulling with wafer backside and top epitaxial vacuum chucked. Using this method the porous silicon layer may be fully or partially fractured.
  • the chucks may use either electrostatic or vacuum chucking to secure the wafer.
  • the wafer is first placed on bottom wafer chuck with TFSS substrate facing upwards.
  • a bottom chuck secures the template side of wafer, and the top wafer chuck is gently lowered and secures TFSS substrate side of the wafer.
  • the activated pulling mechanism lifts top chuck upwards, and the movement may be guided evenly by slider rails.
  • step 188 the released 3-D TFSS backside surface is cleaned by short silicon etching using KOH or TMAH solutions to remove the silicon debris and fully or partially remove the quasi- mono-crystalline silicon (QMS) layer.
  • the template is cleaned in step 175 by using diluted HF and diluted wet silicon etch solution, such as TMAH and/or KOH to remove the remaining porous silicon layers and silicon particles.
  • the template is further cleaned by conventional silicon wafer cleaning methods, such as SCI and SC2 wet cleaning to removal possible organic and metallic contaminations.
  • the template is ready for another re-use cycle.
  • FIGURE 13A is a process flow showing the formation of a front contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 8).
  • FIGURE 13B is a corresponding illustrative depiction of the process steps in FIGURE 13A.
  • FIGURE 13C is a continuation of the process flow in FIGURE 13A showing the formation of a front contact crystalline thin-film silicon solar cell (such as that shown in
  • FIGURE 13D is a corresponding illustrative depiction of the process steps in FIGURE 13C.
  • FIGURE 14A is a process flow showing the formation of a epitaxial silicon cell used for forming a back contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 9).
  • FIGURE 14B is a corresponding illustrative depiction of the process steps in FIGURE 14A.
  • FIGURE 14C is a continuation of the process flow in FIGURE 14A showing the formation of a epitaxial silicon cell used for forming a back contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 9).
  • FIGURE 14D is a corresponding illustrative depiction of the process steps in FIGURE 14C.
  • FIGURE 15A is a process flow showing the formation of a back contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 9).
  • FIGURE 15B is a corresponding illustrative depiction of the process steps in FIGURE 15A.
  • FIGURE 15C is a continuation of the process flow in FIGURE 15A showing the formation of a back contact crystalline thin-film silicon solar cell (such as that shown in
  • FIGURE 15D is a corresponding illustrative depiction of the process steps in FIGURE 15C.
  • FIGURE 16A is a process flow showing the formation of a planar back contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 10).
  • FIGURE 16B is a corresponding illustrative depiction of the process steps in FIGURE 16A.
  • FIGURE 16C is a continuation of the process flow in FIGURE 16A showing the formation of a planar back contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 10).
  • FIGURE 16D is a corresponding illustrative depiction of the process steps in FIGURE 16C.
  • FIGURE 16E is a continuation of the process flow in FIGURE 16A showing the formation of a planar back contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 10).
  • FIGURE 16F is a corresponding illustrative depiction of the process steps in FIGURE 16E.
  • FIGURE 16G is a continuation of the process flow in FIGURE 16A showing the formation of a planar back contact crystalline thin-film silicon solar cell (such as that shown in FIGURE 10).
  • FIGURE 16H is a corresponding illustrative depiction of the process steps in FIGURE 16G.
  • the disclosed subject matter provides ion implantation methods for forming emitter regions, selective emitter regions, front surface fields, back surface fields, and base regions for the formation of crystalline thin-film silicon solar cells.
  • these techniques are particularly suited to solar cells that for various reasons, including but not limited to the thin cell lamination with a reinforcement plate, cannot be heated to high temperatures during part of their fabrication process, particularly during the formation of a surface passivation and anti-reflection coating layer.
  • NBLAC cell Processes for back contacted cells with interdigitated metallization, herein called a NBLAC cell, have been described in PCT applications such as P.C.T. App. Nos.
  • FIGURE 17 is a process flow for commercially manufacturing an all back contact back-junction solar cell using planar thin films (e.g., monocrystalline silicon film thickness of from a few microns to about 100 microns) of crystalline silicon epitaxially deposited on reusable crystalline silicon templates. After cell formation, the thin silicon films are supported on backplanes that connect the solar cell to interconnects in the module.
  • planar thin films e.g., monocrystalline silicon film thickness of from a few microns to about 100 microns
  • FIGURE 18 is a cross section of a back contact/back junction solar cell structure such as that formed by the process described in FIGURE 17, where the backplane is not shown for clarity.
  • the all back-contact back-junction solar cells have the alternating emitter and base regions on the same side (non-sunnyside or backside) in the silicon substrate that are contacted separately to interdigitated metal lines using contact openings in the dielectric overlying the silicon substrate and underneath the metal.
  • the efficiency of these cells is critically dependent on the dimensions of the base regions with smaller dimensions leading to higher efficiency.
  • the n and p regions form alternate stripes.
  • Ion implantation process involves implantation of ions of dopant element in the silicon substrates. Ions of phosphorous (P), arsenic (As), and antimony (Sb), are implanted to form n-type silicon regions, while boron (B), aluminum (Al), Gallium (Ga), and Indium (In), are used to form p-type silicon regions. The most commonly used ions are P and As for n-type, and B for p-type doping of silicon. Advantages of using ion implantation are the ability to control the concentration and the depth of implanted ions by controlling the ion implantation dose and energy.
  • the implanted ions may be placed in silicon in any desired concentration profile (for instance, by a combination of multiple implants at different dose and energy levels).
  • This technique is a non-contact, dry technique. Since the ion implantation is performed essentially at room temperature, this technique is suitable for solar cells that, for various reasons, cannot be heated to high temperatures after the ion implantation process step.
  • pulsed laser annealing may be highly localized (spatially selective on the laser-irradiated surface) and the irradiated surface may be heated to a relatively high temperature (sufficiently high to electrically activate the implanted dopant atoms, for instance, the irradiated surface temperature selectively raised to a temperature in the range of 750°C to up to near silicon melt temperature) while keeping the cell back surface relatively cooler (for instance, limiting the back-surface temperature to no more than 200°C).
  • pulsed laser annealing using fast pulses because of its extremely rapid heating and cooling rates and negligible heat diffusion into the substrate away from the irradiated surface, is ideally suited to producing the sharp dopant gradients where the dopant atoms are not moved (and the bulk substrate below the irradiated surface is not significantly heated) while being electrically activated.
  • the application of laser annealing to improve passivation of surface coated with SiN, a-SI SiN, or other suitable dielectrics have been disclosed (see U.S. Patent Application No. 13/303488 by Mehrdad Moslehi and filed Nov. 23, 2011 and U. S. Pat. App. No. 13/477088 by Virendra V. Rana and filed May 21, 2012 both of which are herein incorporated by reference in their entirety).
  • FIGURE 19 is a modified process flow for the formation of base regions that utilizes ion implantation followed by laser annealing.
  • FIGURE 19 are shown by the solar cell structure depicted in FIGURES 20 to 24.
  • FIGURE 20 is a diagram of a solar cell after base isolation areas have been opened by laser.
  • FIGURE 21 is a diagram of a solar cell after base contacts have been opened by laser.
  • FIGURE 22 is a diagram of a solar cell after base contacts have been implanted with phosphorous and laser annealed.
  • FIGURE 23 is a diagram of a solar cell after emitter contacts have been opened by laser.
  • FIGURE 24 is a diagram of a solar cell after an interdigitated metal pattern is connected to the emitter and base.
  • openings of dimension 'a' are preferably made in this oxide layer using a pulsed picoseconds or a femtoseconds laser (FIGURE 20) that are large enough for the base contacts of size 'b', as well as the required isolation from emitter, 'a' minus 'b' (FIGURE 21).
  • a pulsed picosecond or femtosecond laser significantly reduces the risk of damage to silicon by eliminating the Heat- Affected Zone (HAZ) and preventing / suppressing melting of underlying silicon.
  • a high temperature oxidation (or high-temperature anneal) is carried out at a temperature of preferably in the range of 950°C to 1100°C to dope the n-type silicon surface with boron to form emitter all over the wafer surface except in regions where the boron-doped oxide had been removed with pulsed laser ablation.
  • This oxidation (or oxidizing anneal) also forms a thin layer (from a few nanometers to 10's of nanometers) of thermal oxide in the laser openings as well as at the interface of the born-doped oxide layer with silicon substrate.
  • a thin layer of undoped oxide is deposited (again, preferably using an APCVD process) and opening for base contacts are made in the stack formed by this layer and the thermal oxide underneath, using a pulsed picoseconds or a femtoseconds laser.
  • These openings of dimension 'b' are inside the openings 'a' made earlier and aligned center- to-center.
  • the base contact diameter may range from 10 to over 100 ⁇ , a preferred range being 20 to 50 ⁇ .
  • the width of the isolation zone is 15 ⁇ or more based on the laser beam alignment capability.
  • the percent of base opening may be in the range from about 0.5% to over 10%, a preferred range being about 1 to 3%.
  • a blanket ion implantation of phosphorous (P) is carried out (FIGURE 22).
  • the base contacts are selectively implanted with P since the thermal oxide/deposited oxide stacks act as a mask to prevent the implantation of emitter regions.
  • the concentration (dose) and depth of P implants are suitable to obtain the desired doping for base contacts as well as the gradient required for back-surface field (BSF).
  • the surface concentration of dopants may be from 1 x 10 19 to 1 x 10 21 cm3, a preferred range being from 5 x 10 19 to 1 x 10 20 cm3.
  • the depth of implanted dopants may be from 0.1 to 5 ⁇ , a preferred range being from 0. 3 to 0.5 ⁇ .
  • These implants are electrically activated using pulsed laser anneal (FIGURE 22).
  • Pulsed laser with nanoseconds pulsewidth and wavelength in the blue, green or infrared (IR) are suitable for this operation.
  • the pulsewidth is in the range of approximately a few nanoseconds to a few microseconds, and preferably in the range of approximately 100 to 1,000 nanoseconds.
  • microseconds pulsewidth lasers it may be possible to use.
  • the contacts to emitter are opened using a pulsed picoseconds or a femtoseconds laser (FIGURE 23).
  • the metal layer preferably a metal stack layer comprising an aluminum layer in contact with the cell and at least another layer on top of aluminum comprising a metal from the group of NiV, Ni, or Ag
  • PVD physical vapor deposition
  • the rest of process may be as described in FIGURE 19.
  • an aluminum containing paste can be screen printed and annealed to form the interdigitated metal pattern while also making connection to the emitter and base contacts. The rest of the process may be as described in
  • ion implantation also provides a simple method to obtain the so-called "selective emitter” feature.
  • the doping concentration of emitter is kept low everywhere to reduce the absorption while under the metal contact the emitter is highly doped to reduce the contact resistance, and hence improve the solar cell efficiency.
  • FIGURE 25 is a process flow embodiment for forming a selective emitter.
  • the BSG layer is removed using laser and the silicon so exposed is implanted with a high concentration of boron.
  • the surface concentration of boron dopants may be from 1 x 10 19 to 1 x 10 21 cm3, a preferred range being from 5 x 10 19 to 1 x 10 20 cm3.
  • the depth of implanted dopants may be from 0.1 to 5 ⁇ , a preferred range being from 0.3 to 0.5 ⁇ .
  • the silicon surface is furnace annealed or annealed using a laser.
  • FIGURE 26 shows a cell pattern with discrete islands of base and emitter contacts with selective emitter
  • FIGURE 27 shows a cell pattern where the base isolation and selective emitter openings made using laser ablation may be continuous.
  • the passivation of the front surface (or the cell sunny side) has to be excellent to obtain high cell efficiency.
  • the passivation of the front surface is characterized by the front surface
  • FSRV recombination velocity
  • the FSRV is typically reduced to a very low value using PECVD SiN deposition followed by annealing to a relatively high temperature (e.g., up to 300°C to 850°C), or PECVD amorphous silicon deposition (typically deposited at a temperature of less than 200°C) .
  • PECVD SiN deposition followed by annealing to a relatively high temperature (e.g., up to 300°C to 850°C), or PECVD amorphous silicon deposition (typically deposited at a temperature of less than 200°C) .
  • An alternate scheme to lower the minority charge carrier recombination is to form a 'high-low' electrical field at the front surface.
  • This field electrically repels the oppositely charged carriers so that they are not able to reach the front surface and recombine there.
  • this field is created by a zone of heavier doping of phosphorous (or another n-type dopant such as arsenic or antimony) to create an n+ doped surface.
  • This high-low field at the front surface is called the front surface field (FSF).
  • FSF farnesoid-semiconductor
  • a sufficiently high temperature e.g., in the range of about 750°C up to below the silicon melting point
  • the assembly components on the backside such as the reinforcement or backplane layer on the cell backside
  • in-particular are not exposed to temperatures close to approximately the temperature limit of the backside reinforcement plate (for instance, 200°C or higher).
  • the FSF layer may be performed by using an ion implantation process either before or after formation of the front surface passivation layer (preferably by a PECVD process step), followed by a pulsed laser annealing after formation of the front surface passivation layer.
  • FIGURE 29A is a cross section of a solar cell with a textured frontside surface.
  • FIGURE 29B is a cross section of a solar cell after ion implantation of an n-type dopant such as phosphorous.
  • FIGURE 29C is a cross section of a solar cell after laser anneal to activate the implanted phosphorous (for n-type base).
  • electrically active FSF layer is carried out after surface texture, and preferably after deposition of the passivation and anti-reflection coating (ARC) layer(s) on the front surface of the silicon substrate (for instance, by PECVD formation of a single-layer or multi-layer passivation/ ARC coating comprising a hydrogen-containing silicon nitride and/or a hydrogen-containing amorphous silicon layer).
  • ARC passivation and anti-reflection coating
  • the thin-film monocrystalline silicon substrate is supported by a backplane (either a permanently attached / laminated backplane or a temporary support carrier) that may not be heated to high temperatures due to backplane material temperature limits and/or coefficient of thermal expansion (CTE) mismatch with silicon (typically, these constraints may place an upper temperature limit in the range of approximately 150°C to 300°C, and more likely below 250°C).
  • a backplane either a permanently attached / laminated backplane or a temporary support carrier
  • CTE coefficient of thermal expansion
  • an ion implantation process is a conformal process placing the implanted dopant species (e.g., phosphorus) at a uniformly constant depth conformal to the surface texture random pyramids, resulting in formation of dopant profile in silicon that is conformal to the textured solar cell surface.
  • the ion implantation process can be performed either before or preferably after the formation of the front surface passivation / ARC coating using a relatively low-energy ion implantation process.
  • the ion implantation energy is selected to place the peak concentration of the implanted profile approximately either at the interface between the silicon substrate and the passivation/ ARC coating or within the passivation/ ARC coating layer.
  • the dose of the ion implantation process may be adjusted such that the resulting peak implanted dopant concentration is preferably in the range of about 5 x 10 16 to 1 X 10 19 cm-3.
  • the front surface passivation may be SiN (composed of a single or at least two different refractive indices) or amorphous silicon/SiN stack, or oxide/ SIN stack, or other layers and stacks such as silicon oxynitride, with or without an oxide underlayer, and silicon carbide, etc.
  • the ion implantation process is tuned to provide dopant implantation, such as phosphorus (P) implantation for n-type base, such that the concentration peak is preferably at or near the silicon substrate/passivation layer interface.
  • the surface concentration of dopant, P for n-type base may be from 1E16 to 1E20 cm-3, while the preferred range is 5E16 to 1E19 cm-3.
  • the dopant atoms may be implanted and laser annealed to form an FSF layer to a depth below silicon surface that may range from about 10A to about 1 micron, while FSF layers in the thickness range of about 50A to about 0.1 ⁇ are preferred to prevent blue response degradation.
  • pulsed laser annealing can electrically activate the implanted dopant atoms without an appreciable movement.
  • pulsed laser annealing is performed under conditions which prevent excessive heating and melting of silicon in order to prevent damage to silicon and degradation of the passivation properties. This makes possible the formation of relatively sharp step function profiles of dopant atoms that help to amplify the repulsion field, and FSF field -assisted improvement of the front surface passivation properties.
  • a nanoseconds (to microseconds) pulsed laser with wavelength in the blue or green or red or infrared (IR) is suitable for spatially selective annealing.
  • the preferred pulsewidth is in the range of
  • microseconds pulsewidth lasers approximately 100 to 1,000 nanoseconds.
  • Other pulsed laser sources with pulse width between about 1 nanosecond to 100 nanoseconds or up to several microseconds may also be used.
  • FIGURE 30 A process flow to form a solar cell with an FSF layer based is shown in FIGURE 30.
  • FIGURE 31 shows a combined process flow where a high efficiency solar cell is made with ion implanted and annealed base contacts in the rear with an FSF in the front based on the embodiments of this disclosure.
  • FIGURE 32 shows a process flow where the selective emitter formation is also included.
  • FIGURE 33 is a diagram of a cross section of the solar cell formed in accordance with the disclosed subject matter (the backplane is not shown for clarity).
  • Conventional back contacted solar cells are n-type substrate and use PECVD based SiN based passivation for the sunny side.
  • This passivation also serves as an anti reflection coating and has a positive fixed charge which helps create a field effect by reflecting the minority carriers (holes in this case) away from the surface.
  • the typical good quality passivation deposition temperature for the PECVD SIN is about 400°C.
  • the maximum tolerable temperature can be much less than 400°C, as dictated by the integration scheme. For example, in the case of very thin film crystalline silicon solar cells, which are supported by carriers which are not capable of going higher than a maximum temperature less than 400°C.
  • this temperature can be as low as 200°C.
  • 200°C maximum temperature the issue is to get a passivation quality as good as a 400°C typical passivation.
  • a possible solution is to deposit very thin amorphous silicon (can be between 30A to 100A) range such that it is non-absorptive. The idea is that amorphous silicon contains significant hydrogen, which can passivate the dangling bonds, thereby improving the passivation quality.
  • the problem is that at 200°C temperature, the Hydrogen atoms may not have enough mobility to migrate from amorphous silicon to the silicon interface.
  • laser anneal is deployed, which in its pulsed form lasts for a very short duration. This should be enough to cause the migration of H2 atoms for short distance, without disturbing the integrity of the other parts of the structure.
  • the laser process must be such that the front surface is selectively heated, while ensuring that back surface, which may consist of temperature sensitive metal structures, is not affected.
  • this can be achieved using short wavelength laser, which is absorbed near the sunny side surface of the solar cell. Short wavelength laser (such as green) will be absorbed readily within a distance of lum or less, thus minimizing the chance of hitting the temperature sensitive back structure of a back contacted cell.
  • longer wavelengths such as ⁇ range may be used.
  • a longer wavelength will travel longer distance into silicon and may reach the backside without getting absorbed in the bulk.
  • a process must be designed such that front, sunny side, is heated, while the laser is stopped from hitting the backside. This can be achieved, either by absorbing the laser power in the silicon or by reflecting is before it reaches the backside. The absorption can be done in the bulk after the laser has already passed through the critical front side. This can be achieved using the aforementioned technique of flooding the bulk with carrier excited by potentially a different wavelength laser in a CW mode and relying on plasma dispersion effect to get it absorbed.
  • two specific embodiments are described below.
  • the fact that annealing laser is monochromatic is exploited.
  • a mirror is created on the backside using different refractive index.
  • the thicknesses are tuned in accordance with the refractive index such that laser at lum (or the relevant wavelength in use) is selectively reflective by the dielectric mirror stack.
  • the dielectric mirror stack can be made using Si02 and SIN.
  • the Si02 can either by deposited using myriad techniques such as thermal oxidation or APCVD. While, SiN can be deposited using PECVD. In many instances, at least a part of the dielectric stack might already be part of the back surface passivation. Since the metal is behind the dielectric mirror, thus formed, the laser is reflected back toward the front surface before it touches the back metal.
  • the angle of incidence of the laser may be varied in conjunction with the topography of the front typically textured surface.
  • the frontside consists of a passivation on top of silicon.
  • the light enters typically from a high refractive index to a lower refractive index.
  • the angle of incidence of the annealing laser can be varied in a manner such that when light falls on the back Silicon/dielectric (typically Si02) interface, its angle of incidence at this surface is greater than the critical angle for total internal reflection (henceforth, TIR).
  • TIR critical angle for total internal reflection
  • a process to form isolated islands of base and/or front surface field (FSF), using ion implantation followed by pulsed laser annealing are disclosed for all back-contact back-junction solar cells using thin-film crystalline silicon substrates; processes to form isolated islands of base and front surface field (FSF), using ion implantation followed by pulsed laser annealing are disclosed for all back-contact back-junction solar cells using thin-film crystalline silicon substrates with assemblies such as cell reinforcement plates or backplane laminates that cannot be heated to a temperature above approximately a maximum temperature in the range of 150°C to 3500°C.
  • the surface concentration of boron dopants may be from I x l019 to l x l021 cm3, a preferred range being from 5 x 1019 to l x 1020 cm3.
  • the depth of implanted dopants may be from 0.1 to 5 ⁇ , a preferred range being from 0.
  • processes to form front surface field (FSF), using ion implantation followed by laser annealing are disclosed for all back-contact back-junction solar cells using thin-film crystalline silicon substrates where the depth of the resulting FSF layer formed by a combination of ion implantation and pulsed laser anneal is in the range of approximately 10A to 0.5 ⁇ , the preferred range being about 50 to 1000 A.
  • the FSF formation is carried out for textured thin film silicon substrates that may be passivated with be SiN or amorphous silicon/SiN stack, or oxide/ SIN stack, or other layers and stack such as silicon oxynitride, with or without an oxide underlayer, and silicon carbide, etc, deposited at temperatures lower than 200°C.
  • processes to form front surface field (FSF), using ion implantation followed by pulsed laser annealing are disclosed for all back-contact back-junction solar cells using thin-film crystalline silicon substrates where the concentration peak for the dopant is approximately at the silicon/passivation layer interface.
  • processes to form front surface field (FSF), using ion implantation followed by laser annealing are disclosed for all back-contact back-junction solar cells using thin-film crystalline silicon substrates are disclosed where pulsed laser annealing is carried out using pulses with pulse width in the range of nanoseconds to microseconds, preferably a nanoseconds laser with blue or green or or red or IR wavelength, the preferred pulse width being in the range of approximately 100 to 1000 nanoseconds.
  • processes to form isolated islands of base for all back- contact back-junction solar cells using thin-film crystalline silicon substrates where the isolated base contact islands are formed using aligned laser ablation using picoseconds or femtoseconds pulsed laser with UV, green, or IR wavelengths.
  • the base contact diameter can range from 10 to 100 ⁇ , preferred range being 20 to 50 ⁇ .
  • the width of the isolation zone is preferably >15 ⁇ based on the laser beam alignment capability.
  • the percent of base opening can be in the range from about 0.5% to 10%, the preferred range being 1% to 3%.
  • processes to form isolated islands of base for all back- contact back-junction solar cells using thin-film crystalline silicon substrates where the base doping is carried out by ion implantation and followed by pulsed laser anneal.
  • the surface concentration of dopants can be from 1E19 to 1E21 cm-3, preferred range being from 5E19 to 1E20 cm-3.
  • the depth of implanted and annealed dopant can be approximately from 0. 1 to 5 ⁇ , preferred range being from about 0.3 to 0.5 ⁇
  • processes to anneal the wafer using a laser where the laser beam is prevented from heating the backplane as it is reflected from the
  • Si02/SiN bilayer at the back of the silicon film is Si02/SiN bilayer at the back of the silicon film.
  • process to anneal the wafer using laser are disclosed where the laser beam is prevented from heating the back plane as it undergoes full internal reflection because of the angle at which it is made to be incident on the back plane. This may be performed by controlling the incident angle of the laser beam depending on the dielectric stack on the front surface of the wafer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Sustainable Development (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne une cellule solaire en film mince à jonction arrière et contact arrière, qui est disposée sur une cellule solaire semi-conductrice en film mince. De préférence, la matière semi-conductrice de film mince comprend du silicium cristallin. Des régions émettrices, des régions émettrices sélectives et un champ de surface arrière sont formés par des procédés d'implantation d'ion et de recuit.
PCT/US2012/039901 2011-05-27 2012-05-29 Implantation d'ion et recuit pour des cellules solaires à rendement élevé à jonction arrière et contact arrière WO2012166749A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020137034723A KR101396027B1 (ko) 2011-05-27 2012-05-29 고효율 후면 접촉 후면 접합 태양 전지의 이온 주입 및 어닐링
EP12793962.7A EP2715797A4 (fr) 2011-05-27 2012-05-29 Implantation d'ion et recuit pour des cellules solaires à rendement élevé à jonction arrière et contact arrière

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161490859P 2011-05-27 2011-05-27
US61/490,859 2011-05-27

Publications (2)

Publication Number Publication Date
WO2012166749A2 true WO2012166749A2 (fr) 2012-12-06
WO2012166749A3 WO2012166749A3 (fr) 2013-03-28

Family

ID=47260262

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2012/039901 WO2012166749A2 (fr) 2011-05-27 2012-05-29 Implantation d'ion et recuit pour des cellules solaires à rendement élevé à jonction arrière et contact arrière

Country Status (3)

Country Link
EP (1) EP2715797A4 (fr)
KR (1) KR101396027B1 (fr)
WO (1) WO2012166749A2 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2521457A (en) * 2013-12-20 2015-06-24 Isis Innovation Charge stabilized dielectric film for electronic devices
US9318644B2 (en) 2009-05-05 2016-04-19 Solexel, Inc. Ion implantation and annealing for thin film crystalline solar cells
CN113871494A (zh) * 2020-06-30 2021-12-31 泰州隆基乐叶光伏科技有限公司 一种太阳能电池及其制作方法
CN117374169A (zh) * 2023-12-07 2024-01-09 浙江晶科能源有限公司 背接触太阳能电池的制备方法及背接触太阳能电池

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101925934B1 (ko) 2012-09-06 2018-12-06 삼성에스디아이 주식회사 배터리 팩

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8420435B2 (en) * 2009-05-05 2013-04-16 Solexel, Inc. Ion implantation fabrication process for thin-film crystalline silicon solar cells
US7857907B2 (en) * 2007-01-25 2010-12-28 Au Optronics Corporation Methods of forming silicon nanocrystals by laser annealing
US7727866B2 (en) * 2008-03-05 2010-06-01 Varian Semiconductor Equipment Associates, Inc. Use of chained implants in solar cells
EP2304803A1 (fr) * 2008-06-11 2011-04-06 Solar Implant Technologies Inc. Fabrication de cellule solaire à l aide d une implantation
US8679959B2 (en) * 2008-09-03 2014-03-25 Sionyx, Inc. High sensitivity photodetectors, imaging arrays, and high efficiency photovoltaic devices produced using ion implantation and femtosecond laser irradiation
US9150966B2 (en) * 2008-11-14 2015-10-06 Palo Alto Research Center Incorporated Solar cell metallization using inline electroless plating
MY159267A (en) * 2009-03-24 2016-12-30 Solexel Inc Method for fabricating a three-dimensional thin-film semiconductor substrate from a template
KR20100128153A (ko) * 2009-05-27 2010-12-07 (주)미래컴퍼니 레이저 식각장치 및 이를 이용한 공극 형성 방법
EP2436028B1 (fr) * 2009-05-29 2016-08-10 Solexel, Inc. Substrat semi-transparent semi-conducteur tridimensionnel de cellule solaire en couches minces, et procédés pour sa fabrication

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of EP2715797A4 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9318644B2 (en) 2009-05-05 2016-04-19 Solexel, Inc. Ion implantation and annealing for thin film crystalline solar cells
GB2521457A (en) * 2013-12-20 2015-06-24 Isis Innovation Charge stabilized dielectric film for electronic devices
CN113871494A (zh) * 2020-06-30 2021-12-31 泰州隆基乐叶光伏科技有限公司 一种太阳能电池及其制作方法
CN113871494B (zh) * 2020-06-30 2024-03-15 泰州隆基乐叶光伏科技有限公司 一种太阳能电池及其制作方法
CN117374169A (zh) * 2023-12-07 2024-01-09 浙江晶科能源有限公司 背接触太阳能电池的制备方法及背接触太阳能电池
CN117374169B (zh) * 2023-12-07 2024-03-12 浙江晶科能源有限公司 背接触太阳能电池的制备方法及背接触太阳能电池

Also Published As

Publication number Publication date
EP2715797A2 (fr) 2014-04-09
KR20140041602A (ko) 2014-04-04
EP2715797A4 (fr) 2015-05-27
WO2012166749A3 (fr) 2013-03-28
KR101396027B1 (ko) 2014-05-19

Similar Documents

Publication Publication Date Title
US9318644B2 (en) Ion implantation and annealing for thin film crystalline solar cells
US8420435B2 (en) Ion implantation fabrication process for thin-film crystalline silicon solar cells
CN102763226B (zh) 使用薄平面半导体的高效光伏背触点太阳能电池结构和制造方法
US8637340B2 (en) Patterning of silicon oxide layers using pulsed laser ablation
US9680041B2 (en) Three-dimensional thin-film semiconductor substrate with through-holes and methods of manufacturing
US9455362B2 (en) Laser irradiation aluminum doping for monocrystalline silicon substrates
KR101654548B1 (ko) 태양 전지에서 향상된 광 포획을 위한 시스템 및 방법
US20130130430A1 (en) Spatially selective laser annealing applications in high-efficiency solar cells
US20120225515A1 (en) Laser doping techniques for high-efficiency crystalline semiconductor solar cells
US20130164883A1 (en) Laser annealing applications in high-efficiency solar cells
WO2014127067A1 (fr) Photopiles à contact arrière et à jonction arrière à îlot monolithique utilisant des tranches massives
WO2012092537A2 (fr) Procédés de traitement au laser pour cellules solaires photovoltaïques
US20170005206A1 (en) Patterning of silicon oxide layers using pulsed laser ablation
KR101396027B1 (ko) 고효율 후면 접촉 후면 접합 태양 전지의 이온 주입 및 어닐링
JP2013520821A (ja) 選択的コンタクトを形成する方法
EP2819181A1 (fr) Applications de recuit laser dans des cellules solaires à haut rendement
WO2012162276A2 (fr) Applications de recuisson par laser spatialement sélectif dans des cellules photovoltaïques particulièrement efficaces
CN104205363B (zh) 制造太阳能电池的方法及其设备
WO2015100392A2 (fr) Contacts auto-alignés pour des cellules solaires à jonction arrière et contact arrière à îlot monolithique

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12793962

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20137034723

Country of ref document: KR

Kind code of ref document: A