WO2015100392A2 - Contacts auto-alignés pour des cellules solaires à jonction arrière et contact arrière à îlot monolithique - Google Patents

Contacts auto-alignés pour des cellules solaires à jonction arrière et contact arrière à îlot monolithique Download PDF

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Publication number
WO2015100392A2
WO2015100392A2 PCT/US2014/072299 US2014072299W WO2015100392A2 WO 2015100392 A2 WO2015100392 A2 WO 2015100392A2 US 2014072299 W US2014072299 W US 2014072299W WO 2015100392 A2 WO2015100392 A2 WO 2015100392A2
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Prior art keywords
solar cell
cell
isles
layer
monolithically
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PCT/US2014/072299
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English (en)
Inventor
Anand Deshpande
Pawan Kapur
Mehrdad M. Moslehi
Virendra V. Rana
Sean M. Seutter
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Solexel, Inc.
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Publication of WO2015100392A2 publication Critical patent/WO2015100392A2/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0475—PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates in general to the fields of solar photovoltaic (PV) cells and modules, and more particularly to monolithically isled or tiled photovoltaic (PV) solar cells and associated modules providing numerous benefits.
  • PV solar photovoltaic
  • Crystalline silicon photovoltaic (PV) modules as of 2012, account for approximately at least 85% of the overall global PV annual demand market and cumulative globally installed PV capacity.
  • the manufacturing process for crystalline silicon PV is based on the use of crystalline silicon solar cells, starting with mono- crystalline or multi-crystalline silicon wafers made of czochralski (CZ) silicon ingots or cast silicon bricks.
  • CZ czochralski
  • Non-crystalline-silicon-based thin film PV modules may offer the potential for low cost manufacturing process but typically provide much lower conversion efficiencies (in the range of up to about 14% in STC module efficiency) for commercial thin- film PV modules as compared to the mainstream crystalline silicon PV modules (which may provide module efficiencies in the range of approximately 14% up to about 20%, and mostly in the range of about 14% to 17%), and an unproven long-term track record of field reliability as compared to well-established crystalline silicon solar PV modules.
  • the leading-edge crystalline silicon PV modules offer superior overall energy conversion performance, long-term field reliability, non-toxicity, and life cycle sustainability compared to various other PV technologies.
  • Disruptive monocrystalline silicon technologies such as high-efficiency thin monocrystalline silicon solar cells fabricated using reusable crystalline silicon templates, thin (e.g., crystalline silicon absorber thickness from approximately 10 ⁇ up to about 100 ⁇ , and typically ⁇ 70 ⁇ ) epitaxial silicon, thin silicon support using backplane attachment / lamination, and porous silicon lift-off technology— offer the promise of high-efficiency (solar cell and/or module efficiencies of at least 20% under Standard Test Conditions or STC) and PV module manufacturing cost at well below $0.50/Wp at mass manufacturing scale.
  • STC Standard Test Conditions
  • Bowed or non-planar solar cell substrates may further result in cell microcracks and/or breakage problems during module lamination and also subsequently during the PV module operation in the field (resulting in PV module power degradation or loss). These problems may be further aggravated in larger area solar cells, such as the commonly used 156 mm x 156 mm format (square or pseudo square) solar cells.
  • conventional solar cells particularly those based on an interdigitated back- contact or IBC design, often require relatively thick metallization patterns— due to the relatively high cell electrical current— which may add complexity to cell processing, increase material costs, and add significant physical stresses to the cell semiconductor material.
  • relatively thick e.g., in the thickness range of 10's of microns for
  • crystalline silicon modules often utilize relatively expensive external bypass diodes, which must be capable of handling relatively high forward-biased electrical currents in the range of approximately several amperes up to about 10 amperes and relatively high reverse bias voltages in the range of approximately 10 volts to 20 volts, in order to eliminate hot-spot effects caused by the partial or full shading of solar cells and to prevent the resulting potential solar cell and module reliability failures.
  • Such shade-induced hot-spot phenomena which are caused by reverse biasing of the shaded cell or cells in a PV module, may permanently damage the affected PV cells as well as the PV module encapsulation material and cell-to-cell interconnections, and even cause fire hazards, if the sunlight arriving at the surface of the PV cells in a PV module is partially blocked or not sufficiently uniform within the PV module— for instance, due to full or even partial shading of one or a plurality of solar cells.
  • Bypass diodes are often placed on sub-strings of the PV module— typically one external bypass diode per substring of 20 solar cells in a standard 60-cell crystalline silicon solar module with three 20- cell sub-strings or one external bypass diode per sub-string of 24 solar cells in a 72-cell crystalline silicon solar module with three 24-cell sub-strings, while many other module formats and configurations with different numbers of embedded solar cells are possible for modules with any number of cells.
  • This connection configuration with external bypass diodes across the series-connected cell strings prevents the reverse bias hot spots due to any shaded cells and enables the PV modules to operate with a relatively high degree of reliability throughout their lifetime under various real life shading or partial shading and soiling conditions.
  • each cell in the string essentially acts as an electrical current source with relatively matched electrical current values with the other cells in the series-connected string of cells, with the external bypass diode in the sub-string being reversed biased with the total voltage of the substring in the module (for example, 20 cells in a series-connected string create
  • the majority of solar modules installed or being produced utilize multi- crystalline or mono-crystalline silicon solar cells which are front contact cells (with frontside or sunnyside fingers and busbars). Such front contact cells may suffer from optical shading losses cause by front side metallization, including metallization fingers and busbars. Back contact architectures circumvent this problem.
  • the highest efficiency back contact cells employ interdigitated back-contact (IBC), back-junction architectures which enable close proximity between the harvested carriers in the emitter and the terminals and also allow for lightly doped front surfaces which provide good blue response of the cells.
  • IBC interdigitated back-contact
  • n-type wafers used for back- contact/back-junction (IBC) solar cells typically provide much higher minority carrier lifetimes compared to p-type wafers, resulting in additional higher cell efficiency upsides.
  • back contact back junction IBC solar cells typically require very high minority carrier lifetime wafers - thus higher-lifetime n-type wafers are more suitable than p-type wafers for IBC cells. This may be to a large extent owed to the fact that the mean path that the generated minority carriers (for instance, holes in the case of n-type wafers and n-type IBC cell base) travel to be collected at the emitter junction located at the rear side of the cell is relatively large due to the distance to the rear collecting junction terminal from the cell frontside which is governed by the thickness of the wafer or semiconductor absorber layer.
  • crystalline silicon absorber thicknesses between approximately 20 and 90 ⁇ may be optimal - the actual optimal thickness value depending on the absorber material quality as measured by minority carrier lifetime or diffusion length, and may be somewhat smaller than 20 ⁇ or larger than 90 ⁇ .
  • the practical limitation to producing high-efficiency crystalline silicon cells using very thin wafers is the mechanical yield of such wafers throughout the cell manufacturing process (as well as subsequent module lamination process).
  • the mechanical yield may be decreased due to breakage of such thin wafers during cell fabrication processes and handling, such as screen printing and wet processes, as well as due to breakage from excessive film stress or excessive bow, especially as back contact cells typically require very thick high-conductivity (e.g., plated copper) backside metallization (often many tens of microns thick plated copper to carry the relatively large cell currents, at low voltage, across inter-digitated back-contact, IBC, fingers).
  • high-conductivity e.g., plated copper
  • backside metallization often many tens of microns thick plated copper to carry the relatively large cell currents, at low voltage, across inter-digitated back-contact, IBC, fingers.
  • a monolithically isled solar cell comprises a semiconductor layer having a light receiving frontside and a backside opposite the frontside and attached to an electrically insulating backplane.
  • a trench isolation pattern partitions the semiconductor layer into electrically isolated isles on the electrically insulating backplane.
  • a first metal layer having base and emitter electrodes self aligned to base and emitter regions is positioned on the
  • interconnection and connected to the first metal layer by via plugs is positioned on the backplane.
  • Fig. 1 is a top view diagram of a square-shaped single isle master cell
  • Fig. 2 is a top view diagram of a square-shaped 4x4 isled square master cell (or isled cell "icell");
  • FIGs. 3A and 3B are cross-sectional diagrams showing a backplane-attached solar cell after solar cell processing steps including isolation trench formation;
  • Fig. 4 is a representative process flow for the fabrication of backplane-attached solar cells using epitaxial silicon lift-off processing
  • Figs. 5A through 5C are manufacturing process flows for the formation of back- contact back-junction solar cells.
  • Fig. 5 A shows a process flow based on epitaxial silicon and porous silicon lift-off processing
  • Fig. 5B shows a process flow based on starting crystalline silicon wafers
  • Fig. 5C shows a process flow based on epitaxial silicon and lift-off processing
  • FIGs. 5D and 5E are cross-sectional diagrams showing a backplane-attached solar cell
  • Figs. 6A and 6B are top view diagrams of a square-shaped 3x3 and 5x5 isled square icell, respectively;
  • FIGs. 7A and 7B are top view diagrams of embodiments a triangular-shaped 8 isled square icell;
  • Figs. 7C, 7D, and 7E are top view diagrams of embodiments a triangular-shaped 16, 36, and 32 isled square icell, respectively;
  • Fig. 8 is a schematic diagram showing an equivalent circuit model of a typical solar cell with edge effects
  • Fig. 9A is a backside view diagram showing a busbarless first metallization layer pattern (Ml) formed on a square-shaped 4x4 isled icell and Fig. 9B is an expanded view of a portion of Fig. 9A;
  • Figs. 10A and 10B are backside view diagrams showing a busbarless first metallization layer pattern (Ml) formed on a square-shaped 3x3 and 5x5 isled icell, respectively;
  • Fig. 11A is a backside view diagram showing a busbarless first metallization layer pattern (Ml) formed on a triangular-shaped 36 isled icell and Fig. 11B is an expanded view of a portion of Fig. 11 A;
  • Ml busbarless first metallization layer pattern
  • Fig. 12A is a backside view diagram showing a second metallization layer pattern (M2) formed on a square-shaped 5x5 isled icell and Fig. 12B is an expanded view of a portion of Fig. 12A;
  • Fig. 13 is a backside view diagram showing a second metallization layer pattern (M2) unit cell having interdigitated tapered base and emitter fingers;
  • M2 second metallization layer pattern
  • Fig. 14A is a backside view diagram showing a second metallization layer pattern (M2) formed on a square-shaped 4x4 isled icell and Fig. 14B is an expanded view of a portion of Fig. 14A;
  • Figs. 15A and 15B are backside view diagrams showing a second metallization layer pattern (M2) formed on a square-shaped 3x3 and 5x5 isled icell, respectively;
  • FIG. 16A is a top view diagram of an isled master cell (icell), each isle having a monolithically-integrated bypass switch (MIBS);
  • MIBS monolithically-integrated bypass switch
  • Figs. 16B and 16C are cross-sectional diagrams detailing MIBS rim or full- periphery diode solar cell embodiments of the back-contact/back-junction solar cell for one isle (or unit cell such as In in Fig. 16A);
  • Fig. 17 is a schematic diagram showing an all-series electrically connected icell
  • Figs. 18A and 18B are schematic diagrams showing an icell having an all-series electrically connected and hybrid parallel-series electrically connected 4x4 array of isles (the design of Fig. 18B referred to as 2x8HPS design);
  • FIG. 18C is a schematic diagram showing an icell having a hybrid parallel-series electrically connected 8x8 array of isles (referred to as 8x8HPS design);
  • Figs. 19A, 19B, and 19C show position of a shade management switch on the icells of Figs. 18A, 18B, and 18C, respectively;
  • Fig. 20 is a top view diagram of a pseudo-square shaped master cell substrate;
  • Fig. 21 is a schematic diagram showing a pseudo square-shaped icell having a hybrid parallel-series electrical connection;
  • Fig. 22 is a schematic diagram showing a pseudo square-shaped icell having an all- series electrical connection
  • Figs. 23A and 23B are schematic diagrams showing a master cell overview and the relative position of emitter and base busbars depending on the number of isles and M2 interconnection design;
  • FIGs. 24 through 27 are schematic diagrams depicting 60-cell module connection designs
  • Figs. 28A and 28B are schematic diagrams showing module connections for 600 VDC PV systems using 60-cell PV modules comprising all-series icells as compared to hybrid parallel-series icells;
  • Figs. 29A and 29B are schematic diagrams showing module connections for 1000 VDC PV systems using 60-cell PV modules comprising all-series icells as compared to hybrid parallel-series icells;
  • Fig. 30 is a diagram of monolithically isled solar cell having a 4 x 4 array of sub- cells
  • Fig. 31 is a graph of cell thickness vs open circuit voltage
  • Fig. 32 is a graph of minority carrier lifetime vs silicon thickness
  • Fig. 33 is a process flow diagram illustrating high-level solar cell building blocks
  • Figs. 34A through 34D are process flow embodiments for the manufacture of interdigitated back contact solar cells with no FSF or BSF;
  • Figs. 35A through 35D are process flow embodiments for the manufacture of interdigitated back contact solar cells with a buried BSF;
  • Figs. 36A through 36D are process flow embodiments for the manufacture of interdigitated back contact solar cells with a buried BSF;
  • Fig. 37A illustrates cross-sectional diagrams showing a process comprising a wafer thinning step prior to wafer segmentation
  • FIG. 37B illustrates cross-sectional diagrams showing a process comprising partial wafer segmentation prior to wafer thinning and following wafer thinning and texturing;
  • Figs. 38A through 38D are process flow embodiments for the manufacture of interdigitated back contact solar cells with laser-doped FSF;
  • Figs. 39A through 39D are process flow embodiments for the manufacture of interdigitated back contact solar cells with pulsed laser FSF;
  • Figs. 40A through 40D are process flow embodiments for the manufacture of interdigitated back contact solar cells with ion implantation FSF;
  • Figs. 41A through 41D are process flow embodiments for the manufacture of interdigitated back contact solar cells with gas immersion FSF;
  • Fig. 42 is a process flow embodiment for the manufacture of interdigitated back contact solar cells with pulsed ns laser scribing of isolation trenches using PV-Al/NiV;
  • Fig. 43 is a process flow embodiment for the manufacture of interdigitated back contact solar cells using pulsed ns laser scribing of isolation trenches on pre-etch thick silicon;
  • Fig. 44A is a cross-sectional diagram showing direct oxide ablation of a BSG (or PSG) layer on a silicon layer;
  • Fig. 44B is a cross-sectional diagram showing ablation of a hardmask layer on a BSG 9or PSG) layer on a silicon layer;
  • FIGs. 45 through 49 show several representative process flow embodiments for the fabrication of a backplane-attached back contact solar cell
  • Figs. 50A through 53 are solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a triple print dopant paste process for field emitter, base, and emitter formation;
  • Figs. 54A through 56B are solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a double print dopant paste process for base and emitter formation;
  • Figs. 57A through 59 are solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a cascade process
  • Figs. 60 and 61 are solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a single cascade process and tunnel contacts;
  • Fig. 62 is a solar cell fabrication process flow embodiment for the formation of a back contact back junction solar cell utilizing a single cascade process and tunnel contacts starting with an epitaxial thin film silicon substrate formation;
  • Figs. 63A through 63D are cross-sectional diagrams of solar cells with a self aligned contact structure
  • Figs. 64A through 64E are cross-sectional diagrams of solar cells at various steps during the fabrication of a abutted junction interdigitated back contact solar cell having self aligned contacts;
  • Figs. 65A through 65G are cross-sectional diagrams of solar cells at various steps during the fabrication of a non abutted junction interdigitated back contact solar cell having self aligned contacts;
  • Figs. 66A through 66E are cross-sectional diagrams of solar cells at various steps during the fabrication of a non abutted junction interdigitated back contact solar cell having self aligned contacts.
  • backplane-attached / back-contact solar cells such as interdigitated back-contact (IBC) solar cells using monocrystalline silicon substrates and other described fabrication materials
  • IBC interdigitated back-contact
  • one skilled in the art could apply the principles discussed herein to other solar cells including but not limited to non-IBC back-contact solar cells (such as Metallization Wrap-Through or MWT back-contact solar cells, traditional front contact cells, other fabrication materials including alternative semiconductor materials (such as materials comprising one or a combination of silicon, gallium arsenide, germanium, gallium nitride, other binary and ternary semiconductors, etc.), technical areas, and/or embodiments without undue experimentation.
  • non-IBC back-contact solar cells such as Metallization Wrap-Through or MWT back-contact solar cells, traditional front contact cells
  • alternative semiconductor materials such as materials comprising one or a combination of silicon, gallium arsenide, germanium, gallium nitride, other binary and ternary semiconductors, etc.
  • isled also called tiled
  • icell an acronym for Isled Cell
  • representative manufacturing process flow descriptions are described with reference to thin epitaxial silicon back-contact/back- junction IBC solar cells formed using porous silicon lift-off processing on reusable monocrystalline templates and flexible backplanes
  • novel concepts and embodiments disclosed herein can also be applied and effectively utilized in numerous other types of solar cells (and resulting solar PV modules) including, but not limited to:
  • - Back-contact non-IBC e.g., Metallization Wrap-Through or MWT
  • solar cells formed using wire-sawn cast multi-crystalline wafers and flexible backplanes
  • - Back-contact non-IBC e.g., Metallization Wrap-Through or MWT
  • solar cells formed using wire-sawn cast multi-crystalline wafers and rigid backplanes
  • - Back-contact non-IBC e.g., Metallization Wrap-Through or MWT
  • solar cells formed using wire-sawn Czochralski (CZ) or Float-Zone (FZ) monocrystalline wafers and flexible backplanes;
  • CZ wire-sawn Czochralski
  • FZ Float-Zone
  • - Back-contact non-IBC e.g., Metallization Wrap-Through or MWT
  • solar cells formed using wire-sawn Czochralski (CZ) or Float-Zone (FZ) monocrystalline wafers and rigid backplanes;
  • CZ wire-sawn Czochralski
  • FZ Float-Zone
  • SHJ Semiconductor Heterojunction
  • CZ Czochralski
  • FZ Float-Zone
  • SHJ Semiconductor Heterojunction
  • CZ Czochralski
  • FZ Float-Zone
  • isled master cell icell, or modified main cell refers to the plurality of isles or sub-cells formed from the same original semiconductor substrate layer and the subsequent modified isled solar cell.
  • the original semiconductor layer or substrate from which the mini-cells are formed may be referred to as a master cell.
  • backplane may be used herein to describe a combination of materials on the cell backside - such as metallization layers and electrically insulating layer attached to the solar cell backside - providing mechanical and structural support to a master cell (and its plurality of isles or mini-cells), and to enable an advanced solar cell interconnection design.
  • the term backplane may be used to describe a material layer, such as an electrically insulating flexible prepreg layer, formed and positioned on the backside of the solar cell, hence, enabling a solar cell metallization structure comprising at least two metallization layers on the cell backside.
  • the backplane layer may be made of either a rigid or flexible thin sheet of material (for instance, with backplane sheet thickness in the range of up to about 250 microns).
  • the backplane layer may be made of an electrically insulating material (either a flexible or a rigid material).
  • the backplane layer may be either electrically or electrically conducting.
  • the term backplane refers to the continuous thin sheet of support material, including but not limited to a thin sheet of prepreg material, which can be either flexible or rigid.
  • the use of flexible backplane sheet in conjunction in accordance with the disclosed subject matter also enables packaging the solar cells in flexible, lightweight PV modules (not requiring much heavier glass cover sheets for frontside or for both frontside and backside).
  • the present application provides various structures and methods for monolithic isled solar cells and modules.
  • monolithic integrated circuit is used to describe a plurality of semiconductor devices and corresponding electrical interconnections that are fabricated onto a slice of semiconductor material layer, also known as the semiconductor substrate.
  • a monolithic integrated circuit is typically manufactured on a thin continuous slice or layer of a semiconductor material such as crystalline silicon.
  • the monolithic icell structures described herein are monolithic semiconductor integrated circuits as the integrated sub-cells are all formed or manufactured on a slice of semiconductor substrate layer (from either a starting semiconductor wafer or a grown semiconductor layer formed by a vapor-phase or liquid-phase growth method such as epitaxial deposition). Further, the combination of a continuous backplane attached to the semiconductor substrate layer backside enables monolithic integrated icell embodiments in accordance with the disclosed subject matter.
  • Physically or regionally isolated isles i.e., the initial semiconductor substrate partitioned into a plurality of substrate isles supported on a shared continuous backplane
  • the resulting isles are monolithic - attached to and supported by a continuous backplane (for example a flexible backplane such as an electrically insulating prepreg layer).
  • the completed solar cell comprises a plurality of monolithically integrated isles or mini-cells, in some instances attached to a flexible backplane (e.g., one made of a prepreg materials, for example having a relatively good Coefficient of Thermal Expansion or CTE match to that of the semiconductor substrate material), providing increased solar cell flexibility and pliability while suppressing or even eliminating micro-crack generation and crack propagation or breakage in the semiconductor substrate layer.
  • a flexible backplane e.g., one made of a prepreg materials, for example having a relatively good Coefficient of Thermal Expansion or CTE match to that of the semiconductor substrate material
  • a flexible monolithically isled (or monolithically integrated group of isles) cell also called an icell
  • a flexible monolithically isled (or monolithically integrated group of isles) cell provides improved cell planarity and relatively small or negligible cell bow throughout solar cell processing steps such as any optional semiconductor layer thinning etch, texture etch, post-texture clean, PECVD passivation and anti-reflection coating (ARC) processes (and in some processing embodiments also allows for sunny-side-up PECVD processing of the substrates due to mitigation or elimination of thermally-induced cell warpage), and final solar cell metallization.
  • ARC anti-reflection coating
  • the structures and methods disclosed herein also enable flexible, lightweight PV modules formed from the monolithic isled master cells (i.e., icells) which substantially decrease or eliminate solar cell micro-cracking during module lamination and also during PV module operation in the field.
  • These flexible, lightweight PV modules may be used in a variety of markets and applications including, but not limited to, the residential rooftop (including residential Building-Integrated Photovoltaics or BIPV rooftop shingles / tiles), commercial rooftop, ground mount utility-scale power plants, portable and transportable PV power generation, automotive (such as solar PV sunroof), and other specialty applications.
  • An isled solar cell enables scaling of the solar cell voltage and current, specifically scaling up the solar cell voltage (in other words increasing the master cell output voltage) and scaling down the solar cell current (in other words decreasing the master cell output current) based on the number (e.g., N x N array) of cell isles/tiles (or sub-cells) which, among numerous other advantages including reduced metallization sheet conductance or thickness requirements (hence, reduced metallization material and process cost), lowers the maximum electrical current rating requirement for associated embedded power electronics components such as the embedded shade management diodes (e.g., lower current rating Schottky or pn junction diodes), or the embedded Maximum-Power-Point Tracking (MPPT) power optimizers (such as embedded MPPT DC-to-DC micro- converters or MPPT DC-to-AC micro-inverters).
  • MPPT Maximum-Power-Point Tracking
  • a lower-rated current for example, about 1 to 2 A
  • Schottky barrier diode typically costs much less, can have a much smaller package, and dissipates much less power than a 10 A to 20 A Schottky barrier diode.
  • the embodiments disclosed herein can reduce the resulting solar cell current while increasing the solar cell voltage for the same solar cell power in order to enable the use of lower cost, smaller, and less power-dissipating bypass diode.
  • a crystalline silicon master cell or icell with a maximum- power-point voltage of Vmp ⁇ 0.60V and maximum-power-point current of Imp ⁇ 9.3 A (with the solar cell producing a maximum-power-point power of P mp - 5.6 W).
  • Maximum-Power-Point Tracking (MPPT) power optimizer DC-to-DC or DC-to-AC chips with superior performance such as dynamic range response may be embedded within the module laminate and/or integrated directly on the backsides of the solar cells (for instance, on the backplanes of the backplane- attached icells disclosed herein) due to the higher voltage and lower current master cell (icell) made of a plurality of isles or mini-cells.
  • the icell may use an inexpensive single-chip MPPT power optimizer (DC-to-DC micro-converter or DC-to-AC micro-inverter).
  • MIBS monolithically integrated bypass switch
  • a thinner solar cell metallization structure has a number of benefits relating to solar cell processing and may provide significant manufacturing cost reduction (for instance, much less metallization material required per cell) as well as reducing thermal and mechanical stresses relating to relatively thick (e.g., lO's of microns for interdigitated back-contact or solar cells) metallization structures and the CTE mismatch between conductive metal and semiconductor material.
  • the metallization materials such as copper or aluminum have much higher CTE compared to the semiconductor materials.
  • linear CTEs of aluminum, copper, and silver are about 23.1 ppm/°C, 17 ppm/°C, and 18 ppm/°C, respectively.
  • the linear CTE of silicon is around 3 ppm/°C. Therefore, there is a relatively large CTE mismatch between these high- conductivity metallization materials and silicon. These relatively large CTE mismatches between the metallization materials and silicon can cause serious cell manufacturing yield and PV module reliability problems, particularly when using relatively thick metallization structures for solar cells (such as thick plated copper used in the IBC solar cells).
  • the second level metal (M2) for example comprising aluminum or copper
  • M2 can be made much thinner due to the current and voltage scaling of the icell architecture, and thus deposited without wet plating and using a process which is substantially less mechanically stressful on the cell and chemically intrusive to the cell (for example a dry processing method such as physical-vapor deposition - PVD such as metal evaporation and/or plasma sputtering - or metal paste screen printing or metal ink printing by inkjet printing, etc.).
  • the cost of material forming the backplane is reduced as the icell architecture using a plurality of flexible isles reduces/relaxes the CTE requirements of the prepreg (for instance, by relaxing the relative CTE matching requirement between the backplane layer and semiconductor substrate).
  • Relative CTE matching requirements between the backplane sheet and the semiconductor substrate are reduced as there is less continuous cell area attached to the backplane (because of the trench isolation regions partitioning the semiconductor substrate into a plurality of isles or sub-cells on the continuous backplane sheet) - the continuous mini-cell area attached to the continuous backplane is defined by the isle area or region surrounded by trench isolation.
  • Trench separated and electrically partitioned substrate regions for isles provide relative flexibility, further mitigate cell bow, and maintain relative planarity across the master cell (entire icell area) during cell processing (and in some instances also allowing for cell passivation processing such as sunnyside-up cell PECVD deposition) and reduce long term material stresses after cell fabrication, module lamination, and during the operation of the PV modules in the field under varying weather conditions.
  • Important applications of the disclosed innovations include but are not limited to: flexible solar cells and flexible, lightweight PV modules for the residential rooftop, Building-Integrated Photo Voltaics (BIPV) in residential and commercial buildings, commercial rooftop, ground-mount utility-scale power plants, automotive applications, portable electronics, portable and transportable power generation, and other specialty applications.
  • BIPV Building-Integrated Photo Voltaics
  • the embodiments disclosed herein include both rigid or flexible solar cells which may be packaged or laminated into rigid glass-covered solar PV modules for a wide range of applications, including the above-mentioned residential rooftop, commercial rooftop, BIPV, ground-mount utility, automotive, portable and transportable power generation, and other specialty applications.
  • Fig. 1 is a representative schematic diagram of a square-shaped single isle for cell pattern - prior art standard solar cell geometry without plurality of isles to create an icell. Although shown as a full-square-shaped cell here, the solar cell may be shaped as pseudo square, rectangular, other polygonal shapes, or any other geometrical shape of interest.
  • Fig. 1 is a schematic diagram showing a top or plan view of a single-isle I (or non-isled or non-tiled) standard square-shaped solar cell 10 defined by cell peripheral boundary or edge regions 12 and having a side length L.
  • crystalline silicon solar cells are often rectangular/square shaped (mostly either full square or pseudo square shaped wafers) with cell square area on the order of X by X (with X typically being in the range of about 100 mm up to 210 mm or even larger values), for example, 125 mm x 125 mm or 156 mm x 156 mm or 210 mm x 210 mm solar cells.
  • X typically being in the range of about 100 mm up to 210 mm or even larger values
  • master cell master cell is defined as a single solar cell made from an original continuous semiconductor substrate
  • master cells may come in various shapes (for example pseudo-square) and have various geometrical dimensions.
  • Cell peripheral boundary or edge region 12 has a total length of 4L, thus solar cell 10 has a total peripheral dimension of 4L.
  • a solar cell semiconductor e.g., silicon substrate layer
  • W absorber thickness
  • a solar cell structure should have a relatively small edge area as compared to active cell area (also called edge to cell ratio) - for instance, less than about 5%, and in some instances less than about 1% - in order to minimize the edge-related solar cell recombination losses which may result in reduced open-circuit voltage and/or reduced short-circuit current, and hence, reduced solar cell conversion efficiency.
  • the edge-induced losses can be substantially mitigated by proper passivation of the solar cell edge regions and through isolation / separation of the emitter junction region from the edge region (hence, providing allowance for larger edge area fraction without loss of solar cell efficiency).
  • FIG. 2 is a schematic diagram of a top or plan view of a 4 x 4 uniform isled (tiled) master solar cell or icell 20 defined by cell peripheral boundary or edge region 22, having a side length L, and comprising sixteen (16) uniform square-shaped isles formed from the same original continuous substrate and identified as In through I 44 attached to a continuous backplane on the master cell backside (backplane and solar cell backside not shown).
  • Each isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and in some instances less than or equal to about 100 ⁇ - for instance, in the range of a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 24.
  • Main cell (or icell) peripheral boundary or edge region 22 has a total peripheral length of 4L; however, the total icell edge boundary length comprising the peripheral dimensions of all the isles comprises cell peripheral boundary 22 (also referred to as cell outer periphery) and trench isolation borders 24.
  • the total icell edge length is N x cell outer periphery.
  • N 4
  • square isle side dimensions are approximately 39 mm x 39 mm and each isle or sub-cell has an area of 15.21 cm 2 per isle.
  • Figs. 3A and 3B are representative schematic cross-sectional view diagrams of a backplane-attached solar cell during different stages of solar cell processing.
  • Fig. 3A shows the simplified cross-sectional view of the backplane-attached solar cell after processing steps and before formation of the partitioning trench regions.
  • Fig. 3B shows the simplified cross-sectional view of the backplane-attached solar cell after some processing steps and after formation of the partitioning trench regions to define the trench-partitioned isles.
  • Fig. 3B shows the schematic cross-sectional view of the icell of Fig. 2 along the view axis A of Fig.
  • Figs. 3A and 3B are schematic cross-sectional diagrams of a monolithic master cell semiconductor substrate on a backplane before formation of trench isolation or partitioning regions, and a monolithic isled or tiled solar cell on a backplane formed from a master cell after formation of trench isolation or partitioning regions, respectively.
  • Fig. 3A comprises semiconductor substrate 30 having width (semiconductor layer thickness) W and attached to backplane 32 (e.g., an electrically insulating continuous backplane layer, for instance, a thin flexible sheet of prepreg) similar to that shown in Fig. 1.
  • backplane 32 e.g., an electrically insulating continuous backplane layer, for instance, a thin flexible sheet of prepreg
  • FIG. 3B is a cross-sectional diagram of an isled solar cell (icell) - shown as a cross-sectional diagram along the A axis of the cell of Fig. 2. Shown, Fig. 3B comprises isles or mini- cells In, I21, 131, and I41 each having a trench-partitioned semiconductor layer width (thickness) W and attached to backplane 32.
  • the semiconductor substrate regions of the mini-cells are physically and electrically isolated by an internal peripheral partitioning boundary, trench partitioning borders 24.
  • the semiconductor regions of isles or mini- cells In, I21, 131, and I41 are monolithically formed from the same continuous
  • the icell of Fig. 3B may be formed from the semiconductor / backplane structure of Fig. 3 A by forming internal peripheral partitioning boundaries in the desired mini-cell shapes (e.g., square shaped mini-cells or isles) by trenching through the semiconductor layer to the attached backplane (with the trench-partitioned isles or mini-cells being supported by the continuous backplane). Trench partitioning of the semiconductor substrate to form the isles does not partition the continuous backplane sheet, hence the resulting isles remain supported by and attached to the continuous backplane layer or sheet.
  • the desired mini-cell shapes e.g., square shaped mini-cells or isles
  • Trench partitioning formation process through the initially continuous semiconductor substrate thickness may be performed by, for example, pulsed laser ablation or dicing, mechanical saw dicing, ultrasonic dicing, plasma dicing, water jet dicing, or another suitable process (dicing, cutting, scribing, and trenching may be used interchangeably to refer to the process of trench isolation process to form the plurality of isles or mini-cells or tiles on the continuous backplane).
  • the backplane structure may comprise a combination of a backplane support sheet in conjunction with a patterned metallization structure, with the backplane support sheet providing mechanical support to the semiconductor layer and structural integrity for the resulting icell (either a flexible solar cell using a flexible backplane sheet or a rigid solar cell using a rigid backplane sheet or a semi-flexible solar cell using a semi-flexible backplane sheet).
  • backplane to the combination of the continuous backplane support sheet and patterned metallization structure
  • backplane support sheet for instance, an electrically insulating thin sheet of prepreg
  • PV photovoltaics
  • the monolithic isled solar cell (or icell) innovations disclosed herein are extendible and applicable to various other solar cell architectures such as Metallization Wrap- Through (MWT) back-contact solar cells, Semiconductor HeteroJunction (SHJ) solar cells, front-contact/back-junction solar cells, front-contact/front-junction solar cells, Passivated Emitter and Rear Contact (PERC) solar cells, as well as other front- contact/front-junction solar cells, with all of the above-mentioned cell designs using crystalline silicon (for instance, either mono-crystalline silicon or multi-crystalline silicon with final cell silicon layer thickness in the range of a few microns up to about 200 microns), or another crystalline (mono-crystalline or multi-crystalline) semiconductor absorber material (including but not limited to germanium, gallium arsenide, gallium nitride, or other semiconductor materials
  • a key advantage of the disclosed monolithically isled solar cells or icells is that they may be monolithically fabricated during cell processing and easily integrated into existing solar cell fabrication process flows.
  • the isled master cell embodiments disclosed herein may be used in conjunction with numerous backplane-attached solar cell designs, processing methods, and semiconductor substrate materials, including the backplane-attached, back-contact solar cells fabricated using epitaxial silicon lift-off process flow shown in Fig. 4.
  • FIG. 4 shows the schematic diagram of a general back- contact solar cell manufacturing process flow highlighting key processing steps of one such cell fabrication process - a crystalline-silicon solar cell manufacturing process using relatively thin (in the thickness range of a few microns up to about 100 microns) epitaxial silicon lift-off processing which substantially reduces silicon material usage and eliminates several process steps in the traditional crystalline silicon solar cell
  • Fig. 4 shows the fabrication of backplane-attached crystalline silicon solar cells having backplanes attached to the backsides of the solar cells (for instance, prepreg backplane sheets laminated to the backsides of the solar cells) for solar cells and modules with optional allowances for smart cell and smart module design (i.e., allowing for embedded distributed electronics components for enhanced power harvest from the solar cells and modules), formed using a reusable crystalline (either mono-crystalline or multi- crystalline) silicon template and epitaxial silicon deposition on a seed and release layer of porous silicon, which may utilize and integrate the monolithically isled cell (icell) structures and methods disclosed herein.
  • backplane-attached crystalline silicon solar cells having backplanes attached to the backsides of the solar cells (for instance, prepreg backplane sheets laminated to the backsides of the solar cells) for solar cells and modules with optional allowances for smart cell and smart module design (i.e., allowing for embedded distributed electronics components for enhanced power harvest from the solar cells and modules),
  • the solar cell process flow of Fig. 4 may be used to form monolithic isled solar cells or icells.
  • the process shown in Fig. 4 starts with a reusable (to be reused at least a few times, in some instances between about 10 up to about 100 times) crystalline silicon template, for example a p-type monocrystalline or multi-crystalline silicon wafer, onto which a thin (a fraction of micron up to several microns) sacrificial layer of porous silicon with controlled porosity is formed (for example by an electrochemical etch process for template surface modification in an HF/IPA or HF/acetic acid wet chemistry in the presence of an electrical current).
  • the porous silicon layer may have at least two layers with a lower porosity surface layer and a higher porosity buried layer.
  • the starting material or reusable crystalline silicon template may be a single crystalline (also known as mono-crystalline) silicon wafer, for example formed using crystal growth methods such as float zone (FZ), czochralski (CZ), magnetic stabilized CZ (MCZ), and may further optionally comprise epitaxial layers grown over such silicon wafers.
  • the starting material or reusable crystalline silicon template may be a multi-crystalline silicon wafer, for example formed using either casting or ribbon, and may further optionally comprise epitaxial layers grown over such silicon wafers.
  • the template semiconductor doping type may be either p or n (often relatively heavy p-type doping to facilitate porous silicon formation), and the wafer shape, while most commonly square shaped, may be any geometric or non-geometric shape such as quasi-square (pseudo square), hexagonal, round, etc.
  • a thin layer for example a layer thickness in the range of a few microns up to about 100 microns, and in some instances an epitaxial silicon thickness less than approximately 50 microns
  • in- situ-doped for instance, doped with phosphorus to form a n-type epitaxial silicon layer
  • crystalline either mono-crystalline or multi-crystalline
  • the in-situ-doped crystalline (either mono-crystalline layer on mono- crystalline template or multi-crystalline layer on multi-crystalline template) silicon layer may be formed, for example, by atmospheric-pressure epitaxy using a chemical-vapor deposition or CVD process in ambient comprising a silicon gas such as trichlorosilane or TCS and hydrogen (and the desired dopant gas such as PH3 for n-type phosphorus doping).
  • a silicon gas such as trichlorosilane or TCS and hydrogen
  • the desired dopant gas such as PH3 for n-type phosphorus doping
  • a rather inexpensive backplane layer may attached to the thin epi layer for permanent cell support and reinforcement as well as to support formation of the high-conductivity cell metallization structure of the solar cell (for instance, using a two-layer metallization structure using a patterned first layer of metallization or Ml on the solar cell backside prior to the backplane attachment and a patterned second layer of metallization or M2 on the backside of the backplane-attached solar cell after the backplane attachment and after the lift-off release of the backplane- attached solar cell from the reusable template) .
  • the continuous backplane material may be made of a thin (for instance, with a thickness in the range of about 50 microns to about 250 microns thick), flexible, and electrically insulating polymeric material sheet such as an inexpensive prepreg material commonly used in printed circuit boards which meets cell process integration and reliability requirements.
  • the partially-processed back- contact, back-junction (IBC) backplane-attached solar cell (for instance, with a solar cell area of about 100 mm x 100 mm, 125 mm x 125 mm, 156 mm x 156 mm, 210 mm x 210 mm or larger, or solar cell area in the range of about 100 cm 2 to 100's of cm 2 and even larger) is then separated and lifted off (released) from the reusable template along the mechanically-weakened sacrificial porous silicon layer (for example through a
  • the template may be conditioned (e.g., cleaned) and re-used multiple times (for instance, between about 10 and 100 times) to reduce the overall solar cell manufacturing cost.
  • the remaining post-lift-off solar cell processing may then be performed on the backplane-attached solar cell, for example first on the solar cell sunny-side (or frontside) which is exposed after being lifted off and released from the template.
  • Solar cell frontside or sunny-side processing may include, for instance, completing frontside texturization (for instance, using an alkaline or acitic texturing), post-texture surface preparation (cleaning), and formation of the frontside passivation and an anti-reflection coating (ARC) using a deposition process.
  • the frontside passivation and ARC layer may be deposited using a Plasma-Enhanced
  • PECVD Chemical-Vapor Deposition
  • the monolithically isled cell (icell) structures and methods disclosed herein may be integrated into device fabrication, such as the exemplary disclosed solar cell fabrication process flow, without substantially altering or adding manufacturing process steps or tools and thus without substantially adding to the cost of manufacturing the solar cell and without substantially altering the main solar cell manufacturing process flow.
  • the monolithically isled cell (icell) structures and methods disclosed herein can reduce the cost of manufacturing the solar cell, for instance, by reducing the metallization cost (using less metallization material and lower cost metallization process) and/or by improving the solar cell and module manufacturing yield (due to substantial mitigation of solar cell micro-cracks or breakage).
  • scribing also known as trenching or cutting or dicing
  • scribing of the master cell semiconductor substrate to form the internal isle partitioning trench boundaries and creating the plurality of trench-partitioned isles or mini-cells or sub-cells or tiles
  • a suitable method such as pulsed laser ablation (for instance, pulsed nanoseconds laser scribing) or a mechanical scribing method or a plasma scribing method, through the master cell silicon substrate layer thickness (for example, the epitaxial silicon layer thickness may be in the range of about a few microns up to about 100 ⁇ ).
  • Pulsed laser ablation scribing may be performed such that scribing through the thickness of the semiconductor substrate layer forms relatively narrow (e.g., width of less than 100 microns) trench isolation borders all the way through the entire thickness of the thin silicon layer and essentially stops at/on the backplane (removal and scribing of the continuous backplane material layer being rather small or negligible) - thus monolithically producing fully partitioned monolithic isles (or sub-cells or mini-cells or tiles) supported on a continuous backplane layer.
  • relatively narrow e.g., width of less than 100 microns
  • pulsed laser scribing or dicing, or trenching
  • pulsed nanoseconds laser ablation using a suitable laser wavelength such as UV, green, IR, etc.
  • ultrasonic scribing or dicing mechanical trench formation such as by using a mechanical saw or blade
  • patterned chemical etching both wet and plasma etching
  • screen printing of an etch paste following by etching activation and rinsing of the etch paste residue or any combination of known or the above mentioned trench formation methods.
  • Pulsed laser ablation processing for trench formation may provide several advantages allowing for the direct patterning of the isle or mini-cell boundaries with relatively high process throughput, enabling formation of relatively narrow trenches (e.g., less than about 100 microns trench width), and without any process consumable (hence, very low process cost).
  • relatively narrow trenches e.g., less than about 100 microns trench width
  • process consumable e.g., very low process cost
  • special care should be taken to reduce or minimize the trench width - for example, it may be desired to make the partitioning trench width less than about 100 microns, in order to make the solar cell area loss due to the icell partitioning trenches a relatively small to negligible fraction of the total icell area (for instance less than about 1% of the total icell area).
  • Pulsed nanoseconds laser ablation processing is capable of high- throughput formation of trenches with trench width well below 100 microns (e.g., about 10 to 60 microns).
  • the monolithic isled (tiled) solar cell fabrication methods and structures described herein are applicable to various semiconductor (for example including but not limited to crystalline silicon, such as thin epitaxial silicon or thin crystalline silicon wafer) solar cells (for example, front contact or back contact solar cells of various designs with cell semiconductor absorber having a thickness in the range of about a few microns up to about 200 microns), including those formed using epitaxial silicon lift-off processing (as described earlier) or those formed using crystalline silicon wafers, such as mono- crystalline (CZ or MCZ or FZ) wafers or multi-crystalline wafers (cast or ribbon-grown wafers).
  • semiconductor for example including but not limited to crystalline silicon, such as thin epitaxial silicon or thin crystalline silicon wafer
  • solar cells for example, front contact or back contact solar cells of various designs with cell semiconductor absorber having a thickness in the range of about a few microns up to about 200 microns
  • epitaxial silicon lift-off processing as described earlier
  • crystalline silicon wafers
  • the master cell isles also called tiles, pavers, sub-cells, or mini-cells
  • the master cell isles may be formed (for example, using pulsed nanoseconds laser scribing of crystalline silicon substrate) as an array of N x N square-shaped isles, N x M rectangular-shaped isles, K triangular-shaped isles, or any geometrically shaped isles or combination thereof on the shared master cell (icell) continuous backplane.
  • the isle partitioning trench formation process may occur immediately after the lift-off release of the partially-processed backplane-attached master cell and before the remaining processing steps such as frontside surface texturing and post-texture surface cleaning, or immediately after frontside texturing and post-texture surface cleaning and before the process(es) to form the front-surface passivation and anti-reflection coating (ARC) layer(s).
  • ARC anti-reflection coating
  • Performing the process to form the partitioning or isolation trenches (i.e., trenching process) by pulsed laser scribing or another suitable method (such as one of the other methods described earlier including but not limited to mechanical dicing) before the wet etch texture process (to form the solar cell frontside texture for reduced optical reflection losses) has an added advantage of removing any trenching-process- induced silicon edge damage through wet etching and removal of damaged silicon during the wet texture etch process (which also etches several microns of silicon, including any damaged silicon in the partitioning trench sidewalls, during the texture etch process).
  • the monolithically isled master cells icells
  • the formation of trench-partitioned mini-cells or isles within each icell may be integrated fairly easily and seamlessly in solar cell fabrication methods.
  • the monolithic isled solar cell (icell) fabrication process may improve the solar cell fabrication process flow through a reduction of solar cell manufacturing cost, for example, by reducing the cost of solar cell metallization, such as, for instance, by eliminating the need for a copper plating process and associated manufacturing equipment and facilities requirements for copper plating.
  • Fig. 5 A is a representative backplane-attached icell manufacturing process flow based on epitaxial silicon and porous silicon lift-off processing. This process flow is for fabrication of backplane-attached, back-contact / back-junction solar cells (icells) using two patterned layers of solar cell metallization (Ml and M2).
  • This example is shown for a solar cell with selective emitter, i.e., a main patterned field emitter with lighter emitter doping formed using a lighter boron-doped silicate glass (first BSG layer with smaller boron doping deposited by Tool 3), and more heavily-boron-doped emitter contact regions using a more heavily boron-doped silicate glass (second BSG layer with larger boron doping deposited by Tool 5).
  • first BSG layer with smaller boron doping deposited by Tool 3 lighter boron-doped silicate glass
  • second BSG layer with larger boron doping deposited by Tool 5 more heavily-boron-doped silicate glass
  • the icell designs are applicable to a wide range of other solar cell structures and process flows, including but not limited to the IBC solar cells without selective emitter (i.e., same emitter boron doping in the field emitter and emitter contact regions).
  • This example is shown for an IBC icell with an n-type base and p-type emitter. However, the polarities can be changed so that the solar cell has p- type base and n-type emitter instead.
  • Fig. 5 A is a representative manufacturing process flow embodiment for the fabrication of back-contact back-junction crystalline monolithic isled silicon solar cells (icells). Specifically, Fig. 5 A provides for the formation of an epitaxial (epi) solar cell, optionally with a monolithically integrated bypass switch (MIBS) pn junction diode, and having a double borosilicate glass (BSG) selective emitter. As shown in this flow, mini- cell trench isolation regions are formed at Tool 13, after cell release border scribe and cell lift-off release and before texturization of the exposed released side (also known as frontside or sunnyside of the resulting icell).
  • MIBS monolithically integrated bypass switch
  • BSG double borosilicate glass
  • the mini-cell trench isolation regions may be formed after texture and post texture clean in Tool 14, and before frontside passivation (shown as PECVD).
  • PECVD frontside passivation
  • Performing the pulsed laser scribing before wet etch texture may have an added advantage of removing any laser-induced scribed silicon edge damage through wet etching and removal of damaged silicon.
  • a representative process flow for forming a monolithic isled (tiled) back- contact/back-junction (IBC) solar cell using epitaxial silicon lift-off processing may comprise the following fabrication steps: 1) start with reusable crystalline (mono- crystalline or multi-crystalline) silicon template; 2) form porous silicon on template (for example, bilayer porous silicon with a lower porosity surface layer and a higher porosity buried layer using anodic etch in HF/IPA or HF/acetic acid); 3) deposit epitaxial silicon with in-situ doping (for instance, n-type phosphorus doped epitaxial silicon); 4) perform back-contact/back-junction cell processing while the epitaxial silicon substrate resides on its template, including formation of patterned field emitter junction, backside passivation, doped base and emitter contact regions for subsequent metallized solar cell ohmic contacts, and formation of a first metallization layer (also known as Ml) - see Fig.
  • a first metallization layer also known as
  • a back-contact/back-junction (IBC) solar cell fabrication process flow comprising a selective emitter process (with more lightly doped field emitter and more heavily doped emitter contact regions) using double-BSG (BSG is boron-doped silicate glass or boron doped silicon oxide layer formed, for instance, by an atmospheric-pressure chemical-vapor deposition or APCVD process) process flow for selective emitter formation (other methods of selective emitter formation may be used instead of double BSG process, for instance, using screen printed dopant pastes); 5) attach or laminate backplane layer or sheet on back-contact cell backside; 6) laser scribe release border (lift off release boundary) around the backplane boundary at least partially into epitaxial silicon layer thickness and then release by a lift-off process (e.g., mechanical release liftoff to separate the backplane-attached epitaxial silicon substrate from the reusable template by breaking off the mechanically weakened higher porosity porous silicon layer); 7) perform the trenching (also called s
  • ALD Atomic Layer Deposition
  • passivation layer deposition such as a thin sub-30 nm layer of aluminum oxide, amorphous silicon, or amorphous silicon oxide directly on the cleaned, textured silicon surface and underneath the silicon nitride ARC layer - if using a multi-layer frontside passivation / ARC structure, such as a two-layer structure of one of the above- mentioned passivation layers covered by the silicon nitride ARC layer, the entire stack may also be deposited using PECVD using a vacuum-integrated process).
  • ALD Atomic Layer Deposition
  • the frontside passivation and ARC layer deposition will not only cover the frontside surfaces of the mini-cells or isles, it will also cover the sidewalls of the trench-partitioned isles or mini- cells, hence, substantially improving the passivation and ARC properties of the icell by improving the passivation and light capturing properties of the trench sidewalls as well as the top surfaces of the isles.
  • the remaining solar cell fabrication process step involves completion of the second metallization layer (M2) on the backplane- attached solar cell backside.
  • a plurality of via holes are drilled according to a pre-designed via hole pattern, for instance using laser drilling, into the thin (e.g., 25 microns up to 250 microns backplane thickness), electrically insulating, continuous backplane layer (e.g., a 25 micron to 100 micron thick laminated prepreg sheet).
  • the number of via holes on a solar cell (e.g., 156 mm x 156 mm icell) backplane may be on the order of 100' s to 1000's.
  • the via holes may have average diagonal hole dimension (e.g., average diameter of each via hole) in the range of 10's of microns to 100's of microns (for instance, about 100 microns to 300 microns).
  • the laser-drilled via holes through the electrically insulating backplane layer are positioned to land on the interdigitated base and emitter metallization fingers (formed by the first level of patterned metallization by screen printing of a metallic paste or by physical-vapor deposition and patterning of a metal layer such as a metal comprising aluminum or aluminum-silicon alloy).
  • via holes will serve as the interconnection channels or plugs between the first layer of patterned metallization or Ml formed directly on the solar cell backside prior to the backplane attachment / lamination and the second layer of patterned metal or M2 to be formed immediately after formation of the laser-drilled via holes.
  • the second level of patterned metallization M2 may be formed by one of several methods, including but not limited to one or a combination of: (1) Physical-Vapor Deposition or PVD (thermal evaporation and/or electron-beam evaporation and/or plasma sputtering) of an inexpensive high-conductivity metal comprising, for instance, aluminum and/or copper (other metals may also be used) followed by pulsed laser ablation patterning, (2) Physical-Vapor Deposition or PVD (thermal evaporation and/or electron-beam evaporation and/or plasma sputtering) of an inexpensive high-conductivity metal comprising, for instance, aluminum and/or copper (other metals may also be used) followed by metal etch patterning (e.g.
  • etch paste screen printing of an etch paste or screen printing of a resist followed by a metal wet etch process and subsequent removal of the resist
  • Screen printing or stencil printing of a suitable metal paste such as a paste comprising copper and/or aluminum
  • Inkjet printing or aerosol printing of a suitable metal paste such as a paste comprising copper and/or aluminum
  • Patterned plating of a suitable metal for instance, copper plating.
  • the patterned second layer of metallization may also comprise a thin capping layer (for instance, a thin ⁇ 1 micron capping layer of NiV or Ni formed by plasma sputtering or screen printing or plating) to protect the main patterned M2 (e.g., aluminum and/or copper containing high conductivity metal) and to provide a suitable surface for soldering or conductive adhesive as needed.
  • a thin capping layer for instance, a thin ⁇ 1 micron capping layer of NiV or Ni formed by plasma sputtering or screen printing or plating
  • the back-contact / back-junction (IBC) solar cells described herein may utilize two layers of patterned metallization (Ml and M2), with the first patterned metallization layer Ml forming the interdigitated base and emitter metallization fingers on each mini-cell or isle according to a fine-pitch pattern (for instance, base-emitter Ml finger pitch in the range of about 200 microns to 2 mm, and in some cases in the range of about 500 microns to about 1 mm), and the second patterned layer of metallization M2 forming the final icell metallization and interconnecting the isles or mini-cells according to a pre-specified current and voltage scaling factor.
  • a fine-pitch pattern for instance, base-emitter Ml finger pitch in the range of about 200 microns to 2 mm, and in some cases in the range of about 500 microns to about 1 mm
  • M2 patterned layer of metallization
  • Patterned M2 may be patterned substantially orthogonal or perpendicular to patterned Ml and have a much larger finger-to-finger pitch than patterned Ml fingers. This will substantially facilitate fabrication of patterned M2 according to a low-cost, high-yield manufacturing process. Patterned M2 not only formed the final icell patterned metallization, it also forms the electrically conductive via plugs through the laser-drilled via holes in order to complete the M2-to-Ml interconnections based on desired icell metallization structure.
  • FIG. 5A for epitaxial silicon lift off icell representative embodiment shows the process flow for fabricating monolithic icells with each icell being attached to its own separate pre-cut continuous backplane layer, and each individual backplane attached icell being processed through the entire backend process flow after its backplane lamination.
  • the icells processed using this approach will then be tested and sorted at the end of the process and can be assembled into the PV modules by interconnections of the icells to one another, for instance in electrical series, using tabbing and/or stringing of the cells (also involving soldering and/or conductive adhesives to interconnect the plurality of solar cells to one another as part of PV module assembly), and then completion of the module lamination and final module assembly and testing.
  • an alternative embodiment of an icell implementation resulting in a novel monolithic module structure involves attachment or lamination of a plurality of relatively closely-spaced icells (for instance, with the adjacent icell to icell spacing in the range of 50 microns up to about 2 mm, and often in the range of about 100 microns to 1 mm) on their backsides to a larger continuous backplane sheet at the Backplane Lamination (or attachment step) performed by Tool 12.
  • the remaining process steps after Tool 12 are performed concurrently on the plurality of icells sharing a common continuous backplane layer on their backsides (instead of being performed on the individual separate icells, each with their own separate backplane).
  • the monolithic patterned M2 After completion of the final metallization (patterned second layer of metal M2), the monolithic patterned M2 not only completes the metallization pattern for each icell among the plurality of the icells sharing the larger continuous backplane layer, it also completes electrical interconnections of the plurality of icells to one another according to any desired arrangement, for instance, interconnecting the icells to one another all in series or in a hybrid parallel / series arrangement.
  • This embodiment enables fabrication of icells and the monolithic electrical interconnections among a plurality of icells on a shared continuous backplane layer, hence eliminating the need for subsequent soldering / tabbing / stringing of the icells to one another during the final module assembly.
  • a properly sized continuous backplane sheet e.g., a sheet of prepreg
  • the continuous backplane layer or sheet e.g., an aramid fiber / resin prepreg sheet with a thickness in the range of about 50 to 100 microns
  • a properly sized continuous backplane sheet e.g., a sheet of prepreg
  • the continuous backplane layer or sheet e.g., an aramid fiber / resin prepreg sheet with a thickness in the range of about 50 to 100 microns
  • the monolithic interconnections of the plurality of icells on a shared continuous backplane layer using the second layer of patterned metal M2 results in further reduction of the overall solar cell and PV module manufacturing cost as well as improved projected reliability of the PV modules during field operation (due to the elimination of soldered tabs, strings).
  • the embodiments of this invention can be applied to solar cells using this type of process flow as outlined in the representative process flow of Figure 5 A, as well as many other solar cell designs (as described before) and solar cell fabrication process flows including but not limited to the solar cells fabricated from starting monocrystalline wafers (e.g., Czochralski or CZ, Float Zone or FZ) or multi-crystalline wafers (from cast crystalline bricks or formed by a ribbon pulling process) or epitaxial growth or other substrate fabrication methods.
  • icell embodiments may be applied to other semiconductor materials besides silicon as described before, including but not limited to gallium arsenide, germanium, gallium nitride, other compound semiconductors, or a combination thereof.
  • Fig. 5B is a high level solar cell and module fabrication process flow embodiment using starting crystalline (mono-crystalline or multi-crystalline) silicon wafers.
  • Fig. 5B shows a high-level icell process flow for fabrication of backplane-attached back- contact/back-junction (IBC) icells using two layers of metallization: Ml and M2.
  • the first layer or level of patterned cell metallization Ml is formed as essentially the last process step among a plurality of front-end cell fab processes prior to the backplane lamination to the partially processed icell (or a larger continuous backplane attached to a plurality of partially processed icells when fabricating monolithic modules as described earlier).
  • the front-end cell fab processes outlined in the top 4 boxes of Fig. 5B essentially complete the back-contact/back-junction solar cell backside structure through the patterned Ml layer.
  • Patterned Ml is designed to conform to the icell isles (mini-cells) and comprises a fine-pitch interdigitated metallization pattern as described for the epitaxial silicon icell process flow outlined in Fig. 5A.
  • the fifth box from the top involves attachment or lamination of the backplane layer or sheet to the partially processed icell backside (or to the backsides of a plurality of partially processed icells when making a monolithic module) - this process step is essentially equivalent to the one performed by Tool 12 in Fig.
  • Fig. 5B the sixth and seventh boxes from the top outline the back-end or post-backplane- attachment (also called post-lamination) cell fab processes to complete the remaining frontside (optional silicon wafer thinning etch to form thinner silicon absorber layer if desired, partitioning trenches, texturization, post-texturization cleaning, passivation and ARC) as well as the via holes and second level or layer of patterned metallization M2.
  • the "post-lamination" processes (or the back-end cell fab processes performed after the backplane attachment) outlined in the sixth and seventh boxes of Fig. 5B essentially correspond to the processes performed by Tools 13 through 18 for the epitaxial silicon lift off process flow shown in Fig.
  • the bottom box in Fig. 5B describes the final assembly of the resulting icells into either flexible, lightweight PV modules or into rigid glass-covered PV modules. If the process flow results in a monolithic module comprising a plurality of icells monolithically interconnected together by the patterned M2 (as described earlier for the epitaxial silicon lift off process flow), the remaining PV module fabrication process outlined in the bottom box of Fig. 5B would be simplified since the plurality of the interconnected icells sharing a larger continuous backplane and the patterned M2 metallization for cell-to-cell interconnections are already electrically interconnected and there is no need for tabbing and/or stringing and/or soldering of the solar cells to one another.
  • the resulting monolithic module can be laminated into either a flexible, lightweight PV module (for instance, using a thin flexible fluoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet) or a rigid, glass-covered PV module.
  • a flexible, lightweight PV module for instance, using a thin flexible fluoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet
  • a rigid, glass-covered PV module for instance, using a thin flexible fluoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet.
  • Fig. 5C illustrates an alternative high level solar cell (icell) and module fabrication process flow embodiment using epitaxial silicon and porous silicon lift-off processing as compared to the process flow of Fig. 5A.
  • Fig. 5C also shows a high-level icell process flow for fabrication of backplane-attached back-contact/back-junction (IBC) icells using two layers of metallization: Ml and M2.
  • IBC backplane-attached back-contact/back-junction
  • the first layer or level of patterned cell metallization Ml is formed as essentially the last process step among a plurality of front-end cell fab processes prior to the backplane lamination to the partially processed icell using epitaxial silicon as the solar cell absorber (or a larger continuous backplane attached to a plurality of partially processed epitaxial icells after lift-off release of the individual partially processed icells, when fabricating monolithic modules as described earlier).
  • Patterned Ml is designed to conform to the icell isles (mini-cells) and comprises a fine-pitch interdigitated metallization pattern as described for the epitaxial silicon icell process flow outlined in Fig. 5A.
  • the fifth box from the top involves attachment or lamination of the backplane layer or sheet to the partially processed epitaxial icell backside (or using a larger continuous backplane sheet to be attached to the backsides of a plurality of partially processed and released icells when making a monolithic module) - this process step is essentially equivalent to the one performed by Tool 12 in Fig.
  • FIG. 5C the sixth and seventh boxes from the top outline the back-end or post- backplane-attachment (also called post-lamination) cell fab processes to complete the remaining frontside (icell partitioning trenches, texturization, post-texturization cleaning, passivation and ARC) as well as the via holes and second level or layer of patterned metallization M2.
  • the "post-lamination" processes (or the back-end cell fab processes performed after the backplane attachment) outlined in the sixth and seventh boxes of Fig. 5C essentially correspond to the processes performed by Tools 13 through 18 for the epitaxial silicon lift off process flow shown in Fig. 5A.
  • 5C describes the final assembly of the resulting icells into either flexible, lightweight PV modules or into rigid glass-covered PV modules. If the process flow results in a monolithic module comprising a plurality of icells monolithically interconnected together by the patterned M2 (as described earlier for the epitaxial silicon lift off process flow), the remaining PV module fabrication process outlined in the bottom box of Fig. 5C would be simplified since the plurality of the interconnected icells sharing a larger continuous backplane and the patterned M2 metallization for cell-to-cell interconnections are already electrically interconnected and there is no need for tabbing and/or stringing and/or soldering of the solar cells to one another.
  • the resulting monolithic module can be laminated into either a flexible, lightweight PV module (for instance, using a thin flexible fiuoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet) or a rigid, glass-covered PV module.
  • a flexible, lightweight PV module for instance, using a thin flexible fiuoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet
  • a rigid, glass-covered PV module for instance, using a thin flexible fiuoropolymer cover sheet such as ETFE or PFE on the frontside instead of rigid / heavy glass cover sheet.
  • Fig. 5D is a high level cross-sectional device diagram showing an expanded and selective simplified view of a mini-cell or isle among a plurality of isles in an icell after solar cell fabrication steps of an interdigitated back-contact (IBC) solar cell embodiment.
  • IBC interdigitated back-contact
  • Detailed doped emitter and base regions, optional front-surface field (FSF) and/or optional back-surface field (BSF) regions, contacts for Ml metallization, and conductive via plugs connecting patterned Ml to patterned M2 through the electrically-insulating continuous backplane layer are not shown.
  • Fig. 5E is a more detailed cross-sectional diagram showing an expanded view of a mini-cell or isle among a plurality of isles in an icell after solar cell fabrication steps of an interdigitated back-contact (IBC) solar cell embodiment.
  • IBC interdigitated back-contact
  • the isolation trenches partitioning the main initially continuous semiconductor substrate through the substrate layer thickness (either from a starting crystalline semiconductor wafer or from an epitaxially grown crystalline layer) into a plurality of mini-cells (or isles or sub-cells or tiles) on the continuous supporting backplane layer have average trench width which may be on the order of about 10's of microns (or in the range of about 10 microns to about 100 microns).
  • trench isolation regions partitioning the backplane-attached semiconductor layer into a plurality of mini-cells may be formed by using either pulsed laser ablation / scribing or another technique, for instance, by mechanical dicing / scribing or ultrasonic dicing / scribing or water jet dicing / scribing or another method (the terms scribing, dicing, cutting, and ablation are used interchangeably herein when describing the icell partitioning or isolation trench formation process; moreover, the terms partitioning trenches or isolation trenches are used interchangeably in this document when referring to the trench pattern formed through the semiconductor layer thickness to form a plurality of isles or mini-cells, all supported by and attached to a continuous backplane layer or sheet which is attached to the partially processed semiconductor substrate prior to the partitioning trench formation process).
  • a suitable trench partitioning or isolation formation process such as a pulsed laser scribing or cutting process selectively cuts through the semiconductor layer and effectively stops on the backplane layer or sheet after cutting essentially through the entire thickness of the semiconductor layer without a substantial removal of the backplane material (hence, negligible or relatively small trenching of the backplane layer to maintain the integrity of the continuous backplane sheet).
  • the partitioning trench formation process such as a pulsed nanoseconds ablation scribing process
  • the partitioning trench formation process can be performed to form the desired partitioning trench pattern by cutting through the semiconductor layer thickness based on the desired trench pattern, while limiting the backplane sheet material removal to relatively small range between zero and less than a fraction of the backplane layer thickness (e.g., backplane material trenching depth limited to between zero and less than about 20% of the backplane layer thickness).
  • backplane sheet material removal e.g., backplane material trenching depth limited to between zero and less than about 20% of the backplane layer thickness.
  • a master monolithic cell comprising trench-partitioned or trench-isolated isles (also referred to as tiles, pavers, sub-cells, or mini-cells).
  • a common master monolithic cell (icell) shape is a square
  • the master cell (icell) may be chosen to have any desired geometrical shapes and dimensions, for example a full square, pseudo square, rectangle, pseudo- rectangle, parallelogram, hexagon, triangle, any polygon, circle, ellipse, or a combination thereof.
  • the most common shapes used for crystalline silicon solar cells and modules are the full-square and pseudo-square solar cells.
  • the trench-partitioned isles may be formed of various and individually different geometrical shapes and/or sizes (areas and side / diagonal dimensions), or may be uniformly sized and shaped (in other words uniformly sized and shaped isles having the same geometrical shapes and areas as one another).
  • One consideration determining the shapes and sizes of the isles making up the solar cell is the desired degree of backplane-attached solar cell flexibility or bendability and pliability (when using a flexible backplane sheet such as a prepreg sheet) while minimizing or eliminating crack generation or crack propagation in resulting solar cell comprising the semiconductor absorber layer and in the solar cell metallization structure.
  • the isles may have a uniform shape to produce uniform current under uniform illumination.
  • any number of isle shapes and/or sizes may be used dependent on other considerations such as master cell (icell) flexibility / bendability and isle-to-isle electrical interconnection designs to produce the desired icell voltage and current scaling factor.
  • the isles may be an N x N array where N is an integer with N> 2 (for example N x N is greater than or equal to four, or in other words there are at least four isles in an icell).
  • N x N is greater than or equal to four, or in other words there are at least four isles in an icell.
  • an icell may have as few as 2 isles or subcells (e.g., a square-shaped icell with 2 sub-cells or isles may have two triangular isles).
  • the icell configurations with N x N isles present the advantage of simplicity in terms of the icell processing and interconnection design, as well as good compatibility with full-square and pseudo-square solar cells.
  • the isles may be in an N x M array where N and M are both integers (for example N x M is greater than or equal to 2, in other words there are at least two isles).
  • N x M is greater than or equal to 2, in other words there are at least two isles.
  • the degree of icell flexibility or bendability or pliability may be increased for larger values of N x N or N x M, and/or by using relatively smaller sized isles near the cell edge regions (compared to the isles away from the edge regions).
  • Improved flexibility / bendability of icells are desirable attributes for flexible, lightweight PV modules.
  • the removal of semiconductor material to form the partitioning trenches and corresponding increased cell edge area should be limited, for example to no more than about 2% of the master cell (icell) area (the ratio R as discussed earlier in this document), and in some cases to less than 1% of the icell area.
  • the isles may be an array of triangles, or a combination of squares (and/or rectangles) and triangles (in some embodiments, square- shaped isles proximate the master cell center region and triangular isles proximate the cell edge regions).
  • various combinations of isle shapes and arrangements within the master cell (icell) may be formed in accordance with the disclosed subject matter.
  • FIGs. 6A and 6B are diagrams of backplane-attached solar cell (icell)
  • Fig. 6A is a schematic diagram of a top or plan view of a 3 x 3 uniform isled (tiled) master solar cell or icell 30 defined by cell peripheral boundary or edge region 32, having a side length L, and comprising nine (9) uniform square-shaped isles formed from the same original continuous substrate and identified as In through I33 attached to a continuous (continuous) backplane on the master cell backside (backplane and solar cell backside not shown).
  • Each isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and often less than or equal to about 100 ⁇ - for instance, a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 34.
  • Main cell (or icell) peripheral boundary or edge region 32 has a total peripheral length of 4L; however, the total icell edge boundary length comprising the peripheral dimensions of all the isles comprises cell peripheral boundary 32 (also referred to as cell outer periphery) and trench isolation borders 34.
  • the total icell edge length is N x cell outer periphery.
  • N 3
  • square isle side dimensions are approximately 52 mm x 52 mm and each isle or sub-cell has an area of 27.04 cm 2 per isle.
  • Fig. 6B is a schematic diagram of a top or plan view of a 5 x 5 uniform isled (tiled) master solar cell or icell 40 defined by cell peripheral boundary or edge region 42, having a side length L, and comprising twenty five (25) uniform square-shaped isles formed from the same original continuous substrate and identified as In through I55 attached to a continuous (continuous) backplane on the master cell backside (backplane and solar cell backside not shown).
  • a 5 x 5 uniform isled (tiled) master solar cell or icell 40 defined by cell peripheral boundary or edge region 42, having a side length L, and comprising twenty five (25) uniform square-shaped isles formed from the same original continuous substrate and identified as In through I55 attached to a continuous (continuous) backplane on the master cell backside (backplane and solar cell backside not shown).
  • Each isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and often less than or equal to about 100 ⁇ - for instance, a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 44.
  • Main cell (or icell) peripheral boundary or edge region 42 has a total peripheral length of 4L; however, the total icell edge boundary length comprising the peripheral dimensions of all the isles comprises cell peripheral boundary 42 (also referred to as cell outer periphery) and trench isolation borders 44.
  • the total icell edge length is N x cell outer periphery.
  • N 5
  • square isle side dimensions are approximately 31.2 mm x 31.2 mm and each isle or sub-cell has an area of 9.73 cm 2 per isle.
  • total cell edge length (cumulative lengths of the sidewall edges of all the isles in an icell) to 24L (for example in a 6 X 6 array) in order to limit the total icell edge length and sidewall area.
  • Figs. 7A and 7E are representative plan view diagrams of solar cell embodiments (icells) with triangular shaped isles or mini-cells.
  • the trench isolation pattern for the icell in Fig. 7B is slightly different than that in Fig. 7A.
  • Fig. 7B is slightly different than that in Fig. 7A.
  • the number of triangular isles (mini-cells) in this embodiment is twice the number of triangular isles (mini-cells) in the icell embodiments of Fig. 7A and Fig.
  • the number of triangular isles (mini-cells) in this embodiment is 4.5 times the number of triangular isles (mini-cells) in the icell embodiments of Fig. 7 A and Fig. 7B.
  • the number of triangular isles (mini-cells) in this embodiment is 4 times the number of triangular isles (mini-cells) in the icell embodiments of Fig. 7A and Fig. 7B.
  • Fig. 7A is a diagram of a top view of uniform triangular-shaped isles in an isled master solar cell or icell 50 defined by cell peripheral boundary 52 and having a side length L and comprising eight uniform (equal areas) triangular-shaped isles Ii through Is.
  • Each isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and often less than or equal to about 100 ⁇ - for instance, a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 54.
  • Main cell (or icell) peripheral boundary or edge region 52 has a total peripheral length of 4L; however, the total icell edge boundary length comprising the peripheral dimensions of all the isles comprises cell peripheral boundary 52 (also referred to as cell outer periphery) and trench isolation borders 54.
  • cell peripheral boundary 52 also referred to as cell outer periphery
  • Fig. 7B is a diagram of a top view of uniform triangular-shaped isles in an isled master solar cell or icell 60 defined by cell peripheral boundary 62 and having a side length L and comprising an alternative arrangement of eight uniform (equal areas) triangular-shaped isles Ii through Is, as compared to the triangular isles or mini-cells pattern of Fig. 7A.
  • Each isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and in some cases less than or equal to about 100 ⁇ - for instance, a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 64.
  • Main cell (or icell) peripheral boundary or edge region 62 has a total peripheral length of 4L; however, the total icell edge boundary length comprising the peripheral dimensions of all the isles comprises cell peripheral boundary 62 (also referred to as cell outer periphery) and trench isolation borders 64.
  • Fig. 7C is a diagram of a top view of uniform triangular-shaped isles in an isled master solar cell or icell 70 defined by cell peripheral boundary 72 and having a side length L and comprising an arrangement of sixteen uniform (equal areas) triangular- shaped isles Ii through I 16 .
  • Each isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and in some cases less than or equal to about 100 ⁇ - for instance, a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 74.
  • Main cell (or icell) peripheral boundary or edge region 72 has a total peripheral length of 4L; however, the total icell edge boundary length comprising the peripheral dimensions of all the isles comprises cell peripheral boundary 72 (also referred to as cell outer periphery) and trench isolation borders 74.
  • cell peripheral boundary 72 also referred to as cell outer periphery
  • each triangular isle or sub-cell in this embodiment has an area of 15.21 cm 2 per isle.
  • Fig. 7D is a diagram of a top view of uniform triangular-shaped isles in an isled master solar cell or icell 80 defined by cell peripheral boundary 82 and having a side length L and comprising an arrangement of sixteen uniform (equal areas) triangular- shaped isles Ii through I 36 .
  • Each triangular isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and often less than or equal to about 100 ⁇ - for instance, a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 84.
  • Main cell (or icell) peripheral boundary or edge region 82 has a total peripheral length of 4L; however, the total icell edge boundary length comprising the peripheral dimensions of all the isles comprises cell peripheral boundary 82 (also referred to as cell outer periphery) and trench isolation borders 84.
  • cell peripheral boundary 82 also referred to as cell outer periphery
  • each triangular isle or sub-cell in this embodiment has an area of 6.76 cm 2 per isle.
  • Fig. 7E is a diagram of a top view of uniform triangular-shaped isles in an isled master solar cell or icell 90 defined by cell peripheral boundary 92 and having a side length L and comprising an arrangement of thirty two uniform (equal areas) triangular- shaped isles Ii through I32.
  • Each triangular isle or sub-cell or mini-cell or tile is defined by an internal isle peripheral boundary (for example, an isolation trench cut through the master cell semiconductor substrate thickness and having a trench width substantially smaller than the isle side dimension, with the trench width no more than 100's of microns and often less than or equal to about 100 ⁇ - for instance, a few up to about 100 ⁇ ) shown as trench isolation or isle partitioning borders 94.
  • Main cell (or icell) peripheral boundary or edge region 92 has a total peripheral length of 4L; however, the total icell edge boundary length including the peripheral dimensions of all the isles comprises cell peripheral boundary 92 (also referred to as cell outer periphery) and trench isolation borders 94.
  • cell peripheral boundary 92 also referred to as cell outer periphery
  • triangular isle side dimensions are approximately 39 mm x 39 mm (for the two equal right-angle sides of the triangle) and each triangular isle or sub-cell in this embodiment has an area of 7.605 cm 2 per isle.
  • design of isles or mini-cells may include various geometrical shapes such as squares, triangles, rectangles, trapezoids, polygons, honeycomb hexagonal isles, or many other possible shapes and sizes.
  • the shapes and sizes of isles, as well as the number of isles in an icell may be selected to provide optimal attributes for one or a combination of the following considerations: (i) overall crack elimination or mitigation in the master cell (icell); (ii) enhanced pliability and flexibility / bendability of master cell (icell) without crack generation and/or propagation and without loss of solar cell or module performance (power conversion efficiency); (iii) reduced metallization thickness and conductivity requirements (and hence, reduced metallization material consumption and processing cost) by reducing the master cell (icell) current and increasing the icell voltage (through series connection or a hybrid parallel-series connection of the isles in the monolithic icell, resulting in scaling up the voltage and scaling down the current); and (iv) providing relatively optimum combination of electrical voltage and current range
  • a full-square master cell (icell) having an array of equivalently or uniformly sized N x N square-shaped isles or a plurality of equally sized triangular-shaped isles may be formed to match the photo-generated electrical current among isles or subgroups of isles connected in series.
  • the square-shaped master cell (icell) may comprise N x N uniform (equally sized in terms of the isle areas) square-shaped or nearly square-shaped isles (with N being an integer: 2, 3, 4, ...) or K uniform triangular-shaped isles (with K being an integer, for example an even integer, equal to 4 or larger).
  • Fig. 8 is a schematic circuit diagram showing a simplified equivalent circuit model of a typical solar cell with edge recombination effects (as well as finite series resistance and shunt resistance values, and finite dark current).
  • a realistic solar cell includes parasitic series and shunt resistances as well as edge recombination effects and dark current, all having detrimental impacts on the solar cell performance.
  • An ideal solar cell has a zero series resistance, an infinite shunt resistance, zero dark current, and negligible or zero edge recombination effects.
  • a typical ratio of crystalline silicon wafer solar cell edge area to cell active (sunnyside) area is on the order of at least 0.50%.
  • the increased edge length of the monolithic isled solar cells (icells) described herein may (but not necessarily) increase solar cell edge recombination effects; however, very effective mitigation measures may be used to substantially decrease the edge effects of the mini-cell (isle) boundary trenches.
  • Solar cell edge recombination currents may cause non-linear shunts and linear or super-linear reverse current instead of normal saturation behavior.
  • recombination currents may be substantially reduced and/or eliminated by taking practical and effective measures in the design and during processing of solar cells.
  • Edge recombination currents are caused by edge regions that are highly disturbed and/or relatively un-passivated, and edge regions which may be in direct contact with the pn-junction (i.e., the solar cell pn junction and its depletion region contacting the edge regions).
  • Edge losses occur due to cell damage (e.g., residual edge sidewall damage if not properly removed by an effective process, such as during the texturization wet etch after formation of the icell trenches, as described earlier) and poor or insufficient passivation of the solar cell edge sidewall areas (the main cell peripheral sidewall areas as well as the partitioning trench sidewall areas in the case of icells) and may be further exacerbated when the solar cell pn junction contacts the solar cell edge area (either around the main solar cell peripheral sidewalls and/or the partitioning trench sidewall areas in icells).
  • cell damage e.g., residual edge sidewall damage if not properly removed by an effective process, such as during the texturization wet etch after formation of the icell trenches, as described earlier
  • poor or insufficient passivation of the solar cell edge sidewall areas the main cell peripheral sidewall areas as well as the partitioning trench sidewall areas in the case of icells
  • the solar cell pn junction contacts the solar cell edge area (
  • Measures to minimize or eliminate the trench isolation edge recombination currents in monolithic isled (tiled) solar cells (icells) which may be used individually or in combination, include: 1) separate/recess the emitter junction (for instance, the p+n emitter junction when using n-type base) of each isle (or mini-cell or sub-cell or tile) from the trench isolation edge (and from the main icell boundary edges) by a narrow base (e.g., n-type base when using n-type base and p+n emitter junction) rim, the separation may be as small as a one micron and as large as 100's of microns depending on the master cell (icell) size and isle size (and resolution of pattern formation during solar cell processing); 2) use laser scribing to form trench isolation regions from the cell sunnyside before wet etch texture process (to allow for the wet texture etch chemistry to etch off and remove any trenching-induced residual damage in the sidewalls of isles or mini-cells as
  • PECVD PECVD
  • ALD Atomic Layer Deposition
  • the following exemplary solar cell designs and manufacturing processes utilize a multi-layer metallization structure, and specifically two levels (or two layers) of solar cell metallization (i.e., dual layer metallization) which are physically separated by an electrically insulating backplane layer (backplane layer attached to the backside of the solar cell).
  • the solar cell base and emitter contact metallization pattern (first layer of patterned metallization or Ml) is formed directly on the solar cell backside, for instance using a relatively thin layer of screen printed paste (e.g., paste comprising aluminum or aluminum-silicon alloy) or plasma sputtered or evaporated (PVD) aluminum (or aluminum silicon alloy) material layer (followed by laser ablation or etchant patterning in the case of PVD-formed metal layer).
  • screen printed paste e.g., paste comprising aluminum or aluminum-silicon alloy
  • PVD plasma sputtered or evaporated
  • This first patterned layer of metallization (herein also referred to as Ml) defines the solar cell contact metallization pattern, such as fine- pitch interdigitated back-contact (IBC) conductor fingers defining the base and emitter metallization regions of the IBC cell.
  • the Ml layer extracts the solar cell electrical power (current and voltage of the solar cell) and transfers the solar cell electrical power to the second patterned level/layer of higher-conductivity solar cell metallization (herein referred to as M2) formed after Ml .
  • the second layer or level of patterned metallization (M2) may comprise a relatively inexpensive and high-electrical-conductivity metal layer such as aluminum and/or copper (along with a suitable thin capping layer of NiV or Ni or another suitable capping metal).
  • the patterned high sheet conductivity M2 layer is formed on the backplane (which forms both the patterned M2 layer as well as the conductive via plugs for the electrical interconnections between the patterned M2 and Ml metallization layers).
  • Via holes are drilled into the backplane (for example by laser drilling). These drilled via holes land on pre-specified regions of patterned Ml for subsequent electrical interconnections between the patterned M2 and Ml layers through conductive via plugs formed in these via holes (plugs may be formed concurrent with and as part of the patterned M2 formation process, or separately). Subsequently, the patterned higher-conductivity metallization layer M2 may be formed (for example, by screen printing, thermal or electron-beam evaporation, plasma sputtering, plating, or a combination thereof - using a relatively inexpensive high-conductivity M2 material comprising aluminum and/or copper).
  • the patterned M2 layer may be designed to be substantially orthogonal or perpendicular to the patterned Ml fingers - in other words the patterned M2 rectangular or tapered (e.g., triangular or trapezoidal) fingers are essentially perpendicular to the Ml fingers. Because of this orthogonal transformation of M2 fingers with respect to Ml fingers, the patterned M2 layer may have far fewer IBC fingers than the Ml layer (for instance, by a factor of about 10 to 50 fewer M2 fingers per mini-cell or unit-cell in some instances). Hence, the M2 layer may be formed in a much coarser pattern with much wider IBC fingers (and much larger base-emitter metal finger pitch) than the
  • Solar cell busbars may be positioned on the M2 layer, and not on the Ml layer (in other words a busbarless patterned Ml layer), to eliminate electrical shading losses associated with on-cell busbars.
  • interconnections and busbars may be positioned on the patterned M2 layer on the solar cell backside backplane, electrical access is provided to both the base and emitter terminals of the solar cell on the backplane from the backside of the solar cell.
  • the continuous backplane material formed between the patterned Ml and M2 layers may be a thin sheet of an electrically insulating material, for instance, a suitable polymeric material such as an aramid fiber prepreg material, with sufficiently matching coefficient of thermal expansion (CTE) with respect to CTE of the semiconductor layer (e.g., crystalline silicon for crystalline silicon solar cells) to avoid causing excessive thermally induced stresses on the thin silicon layer.
  • a suitable polymeric material such as an aramid fiber prepreg material
  • the backplane layer should meet the solar cell process integration requirements for the backend cell fabrication processes, in particular relatively good chemical resistance during optional wet silicon thinning etch and during wet texturing of the cell frontside, and relatively good thermal stability (for instance, up to about 400°C thermal stability) during the subsequent deposition of the frontside passivation and ARC layer(s) as well as during the subsequent M2 fabrication process (if applicable).
  • the electrically insulating continuous backplane layer should also meet the module-level lamination processing and long-term PV module reliability requirements. While various suitable polymeric (such as plastics,
  • fluropolymers, prepregs, etc.) and suitable non-polymeric materials may be used as the electrically insulating backplane material
  • the desired backplane material choice depends on many considerations including, but not limited to, cost, ease of process integration, relative CTE match to silicon, thermal stability, chemical resistance, reliability, flexibility / pliability, etc.
  • prepreg sheet comprising a combination of fibers and resin.
  • Prepreg sheets are used as building blocks of printed circuit boards and may be made from combinations of resins and CTE- reducing fibers or particles.
  • the backplane material may be a relatively inexpensive, low- CTE (typically with CTE ⁇ 10 ppm/°C, or in some instances with CTE ⁇ 5 ppm/°C), thin (usually 50 microns to 250 microns, and in some instances in the range of about 50 to 150 microns) prepreg sheet which is relatively chemically resistant to the optional silicon thinning etch chemistry (e.g., alkaline or acidic silicon etch chemistry) and texturization chemicals (e.g., alkaline or acidic silicon texturization chemistry), and is relatively thermally stable at temperatures up to at least 180°C (and in some instances to temperatures as high about 400°C during the back-end solar cell processing).
  • silicon thinning etch chemistry e.g., alkaline or acidic silicon etch chemistry
  • texturization chemicals e.g., alkaline or acidic silicon texturization chemistry
  • the prepreg sheet may be attached to the solar cell backside after completion of the solar cell backside processing through the formation of the patterned Ml layer, while still on the reusable template (before the cell lift off release process if applicable) using a thermal-vacuum laminator.
  • the prepreg sheet may be attached to the solar cell wafer backside after completion of the solar cell backside processing through the formation of the patterned Ml layer, again using a thermal-vacuum laminator.
  • the thin continuous prepreg sheet (for instance, a 50 to 250 micron thick layer of aramid fiber prepreg sheet) is permanently laminated or attached to the backside of the processed solar cell (or a plurality of solar cells in the case of monolithic module embodiment).
  • the lift-off release boundary is defined around the periphery of the solar cell (near the reusable template edges), for example by using a pulsed laser scribing tool, and the backplane-laminated solar cell is then lifted off and separated from the reusable template using a mechanical release or lift-off process (the solar cells made on starting crystalline silicon wafers do not use a lift-off release process and directly proceed to the back-end solar cell processing after the backplane attachment / lamination process).
  • Subsequent back-end process steps may include: (i) optional silicon thinning etch in the case of solar cells made on starting crystalline silicon wafers, completion of the wet texture and passivation and ARC deposition processes on the solar cell sunnyside, (ii) completion of formation of the solar cell backplane via holes and high-conductivity second layer metallization (M2) on the backplane-attached solar cell backside (which is formed on the solar cell backplane surface).
  • the high-conductivity metallization for patterned M2 (for example comprising aluminum and/or copper, as opposed to silver in order to reduce the overall solar cell manufacturing and material costs) including interdigitated M2 metal fingers for both the emitter and base polarities is formed on the laminated solar cell backplane comprising the laser-drilled via holes.
  • the backplane material may be made of a thin (for instance, about 50 to 250 microns in thickness), flexible, and electrically insulating polymeric material sheet such as a relatively inexpensive prepreg material commonly used in printed circuit boards (PCB) and other industrial applications, which meets the overall process integration and reliability requirements.
  • prepregs are reinforcing materials pre -impregnated with resin and ready to use to produce composite parts (prepregs may be used to produce composites faster and easier than wet lay-up systems).
  • Prepregs may be manufactured by combining reinforcement fibers or fabrics with specially formulated pre-catalyzed resins using equipment designed to ensure
  • prepregs may be easily handled and remain flexible / pliable for a certain time period (out-life) at room temperature. Further, prepreg advances have produced materials which do not require refrigeration for storage, prepregs with longer shelf life, and products that cure at lower temperatures. Prepreg laminates may be cured by heating under pressure (heat-pressure lamination).
  • the monolithically isled cell (icell) designs and fabrication methods disclosed herein may be integrated with known solar cell designs and fabrication process flows, including for back-contact solar cells, without substantially altering or adding manufacturing process steps or tools, and thus without substantially adding to the cost of manufacturing the solar cell.
  • the manufacturing costs of solar cells and modules may be reduced as a result of the icell innovations (as well as the monolithic module embodiment innovations comprising icells).
  • the combination of cell designs in conjunction with a continuous backplane and metallization structure (specifically two patterned metallization layers or levels - Ml and M2) provides a back-junction/back-contact solar cell architecture.
  • backplane and metallization layers may serve as permanent flexible or semi-flexible or rigid structural support/reinforcement and provide high-conductivity (e.g., comprising aluminum and/or copper metallization material) interconnects for a high- efficiency crystalline silicon solar cell without significantly compromising solar cell power or adding to solar cell manufacturing cost.
  • high-conductivity e.g., comprising aluminum and/or copper metallization material
  • Fig. 9A is a schematic diagram showing a backside plan view of a busbarless first metallization layer pattern (Ml) formed on master cell or icell with 4 x 4 square-shaped isles (this icell Ml pattern rear view corresponds to the frontside view shown in Fig. 2 for an icell with the same 4 x 4 square-shaped isles arrangement).
  • Fig. 9B is an expanded view of a section of the schematic diagram of Fig. 9A, showing the expanded backside plan view of one of the isles of Fig.
  • 9A e.g., the isle designated by 114
  • island of busbarless first metallization layer pattern (Ml) interdigitated base and emitter metal fingers electrically isolated from the interdigitated base and emitter Ml fingers of the other isles in the icell.
  • Fig. 9A is a schematic diagram showing a backside plan view of a busbarless first metallization layer pattern (Ml), comprising a plurality of islands (corresponding to the plurality - 4x4 array in this representative example - of isles in the icell) of patterned fine- pitch interdigitated base and emitter metallization fingers, formed on master cell or icell 100 prior to the backplane attachment or lamination to the epitaxially grown (e.g., on porous silicon on template) or crystalline wafer-based semiconductor substrate.
  • This design corresponds to the icell with a 4 x 4 array of square-shaped isles shown in Fig. 2.
  • Fig. 9B is an expanded backside view of a solar cell isle from Fig.
  • the isle-partitioning borders 104 also define the Ml metallization islands (plurality of islands of interdigitated base and emitter metallization fingers formed by patterned Ml) for the isles forming the icell (array of 4x4 isles in this embodiment).
  • the 4 x 4 islands of interdigitated Ml fingers may be physically separated (i.e., the interdigitated fingers do not cross or violate the partitioning borders 104) and electrically isolated from each other.
  • the entire plurality of patterned Ml islands (4 x 4 array of Ml islands in this embodiment, comprising a relatively high conductivity and inexpensive metal capable of making good ohmic contacts to both n-type and p-type silicon, such as aluminum) are formed concurrently on the backside of the solar cell by a suitable process such as screen printing of a suitable paste (aluminum or aluminum-silicon alloy paste) or PVD and post-PVD patterning (by pulsed laser ablation patterning or patterned etching).
  • a suitable paste aluminum or aluminum-silicon alloy paste
  • PVD and post-PVD patterning by pulsed laser ablation patterning or patterned etching.
  • the isles or sub- cells or mini-cells are monolithically formed (from the same initially continuous semiconductor layer) trench partitioned and isolated islands of a semiconductor layer (for example, an epitaxially grown silicon layer or a silicon layer from a starting crystalline silicon wafer) ) on a shared continuous or continuous backplane layer / sheet (backplane not shown here but will be attached or laminated to the solar cell backside comprising the backside passivation and patterned on-cell Ml layers).
  • a semiconductor layer for example, an epitaxially grown silicon layer or a silicon layer from a starting crystalline silicon wafer
  • the interdigitated base and emitter metal fingers on each Ml islands are shown without cell busbars on the Ml pattern (shown as alternating emitter Ml metal fingers 110 and base Ml metal fingers 112 formed on solar cell substrate backside 108, prior to the backplane attachment) - thus, there are no on-cell busbars.
  • the electrical interconnections among various trench-partitioned isles of an icell are made through the second patterned metallization layer M2 after completion of the backplane attachment to the partially- processed solar cell backside and towards the end of the back-end processing of the solar cell.
  • Some embodiments may utilize the patterned Ml layer to also interconnect the adjacent or neighboring trench-partitioned isles, for instance, in electrical parallel and/or series connections.
  • Ml metallization layer may be formed on the solar cell substrate backside 108, such as in the case of solar cell being made from an epitaxially grown silicon substrate, while the partially-processed epitaxial solar cell is still attached to its supporting crystalline silicon template structure on the cell sunnyside. This was described earlier in conjunction with the epitaxial silicon solar cell fabrication process flows.
  • Fig. 10A is a schematic diagram showing a backside plan view of a busbarless first metallization layer pattern (Ml) formed on master cell or icell with 3 x 3 square- shaped isles (this icell Ml pattern rear view corresponds to the frontside view shown in Fig. 6 A for an icell with the same 3 x 3 square-shaped isles arrangement).
  • Fig. 10B is a schematic diagram showing a backside plan view of a busbarless first metallization layer pattern (Ml) formed on master cell or icell with 5 x 5 square-shaped isles (this icell Ml pattern rear view corresponds to the frontside view shown in Fig. 6B for an icell with the same 5 x 5 square-shaped isles arrangement).
  • Ml busbarless first metallization layer pattern
  • the partitioning borders 124 also define the Ml metallization islands (plurality of islands of mterdigitated base and emitter metallization fingers) for the isles forming the icell (3 x 3 isles in this embodiment).
  • the 3 x 3 islands of mterdigitated Ml fingers may be physically separated (i.e., the mterdigitated fingers do not cross or violate the partitioning borders 124) and electrically isolated from each other.
  • the entire plurality of patterned Ml islands (3 x 3 array of Ml islands in this embodiment, comprising a relatively high conductivity and inexpensive metal capable of making good ohmic contacts to both n-type and p-type silicon, such as aluminum) are formed concurrently on the backside of the solar cell by a suitable process such as screen printing of a suitable paste (such as a paste comprising aluminum or aluminum-silicon alloy) or PVD and post-PVD patterning (by pulsed laser ablation patterning or patterned etching).
  • a suitable paste such as a paste comprising aluminum or aluminum-silicon alloy
  • PVD and post-PVD patterning by pulsed laser ablation patterning or patterned etching.
  • the isles or sub-cells or mini-cells are monolithically formed (from the same initially continuous semiconductor layer) trench partitioned and isolated islands of a semiconductor layer (for example, an epitaxially grown silicon layer or a silicon layer from a starting crystalline silicon wafer) on a shared continuous or continuous backplane layer / sheet (backplane not shown here but will be attached or laminated to the solar cell backside comprising the backside passivation and patterned on-cell Ml layers).
  • each island of mterdigitated base and emitter metal fingers corresponding to the metallization region for each isle.
  • the mterdigitated base and emitter metal fingers on each Ml islands are shown without cell busbars on the Ml pattern (shown as alternating emitter and base Ml metal lines 122 formed on solar cell substrate backside, prior to the backplane attachment) - thus, there is no on-cell busbar.
  • the patterned interdigitated Ml metallization fingers for each Ml island (corresponding to each trench-partitioned isle for the resulting icell) are physically and electrically isolated from the patterned interdigitated Ml metallization fingers of the other neighboring islands.
  • the electrical interconnections among various trench-partitioned isles of an icell are made through the second patterned metallization layer M2 after completion of the backplane attachment to the solar cell backside and towards the end of the back-end processing of the solar cell.
  • Some embodiments may utilize the patterned Ml layer to also interconnect some adjacent or neighboring trench-partitioned isles, for instance, in electrical parallel and/or connections.
  • Ml metallization layer may be formed on the solar cell substrate backside, such as in the case of solar cell being made from an epitaxially grown silicon substrate, while the partially-processed epitaxial solar cell is still attached to its supporting crystalline silicon template structure on the cell sunnyside. This was described earlier in conjunction with the epitaxial silicon solar cell fabrication process flows.
  • the entire plurality of patterned Ml islands (5 x 5 25 array of Ml islands in this embodiment, comprising a relatively high conductivity and
  • inexpensive metal capable of making good ohmic contacts to both n-type and p-type silicon, such as aluminum) are formed concurrently on the backside of the solar cell by a suitable process such as screen printing of a suitable paste (such as comprising aluminum or aluminum-silicon alloy) or PVD and post-PVD patterning (by pulsed laser ablation patterning or patterned etching).
  • a suitable paste such as comprising aluminum or aluminum-silicon alloy
  • PVD and post-PVD patterning by pulsed laser ablation patterning or patterned etching.
  • the isles or sub-cells or mini-cells are monolithically formed (from the same initially continuous semiconductor layer) trench partitioned and isolated islands of a semiconductor layer (for example, an epitaxially grown silicon layer or a silicon layer from a starting crystalline silicon wafer) on a shared continuous or continuous backplane layer / sheet (backplane not shown here but will be attached or laminated to the solar cell backside comprising the backside passivation and patterned on-cell Ml layers).
  • a semiconductor layer for example, an epitaxially grown silicon layer or a silicon layer from a starting crystalline silicon wafer
  • backplane layer / sheet backplane not shown here but will be attached or laminated to the solar cell backside comprising the backside passivation and patterned on-cell Ml layers.
  • the interdigitated base and emitter metal fingers on each Ml islands are shown without cell busbars on the Ml pattern (shown as alternating emitter and base Ml metal lines 132 formed on solar cell substrate backside, prior to the backplane attachment) - thus, there are no on-cell busbars (to prevent or minimize electrical shading losses).
  • the patterned interdigitated Ml metallization fingers for each Ml island are physically and electrically isolated from the patterned interdigitated Ml metallization fingers of the other neighboring islands.
  • the electrical interconnections among various trench-partitioned isles of an icell may be made through the second patterned metallization layer M2 after completion of the backplane attachment to the solar cell backside and towards the end of the back-end processing of the solar cell.
  • Some embodiments may utilize the patterned Ml layer to also interconnect the adjacent or neighboring trench-partitioned isles, for instance, in electrical parallel connection.
  • Ml metallization layer may be formed on the solar cell substrate backside, such as in the case of solar cell being made from an epitaxially grown silicon substrate, while the partially-processed epitaxial solar cell is still attached to its supporting crystalline silicon template structure on the cell sunnyside. This was described earlier in conjunction with the epitaxial silicon solar cell fabrication process flows.
  • Fig. 11B is an expanded view of a section of the schematic diagram of Fig. 11 A, showing the expanded backside plan view of a group of triangular isles of Fig.
  • 11A e.g., the isles designated by II , 12, 13, 14
  • Ml busbarless first metallization layer pattern
  • Ml busbarless first metallization layer pattern
  • Fig. 11B is an expanded backside view of a solar cell isle from Fig.
  • various border lines 144 and 154 shown as dark axial - horizontal and vertical - lines, and white diagonal border lines, separating the triangular islands of interdigitated Ml metal fingers
  • the partitioning trenches will be formed from the sunnyside of the semiconductor substrate on the opposite side of the backplane.
  • the isles or sub-cells or mini-cells are monolithically formed (from the same initially continuous semiconductor layer) trench partitioned and isolated islands of a
  • the semiconductor layer for example, an epitaxially grown silicon layer on porous silicon on template or a silicon layer from a starting crystalline silicon wafer) ) on a shared continuous or continuous backplane layer / sheet (backplane not shown here but will be attached or laminated to the solar cell backside comprising the backside passivation and patterned on-cell Ml layers).
  • interdigitated base and emitter metal fingers on each Ml islands are shown without cell busbars on the Ml pattern (shown as alternating emitter Ml fingers 150 and base Ml fingers 152 formed on solar cell substrate backside 148, prior to the backplane attachment) - thus, there are no on-cell busbars (in order to avoid or eliminate electrical shading losses).
  • the patterned interdigitated Ml metallization fingers for each triangular-shaped Ml island are physically and electrically isolated from the patterned interdigitated Ml metallization fingers of the other neighboring islands.
  • the electrical interconnections among various trench-partitioned isles of an icell are made through the second patterned metallization layer M2 after completion of the backplane attachment to the solar cell backside and towards the end of the back-end processing of the solar cell.
  • Some embodiments may utilize the patterned Ml layer to also interconnect the adjacent or neighboring trench-partitioned isles, for instance, in electrical parallel and/or series connections.
  • Ml metallization layer may be formed on the solar cell substrate backside, such as in the case of solar cell being made from an epitaxially grown silicon substrate, while the partially-processed epitaxial solar cell is still attached to its supporting crystalline silicon template structure on the cell sunnyside.
  • Fig. 12A is a schematic diagram showing a backside plan view of a second and final metallization layer pattern (M2) formed on master cell or icell backside for an icell with an array of 5 x 5 square-shaped isles (this M2 pattern applies to the solar cell design shown in Fig. 6B on which Ml is formed as shown in Fig. 10B).
  • Fig. 12B is an expanded view of a section of M2 structure in the schematic diagram of Fig.
  • FIG. 12A showing the expanded backside plan view of the M2 pattern for a few of the series-connected isles within one quadrant region of Fig. 11A (e.g., including the M2 pattern for the isles designated by 114, 115, 124, 125, indicating the interdigitated base and emitter M2 metal fingers.
  • Fig. 12B is an expanded view of the M2 metallization layer pattern in a few of the isles within a quadrant of the solar cell of Fig. 12A.
  • Patterned M2 metallization layer 162 is formed on the continuous backplane layer 177 attached or laminated to the backside of the solar cell after formation of the patterned Ml layer. The patterned Ml and M2 layers are separated from each other by the backplane layer 177 and interconnected together through the conductive via plugs as described earlier.
  • Patterned M2 metallization layer 162 shown in Figs. 12A and B comprises substantially rectangular interdigitated emitter and base metal fingers which connect to the underlying patterned Ml layer through a plurality of conductive via plugs (formed by the M2 metallization process through the laser-drilled via holes through the backplane layer).
  • the patterned M2 interdigitated rectangular fingers are may be patterned such that they are substantially perpendicular or orthogonal to the underlying patterned Ml interdigitated base and emitter fingers, hence, allowing for substantially smaller number of M2 base and emitter fingers as compared to the number of Ml base and emitter fingers.
  • the isles in each column comprising a group of 5 isles in this embodiment are connected in electrical series by M2 series connections 170 (base M2 metal of each isle connected to the emitter M2 metal of its adjacent isle and emitter M2 metal of each isle connected to the base M2 metal of its adjacent isle in the same column and when transitioning from the end of one column to the beginning of its adjacent column; the base M2 busbar of one corner isle and the emitter M2 busbar of another diagonally opposite isle corner isle serve as the icell base and emitter busbars for icell to icell interconnections either through extensions of M2 in monolithic module embodiments or through tabbing / stringing / and/or soldering of the solar cells together when not using Monolithic Module embodiment).
  • emitter lead or busbar 166 emitter terminal for isle In (top left corner isle) and base lead or busbar 168 (base terminal) for isle I55 (bottom right corner isle) serve as the main busbars of the icell 160.
  • the adjacent columns of patterned M2 layer corresponding to the adjacent columns of isles (5 isles per column in this embodiment) are separated by M2 column electrical isolation gap regions 178 (i.e., no M2 metal in these isolation regions), exposing backplane layer 177.
  • the M2 column electrical isolation gap regions 178 are formed concurrently along with formation of all the M2-level patterned base and emitter fingers as well as emitter lead or busbar 166 (emitter terminal) and base lead or busbar 168 (base terminal) as part of monolithically- fabricated patterned M2 metallization layer.
  • M2 series connections 170 between adjacent isles in columns electrically connect the M2 base fingers 174 from isle In to the M2 emitter fingers 176 of isle I21.
  • the M2 base fingers 174 of isle I21 are electrically connected to the M2 emitter fingers 176 of isle I31 and so on vertically to isle I51, hence, completing the electrical series connections of the isles in the first column.
  • M2 series connection lateral jumper 172 electrically connects the M2 base fingers 174 of isle I51 (in column 1) to M2 emitter fingers 176 of isle I52 (in column 2).
  • Each mini-cell or isle may be connected in series to at least one of the other isles in the array, with all the isles in the array of 5 x 5 isles connected in electrical series, such as that shown in Fig. 12A, which is herein referred to as an all-series connection.
  • each isle (or each sub-group of Ml parallel connected isles) has a corresponding M2 unit cell design of interdigitated rectangular fingers formed on and orthogonal to the underlying interdigitated Ml finger unit cell for that isle - In in Fig. 6B corresponding to In in Fig. 10B corresponding to In in Fig. 12A.
  • the metal fingers comprising the M2 unit cell design for icells may be tapered, for instance, triangular or trapezoidal shaped, as shown in Fig. 13.
  • Fig. 13 is a schematic diagram showing a backside plan view of a second metallization layer pattern (M2) unit cell having a plurality of interdigitated tapered/ right-angle triangular base and emitter fingers.
  • Fig. 13 is a schematic diagram showing a backside plan view of a second metallization layer pattern (M2) unit cell 180 having, for instance, six pairs of tapered/ right-angle triangular fingers - M2 tapered base fingers 184 (all attached to M2 base busbar) and M2 tapered emitter fingers 182 (all attached to M2 emitter busbar) separated by electrical isolation gaps 186 formed during M2 patterning.
  • M2 tapered is used herein to describe M2 fingers which are wider at the isle busbar connection and narrower as the fingers extend from the busbar towards the other end of isle.
  • a tapered M2 finger design may reduce ohmic losses and reduce M2 layer thickness requirements by about 30% as compared to rectangular M2 fingers - thus allowing for a thinner M2 layer for given allowable metallization ohmic losses.
  • Tapered base and emitter M2 fingers (tapered away from corresponding isle M2 busbar) may be shaped as nearly triangular (right-angle, equilateral, or other desired triangular shape) or nearly trapezoidal.
  • Fig. 13 is a diagram showing a backside view of a second metallization unit cell layer pattern (M2) formed on master cell isle 180 (concurrently and monolithically along with the patterned M2 for all the other isles in the icell), having triangular-tapered interdigitated base fingers 184 and emitter fingers 182 defined and electrically isolated by isolation metallization electrical isolation gap 186 (formed as part of patterned M2 formation).
  • the M2 metallization pattern shown in Fig. 13 may be positioned for example orthogonal or perpendicular to the patterned Ml fingers, on each individual isle (such as each isle connected in series with the other isles in the icell) or on a sub-group of Ml -parallel-connected isles. Tapered fingers may further reduce M2 thickness requirements (typically by about 30% with respect to rectangular fingers) and allow for a thinner M2 metallization layer (due to the reduced electrical sheet conductance requirements).
  • Fig. 14A is a schematic diagram showing a backside plan view of a second metallization layer pattern (M2) formed on the backside of an icell (similar to the cell shown in Fig. 2 on which patterned Ml is formed as shown in Fig. 9A).
  • M2 second metallization layer pattern
  • This shows an icell M2 pattern to make electrical series connections of the 4 x 4 16 array of square- shaped isles.
  • Patterned M2 fingers use triangular base and emitter metal fingers (number of M2 fingers is less than the number of Ml fingers per isle). In some instances M2 fingers may be orthogonal or perpendicular to the Ml fingers. M2 fingers can be much wider and coarser pitch than Ml fingers.
  • Fig. 14B is a schematic diagram showing an expanded backside plan view of a portion of the solar cell from Fig. 14A, with a patterned M2 metallization layer, specifically showing full view of isle 114 along with partial views of isles 113, 123, and 124.
  • Fig. 14A is a diagram showing a backside plan view of an second metallization layer pattern (M2) formed on master cell or icell 190 (similar to the cell shown in Fig. 2 on which patterned Ml is formed as shown in Fig. 9A).
  • Fig. 14B is an expanded schematic plan view of a portion of the solar cell from Fig. 14A, with a patterned M2 metallization layer, specifically showing full view of isle I 14 along with partial views of isles Ii3, 123, and I 24 .
  • M2 second metallization layer pattern
  • Patterned M2 unit cell metallization layer 192 is formed on the backplane layer attached to the solar cell backside comprising the patterned Ml layer, and on the backside of each isle in the icell, as tapered (e.g., triangular shaped as shown) interdigitated emitter and base metal fingers which are electrically interconnected to the underlying Ml layer through a plurality of conductive via plugs.
  • the patterned M2 interdigitated triangular fingers (M2 emitter fingers 206 and M2 base fingers 204 which are electrically isolated in the patterned M2 layer by isolation gaps 210) are patterned substantially orthogonal or perpendicular to the underlying Ml interdigitated fingers allowing for substantially fewer M2 fingers as compared to the number of Ml fingers for each isle.
  • emitter lead 194 emitter terminal or busbar for icell
  • base lead 196 base terminal or busbar for icell
  • each isle column is separated by M2 column isolation regions 198, also formed as part of the patterned M2 formation process.
  • M2 series connections 200 electrically connect the M2 base fingers 204 from isle In to the M2 emitter fingers 206 of isle I21.
  • the M2 base fingers 204 of isle I21 are electrically connected to the M2 emitter fingers 206 of isle I31 and so on vertically to isle I41.
  • M2 series connection lateral jumper 202 electrically connects the M2 base fingers 204 of isle I41 (in column 1) to M2 emitter fingers 206 of isle I 42 (in column 2).
  • Patterned M2 fingers use triangular base and emitter metal fingers (number of M2 fingers is less than the number of Ml fingers per isle). In some instances, M2 fingers may be orthogonal or
  • M2 fingers can be much wider and coarser pitch than Ml fingers.
  • Fig. 15A is a diagram showing a backside plan view of a second metallization layer pattern (M2) formed on master cell or icell 220 (similar to the cell shown in Fig. 6A on which patterned Ml is formed as shown in Fig. 10A).
  • the M2 metallization pattern may scale up the solar cell voltage (V mp and V oc ) by a factor of nine and scale down the solar cell current (I mp and I sc ) by a factor of nine as compared to a prior art single isle master cell.
  • Patterned M2 unit cell metallization layer 222 is formed on the continuous electrically insulating backplane attached to the solar cell backside after formation of the patterned Ml layer, on the backside of each isle as tapered (e.g., triangular shaped) interdigitated emitter and base M2 metal fingers which are electrically connected to the underlying patterned Ml layer fingers through a plurality of conductive via plugs formed through the backplane.
  • tapered e.g., triangular shaped
  • the patterned M2 interdigitated triangular fingers are patterned substantially orthogonal or perpendicular to the underlying patterned Ml interdigitated fingers allowing for substantially fewer M2 fingers as compared to the number of Ml fingers for each isle.
  • each isle column is separated by M2 column isolation regions 228 formed during the patterned M2 formation process.
  • M2 series connections 230 electrically connect the M2 base fingers 234 from isle In to the M2 emitter fingers 232 of isle I21.
  • the M2 base fingers 234 of isle I21 are electrically connected to the M2 emitter fingers 232 of isle I31.
  • M2 series connection lateral jumper 228 electrically connects the M2 base fingers 234 of isle I31 (in column 1) to M2 emitter fingers 232 of isle I32 (in column 2).
  • Patterned M2 fingers use triangular base and emitter metal fingers (number of M2 fingers is less than the number of Ml fingers per isle). In some instances M2 fingers may be orthogonal or perpendicular to the Ml fingers. M2 fingers can be much wider and coarser pitch than Ml fingers
  • Fig. 15B is a diagram showing a backside plan view of an second metallization layer pattern (M2) deposited on icell or master cell 240 (similar to the cell shown in Fig. 6B on which Ml is deposited as shown in Fig. 10B).
  • the M2 metallization pattern may scale up the voltage (V mp and V oc ) by a factor of 25 and scale down the current (I mp and I sc ) by a factor of 25 as compared to a prior art single isle master cell.
  • V mp and V oc the voltage
  • I mp and I sc scale down the current
  • icell ore master cell 240 is defined by a cell peripheral boundary 258 and comprises 25 uniform square shaped isles In through I55 defined by trench isolation borders.
  • Patterned M2 unit cell metallization layer 242 is formed on the electrically insulating continuous backplane attached to the solar cell backside after formation of the patterned Ml layer, on the backside of each isle as tapered (triangular shaped) interdigitated emitter and base metal fingers which are electrically interconnected to the underlying Ml layer through a plurality of conductive via plugs through the backplane layer.
  • the M2 interdigitated triangular fingers (M2 emitter fingers 252 and M2 base fingers 254 which are electrically isolated by isolation gaps) are patterned substantially orthogonal or perpendicular to the underlying patterned Ml interdigitated fingers allowing for substantially fewer M2 fingers as compared to the number of Ml fingers.
  • each isle column is separated by M2 column isolation regions 256.
  • M2 series connections 250 electrically connect the M2 base fingers 254 from isle In to the M2 emitter fingers 252 of isle I21.
  • the M2 base fingers 254 of isle I21 are electrically connected to the M2 emitter fingers 252 of isle I31 and so on vertically to isle I51.
  • M2 series connection lateral jumper 248 electrically connects the M2 base fingers 254 of isle I51 (in column 1) to M2 emitter fingers 252 of isle I52 (in column 2).
  • the Ml and M2 unit cell patterns disclosed herein may be designed for square or pseudo-square shaped isles, triangular isles, or various other geometric shaped isles and any combination thereof.
  • the isle design and interconnection pattern may dictate patterned Ml and M2 designs.
  • the required electrical conductivity for M2 is less for a master cell having S isles (or S subgroups of isles) connected in electrical series (or hybrid-parallel-series) as compared to a master cell comprising a single isle because of the reduced cell current and increased cell voltage of an icell with a current and voltage scaling factor of S.
  • S in other words the number of series connected sub-cells or isles— the smaller the M2 thickness requirement as cell current is reduced and cell voltage increased by a factor of S (number of series connected isles or sub-groups of isles in the icell).
  • copper M2 layer thickness for an IBC solar cell may be decreased from the thickness range of about 20 to over 80 microns for a non-tiled solar cell (for instance, 156 mm x 156 mm IBC solar cells) such as that shown in Fig. 1 to less than approximately 20 microns, and in some instances less than 10 microns to as low as about 1 micron to 5 microns, for tiled master cell with series-connected isles (hence, scaling up the voltage and scaling down the current for the icell by the factor S).
  • a non-tiled solar cell for instance, 156 mm x 156 mm IBC solar cells
  • the monolithically tiled solar cell or icell structures and fabrication methods disclosed herein provide for substantially reduced metallization sheet conductance and thickness requirements which in turn can reduce metal consumption, process cost, fabrication process equipment cost, and corresponding capital expenditures. Further hazardous waste byproducts from particular cell fabrication processes, such as that produced during metal plating (for example copper plating), may be reduced or eliminated due to reduced and relaxed metallization sheet conductance and thickness requirements (hence, the capability to eliminate dependency on thick metal plating, by replacing it with a much simpler and lower cost metallization process such as evaporation, plasma sputtering, and/or screen printing.
  • a thinner and simpler M2 metallization pattern may reduce solar cell semiconductor layer microcracks and improve the overall solar cell and module manufacturing yields - for example due to substantially reduced tensilary / mechanical stresses of the thinner patterned M2 metallization and elimination of dependency on metal plating processing (such as copper plating) and associated handling, edge sealing, and plating electrical contacting requirements.
  • metal plating processing such as copper plating
  • the thinner M2 metallization layer enabled by the icell innovative aspects also enable improved flexibility and bendability of the solar cells and flexible, lightweight PV modules without increasing the risk of solar cell microcracks or breakage.
  • Copper plating process used to form the relatively thick (e.g., about 30 to 80 microns) copper metallization for the prior art interdigitated back-contact (IBC) solar cells may degrade the manufacturing yield due to the intrusive nature of copper plating process (requiring one-sided plating, preventing exposure of the IBC solar cell frontside to the plating chemistry) and risk of mechanical breakage of the cells due to handling as well as clamping/sealing and declamping/unsealing of the solar cells during and after the plating process.
  • copper plating processing of solar cells with pre-existing microcracks may plate copper along the silicon microcracks causing hard shunts or soft shunts, resulting in yield or performance degradation.
  • the elimination of copper plating processing due to substantially reduced M2 sheet conductance (or M2 metal thickness) requirements eliminates the need for special Ml designs allowing for the patterned M2 layer to be recessed or offset from the edge of the solar cell to accommodate edge-sealed copper plating.- in other words the laxed M2 sheet conductance requirements of the isled master cells or icells enable replacing thick copper plating process with a dry non-plating process to form the patterned M2 layer, hence eliminating the need for clamping or sealing of the frontside of the cells to eliminate exposure to plating processing. Therefore, the underlying patterned Ml fingers may be extended nearly end-to-end between the edges or partitioning borders of the isles.
  • Thinner solar cell metallization enabled by the icell reduces solar cell bow and mechanical stress, for example on backplane-laminated solar cells disclosed herein, as compared to known solar cells using relatively thick (typically in the range of about 30 to 80 microns for IBC solar cells) plated metal, often plated copper.
  • the reduction of M2 metal thickness in a dual level metallization structure results in enhanced solar cell and PV module flexibility/pliability without crack generation and without PV module
  • patterned M2 may be made of a relatively inexpensive, high-conductivity metal such as copper (bulk resistivity 1.68 ⁇ ⁇ ) or aluminum (bulk resistivity 2.82 ⁇ ).
  • copper has a linear CTE of about 17 ppm/°C and crystalline silicon has a linear CTE of approximately 2.7 ppm/°.
  • the number of series-connected sub-cells or isles may be chosen such that the required low-resistivity or high-conductivity metal (for example inexpensive high-conductivity metals such as copper and/or aluminum, although another high-conductivity metal such as silver may also be used) thickness is sufficiently small in order to use a relatively low- cost metal deposition process, such as plasma sputtering or evaporation (Physical- Vapor Deposition or PVD processes), particularly in instances where the M2 thickness (such as the copper or aluminum thickness) is reduced to less than about 10 microns and in some instances less than approximately 5 microns.
  • a relatively low- cost metal deposition process such as plasma sputtering or evaporation (Physical- Vapor Deposition or PVD processes
  • the M2 thickness such as the copper or aluminum thickness
  • another inexpensive metallization process such as screen printing may be used instead of copper plating.
  • M2 may be patterned to be substantially orthogonal or perpendicular to Ml and the number of M2 fingers (such as tapered fingers) may be much less than the number of Ml fingers, for example by a factor in the range of about 5 to 50. And in some instances, M2 fingers designed in tapered finger shapes such as triangular or trapezoidal shapes, as compared to rectangular shaped fingers, will further reduce the M2 metal thickness requirement (typically by about 30%).
  • each series-connected isle (or subgroups of isles connected in parallel and then in series) will have a maximum-power current of I mp /N 2 (assuming N 2 isles connected in series) and a maximum-power voltage of Vmp (no change in voltage for the isle).
  • a monolithically isled master cell or icell architecture reduces ohmic losses due to reduced solar cell current and allows for thinner solar cell metallization structure generally and a much thinner M2 layer if applicable or desired. Further, reduced current and increased voltage of the master cell or icell allows for relatively inexpensive, high- efficiency, maximum-power-point-tracking (MPPT) power optimizer electronics to be directly embedded into the PV module and/or integrated on the solar cell backplane.
  • MPPT maximum-power-point-tracking
  • the reduced current and increased voltage of the isles may also allow for a relatively inexpensive, high-efficiency, maximum-power-point-tracking (MPPT) power optimizer electronics to be directly embedded into the PV module and/or integrated on the solar cell backplane.
  • MPPT maximum-power-point-tracking
  • the innovative aspects of an icell also enable distributed shade management based on implementation of inexpensive bypass diodes (e.g. pn junction diodes or Schottky diodes) into the module, for instance, one bypass diode embedded with each solar cell prior to the final PV module lamination.
  • the Ml metallization layer may be a busbarless, fine-pitch (base-to-base pitch in the range of approximately about 200 ⁇ to 2 mm, and more specifically in the range of about 500 ⁇ to 1,500 ⁇ ) interdigitated Al and/or Al/Si metal finger pattern (formed by screen printing or PVD and post-PVD patterning) contained within each isle.
  • the Ml fingers may be slightly recessed from the partitioning trench isolation edges (for example recessed or offset from the isle trench isolation edges by approximately 50 ⁇ to 100's ⁇ ).
  • the Ml fingers for each isle in the master cell are electrically isolated and physically separated from each other (the Ml pattern corresponding to a particular isle may be referred to herein as an Ml unit cell).
  • the electrical interconnection configuration of the isles may be defined by the M2 pattern design wherein Ml serves as an on-cell contact metallization for all of the master cell isles and M2 provides high- conductivity metallization and electrical interconnection of the isles within the icell or master cell.
  • An M2 design (for example an M2 pattern using rectangular or tapered interdigitated M2 base and emitter fingers) may provide all-series, hybrid parallel-series, or all-parallel electrical interconnections of the isles in the icell.
  • M2 designs which provide all-series or hybrid parallel-series electrical connections of the isles may be used to scale up the main/master cell voltage and scale down the main/master cell current (for instance, by a factor of S, S being the number of series connected isles or sub-groups of isles).
  • Increasing cell voltage while decreasing cell current relaxes/decreases metallization conductivity requirements and allows for thinner metallization and lower metal sheet conductance, thus reducing or mitigating process costs, process complexity, fab equipment and facilities costs (e.g., because of elimination of the need for copper plating for cell metallization), cracks, reliability concerns, and overall yield loss associated with relatively thick metallization processing such as relatively thick metallization formed using copper plating.
  • the enhanced- voltage/reduced-current main/master solar cell or icell provides for the integration of a relatively inexpensive, high-performance, high- efficiency maximum-power-point-tracking (MPPT) power optimizer electronics embedded within each module and associated with each icell and/or each isle, - thus providing enhanced power and energy harvest capability across a master cell having shaded, partially shaded, and unshaded isles.
  • MPPT maximum-power-point-tracking
  • each icell or even each isle within each icell may have its own inexpensive bypass diode (pn junction diode or Schottky barrier diode) in order to provide distributed shade management capability for enhanced solar cell protection and power harvest under shading and partial shading conditions.
  • An all-parallel electrical connection of isles provided by an all-parallel M2 pattern, as compared to all-series or hybrid parallel-series connection, also provides some of the numerous advantages of a monolithically isled solar cell as described above, particularly the increased flexibility and bendability of the resulting icells and PV modules..
  • a metal stack may be PVD Al (main metal) capped with a relatively thin layer of Ni or NiV (e.g., formed by plasma sputtering), optionally followed by Sn (e.g., formed by plasma sputtering) to provide M2 solderability.
  • the aluminum layer may be deposited using an electron-beam or thermal evaporation process.
  • each "isle" to be connected in electrical series may comprise a subgroup of smaller isles, such as triangular isles, connected in electrical parallel.
  • M2 finger pattern is substantially orthogonal or perpendicular to Ml pattern - this allows the number of M2 fingers to be substantially smaller than the number of Ml fingers (by about a factor of 5x to about 50x).
  • a 156 mm x 156 mm cell (without tiling or isles) with a base-to-base Ml metal pitch of 750 microns may have about 416 Ml fingers and approximately 8 to 40 M2 orthogonal fingers.
  • each isle may have about 140 Ml fingers (running over a distance of about 52 mm in each isle) and an M2 finger count of 12 (for example with the M2 base and emitter metal fingers having combined width or pitch of about 6.5 mm, much larger than the Ml pitch of about 750 microns).
  • the M2 layer may provide a relatively large cell coverage ratio (close to 100%) - in one instance the deposited M2 layer (for example deposited by PVD) is patterned using pulsed nanoseconds laser ablation creating a finger-to-fmger isolation gap less than
  • I mp is the master cell maximum-power-point (MPP) current (base or emitter current) extracted from the entire Ml layer under the STC conditions.
  • MMP master cell maximum-power-point
  • the entire current extracted from cell contact metallization level Ml and flowing through conductive M2-M1 via plugs is Imp for base and Imp for emitter (2I mp without current direction consideration).
  • P mp and V mp are the maximum-power-point (MPP) power and voltage of the cell, respectively.
  • P mp V mp x I mp
  • the total electrical cell current per unit area extracted from Ml including both base and emitter currents, irrespective of flow direction
  • 2I mp /L 2 2I mp base current
  • I mp emitter current 2I mp emitter current
  • patterned M2 metal layer thickness may be limited to less than approximately 5 ⁇ , and in some instances M2 PVD metal layer thickness limited to less than approximately 3 ⁇ , providing numerous economical (for example, reduced PVD material cost and processing simplification) as well as fabrication advantages.
  • electron-beam evaporation or thermal evaporation or DC Magnetron Plasma Sputtering may be used to deposit a high-quality M2 metal layer with near-bulk material resistivity (for example with metal resistivity close to the bulk resistivity values of 1.68 ⁇ for copper or 2.82 ⁇ ⁇ for aluminum) using high-throughput, in-line, evaporation and/or plasma sputtering tools commercially available for high-productivity solar PV
  • an in-line evaporation and/or DC magnetron plasma sputtering (PVD) tool for aluminum M2 sputter deposition may have the following stations: (i) Argon plasma sputter etch to clean laser-drilled through-backplane vias, for low M2-M1 via plug contact resistance and for improved metal adhesion to the backplane; (ii) electron-beam evaporation or thermal evaporation or DC magnetron sputtering of pure aluminum, M2 layer thickness may be based on loss factor design rules, for instance, 3 to 5 microns of aluminum; (iii) DC magnetron sputtering of a thin, for example a layer thickness in the range of approximately 0.05 ⁇ to 0.25 ⁇ , of NiV or Ni capping layer; and (iv) DC magnetron sputtering of Sn, a Sn alloy, or alternative suitable solder material, with a layer thickness of approximately 0.5 ⁇ to several ⁇ .
  • PVD DC magnetron plasma
  • an in-line DC magnetron plasma sputtering (PVD) tool for copper M2 sputter deposition may have the following stations: (i) Argon plasma sputter etch to clean Ml contact areas exposed through laser-drilled backplane via holes, for low M2- Ml via plug contact resistance and improved M2 adhesion to the backplane; (ii) DC magnetron sputtering of a thin, for example a layer thickness in the range approximately 0.05 ⁇ to 0.25 ⁇ , of NiV or Ni as a diffusion barrier and adhesion layer; (iii) DC magnetron sputtering of pure copper, copper thickness may be based on loss factor design rules; and (iv) DC magnetron sputtering of Sn, a Sn alloy, or alternative suitable solder material, with a layer thickness of approximately 0.5 ⁇ to several ⁇ .
  • N may be chosen in order to meet particular design criteria for a given desired loss factor k and corresponding maximum allowable M2 thickness value. And by keeping the M2 copper or aluminum thickness less than about 5 ⁇ , M2 may be easily patterned using pulsed laser ablation.
  • M2 metal layer formation methods include, but are not limited to: PVD aluminum or copper (as well as any applicable barrier and/or capping layers) followed by wet patterning (screen print mask, wet etch metal / strip mask); screen print high-conductivity, low-temperature-cure metal paste such as high- conductivity silver paste, copper paste, aluminum paste, etc.
  • Using aluminum as compared to copper for M2 may allow the cell fabrication line and the resulting cell to be free of copper and in some instances cell fabrication using all dry processing. Thus, improving risk mitigation in cell fabrication (due to inherent complications involved in copper processing such as with copper plating) and for the cell modules in the field as the long-term reliability concerns of copper contamination and lifetime degradation are eliminated.
  • the M2-M1 contact (the metallization in the via holes, or via plugs) may be an aluminum-to-aluminum contact thus eliminating the need for a diffusion barrier layer between M2 and Ml .
  • an M2 Sn/NiV/Al stack or another suitable metal stack comprising aluminum as the main M2 conductor metal may allow for pulsed laser ablation patterning, thus providing all-dry cell backend metallization process and increasing cell yield.
  • a monolithic isled master cell or icell may integrate monolithically-integrated bypass switch (MIBS) with each icell and/or with each isle in the icell to provide high-performance lightweight, thin-format, flexible, high-efficiency (e.g., greater than 20%) solar modules with distributed shade management - for example a pn junction diode, such as a rim pn junction diode, formed around the periphery of each isle.
  • MIBS monolithically-integrated bypass switch
  • the MIBS device may be a metal-contact Schottky diode, such as a rim Schottky diode formed around the periphery of each isle made of, for example, an aluminum or aluminum-silicon alloy Schottky contact on n-type silicon.
  • the pn junction MIBS diode pattern may be one of many possible pattern designs. For instance, in one MIBS diode pattern the rim diode p+ emitter region is a continuous closed-loop band sandwiched between (or surrounded by) the n-type base regions.
  • MIBS integration benefits for a monolithic isled master cell include materials cost reductions combined with substantial manufacturing risk mitigation and higher manufacturing yield due to process simplification (no plating, much reduced cracks) and enhanced overall projected reliability (for example by eliminating the discrete components from cells).
  • a monolithic isled MIBS integrated master cell module may reduce the weight, reduce the volume/size (and thickness), and increase power density (W/kg) of the module by significant factors - further reducing installed system Balance of System (BOS) costs.
  • BOS Balance of System
  • a monolithic isled MIBS integrated master cell module may provide some or all of the following advantages: distributed MIBS shade management without external components; a relatively small average module weight per unit area, for instance, on the order of approximately 1.2 kg/m 2 (-0.25 lb/ft 2 ), which may be at least lOx lighter than the standard rigid c-Si modules; module power density of approximately 155 W/kg (-70 W/lb), which is at least lOx higher than the standard rigid c-Si modules; high-efficiency (greater than 20%) lightweight flexible modules for various applications; module shipping weight and volume (per MW shipped) reductions by approximately lOx and 40x, respectively; reduced overall BOS cost, enabling a lower installed PV system cost compared to installed PV system costs using standard rigid c-Si modules; and reduced BOS and miscellaneous costs relating to shipping and handling, labor, mounting hardware, and wiring costs.
  • MIBS formation may be integrated and performed concurrent with partitioning trench isolation formation processing. If a rim diode design is utilized, the monolithically integrated bypass switch (MIBS) rim may also provide the additional benefit of mitigating or eliminating the generation and/or propagation of micro-cracks in the solar cell during and/or after fabrication of the solar cells.
  • a full-periphery through-silicon partitioning trench separating and isolating the rim bypass diode from the isles may have, for example, an isolation width in the range of a few microns up to about 100 microns depending on the laser beam diameter (or capability of the trenching process if using a process other than laser trenching) and semiconductor layer thickness.
  • a typical trench isolation width formed by pulsed nanoseconds (ns) laser scribing may be around 20 to 50 microns although the trench isolation width may be smaller. While pulsed laser ablation or scribing is an effective and proven method to form the trench isolation regions, it should be noted that other non- mechanical and mechanical scribing techniques may also be used instead of laser scribing to form the trench isolation regions for all trench formation processing. Alternative nonlaser methods include plasma scribing, ultrasonic or acoustic drilling/scribing, water jet drilling/scribing, or other mechanical scribing methods.
  • Fig. 16A is a schematic diagram showing a sunnyside view of isled master cell with a plurality of isles (example shows 4 x 4 isles) and monolithically-integrated bypass switch or MIBS devices integrated with the isles.
  • MIBS using full-periphery bypass diodes isolated from the solar cells using full-periphery isolation trenches for an icell sharing a continuous backplane.
  • Fig. 16A is a schematic diagram showing a sunnyside plan view of isled MIBS (Monolithically Integrated Bypass Switch) master cell 270 (icell embodiment shown with 4 x 4 array of square-shaped isles) with a plurality of full-periphery closed loop MIBS bypass diodes, for example MIBS bypass diode 272 electrically isolated from isle In by isle partitioning isolation trench 274.
  • MIBS Monitoring Integrated Bypass Switch
  • Each isle (In through I 44 ) isolated by full-periphery partitioning trenches (either formed by laser ablation / scribing or scribed by another suitable technique as described above), such as cell isolation trenches 276, to form an icell with a 4 x 4 array of isles (a solar cell comprising a plurality of mini-cells or isles) sharing a shared continuous backplane and formed from a common originally continuous and subsequently partitioned solar cell semiconductor substrate.
  • full-periphery partitioning trenches either formed by laser ablation / scribing or scribed by another suitable technique as described above
  • cell isolation trenches 276 to form an icell with a 4 x 4 array of isles (a solar cell comprising a plurality of mini-cells or isles) sharing a shared continuous backplane and formed from a common originally continuous and subsequently partitioned solar cell semiconductor substrate.
  • Fig. 16A shows the sunnyside view of the MIBS-enabled solar cell (icell) with mini-cells or isles and full-periphery closed- loop rim diodes (either pn junction diodes or Schottky barrier diodes).
  • Each mini-cell isle In through I 44 has a corresponding full periphery isolation trench (276) and full-periphery MIBS rim diode (such as MIBS bypass diode 272 and periphery isolation trench 274 for cell In) - thus each mini cell or isle has a corresponding MIBS rim diode, or in other words there is one MIBS rim diode per isle or mini cell.
  • the isles or mini-cells may be electrically connected in series through the cell metallization pattern design although other connections such as parallel or a hybrid combination of series and parallel are also possible.
  • Fig. 16A shows a 4 x 4 array of equally sized and shaped mini-cells and each mini-cell having a corresponding full-periphery closed-loop rim diode.
  • this architecture may use N x N array of mini-cells and
  • mini-cell or isle array design may have an asymmetrical array of N x M mini-cells.
  • the mini-cells of a master cell may optionally have substantially equal areas although this is not required.
  • the semiconductor layers for the array of isles or mini-cells are electrically isolated from each other using partitioning trench isolation formed by a suitable scribing technique such as laser scribing or plasma scribing.
  • each mini-cell or isle semiconductor substrate is partitioned and isolated from its corresponding full-periphery closed- loop MIBS diode semiconductor substrate using trench isolation. All the trench isolation regions on the master cell may be formed during the same manufacturing process step, for example using a single laser- scribe process step during the cell fabrication process flow.
  • Figs. 16B and 16C are cross-sectional diagrams detailing MIBS rim or full- periphery diode solar cell embodiments of the back-contact/back-junction solar cell for one isle (or unit cell such as In in Fig. 16 A) on a shared continuous backplane 288 after completion of manufacturing processes to form a MIBS-enabled back-contact/back- junction isled master cell such as that shown in Fig. 16 A, including frontside passivation and ARC coating on the textured surface of the solar cell (and MIBS device) shown as passivation/ ARC coating layer 280 in the solar cell in the MIBS device.
  • the solar cell isle and MIBS structural details such as the patterned Ml and M2 metallization layers are not shown here.
  • Fig. 16B shows a MIBS implementation using a pn junction peripheral rim diode bypass switch. Trench-isolated MIBS rim pn junction diode region 282
  • MIBS rim pn junction diode region 282 may be a full peripheral rim diode, for example with a width in the range of about 200 to 600 microns (smaller or larger dimensions are also possible as described earlier). The MIBS rim diode and solar cell relative dimensions are not shown to scale. In one fabrication embodiment, Fig.
  • 16B shows a backplane-laminated (or backplane-attached) MIBS- enabled solar cell after completion of manufacturing processes for a MIBS-enabled back- contact/back-junction (IBC) solar cell comprising completion of back-contact/back-junction cell processing through patterned first- level metallization or Ml (for example made of screen printed or PVD aluminum or aluminum-silicon alloy or another suitable metal comprising nickel, etc.), backplane lamination, epitaxial silicon lift-off release and separation from a crystalline silicon reusable template (if using an epitaxial silicon lift-off process to form the substrate - this process not applicable when using a starting crystalline silicon wafer), formation of trench isolation regions (e.g., by pulsed laser scribing or cutting) to define the MIBS rim diode border, optional silicon etch, texture and post-texture clean, passivation & ARC deposition (e.g., by PECVD or a
  • the process used to form the p+ emitter regions (field emitter regions and/or heavily doped emitter contact regions) of the solar cell may also be used to form p+ junction doping for the MIBS pn junction formation.
  • the patterned Ml metal (not shown), for example made of aluminum or an aluminum alloy such as aluminum with some silicon addition, not only provides the contact metallization or the first-level metallization for the solar cell but also creates metallization contacts (to both the p+ region and the n-type substrate region through n+ doped contact windows) for the MIBS pn junction diode.
  • the n-doped silicon region of the MIBS pn junction diode is formed from the same n-type silicon substrate which also serves as the base region of the solar cell (e.g., from the n-type silicon wafer when using starting n-type crystalline silicon wafers without epitaxy, or from in-situ-doped n-type crystalline silicon layer formed by epitaxial deposition when using epitaxial silicon lift-off processing to form the solar cell and MIBS substrate) - the substrate bulk region doping may also be referred to as the background doping of the substrate.
  • the patterned Ml and M2 metallization structures complete the required monolithic solar cell and MIBS pn junction diode electrical interconnections and also ensure the MIBS diode terminals are properly interconnected to the respective solar cell base and emitter terminals to provide cell-level integrated shade management and continual solar cell protection against shading.
  • the sidewall edges and the top surface of the MIBS pn junction diode are also passivated using the same passivation layer(s) and processes used to passivate the sunny- side and edges of the solar cell, passivation/ ARC coating layer(s) 280.
  • 16A does not show some details of the solar cell and MIBS structure such as the patterned Ml and M2 metallization, rear side passivation layer, Ml contact holes, Ml- M2 via holes through the backplane, and the n+ doped contact windows for n-type substrate Ml connections in the MIBS device structures.
  • Fig. 16C shows a MIBS implementation using a peripheral Schottky rim diode bypass switch.
  • Isolated Schottky rim diode bypass switch region 286 isolated from isle In by corresponding isolation trench 274) comprises an n-doped region and an inner and outer n+ region and is used as a Schottky diode bypass switch.
  • Schottky rim diode bypass switch region 286 may be a full peripheral rim diode with a width in the range of 200 to 600 microns (this dimension may be chosen to be larger or smaller than this range).
  • Fig. 16C shows a backplane-laminated or backplane-attached MIBS-enabled solar cell after completion of manufacturing processes for the MIBS-enabled back-contact/back-junction isled master cell comprising completion of the back-contact/back-junction cell processing through a patterned first- level metallization or Ml (for example made of a suitable conductor which can serve as both an effective ohmic contact on heavily doped silicon as well as an effective Schottky barrier contact on lightly doped silicon, such as aluminum or aluminum-silicon alloy), backplane lamination, epitaxial silicon lift-off release and separation from a crystalline silicon reusable template when using an epitaxial lift off silicon substrate (this process not applicable or required when using starting crystalline silicon wafers instead of epitaxial lift off substrates), formation of the trench isolation (e.g., by pulsed laser scribing or cutting) to define MIBS rim Schottky diode border, optional silicon thinning etch,
  • Ml for example made of
  • the n-type silicon substrate also used as the base region of the solar cell (for instance formed through in-situ-doped epitaxial deposition when using epitaxial lift off processing, or from a starting n-type crystalline silicon wafer when not using epitaxial lift off processing) is also used as the n-type silicon substrate region for the MIBS Schottky diode.
  • the Ml metal (not shown), for example made of aluminum or a suitable aluminum alloy such as aluminum with some silicon addition, not only makes the Ml ohmic contact metallization for the solar cell (for both base region through n+ doped contact openings and emitter contact region through p+ doped contact openings of the solar cell), but also creates the metallization contacts for the MIBS Schottky diode (both the non-ohmic Schottky barrier contact on the lightly doped n-type silicon substrate region and the ohmic contact to n-type silicon through heavily doped n+ doped regions).
  • the lightly doped n-type silicon substrate region of the MIBS diode is from the same n-type substrate used for the solar cell and serving as its base region (e.g., the n-type substrate may be formed by in-situ-doped n-type epitaxial silicon deposition when using epitaxial silicon lift-off processing, or from a starting n-type crystalline silicon wafer when not using epitaxial silicon lift off processing).
  • the heavily doped n+ diffusion doping of the n-type silicon region for the MIBS Schottky diode ohmic contacts to the n-type silicon substrate may be formed at the same time and using the same process also used for producing the heavily doped n+ doped base contact regions for the solar cell (in preparation for the subsequent patterned Ml metallization).
  • the combination of patterned Ml and M2 metallization structures complete the solar cell and MIBS Schottky diode electrical interconnections and ensure the MIBS diode terminals are properly connected to the solar cell terminals to provide cell-level integrated shade management and solar cell protection. As can be seen Fig.
  • the sidewall edges and the top surface of the MIBS Schottky diode are also passivated using the same passivation and ARC layer(s) and process(es) used to form the passivation and ARC layer(s) on the sunny-side and edges of the solar cell - note passivation/ ARC coating layer(s) 280.
  • Fig. 16C does not show some structural details of the solar cell structure including but not limited to the patterned Ml and M2 metallization layers.
  • the monolithically isled solar cells, and optionally MIBS embodiments, disclosed herein employ trench isolation in conjunction with a shared backplane substrate to establish partitioning and electrical isolation between the semiconductor substrate regions (isles) and also optionally for the MIBS device and adjacent isles or solar cell region.
  • One method to create the trench isolation regions is pulsed (such as pulsed nanoseconds) laser scribing.
  • Pulsed laser scribing for trench isolation formation may use a pulsed nanoseconds (ns) laser source at a suitable wavelength (e.g., green, or infrared or another suitable wavelength to ablate the semiconductor layer with relatively good selectivity to cut through the semiconductor substrate layer with respect to the backplane material) commonly used and proven for scribing and cutting through silicon.
  • the laser source may have a flat-top (also known as top-hat) or a non-flat-top (e.g., Gaussian) laser beam profile.
  • a pulsed laser source wavelength which is highly absorptive in silicon but can partially or fully transmit through the backplane (hence, cut through the semiconductor layer without substantially removing the backplane material after the through-semiconductor layer laser cutting is complete and the beam reaches the backplane sheet).
  • a pulsed nanoseconds IR or green laser beam which may effectively cut through the silicon substrate layer and partially transmit through the backplane material (hence, removing little to negligible amount of backplane material during the trench isolation cut).
  • the pulsed laser beam diameter and other properties of the pulsed nanoseconds laser source may be chosen such that the isolation scribe width is in the range of a few microns up to 10's of microns as a width much larger than about 100 microns would be rather excessive and result in unnecessary waste of precious silicon substrate area and some reduction of the total-area efficiency of the solar cells and modules. Thus, it is beneficial to minimize the trench isolation areas as compared to the highly desirable solar cell area. In practice, pulsed nanoseconds laser cutting can produce trench isolation regions with width in the desirable range of about 20 microns up to about 60 microns.
  • a trench isolation width of 30 microns corresponds to an area ratio of 0.077% for the trench isolation area as a fraction of the cell area. This represents a rather negligible area compared to the solar cell area, in other words, this small ratio provides negligible waste of solar cell area and ensures negligible loss of total-area solar cell and module efficiency.
  • Pulsed nanoseconds (ns) laser scribing or cutting to form trench isolation may be performed immediately after the backplane lamination process when using starting crystalline silicon wafers to fabricate the solar cells (and in the case of solar cells using epitaxial silicon lift-off processing, after completion of the backplane lamination process and subsequent lift-off release of the laminated cell from the reusable template and after or before pulsed laser trimming of the solar cell) in a back-contact/back-junction solar cell fabrication process as described herein.
  • the trench isolation scribing or cutting process may optionally use the same pulsed laser tool and source used for pre-release scribing of the epitaxial silicon layer to define the lift-off release boundary and/or used for post-release trimming of the laminated solar cell.
  • no additional laser process tool may be needed in order to form the trench isolation regions.
  • Pulsed nanoseconds (ns) laser scribing to form trench isolation may also be used to partition the isles and define the fully isolated MIBS rim diode region outside an isolated solar cell island surrounded by and defined by the rim.
  • the pulsed ns laser scribing process may form other designs of the MIBS diode, such as in a multiple MIBS diode island design as well as and many other possible MIBS pattern designs.
  • Pulsed laser scribing may be used to cut through the thin (such as sub-200 microns and more particularly sub- 100 microns) silicon substrate layer (from the sunny side) and substantially stop on the backplane material sheet.
  • a simple real-time in-situ laser scribe process end-pointing such as using reflectance monitoring, may be used for process control and endpointing to minimize trenching or material removal in the backplane sheet while enabling complete through-semiconductor- layer laser cut.
  • the sidewalls of the solar cell and the MIBS rim diode regions may be subsequently wet etched (for instance, as part of the solar cell sunny-side wet etch / texture process), post-texture cleaned, and passivated (by deposition of the passivation and ARC layer) during the remaining solar cell fabrication process steps.
  • the MIBS diode may be a pn junction diode used as the MIBS bypass device or shade management switch.
  • a pn junction MIBS diode fabrication process to produce a MIBS-enabled solar cell of may have the following, among others, attributes and benefits:
  • MIBS for example a back-junction/back-contact crystalline silicon solar cell fabrication using either crystalline silicon starting wafers or epitaxial silicon and porous silicon/lift-off processing in conjunction with a reusable crystalline silicon template, and an electrically insulating backplane.
  • MIBS for example a back-junction/back-contact crystalline silicon solar cell fabrication using either crystalline silicon starting wafers or epitaxial silicon and porous silicon/lift-off processing in conjunction with a reusable crystalline silicon template, and an electrically insulating backplane.
  • a back-contact/back-junction epitaxial silicon lift-off cell process following the completion of the on-template cell processing involving most of the back-contact, back-junction cell process steps, the following processes may be performed (provided as an example of various possible process flows): (i) backplane lamination to the solar cell backside; (ii) pre-release trench scribe (for example using a pulsed nanoseconds laser scribe tool or alternatively using another scribing tool such as plasma scribe) of the thin epitaxial silicon substrate to define the epitaxial silicon lift-off release boundary; (iii) mechanical lift-off release of the backplane-supported cell and its detachment from the reusable crystalline silicon template; (iv) laser trim (for example using a pulsed nanoseconds laser source) of the backplane-laminated cell for precision trim and to establish the final desired dimensions for the solar cell in conjunction with its associated MIBS; (v) pulsed nanoseconds laser scribing (or plasma scribing
  • the process flow is fairly similar to the flow described above, except that there is no reusable template, porous silicon, epitaxial silicon, or release process.
  • the trench isolation scribing process and tool may be essentially the same as the process and tool used for pre-release trench scribe and/or the post-release precision trim of the backplane-laminated solar cell and MIBS substrate.
  • the laser scribed trench isolation process may be performed (for example using a pulsed nanoseconds laser source) to create complete through-semiconductor trench(es) within the semiconductor layer through the entire thickness of the crystalline silicon layer and substantially stopping at the backplane - thus forming the electrically isolated n-type silicon rim region for the MIBS diode and the n- type silicon island region for solar cell assuming an n-type base and p+ emitter solar cell (a common doping type for a back-contact/back-junction IBC solar cell).
  • an M2 cell metallization design which results in sufficiently low or negligible ohmic losses should be used due to the current flow on lateral M2 connectors between the adjacent series-connected columns.
  • Lateral M2 jumpers or connectors (which may be formed in conjunction with the patterned M2 layer) are used to interconnect the adjacent columns of icell in electrical series.
  • all-series-connected icell or master cell 300 has an N x N array (N rows and N columns, shown as 4 x 4 in this representative example) of electrical series-connected isles In through I 44 (isles defined by outer cell boundary 302 and electrical isolation trenches 304) from emitter busbar 308 to base busbar 310, each isle in a column electrically connected by M2 series connections 306 (simply shown as arrows) and each column in series electrically connected by lateral M2 jumpers 312.
  • a lateral M2 jumper half-segment has a length of H (with H being the side dimension of each square-shaped isle) and width of W.
  • M2 metallization pattern is not shown in Fig. 17; however an M2 unit cell such as that shown in Fig. 13 may correspond to each isle (In through I 44 ).
  • N and k j Values N ⁇ 3 1 N-4 j N-5
  • k j 0.0025 1,809 cm j 0.644 cm 1 0.281 cm k j - 0.0050 0.905 cm 1 0.322 cm 1 0.141 cm k j - 0.0100 j 0.452 cm j 0.161 m 1 0.070 cm
  • the total lateral M2 jumper ohmic power loss is reduced for higher values of N and/or lower resistivity metal
  • the M2 jumper width may be limited to less than 1 cm for M2 metal thickness of either 3 ⁇ or 5 ⁇ (or any width approximately in this range) while maintaining the maximum total lateral M2 jumper power loss to no more than about 0.50% relative ohmic losses - corresponding to approximately 0.1% absolute cell efficiency loss due to the M2 jumpers;
  • isles may be electrically connected in an all- series, an all-parallel, or a hybrid series-parallel M2 interconnection design.
  • the M2 interconnection pattern should maintain the benefits of substantially reduced R.I 2 ohmic losses in the cell, module, and system due to the scaled up the voltage and scaled down the current of the master cell.
  • the isle designs are described generally as square shaped, the isles may be formed in any geometric shape in accordance with the disclosed subject matter. And in most instances, it is desirable to eliminate area-related current mismatches between the series-connected isles - in other words, to design and pattern the array of isles symmetrically to maintain equivalent area between isles or subgroups of isles connected in parallel.
  • the M2 interconnection designs disclosed herein provide relatively optimum-range current-voltage parametrics for integration of inexpensive, embedded, high-performance distributed MPPT power optimizer and/or shade management electronics components assuming a master cell maximum-power voltage (V mp ) in the range of approximately ⁇ 5 V to 10 V and a master cell maximum-power current (Imp) in the range of approximately -0.5 A to 1 A.
  • V mp master cell maximum-power voltage
  • Imp master cell maximum-power current
  • the M2 interconnections provided herein are capable of supporting various installed PV arrays, such as 600 VDC and 1 ,000 VDC PV systems for maximum system-level efficiency in residential and commercial rooftop as well as ground-mount utility-scale applications.
  • Figs. 18A, 18B, and 18C are schematic diagrams for a full square master cell or icell showing an all-series (1x16) master cell configuration ⁇ x 4 array of isles) referred to herein as a lxl6S design (Fig.
  • all-series master cell or icell configuration lxl6S 320 has an 4x4 array of electrical series-connected isles In through I 44 from emitter busbar 322 to base busbar 324, each isle in a column electrically connected by M2 series connections 328 and each column in series electrically connected by lateral M2 jumpers 326.
  • hybrid parallel-series master cell configuration 2x8HPS 340 has a 4 x 4 array of electrical series and parallel connected isles In through I 44 from emitter busbar 342 to base busbar 344, adjacent isles in a column connected in parallel by M2 parallel connections 350 and each isle in a column electrically connected by M2 series connections 348 and combined parallel connected adjacent isles electrically connected in series by lateral M2 jumpers 346.
  • the 2X8HPS design of Fig. 18B may be particularly suitable for a master cell having a thin silicon absorber layer (for example having a thickness in the range of about a few microns up to 100 microns).
  • hybrid parallel-series master cell configuration 8x8HPS 352 has an 8x8 array of electrical series and parallel connected isles In through Iss from emitter busbar 354 to base busbar 356, adjacent isles in a column connected in parallel by M2 parallel connections and isles in a column electrically connected by M2 series connections and combined parallel connected adjacent isles electrically connected in series by lateral M2 jumper 358.
  • the 8X8HPS design of Fig. 18C may be particularly suitable for a master cell having a somewhat thicker silicon absorber layer (for example having a silicon thickness in the range of about 50 to 150 microns).
  • Figs. 19 A, 19B, and 19C are diagrams showing example placement/position of a relatively small shade management bypass switch (e.g., either a pn junction diode or a Schottky barrier diode) on the M2 interconnection designs of the master cells shown in Figs. 18 A, 18B, and 18C, respectively.
  • a relatively small shade management bypass switch e.g., either a pn junction diode or a Schottky barrier diode
  • all-series master cell configuration lxl6S 360 has a 4 x 4 array of electrical series-connected isles In through I 44 from emitter busbar 362 to base busbar 364, each isle in a column electrically connected by M2 series connections 368 and each column in series electrically connected by lateral M2 jumpers 366.
  • Lateral M2 jumper 370 has been offset from the master cell peripheral edge for direct placement and connection of a relatively small-package bypass switch 376 to emitter busbar 362 and base busbar 364.
  • Busbar extensions 374 connect emitter busbar 362 and base busbar 364 to bypass switch 376.
  • hybrid parallel-series master cell configuration 2x8HPS 380 has a 4 x 4 array of electrical series and parallel connected isles In through I 44 from emitter busbar 382 to base busbar 384, adjacent isles in a column connected in parallel by M2 parallel connections 390 and each isle in a column electrically connected by M2 series connections 388 and combined parallel connected adjacent isles electrically connected in series by lateral M2 jumpers 386.
  • Bypass switch 392 is positioned between and directly connected to emitter busbar 382 and base busbar 384.
  • hybrid parallel-series master cell configuration 8x8HPS 394 has an 8x8 array of electrical series and parallel connected isles In through Iss from emitter busbar 395 to base busbar 396, adjacent isles in a column connected in parallel by M2 parallel connections and isles in a column electrically connected by M2 series connections and combined parallel connected adjacent isles electrically connected in series by lateral M2 jumper 397.
  • Bypass switch 398 is positioned between and directly connected to emitter busbar 395 and base busbar 396.
  • a master cell may be formed as a pseudo-square solar cell - as shown in Fig. 20.
  • Fig. 20 is a schematic diagram showing a top view of a pseudo-square shaped master cell substrate fabricated from a cylindrical ingot (shown by cylindrical ingot periphery).
  • isles within a pseudo-square shaped master cell may be individually designed in various shapes and configurations.
  • Fig. 20 is a diagram showing a top view of a pseudo-square shaped master cell substrate 400 fabricated from a cylindrical ingot (shown by cylindrical ingot periphery 402). Excluded corners 404 have area a' per corner and have been removed/excluded from the pseudo-square master cell substrate design in order to minimize the ingot waste while providing a nearly (but not full) square wafer for solar cell fabrication.
  • L 156mm
  • standard pseudo- square wafers have a cell area of 239.36 cm 2 as compared to standard 156mm x 156mm square wafers having cell area of 243.36 cm 2 - resulting in approximately 1.64% less area (4/243.36).
  • Fig. 21 is a diagram of a hybrid parallel-series pseudo-square master cell configuration 2x8HPS 420 having a 4 x 4 array of electrical series and parallel connected isles In through I44 (isles defined by isolation trenches 424) from emitter busbar to base busbar similar to the cell shown in Fig. 18B (emitter busbar, base busbar, and lateral M2 jumpers not shown in Fig. 21).
  • pseudo-square master cell 420 has a side length L (for instance, 156mm for a 156 mm x 156 mm pseudo-square icell) and is missing corners 422 each having area a'.
  • master cell 420 is horizontally and vertically symmetrical (resulting in eight pairs of parallel connected isles) and the dimensional expressions following are for one quadrant (for example In, I21, 112, and I22).
  • Fig. 22 is a diagram of an all-series pseudo-square master cell configuration lxl 6S 430 having a 4 x 4 array of electrical series connected isles In through I44 (isles defined by isolation trenches 434) from emitter busbar to base busbar similar to the cell shown in Fig. 18A (emitter busbar, base busbar, and lateral M2 jumpers not shown in Fig. 22).
  • pseudo-square master cell 420 has a side length L (for example 156 mm for a 156 mm 156 mm pseudo square solar cell) and is missing corners 422 each having area a'.
  • isles in the second and third columns (I12, 122, 132, 142, Ii3, 123 , 133 , 143) are rectangular, each having an area (L/4).W2. Isles in the first and fourth columns are non-rectangular: isles I21, 131, 124, and I34 are trapezoidal; and corner isles In, I41, Ii4, and I44 are polygons.
  • the three vertical scribe lines (isolation trenches) and the central horizontal scribe line (isolation trench) are straight lines running from edge to edge of the master cell.
  • master cell 430 is horizontally and vertically symmetrical (resulting in 16 connected isles each having an equivalent area and four symmetrical quadrants).
  • the dimensional expressions following are for one quadrant (for example In, I21, 112, and I22).
  • Wi.(L/4) + [Wi 2 / tan(0)]/2 - a 14.96 cm2
  • Wl .L + 2[Wi 2 / tan(0)] 63.84 cm 2
  • Wi.(L/4) - [Wi 2 / tan(0)]/2 14.96 cm2
  • Wl .L - 2[Wi 2 / tan(0)] 59.84 cm 2 .
  • each isle area 14.96 cm 2
  • Monolithically isled master cell interconnections in PV modules may be connected in electrical series, parallel, or hybrid parallel-series arrangements in PV modules. These interconnections may be performed using Monolithic Module embodiments described earlier (for example when a plurality of icells are attached to a continuous backplane layer and all the icell to icell electrical interconnections are performed using the patterned M2 layer). Master cell
  • interconnection design choice in the module may be based on the master cell maximum-power-point (MPP) current and voltage (Imp and V mp ), the number of master cells in the module, as well as the desired MPP current and voltage of the module.
  • MPP master cell maximum-power-point
  • Imp and V mp the number of master cells in the module
  • One exemplary module configuration embodiment for master cell interconnects (assuming N is at least 3) in a module of 6x10 (or more) master cells is a hybrid parallel- series configuration.
  • master cell interconnections may be optimized using a hybrid parallel-series design to provide the desired maximum module MPP current or the desired maximum module MPP current.
  • an all-parallel configuration is possible, in some instances an all-parallel configuration may result in an excessively large module current resulting in significant ohmic losses.
  • an all-series configuration may result in an excessively high (for example larger than several hundred volts) module voltage (module V mp ) which may cause safety concerns and/or may demand higher wiring costs due to the dielectric insulation requirements.
  • Figs. 23A and 23B are diagrams showing a master cell or icell overview highlighting the position of the emitter and base busbars as dependent on the number of isles (odd or even number of isles), as well as M2 interconnection design.
  • master cell 452 N is an odd integer and in master cell 462 N is an even integer.
  • Fig. 23A and 23B are diagrams showing a master cell or icell overview highlighting the position of the emitter and base busbars as dependent on the number of isles (odd or even number of isles), as well as M2 interconnection design.
  • master cell 452 when N is an odd integer and the isles (or subgroup of parallel- connected isles) are connected in electrical series, the master cell emitter and base busbars are positioned opposite the cell diagonal in two opposite quadrants - shown as emitter busbar 454 and base busbar 456 in Fig. 23A (for example see the master cells shown in Figs. 15A and 15B).
  • master cell 462 N is an even integer and the isles (or subgroup of parallel-connected isles) are connected in electrical series
  • the master cell emitter and base busbars are positioned on the two opposite corners on the same side of the square cell - shown as emitter busbar 464 and base busbar 466 in Fig. 23B (for example see the master cells shown in Fig. 14A).
  • Figs. 24 through 27 are diagrams depicting various 60 cell module connection designs for master cells designs having both an even and odd number of series connected isles (or subgroups of parallel-connected isles), such as those shown in of Figs. 23 A (N is odd) and 23B (N is even).
  • the diagrams of Figs. 24 through 27 are top module views (showing the frontside of the master cell) showing emitter busbars and base busbars for each master cell although the busbars are actually positioned on the backsides of the master cells. In other words, the emitter and base busbars and module interconnections are shown as visible through the master cell frontside to emphasize various cell-to-cell interconnection designs.
  • Each of these representative modules may be made as a monolithic module by attaching or laminating a plurality of icells (e.g., 60 icells in a 6 x 10 arrangement as shown in these embodiments) to a continuous backplane sheet after completion of the solar cell backside processing through the patterned Ml layer and then performing the remaining post-backplane-lamination back-end solar cell processing on the continuous multi-cell backplane substrate through completion of the patterned M2 layer on the large continuous backplane sheet comprising the plurality of icells.
  • This approach will result in interconnections of the icells to one another according to a desired electrical interconnection arrangement (all series or hybrid parallel-series) using the monolithic patterned M2 metallization layer.
  • each of these representative modules may also be made without the monolithic module embodiments disclosed herein by conventional tabbing and/or stringing and/or soldering of the solar cells to each other for module assembly.
  • Fig. 24 is an example of a module interconnection design (which is made using the patterned M2 layer if using monolithic module embodiments disclosed herein) for master cells or icells with emitter and base busbars positioned on opposite diagonal corners of the master cell (i.e., N is an odd number) and all icells connected in electrical series (all-series).
  • Fig. 26 is an example of a module interconnection design (which is made using the patterned M2 layer if using monolithic module embodiments disclosed herein) for master cells with emitter and base busbars positioned on corners on the same side of the master cell (N is an even number) and the cells connected in electrical hybrid parallel- series.
  • N an even number
  • each master cell in a row of 10 master cells is connected in series and the 6 rows of 10 master cells are connected in parallel.
  • module voltage 10 x master cell voltage.
  • Fig. 27 is an alternative example of a module interconnection design (which is made using the patterned M2 layer if using monolithic module embodiments disclosed herein) for master cells with emitter and base busbars positioned on corners on the same side of the master cell (N is even number) and the cells connected in electrical hybrid parallel-series.
  • each master cell in a column of 6 master cells is connected in series and the 10 columns of 6 master cells are connected in parallel.
  • module voltage 6 x master cell voltage.
  • the monolithically isled architecture disclosed herein may integrate an embedded module-level or a cell-level DC-to-DC (or DC-to-AC) power optimizer which may be mounted directly on the master cell backplane prior to final module lamination or embedded within the module laminate.
  • the MPPT Power optimizer may be a high-conversion-efficiency (for example greater than 97% efficiency) monolithic or hybrid chip (possibly including some discrete components comprising at least an inductor and a capacitor) which converts cell DC output to either DC or AC output at a specified voltage or constant current (range).
  • a cell-level MPPT power optimizer chip may be used to produce AC cells while performing maximum- power-point tracking (MPPT), by converting master cell DC voltage and current (V mp and Imp) to AC voltage and current.
  • MPPT maximum- power-point tracking
  • the cell-level embedded MPPT may be set to produce a pre-specified fixed output current in each master cell under all illumination conditions while performing the MPPT power optimization function. This may ensure that all the master cells connected in series are current-matched.
  • the cell-level embedded MPPT may be set to produce a pre- specified fixed output current in each master cell to provide a pre-specified parallel-string voltage under all illumination conditions while performing the MPPT power optimization function (and providing a pre-specified string voltage). This may ensure that all master cells or icells connected in series in each series string are current-matched while the parallel strings are also voltage matched.
  • Figs. 28A and 28B are diagrams showing some representative examples of module interconnections embodiments for a 600 VDC PV system.
  • Fig. 28B shows module
  • Figs. 29 A and 29B are schematic diagrams showing module interconnections for a 1000 VDC PV system.
  • Vos and V mp are increased in 2x8HPS design for a 1000 VDV PV system as compared to a 2x8HPS design for a 600 VDV PV system or a lxl 6S design for 600 or 1000 VDV PV systems.
  • a 2x8 Hybrid Parallel-Series (2x8HPS) interconnection design may be chosen for the following advantages:
  • a 1000 VDC PV system may have higher system-level efficiency and lower BOS costs as compared to a 600 VDC system. (It has been noted, due to higher efficiency and lower BOS cost, a higher string voltage (1,000 VDC vs. 600 VDC) may provide an economic value of approximately $0.10/W for an installed PV system).
  • the module voltages can be set (e.g., lowered compared to an all-series module arrangement) by interconnections of the icells within the module according to a hybrid parallel- series configuration.
  • the benefits of the innovative aspects disclosed herein include but are not limited to: (i) reduced solar cell manufacturing (fab) process equipment and facilities capital expenditures (CAPEX); (ii) substantially reduced hazardous waste byproducts in the solar cell fab; (iii) reduced solar cell microcracks and/or breakage (for instance, due to elimination of the need for copper plating and its associated handling, sealing, and contacting requirements) and enhanced overall manufacturing yield; (iv) improved projected long-term PV module field reliability; (v) reduced bow and mechanical stress for backplane-laminated solar cells due to elimination of the need for thick (typically lO's of microns for IBC solar cells) electroplated copper on the backside.
  • fab process equipment and facilities capital expenditures
  • CAEX substantially reduced hazardous waste byproducts in the solar cell fab
  • reduced solar cell microcracks and/or breakage for instance, due to elimination of the need for copper plating and its associated handling, sealing, and contacting requirements
  • enhanced overall manufacturing yield for instance, due to elimination of the need for
  • the disclosed subject matter provides monolithically isled master cells (icells) which may provide any combination of the following advantages: enhanced flexibility and crack mitigation; reduced cell bow and improved planarity; scaled-up voltage and scaled-down current, resulting in reduced RI 2 ohmic losses; a reduction in cell metallization thickness (as much as lOx) may allow for the elimination of copper plating if desired which may reduce cell metallization cost (for example ⁇ 5 ⁇ Al); the elimination of thick metallization, such as thick-copper, reduces stress effects (and resulting cracks) during module lamination; distributed cell parametrics at test and sort; reduced current allows for an inexpensive shade -management switch; allows for the use of an inexpensive, high-efficiency (>98%) MPPT DC-DC buck converter; and a fully plating-free solar cell.
  • icells monolithically isled master cells
  • the present application relates to cost-effective, high-efficiency solar cells and related modules, their device structure and methods for manufacture. More specifically, the disclosed subject matter relates to solar cell structures and manufacturing methods using wire-sawn, standard thickness (e.g., 125 mm x 125 mm or 156 mm x 156 mm or larger-area silicon wafers with starting thicknesses in the range of about 120 to about 250 microns) starting crystalline silicon wafers which may be thinned in conjunction with a supporting backplane (such as a flexible polymeric backplane which is permanently attached to the thin silicon cell absorber).
  • the semiconductor absorber layer may be segmented using a monolithic fabrication process to provide multiples of the standard operating voltage of standard monolithic silicon cells while scaling down the solar cell current for a given solar cell power as described above.
  • the disclosed subject matter addresses limitations of known methods relating to the use of bulk wafers and thin- film solar cell fabrication challenges and provides the combination of low-cost and high efficiency inter-digitated back contact (IBC) solar cells made using starting crystalline silicon wafers.
  • IBC inter-digitated back contact
  • n-type wafers may be chosen, for example with starting minority carrier lifetimes on the order of about >100 or more and manufactured using Czochralski (CZ) ingot growth, continuous or quasi-continuous CZ growth, or other methods which address the inherent n-type doping concentration gradient across n-type silicon ingots.
  • CZ Czochralski
  • quasi-monocrystalline cast n-type silicon ingots or even multicrystalline silicon material may be chosen dependent on material quality and other process integration requirements. It is to be noted that some of the subsequent processes, such as texturing, require suitable adjustment depending on the starting material choice, for instance alkaline texture for monocrystalline compared to acidic texture for multicrystalline material (although both acidic and alkaline textures may be used for any type of starting crystalline silicon material).
  • n-type (typically phosphorus doped) starting crystalline wafers are provided for descriptive purposes, the fundamental concepts presented herein adhere to and may be applied by one skilled in the art to p-type silicon wafers. It is further to be noted that the fundamental concepts presented apply to bulk wire-sawn wafer-based absorber cells but may also be transferred to absorber cells generated using kerfless techniques such as those using porous silicon on a reusable template as a release layer system followed by epitaxial or otherwise chemical vapor deposited film growth with subsequent release with subsequent reuse of the template.
  • kerfless wafer methods such as those using high-dose hydrogen ion (proton) implantation and subsequent exfoliation or laser splitting or mechanical stress induced exfoliation of thin silicon substrates from thicker reusable starting substrates.
  • Various solar cell processing steps may be applied to the wafers, particularly back side processing steps, including the patterned formation of base contact and emitter diffusions (the formation of emitter and base contact regions) and the application of a patterned thin first metal layer (Ml).
  • base contact and emitter diffusions may be it in a selective or non-selective emitter structure, may be formed, for instance, using laser ablation of doped dielectrics and subsequent drive-in.
  • These patterned regions, formed by local removal of doped dielectric layers may also be generated by the application of etching paste by means of printing such as screen printing.
  • patterned regions of different dopant level or polarity may also be created by the local application of dopant pastes, with subsequent thermal drive-in steps. Combinations of such above patterning methods are also readily deducible.
  • a low cost backplane such as a low-cost prepreg or polymeric material having an expansion coefficient (CTE) relatively matched to the solar cell absorber material (for example crystalline silicon) is laminated to the backside of the processed wafer.
  • the crystalline silicon wafer may then be thinned (for example using either a chemical wet etch or alternatively using a dry etch process) to the desired absorber thickness range providing an optimal balance between value-add optical absorption and minority carrier lifetime.
  • Providing a thin silicon e.g.
  • the silicon substrate attached to a backplane may be segmented by forming trench isolation regions, for example using pulsed laser cuts to electrically isolate individual silicon islands or segments (isles, sub-cells, or mini-cells) as described in detail above, thus enabling monolithic solar cell fabrication.
  • Fig. 30 illustrates such a cell structure.
  • Fig. 30 is a diagram of solar cell 500 having a 4 x 4 array of sub-cells 502 In through I 44 defined and electrically isolated by trenches 504 and which is reinforced by contiguous monolithic backplane sheet 506 (for example an electrically insulating, low-cost, flexible material such as a prepreg sheet or any suitable polymeric sheet).
  • the isles are physically segmented and therefore electrically segmentable sub-cell active absorber units which may be referred to as isles or sub-cells - in other words the group of monolithically integrated sub-cellsisles form the main/master cell having a common backplane used for all the sub-cells.
  • the segmented sub-cells may be electrically interconnected in parallel, in series or in a combination thereof, depending on various considerations including the desired master cell (also referred to as icell) current and voltage values.
  • the monolithic master cell itself, held together by the backplane to e.g. a 156 mm x 156 mm square or pseudo-square form factor can provide operating voltages that are scaled-up a multiple of the standard voltage range a traditional silicon solar cell may generate, for instance N-times 0.6-0.7 V.
  • metal e.g., copper
  • these scaled-up voltage scaled-down current solar cells also allow for improved economical novel solutions for module power harvesting and energy yield optimization. This is owed in part to the fact that the individual cell operating current and voltage may be selected to be in the same ranges as the cost optimized current and voltage values for low cost commercial individual switches.
  • the active silicon absorber layer may be generated from a layer of in-situ-doped (typically doped with phosphorus for n-type silicon) crystalline silicon which is deposited using a chemical vapor deposition (CVD) process such as epitaxy on a reusable mono- or multi- or quasi-mono- crystalline template with a sacrificial layer or layer structure of, for instance, porous silicon, which is then subsequently partially processed on one side, for example to form patterned base contacts and emitter junction structures and a patterned first metal layer (such as by screen printing of a suitable metal paste such as aluminum-containing paste, or by PVD and laser ablation patterning), which is then subsequently laminated to a backplane, exfoliated by a release process and then finished off with the same isle segmenting (trench isolation) cuts, frontside texturing, passivation, backside via drill and a patterned second layer metal.
  • CVD chemical vapor deposition
  • Fig. 31 is a graph showing that the attainable V oc limit increases with reduced cell thickness
  • Auger recombination is dominant at a background doping concentration of around Nd > lxlO 17 cm "3 in high- quality crystalline Si the effective lifetime (t e ff) depends on bulk lifetime tb, effective surface recombination velocity Seff, and the silicon absorber thickness (Wsi).
  • Seff Seff ⁇ Dh/4W where Dh is the diffusivity of holes in Si
  • Wsi silicon absorber thickness
  • Leff 15. Wsi . Therefore, for an approximately 40 ⁇ thick Si absorber, an Leff > 600 ⁇ is desirable; for a hole diffusivity of Dh » 12 cm 2 /s, this condition amounts to a requirement of effective minority carrier lifetime teff > 300 ⁇ .
  • Fig. 32 is a graph illustrating the silicon absorber effective minority carrier lifetime requirement (x-axis) versus final cell absorber thickness requirements (y-axis) for high-efficiency solar cells, showing the requirements for high performance of V oc and Jsc. It can be seen that the high V oc requirement places more stringent demand on the maximum allowable silicon thickness and/or minimum required minority carrier lifetime (as compared to the high J sc requirement).
  • the post-etch and texture processes thin silicon thickness depicted show the thickness and lifetime requirements based on certain J sc and Voc design rules (for example, the effective minority carrier diffusion length in the absorber being at least ⁇ 6x the absorber thickness to meet the high J sc requirement and ⁇ 15x the absorber thickness to meet the high Voc requirement).
  • the starting material for the thin-semiconductor-absorber solar cell structures may be pseudo-square or full-square, n-type monocast (also called quasi-mono or cast mono) silicon or n-type CZ silicon wafers (for instance produced by wire saw from CZ-grown mono-crystalline ingots or cast crystalline bricks) or depending on the material quality also multicrystalline silicon or upgraded metallurgical grade silicon.
  • n-type monocast also called quasi-mono or cast mono
  • CZ silicon wafers for instance produced by wire saw from CZ-grown mono-crystalline ingots or cast crystalline bricks
  • CZ silicon is used growing methods that enable a tighter distribution of dopant concentration and resistivity, such as using a continuous CZ (CCZ) or quasi-continuous CZ growth of silicon ingots, may be selected.
  • Wafer size may be at least 156 mm x 156 mm or larger and the starting average wafer thickness may be in the range of approximately 80 ⁇ to 250 ⁇ . Thinner and/or lower cost wafers may be utilized as long as manufacturing yield is not compromised by reduced mechanical yield due to enhanced wafer breakage during and after cell processing. And wafer bulk minority carrier lifetime may be at least 100 and in some instances several hundreds of - carrier lifetimes obtainable using inexpensive n-type CZ wafers.
  • the solar cell fabrication process may be started by single-sided in-line or batch immersion Saw Damage Removal (SDR), which is a wet etch process, optionally followed by a chemical polishing step to smooth out surface asperities.
  • SDR Saw Damage Removal
  • Such polishing steps may be performed single sided or double sided, for instance using chilled or room temperature mixtures containing hydrofluoric acid (HF) and nitric acid (HNO3) or alternatively using alkaline etch processes such as hot potassium hydroxide at
  • etches may be followed up by a metal removal etch such as with HC1, HF or HC1 / HF combinations and then completed with an HF containing clean to remove the native oxide and to leave the surface hydrophobic and hydrogen
  • a large part of the solar cell backside processing may be performed, namely the patterned formation of emitter and base contact diffusions, for example using a combination of dielectric deposition steps such as doped glass depositions using atmospheric pressure chemical vapor deposition (APCVD) and/or plasma-enhanced chemical-vapor deposition (PECVD), subsequent damage-free or low-damage laser patterning, for example using pulsed nanosecond, picosecond or femtosecond laser ablation patterning and thermal (e.g., batch tube or in-line furnace) drive-in for emitter junction (and doped base and emitter contact diffusion regions, as required) formation - in other words, generally the formation of emitter and base contact regions.
  • APCVD atmospheric pressure chemical vapor deposition
  • PECVD plasma-enhanced chemical-vapor deposition
  • subsequent damage-free or low-damage laser patterning for example using pulsed nanosecond, picosecond or femtosecond laser ablation patterning and thermal (e.g., batch tube or in-line
  • Laser beams for such processes may be homogenized to a spatial top hat profile for best uniformity or be Gaussian or have intermediate intensity distribution shapes.
  • Backside dielectric depositions may consist of doped or undoped silicon-oxide glasses such as boron-silicate glass (BSG), phosphorus-silicate glass (PSG) or undoped-silicate glass (USG) or of other dielectrics such as aluminum oxide or silicon nitride, doped or undoped, or a combination thereof.
  • a patterned first metal layer may be applied to the backside of the cell, for example a metal consisting of an aluminum or aluminum containing alloy (such as a screen-printable paste or inkjet-printing ink comprising aluminum-silicon) paste.
  • the first metal layer may be annealed particularly if it consists of a screen, ink jet or otherwise printed paste.
  • PVD physical vapor deposition
  • metallic materials such as aluminum or aluminum-silicon alloy
  • the emitter and base structure as well as the patterned first-level relatively thin metal layer may be formed and patterned as a busbar-less interdigitated back contact (IBC) base and emitter metallization (Metal- 1 or Ml metal layer) scheme.
  • IBC interdigitated back contact
  • Ml metal layer Metal- 1 or Ml metal layer
  • a flexible thin backplane (such as a suitable prepreg or polymeric material in the thickness range of about 50 ⁇ to 200 ⁇ ) may be laminated to the IBC Ml metal side.
  • the backplane sheet may be substantially the same size and shape as the wafer (or slightly larger if desired for cell edge
  • the backplane serves several important functions including as a permanent support to provide high yield thin silicon cell manufacturing and support the
  • the backplane supported silicon wafer may then be thinned down to an optimal thickness (for example in the range of approximately 80 ⁇ to as thin as a few microns depending on the specific application for the resulting solar cell) using a wet (such as with hot KOH or TMAH or with mixtures containing HF and FfNCb) or dry (plasma or reactive ion etch RIE) silicon etching process.
  • a wet such as with hot KOH or TMAH or with mixtures containing HF and FfNCb
  • dry (plasma or reactive ion etch RIE) silicon etching process Alternatively, abrasive processes such as grinding or lapping or chemical-mechanical polishing (CMP) may be used to reduce the silicon thickness.
  • CMP chemical-mechanical polishing
  • Other methods such as laser splitting or MeV-range hydrogen ion implantation followed by thin silicon cleavage / exfoliation may be used and the separated substrate may be reused to make additional solar cells depending on the starting wafer thickness.
  • the iCell (isled solar cell) structure may then be formed through pulsed ns or ps (or fs) laser ablation, ultrasonic drilling, or mechanical sawing of the silicon wafer to form silicon isolation trenches and create sub-cells or isles (all supported by the common backplane). Cutting or scribing processes may be tuned such that the trench goes all the way through silicon to the backplane, or that the trench ends with a thin layer of silicon still remaining which is then removed during a subsequent final wet etch and/or wet texturing process (which may also remove sidewall damage caused by the cutting process).
  • remaining cell process steps may be carried out including, for example, the aforementioned sunnyside texture (for improved light trapping), followed by post-texture cleaning.
  • front side passivation and anti-reflective coating (ARC) layer deposition may be performed (for example by PECVD followed by drilling vias into the backplane to access the buried Ml layer) followed by the backside final patterned solar cell metallization (second level metallization: Metal-2 or M2) process for isle/subcell interconnection.
  • ARC anti-reflective coating
  • M2 deposition may be performed as a patterning process (for instance, PVD with in-situ shadow masking) or as a blanket process with subsequent patterning (for instance, using blanket PVD of aluminum with a suitable capping layer such as an optional nickel or nickel-vanadium, which may further comprise an optional top cap of tin (Sn) or other solderable surface material, and a subsequent pulsed laser ablation to pattern the M2 metal).
  • a patterning process for instance, PVD with in-situ shadow masking
  • a blanket process with subsequent patterning for instance, using blanket PVD of aluminum with a suitable capping layer such as an optional nickel or nickel-vanadium, which may further comprise an optional top cap of tin (Sn) or other solderable surface material, and a subsequent pulsed laser ablation to pattern the M2 metal.
  • GaAs gallium arsenide
  • Ge germanium
  • Sii- x Ge x silicon-germanium buffer layer between the Si and the GaAs.
  • inventive concepts disclosed herein may be extended and readily adopted to other cell designs, such as non-IBC back-contact cells, or front contact cells, and may be especially applicable as a technological simplification choice when integrating GaAs into the Si process.
  • the structure of Figs. 5D and 5E is an interdigitated back-contact/back-junction crystalline semiconductor solar cell comprising a thin (for example having a thickness sub- 100 ⁇ in the range of a few microns up to approximately 100 microns) crystalline silicon layer formed by optionally etching back a thicker CZ or monocast (quasi-mono) silicon layer using wet or dry etching or by abrasive thickness reduction such as grinding or lapping (or alternatively using a starting thin sub- 130 ⁇ wafer, without a need for dedicated silicon thinning etch back process).
  • a thin for example having a thickness sub- 100 ⁇ in the range of a few microns up to approximately 100 microns
  • crystalline silicon layer formed by optionally etching back a thicker CZ or monocast (quasi-mono) silicon layer using wet or dry etching or by abrasive thickness reduction such as grinding or lapping (or alternatively using a starting thin sub- 130 ⁇
  • thinning/etching back the silicon after backplane lamination may not be required in some instances if a wafer with suitably high lifetime and/or sufficiently reduced starting thickness is used.
  • Such a structure optionally allows for completing the front surface processing, including texture and passivation to a point prior to lamination.
  • FSF doped front- surface field
  • a diffused front surface field from diffused Phosphosilicate glass: PSG, POCb or implanted phosphorus as precursors may then be employed.
  • the use of the backplane enables the physical segmentation of the cells into isles/sub-cells for icell fabrication and with it the high voltage - low current solar cell architecture which in turn removes the need for a thick metallization scheme and the need for thick metal (such as copper/nickel/tin) plating process and associated technological risks, such as contamination of the active silicon with copper. Elimination of plating also reduces the overall solar cell
  • Backside passivation may include a material stack such as a phophosilicate glass on a borosilicate glass.
  • the sunny side of the thin-silicon solar cell comprises a light-trapping texture (formed by wet etch texturing and/or dry laser or plasma texturing) and a subsequent PECVD process to form the passivation and anti-reflection coating (ARC) layer(s).
  • ARC passivation and anti-reflection coating
  • the back-contact/back-junction solar cell of Figs. 5D and 5E comprises semiconductor absorber layer having a first level metal (Ml) made using a suitable (low- cost and high electrical conductivity) metal layer such as aluminum or aluminum-silicon alloy forming an interdigitated back-contact (IBC) emitter and base metal finger pattern, for example a busbar-less IBC finger pattern (fine pattern pitch). Lack of busbars on Ml may eliminate efficiency losses due to busbar-induced electrical shading. Based on the two-level metallization scheme here, Ml serves as the contact metallization layer (with fine-pitch interdigitated base and emitter metal fingers) while M2 provides the higher sheet conductivity interconnect layer to extract the solar cell power with minimal ohmic losses.
  • Ml first level metal
  • suitable metal layer such as aluminum or aluminum-silicon alloy
  • IBC interdigitated back-contact
  • Ml serves as the contact metallization layer (with fine-pitch interdigitated base and emitter metal fingers) while M2 provides the higher sheet conductivity inter
  • the backside of the thin-silicon solar cell is a thin backplane sheet, for example between 50 and 200 um thick, and may be a flexible polymeric laminated sheet containing fibers, such as a prepreg sheet.
  • the backplane sheet is relatively thermal- expansion-matched (or CTE matched) to silicon in terms of the respective coefficients of thermal expansion (CTE) to mitigate cell breakage during thermal processing.
  • CTE coefficients of thermal expansion
  • the interdigitated back-contact/back-junction solar cell comprises a patterned second level metal (M2) which may have a thickness in the range of approximately 1 to 55 um, in some instances having a coarser pitch (and hence less fingers) as compared to Ml and a substantially orthogonal pattern with respect to Ml .
  • Patterned M2 is electrically connected to patterned Ml through pre-specified M1-M2 conductive via plugs formed in the backplane.
  • M2 may be any conductive material or material stack including materials such as aluminum, copper, or aluminum with Al/Zn or NiV.
  • Fig. 5E provides a high level cross-sectional diagram representation of the final solar cell structure for the back contact / back junction thin silicon solar cell, comprising a thin semiconductor (e.g. sub-100 ⁇ crystalline silicon) cell absorber which is formed by etching back a thicker starting silicon wafer, a passivation and anti-reflection coating (ARC) on a textured surface on the sunny side, for example a stack comprised of amorphous silicon (a-Si) and silicon nitride or one of aluminum oxide and silicon nitride; a backplane, for example a laminated flexible polymeric sheet such as prepreg, an interdigitated Ml pattern, for instance, busbarless thin aluminum metal fingers on the cell backside; a patterned orthogonal second level metal, shown here for M2 using patterned metal comprising aluminum and / or copper, where the M2 PVD metal is less than about 10 microns in thickness and in some instances having a thickness in the range of between about 1 and 5 um thick
  • Each of the sub-cells or isles in the monolithic icell may include a set of mini bus bars of at least one per polarity through which the connections to adjacent sub-cells are made, in parallel or in series.
  • the emitter and base diffusion regions as well as the IBC metallization pattern may be arranged in an advanced geometry to minimize electrical shading underneath the mini bus bars.
  • a starting material of n-type crystalline silicon may be selected from
  • the starting wafer size may be a full-square (or full rectangle), pseudo-square (or pseudo rectangle) or other geometrical shapes (e.g., hexagonal, other polygonal shaped, etc.) with areas at least 150 cm 2 and in some instances at least 240 cm 2 .
  • the starting wafer thickness may be less than approximately 250 ⁇ and optionally having the thinnest thickness allowing for the combination of lowest starting wafer cost and high fab yield to enable negligible breakage.
  • a first metal (Ml) solar cell contact metallization may be formed directly on the silicon contact regions, where the metal extent may be larger than the silicon contact opening.
  • This first metal (Ml) layer may be formed for example, using one of the following methods: screen printing of a paste, inkjet printing of an ink, aerosol jet printing of an ink, or physical-vapor deposition (plasma sputtering, thermal evaporation, electron-beam evaporation, ion beam deposition, or thermal/arc spray deposition).
  • PVD of Ml may require a patterning step such as selective laser ablation of metal after deposition unless the PVD process deposits a patterned Ml layer such as by using an in-situ shadow mask.
  • the backplane may be a sheet or plate, for example a flexible thin polymeric or composite epoxy resin with fiber content (such as prepreg) sheet laminated to the cell backside after completion of patterned Ml .
  • the backplane may also be applied by screen printing, spray coating, or alternative deposition method.
  • a silicon etch back may be performed for example by wet etch or dry etch (plasma or RIE) or alternatively using a suitable grinding or lapping process.
  • This wafer thinning may be economically carried out using hot concentrated KOH (or NaOH) for example with concentrations of KOH above 15% (and as high as 45%) and with temperatures of 90°C or higher (in some instances, depending on the process controllability, as high as 150°C).
  • a second metal layer (M2) on the backplane may be formed for example by a PVD method (e.g., plasma sputtering and/or thermal evaporation, e-beam evaporation, thermal spray, or arc spray) and pulsed laser ablation patterning (for instance using pulsed nanoseconds laser ablation), or by screen printing of a high-conductivity paste comprising aluminum and/or copper or by PVD through an in-situ shadow mask.
  • a PVD method e.g., plasma sputtering and/or thermal evaporation, e-beam evaporation, thermal spray, or arc spray
  • pulsed laser ablation patterning for instance using pulsed nanoseconds laser ablation
  • screen printing of a high-conductivity paste comprising aluminum and/or copper or by PVD through an in-situ shadow mask.
  • the latter is feasible as the pattern size and alignment requirements for M2 are substantially coarser than those for Ml (in some instances due to the substantially orthogonal alignment of
  • the thin silicon n-type base parasitic resistance may be reduced by either an optional doped front-surface field (FSF) formed by laser doping of phosphorus (or arsenic, antimony, or indium) or by laser activation of implanted phosphorus, arsenic, or antimony on the textured surface, or by formation of a blanket phosphorus buried layer adjacent to the emitter by either phosphorus (e.g., POCb) diffusion or phosphorus ion implantation with a subsequent shared anneal.
  • FSF front-surface field
  • Fig. 33 is a process flow diagram illustrating high-level solar cell building blocks.
  • the first building block includes starting wafer inspection, selection, and preparation.
  • the second block includes back surface engineering, with and without the addition of a doped back surface field (BSF) during this process sequence.
  • the third block is first level metal (Ml) formation (also known as contact metallization).
  • the fourth block is lamination of the backplane to attach the permanent reinforcement backplane.
  • the fifth block includes wafer segmentation into sub-cell units or isles for the formation of the overall monolithic icell architecture, the etch-back, texturing and post texture cleaning.
  • the sixth block includes front-surface engineering, including the front- surface passivation, with and without the addition of an internal front-surface field (FSF).
  • the seventh block consists of generating access to the buried back side as well as the second-level metal (M2) formation and an optional final anneal (which may be done in situ during the M2 PVD process).
  • Each of these building blocks may contain a variety of process flow embodiments, various examples of which will be described. Different process route options or embodiments within each building block may be combined with different process route options or embodiments of other building blocks. As there are a multitude of
  • the starting wafers may first receive an optional inspection followed by an optional pre-clean, followed by saw damage removal (SDR), for instance, using an alkaline chemistry such as hot KOH or NaOH, or acidic chemistry such as HF/FiN03. Following this the wafers may optionally receive a chemical polishing etch, either single or double sided, for instance, using highly concentrated mixtures of HF and HN03, in some instances chilled. This polishing etch is followed by a short KOH etch to remove etching stains such as porous silicon from the surface.
  • SDR saw damage removal
  • wafers receive a metal removal clean, for instance, using HCl or mixtures of HCl with HF, or ozonated HF, optionally followed by a final HF dip to render the surface hydrophobic and remove the native silicon dioxide (and to make the crystalline silicon surface hydrogen terminated as a result of dilute HF dip treatment).
  • a metal removal clean for instance, using HCl or mixtures of HCl with HF, or ozonated HF, optionally followed by a final HF dip to render the surface hydrophobic and remove the native silicon dioxide (and to make the crystalline silicon surface hydrogen terminated as a result of dilute HF dip treatment).
  • the first embodiment is shown in the example flows in Figs. 35A through 35D and provides the introduction of an n-type dopant such as phosphorus by means of POC13 thermal furnace doping, in conjunction with a thermal drive-in step, and by a subsequent wet etch (HF dip) removal of the remaining phosphorus doped glass
  • phosphor-silicate glass or PSG from the surface.
  • a second embodiment is shown in the example flows in Figs. 36A through 36D and provides an ion implantation step of n-type dopant species such as phosphorus (P), arsenic (As), antimony (Sb), or indum (In).
  • This implant (such as phosphorus implant) is then thermally annealed as part of a later furnace anneal step described below and which serves several purposes.
  • an atmospheric pressure chemical vapor deposition (known as APCVD), or alternatively PECVD, of a first layer of boron-doped glass (such as BSG) is performed.
  • the BSG layer may have a comparatively low boron concentration to enable the formation of a selectively lighter-doped emitter with a comparatively higher sheet resistance across the cell, and is subsequently patterned, for example using a pulsed picoseconds (ps) or femtoseconds (fs) laser or alternative laser capable of ablating the BSG dielectric at minimal to no damage to the underlying silicon.
  • ps pulsed picoseconds
  • fs femtoseconds
  • a higher boron-doped emitter (to be utilized for low-resistance emitter contact regions) will be formed in further processing.
  • a second layer of BSG which may have a comparatively higher concentration of boron, is deposited by APCVD (or alternatively PECVD) and which may serve as a precursor for the selective emitter contact.
  • an additional patterning step using a pulsed picoseconds or femtoseconds laser may be employed removing BSG in regions where the n+ doped base contact regions should be formed.
  • a layer of phosphosilicate glass (PSG) may then be deposited (by either APCVD or PECVD) which serves as the precursor for the phosphorus doped base contact regions (with n+ doping for low base contact resistance).
  • the evolving solar cell structure then undergoes a high temperature furnace anneal which drives in the patterned p-type and n-type diffused regions into the structure backside.
  • This anneal may be performed in an inert and/or oxidizing ambient or a stepwise mixture of inert and oxidizing ambient and at temperatures above 800°C, more specifically between 850 and 1100°C. Additional steps such as gettering, for instance in temperature ranges around 550°C to 650°C , or even forming gas anneals, typically carried out in temperature range of 400°C to 500°C deg C (e.g. at 450°C) may also be integrated into the above annealing step. In cases where the back surface had previously received an implanted dopant, as mentioned above, for instance, using phosphorus and arsenic, then this thermal anneal step also serves to anneal, activate and diffuse the implant region.
  • Example pushing and pulling temperatures are chosen such that the boats are pushed and pulled at temperatures above 600°C, and in some instaces at or above 800°C to 850°C .
  • Such high temperature pushing and pulling of the furnace boats may be implemented instead of or in conjunction with the lower temperature gettering and FGA depicted in most flow embodiment examples.
  • a laser for example a pulsed picoseconds or femtoseconds laser is employed to open the contacts to the respective emitter and base contact regions for subsequent Ml contact metallization process.
  • an additional anneal for instance in an inert non-oxidizing ambient, may then be performed to reduce potential damage from the laser contact opening step.
  • ablation processes to locally remove dielectric such as doped glasses using a laser to generate the desired pattern may also be achieved by means of using a suitable etchant paste.
  • the etching paste is applied locally, for instance using screen printing.
  • the etching mechanism may require a thermal activation (for such pastes not based on hydrofluoric acid). This activation may be achieved, for instance, in a belt or roller furnace and is part of the etch dimension and depth control.
  • the etching paste may be removed by means of a cleaning and rinsing step, for instance using light alkaline solutions, followed by DI water rinsing and optional metal removal steps such as a short HC1 containing wet clean.
  • concentration and opposite polarity may also be formed using dopant paste, applied for instance using screen printing, with subsequent thermal drive-in. This replaces the deposition and subsequent patterning of dielectric dopant precursors such as doped glasses. Combinations of the above processes are also readily derivable.
  • Block 3 of Fig. 33 includes the first level metallization (Ml or solar cell contact metallization) formation.
  • Ml first level metallization
  • two distinctly different path examples or process embodiments are provided.
  • patterned first level metal Ml in the form of screen, stencil, inkjet or otherwise printing a paste or ink, in one printing step or optionally in more than one coat, with optional drying steps in between, followed by a main curing process, which in turn may consist of several curing steps in one curing tool such as a tube furnace or an in-line furnace, to first drive out or burn off binder from a paste, followed by a resistivity reduction sintering step.
  • Suitable pastes may be made of aluminum, aluminum alloyed with silicon and/or germanium, as well as nickel, silver, or other conductive materials. Process examples printing the Ml layer are depicted in Figs. 34A through 36D and Figs. 38A through 41B.
  • the first level metal may be deposited in a blanket mode, for instance using PVD (such as DC magnetron plasma sputtering), of for example aluminum, aluminum alloyed with silicon and/or germanium, as well as nickel (Ni) or nickel-vanadium (NiV).
  • the blanket metal layer is patterned, for instance using a pulsed nanoseconds, picoseconds, or femtoseconds laser to ablate metal between the terminals or anywhere else where it is not desired. Illustration of an example of such a process flow is depicted in Fig. 42.
  • Combinations of printing and PVD are also feasible, as well as the addition of conductive dots such as paste or ink dots in regions where additional thickness and/or an alternate metal is desired.
  • the selective emitter design (comprising less heavily doped main field emitter and more heavily doped emitter contact regions) previously presented utilizes a dual layer BSG deposition and a pulsed picoseconds or femtoseconds laser patterning step may also utilize a single BSG layer to generate the lightly doped emitter region and a selective pulsed nanoseconds laser drive-in and alloying step for the highly doped part of the emitter (using p++ doping from subsequent Ml aluminum layer) which serves directly as an emitter contact.
  • the first BSG patterning and the second BSG deposition processes are omitted.
  • the first level metal in this case aluminum or an alloy of aluminum with silicon and/or germanium
  • the first level metal is driven in (serving as p-type heavy emitter contact doping) subsequent to deposition by using a pulsed nanosecond laser which melts the surface of Ml layer, for instance Al and creating a eutectic Al-Si melt, and alloys it with the underlying silicon.
  • the deposited Ml, for instance Al may be deposited and patterned using PVD with a subsequent laser ablation for patterning or may be formed using a screen printing or inkjet printing (or another printing) process using a frit-less aluminum-containing paste.
  • the PVD with subsequent laser ablation pulsed laser ablation may be used for patterning in the same tool or same step as the laser emitter contact alloying - in other words using two different laser processes in the same tool.
  • a suitable Ml paste with a frit or other etching component may be used, which, upon thermal processing, locally etches through the dielectric and makes contact to emitter and base regions without the need of a laser based contact area dielectric ablation.
  • the Ml paste containing frit may also be split into a dual print paste with different pastes for the different polarity regions (emitter and base) and which may be thermally annealed at the same time or in two different steps, depending on the optimum annealing conditions for high quality ohmic contact while retaining reasonably low contact recombination for both polarities.
  • the wafer is ready for the fourth process block, Block 4 in Fig. 33, laminating a backplane, for example a flexible backplane, onto the structured wafer backside.
  • a backplane for example a flexible backplane
  • the backplane may be made of a variety of materials, it may be advantageous that the backplane adheres to several requirements depending on the solar cell fabrication method and resulting cell use: 1) the backplane may have a close thermal expansion coefficient match to the underlying patterned silicon stack; 2) the backplane may have flexibility; 3) the backplane may be chemically resistant to subsequent wet and dry processing steps such as silicon etching and texturing (unless all wet processing is performed prior to the lamination process), and; 4) the backplane should withstand the thermal budgets of the subsequent passivation dielectric anneal and second level metal deposition processes and allow for sufficiently high temperature processing (e.g., up to approximately 300 or even 400 °C ).
  • the lamination process may be a vacuum lamination process to avoid formation of bubbles at the interface between the backplane sheet and the silicon layer with the structured Ml -metallized backside. Sufficient pressure should be exerted (between 10 and 400 psi or in some instances more specifically between 50 and 250 psi) during the lamination to enable the flow of resin from the prepreg backplane laminate which in turn planarizes the laminated cell structure.
  • the size of the prepreg may be be chosen to closely match that of the cell to be laminated while slight over- or undersizing may bear advantages for subsequent processing.
  • the backplane sheet may have a thickness in the range of about 50 microns to 250 microns.
  • an optional edge trim may be performed, for example using a pulsed nanosecond laser.
  • the fifth process block Block 5 in Fig. 33 pertains to the optional segmentation of the wafer into sub-cells (isles) to form an icell (or isled master cell), silicon thinning for example using wet or dry chemical etching or abrasive methods, and texturing and post texture cleaning.
  • the wafer backside structure is laminated to the backplane and the backplane itself protects the buried backside structures from subsequent processes.
  • the wafer may be: 1) thinned - to enable the use of lower lifetime wafers for making highly efficient back-contact solar cells with thinned absorbers; 2) the absorber material segmented into electrically isolated (via trench isolation) monolithically-integrated individual sub-cells (isles) which are later electrically interconnected in series or in parallel or in a combination of parallel and series; 3) textured on the front surface, for example to form random pyramidal structures on the front surface, followed by cleaning of the textured surface prior to the PECVD passivation process.
  • FIG. 37A illustrates cross-sectional diagrams showing a process comprising a wafer thinning step prior to wafer segmentation (for example using laser trench formation)
  • Fig. 37B illustrates cross-sectional diagrams showing a process comprising partial wafer segmentation (for example using laser trench formation) prior to wafer thinning and following wafer thinning and texturing.
  • the segments/isles are first formed with a pulsed laser isolation trench either fully through the complete absorber layer or partially through the absorber layer (for instance a trench depth suitable such that a subsequent absorber layer removal/thinning by etching and texturing etches far enough to effectively and reproducibly form the trench-isolated sub-cells/isles.
  • the absorber layer e.g. the silicon wafer
  • the absorber layer is first thinned to its final thickness (plus the silicon that is to be textured later), then segmented either fully through the remaining thinned absorber layer or almost completely such that the subsequent texturing process is sufficient to separate the individual sub-cells or isles.
  • a third embodiment utilizes a combination between the two above sequences where in a first step most of the thinning etch is performed, followed by complete or almost complete trench-isolated
  • the isolation cut is performed after thinning and texturing are both completed.
  • This embodiment may include two additional options. In one option, after the segmentation cut the wafer surface goes directly into passivation. This has the advantage of reducing the overall number of wet process steps. Another option is perform a slight cleanup step to remove debris and potential damage from the laser step. Such cleanup steps may consist of a short immersion in an alkaline chemistry such as the texture chemistry itself, followed by suitable post texture clean, or by mild debris removals such as megasonic cleans.
  • the trench isolation segmentation process itself should leave the backplane material relatively intact to retain structural integrity of the cell such that the cell sandwich may be processed using a typical cell form factor, such as 156 mm x 156 mm square or pseudo square with the respective automated equipment that can handle such standard sizes.
  • a prepreg backplane and a silicon absorber it may be advantageous to cut the absorber with a laser source using a laser wavelength with good absorption in silicon while having with poor absorption in prepreg (i.e., being transmitted and/or reflected by the prepreg with little absorption) - a concept which holds for other backplane/absorber material combinations as well.
  • Many prepregs do not absorb strongly in the infrared (IR) wavelength so cutting with IR enhances the relative selectivity of silicon cutting versus prepreg cutting. Cutting or scribing using IR lasers is also comparatively cheap, as capex (capital expenditure) and maintenance for IR lasers (e.g. pulsed nanosecond lasers) are typically lower as compared to UV lasers.
  • isolation trenches may be formed using water jet guided lasers, such as water jet guided green or IR lasers.
  • Water jet guided laser cuts may exhibit cutting regions with lower damage while retaining the absorption and therefore selectivity advantage of the lower wavelength laser or lasers.
  • Other segmentation methods to generate a monolithic backplane-attached icell solar structure include buried focused laser beams for splitting where the focus may be placed within the material and temperature gradient and with it internal vapor pressure induced material splitting is the result. Such induced splitting may be assisted by splitting from a laser source which is closely traced and followed by a cooling source such as a water or dry ice jet. Dicing methods, such as diamond wheel saw cutting, may also be employed for the
  • the silicon wafer thinning itself may be performed using a high etch rate wet etch solution, such as for instance concentrated KOH or other hydroxides such as NaOH, TMAH, NH40H or LiOH, using relatively high temperatures of 80°C and above (in some instances up to approximately 145°C).
  • a high etch rate wet etch solution such as for instance concentrated KOH or other hydroxides such as NaOH, TMAH, NH40H or LiOH
  • Alternative wet chemistries such as mixtures containing at least HF and HN03 with optional additive such as acetic, phosphoric or sulfuric acid may be used but are typically more expensive.
  • This acidic etching is performed at room temperature or below and in solutions that allow for chilling to remove heat generated from the exothermic etching reaction.
  • flocculating agents may be introduced during the process to help flocculate out the reaction product of potassium silicate (in the case of a silicon etch) and a KOH etchant or hexafluorosilicilic acid (in the case of an HF / HN03 based etchant chemistry) and which then support a mechanical separation of reaction product, for instance either by sedimenting bed or centrifugal demixing.
  • An alternative method for removing byproduct out of solution is by thermally cycling the solution (i.e. cooling it down to reduce the solubility and removing the components that fall out of solution, such as silicate, and reheating).
  • byproduct may be separated from the etchant and thus the bath lifetime of the etchant extended as the balance of the spent etchant such as KOH or NaOH may be spiked back into the bath, either from solid bricks or flakes of KOH (or other hydroxides) or from highly concentrated aqueous solution.
  • silicon thinning by etching is the use of plasmas, such as halogen containing plasmas for silicon etching. Also, a high etch rate molecule radical etch is envisioned. Other options for silicon wafer thinning include mechanical grinding or lapping down the silicon. In some instances, grinded silicon is potentially more readily separable for recovery and recycling.
  • a surface cleaning process such as those containing HC1, HF or HN03 or ozonated HF followed by a final dilute HF etch treatment is carried out and an optional final HF containing step may leave the surface without a native oxide.
  • the presented process flows depict a cut of approximately 30-70% of the thickness with the subsequent etch extending the depth of the cut to the prepreg boundary to complete the isolation.
  • the initial segmentation cut may also be a complete cut (and not to rely on the etching to provide the full segmentation isolation) as shown in the process flow of Fig. 43.
  • Block 6 of Fig. 33 includes solar cell front surface engineering including front surface passivation application with or without an additional doped front surface field (FSF).
  • FSF doped front surface field
  • a dopant source for n-type absorber cells typically containing phosphorus, arsenic or antimony or indium dopant and a drive-in and/or dopant activation mechanism, such as pulsed nanoseconds laser annealing or pulsed nanoseconds laser doping .
  • the dopant sources may be provided by various methods, including ion implantation, predeposition of material layers containing dopants, predeposition of sprays containing dopants, plasma immersion ion implanation - for instance using PH3, or gas immersion laser doping (GILD).
  • GILD gas immersion laser doping
  • Process flow embodiments that implement doped front surface fields (FSF) are outlined in Figs. 38A-38D, 39A-39D, 40A-40D, and 41A-41B.
  • an effectively low temperature drive-in mechanism such as a pulsed nanoseconds laser annealing or melting, or melting in a dopant ambient (GILD), so that the heat is concentrated to the front of the solar cell and the backplane does not receive excessive heat and remains relatively unheated and unaffected by the frontside pulsed laser processing.
  • a pulsed nanoseconds laser annealing or melting or melting in a dopant ambient (GILD)
  • GILD dopant ambient
  • pulses sources such as pulsed nanoseconds lasers, may be used for formation of doped FSF.
  • anneal may be performed using a pulsed nanoseconds (with pulse length in the range of about 10 ns up to 100's of ns) green laser that can distribute the heat into the top few microns of absorber, or a pulsed UV laser which, from a heat dissipation point of view, will deliver most of the heat in the pyramid tips.
  • a pulsed nanoseconds with pulse length in the range of about 10 ns up to 100's of ns
  • a pulsed UV laser which, from a heat dissipation point of view, will deliver most of the heat in the pyramid tips.
  • Top hat or flat-top homogenized laser beams may also be used.
  • Various options for front surface passivation layers there are also various options, from silicon nitride to stacks of amorphous silicon (a-Si) with silicon nitride, or specifically intrinsic a-Si, followed by n-doped a-Si, followed by silicon nitride.
  • silicon nitride oxide nitride or oxynitrides with fixed or variable oxygen content may also be used.
  • the initial layer may also contain some fraction of oxygen to become an amorphous silicon-oxide (also possible with sub-stoichiometric content of oxygen), or amorphous silicon-carbon with a relatively small portion of carbon.
  • AI2O3 aluminum oxide
  • ALD atomic layer deposition
  • PECVD PECVD
  • APCVD atomic layer deposition
  • silicon nitride silicon nitride is deposited after as a second layer.
  • the stoichiometric ratio between nitrogen and silicon may be fixed or variable throughout the film to enable optimized optical and electrical performance, where optimized optical performance is achieved at low or zero absorption in the film and the correct effective film thickness and refractive index and best electrical performance may be achieved with sufficient hydrogen content and relatively large fixed positive charge density (in the case of n-based cells).
  • the seventh building block Block 7 of Fig. 33 involves the formation of access holes (vias) to make contact to the buried metal 1 (Ml) layer and the deposition and structuring of metal 2 (M2).
  • Metal 2 (M2) forms the final high-conductivity solar cell metallization, isle to isle interconnection, with the cell busbars.
  • Via holes may be drilled using lasers such as pulsed C02 lasers, or pulsed UV lasers. In some instances, vias may be positioned on an optionally widened Ml layer finger in order to have more forgiving alignment tolerances.
  • Alignment of the vias to underlying interdigitated Ml fingers, as well as alignment of the trench isolation segmentation cuts to the structures on the backside of the absorber wafer, may utilize infrared illumination of alignment marks which have sufficient transmission through the silicon absorber layer as well as through the backplane.
  • the structure After formation of the via holes in the backplane with via holes landing on the designated portions of Ml interdigitated fingers, the structure is ready for the M2 deposition and patterning, which may be preceded by a pre-deposition in-situ sputter etch clean (for instance using argon, oxygen or other plasmas or ions) to etch off poorly conductive surface layers such as aluminum oxide or carbon residue on top of the Ml contact and to promote M2 adhesion on the backplane surface.
  • a pre-deposition in-situ sputter etch clean for instance using argon, oxygen or other plasmas or ions
  • Such a process may be performed in a vacuum PVD system comprising vacuum- integrated plasma sputtering and evaporation process capabilities. Subsequently, and preferably without breaking vacuum, the M2 layer can be deposited.
  • the M2 layer may be depositing using, for example, PVD such as aluminum evaporation (by thermal or electron-beam evaporation of aluminum) or plasma sputtering, optionally followed by at least one capping layer that serves as adhesion, anti-oxidant and contacting layer, such as a thin (having a thickness in the range of approximately 100 nm to 500 nm) nickel or nickel-vanadium layer and an optional tin (Sn) or other solderable material coat.
  • PVD such as aluminum evaporation (by thermal or electron-beam evaporation of aluminum) or plasma sputtering
  • at least one capping layer that serves as adhesion, anti-oxidant and contacting layer, such as a thin (having a thickness in the range of approximately 100
  • the cell may be annealed to further improve surface passivation properties with reduced surface recombination velocities and reduce cell metallization contact and via resistances.
  • M2 may then be subsequently patterned, for instance using pulsed laser ablation, to separate emitter from base contact regions while establishing (and leaving intact) the suitable pre-designed interconnections (serial, parallel or combinations) between the individual isles or sub-cells.
  • the patterned M2 may also comprise the final solar cell busbars.
  • PVD plasma sputtering and/or evaporation
  • other deposition techniques such as screen or ink jet printing, or thermal spray coating, or arc plasma spray coating, or plating may be employed.
  • SDR may be either double-sided or single-sided etch tool (batch or in-line design).
  • a patterned screen-printed Ml paste for example using a suitable high- conductivity fritless paste comprising aluminum.
  • Patterned M2 formed by PVD (plasma sputtering, and/or evaporation, and/or another suitable PVD method such as arc or thermal spray) followed by pulsed laser ablation patterning of the deposited metal layer; while M2 is shown with PVD AL/NiV, other material options are possible, including: Al/Ni, Al/Zn, Cu/Ni, Cu/Zn, etc.
  • PVD copper may be used as the main M2 conductor instead of aluminum.
  • this laser partitioning scribe may be removed from the flow and Tools 11 and 13 combined into a single wet processing equipment (i.e., 15 process tools without isle partitioning as compared to 17 process tools with isle partitioning in the flow of Fig. 34A) - a process removal step which holds true in all process flows.
  • a silicon etch back is performed to reduce the absorber thickness to a range of approximately 50 to 80 microns (Tool 11 in Fig. 34A, note this tool number reference varies in different process flow embodiments) and subsequently another 5 to 15 micron thickness reduction during the texture etch process (Tool 13 in Fig. 34A, note this tool number reference varies in different process flow embodiments) for a final silicon absorber thickness in the range of approximately 35 to 75 microns although thinner or thicker absorber Si may be formed.
  • Trench isolation regions may be formed (may also be referred to as "iCell"
  • Isolation trenches are formed using pulsed ns laser scribing after Si etch back (wafer thinning).
  • Figs. 34A through 34D are process flow embodiments for the manufacture of interdigitated back contact solar cells with no FSF or BSF formation for base
  • Flows 34A and 34B describe flows without and with In-Situ Masking of PVD for M2 and the isle laser cut ("iCell Pulse ns Laser Scribe" ) is performed between Si thinning Etch Back and sunnyside Texture/Post-Texture Clean.
  • Flow 34A shows PVD M2 without in-situ PVD masking of M2 and using laser ablation patterning.
  • Flow 34B shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Flows 34C and 34D describe flows without and with In-Situ shadow Masking of PVD for M2 and the isle laser cut is performed before Si Etch Back (Reduces Tool Count by One).
  • Flow 34C shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 34D shows PVD M2 with in-situ PVD shadow masking for patterned M2
  • Figs. 35A through 35D are process flow embodiments for the manufacture of interdigitated back contact solar cells with a buried BSF for base conductivity - in other words additional n+ doping in the n-type base for reducing the base resistance, process shown using POC13 doping after SDR followed by POC13 glass etch + Si etch.
  • Flows 35A and 35B describe flows without and with In-Situ shadow Masking of PVD for M2 and the isle laser cut is performed between Si Etch Back and Texture/Post-Texture Clean.
  • Flow 35A shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 35B shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Flows 35C and 35D describe flows without and with In-Situ shadow Masking of PVD for M2 and the isle laser cut performed before Si Etch Back (Reduces Tool Count by One).
  • Flow 35C shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 35D shows PVD M2 with in-situ PVD masking for patterned M2.
  • Figs. 36A through 36D are process flow embodiments for the manufacture of interdigitated back contact solar cells with a buried BSF for base conductivity - in other words additional n+ doping in the n-type base for reducing the base resistance, process shown using phosphorus ion implantation and subsequent shared furnace anneal (ion implant places the peak of P below the subsequent emitter-base junction).
  • Flows 36A and 36B describe flows without and with In-Situ Masking of PVD for M2 and the isle laser cut between Si Etch Back and Texture/Post-Texture Clean.
  • Flow 36A shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 36B shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Flows 36C and 36D describe flows without and With In-Situ Masking of PVD for M2 and isle laser cut performed before Si Etch Back (Reduces Tool Count by One).
  • Flow 36C shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 36D shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Figs. 38A through 38D are process flow embodiments for the manufacture of interdigitated back contact solar cells with laser-doped FSF for base conductivity - in other words additional n+ doping in the n-type base for reducing the base resistance, process shown using laser doping on front-side after Si etch back and texture/clean (pulsed ns laser doping is done after applying the phosphorus liquid source, post texture).
  • Laser-doped FSF may serve two objectives: improved front-side passivation and reduced base resistance (for example doping depth -0.1 to 0.5 microns, surface cone. -1E17 to 5E19 cm “3 , lower surface concentrations for deeper doping and vice versa).
  • Flows 38A and 38B describe flows without and with In-Situ Masking of PVD for M2 and isle laser cut between Si Etch Back and Texture/Post-Texture Clean.
  • Flow 38A shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 38B shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Flow 38C is for PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 38D shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Figs. 39A through 39D are process flow embodiments for the manufacture of interdigitated back contact solar cells with pulsed laser FSF for base conductivity - in other words additional n+ doping in the n-type base for reducing the base resistance, process shown using laser doping on front-side after Si etch back and texture/clean (pulsed ns or ps laser is applied after depositing a thin sub-250 nm layer of n+
  • phosphorus or arsenic doped amorphous Si to perform epitaxial alignment of the doped amorphous Si to reduce base resistance, with surface cone. -1E17 to 5E20 cm “3 , lower surface concentrations used for thicker n+ amorphous Si and vice versa).
  • Flows 39A and 39B describe flows without and with In-Situ Masking of PVD for M2 and isle laser cut between Si Etch Back and Texture/Post-Texture Clean.
  • Flow 39A shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 39B shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Flows 39C and 39D describe flows without and with In-Situ Masking of PVD for M2 and isle laser cut before Si Etch Back (Reduces Tool Count by One).
  • Flow 39C shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 39D shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Figs. 40A through 40D are process flow embodiments for the manufacture of interdigitated back contact solar cells with ion implantation FSF for base conductivity - in other words additional n+ doping in the n-type base for reducing the base resistance, process shown using ion implantation of phosphorus or arsenic on the textured sunny side followed by laser annealing to activate implanted dopant after Si etch back and texture/clean (pulsed ns laser is applied after implanting a thin, for example sub-500 nm, implanted layer of n+ phosphorus or arsenic doped layer, to form an activated n+ layer to reduce base resistance, with surface cone. -1E17 to 5E20 cm "3 , lower surface
  • Flows 40A and 40B describe flows without and with In-Situ Masking of PVD for M2 and isle laser cut performed between Si Etch Back and Texture/Post-Texture Clean.
  • Flow 40A shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 40B shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Flows 40C and 40D describe flows without and with In-Situ Masking of PVD for M2 and isle laser cut performed before Si Etch Back (Reduces Tool Count by One).
  • Flow 40C shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 40D shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Figs. 41A through 41D are process flow embodiments for the manufacture of interdigitated back contact solar cells with gas immersion FSF for base conductivity - in other words additional n+ doping in the n-type base for reducing the base resistance, process shown using laser gas immersion doping in PH3 on front-side (FSF depth ⁇ 0.1 to 0.3 ⁇ ) after Si etch back and texture/clean (pulsed ns laser is applied in PH3/H2 for gas- immersion laser doping to reduce base resistance, with surface cone. -1E18 to 5E20 cm “3 , lower surface cone, used for deeper doped region and vice versa).
  • Flows 41 A and 41B describe flows without and with In-Situ Masking of PVD for M2 and isle laser cut peformed between Si Etch Back and Texture/Post-Texture Clean.
  • Flow 41 A shows PVD M2 without in-situ PVD shadow masking of M2 and using pulsed laser ablation patterning.
  • Flow 41B shows PVD M2 with in-situ PVD shadow masking for patterned M2.
  • Figs. 42 is a process flow embodiment for the manufacture of interdigitated back contact solar cells with no FSF or BSF for base conductivity and pulsed ns laser scribing of isolation trenches using PV-Al/NiV and laser ablation patterning of Ml .
  • Figs. 43 is a process flow embodiment for the manufacture of interdigitated back contact solar cells using pulsed ns laser scribing of isolation trenches on pre-etch thick silicon.
  • first metal (Ml) layer includes, among others, screen printing or stencil printing or depositiong using physical vapor deposition (PVD) such as a DC magnetron plasma sputtering process with a subsequent patterning step, for instance using pulsed laser ablation patterning.
  • PVD physical vapor deposition
  • Ml material choices include, among others, screen printed aluminum (Al), aluminum with silicon and/or germanium content, aluminum and silver combinations (if different metals are to be used for emitter and base), as well as nickel, for instance deposited in a patterned or blanket way using ink jet printing.
  • Material choices for Ml PVD also include Al, Al with Si and/or Ge, followed by Ni or NiV. The considerations outlined below should be weighed relating to material choices for Ml .
  • PVD Al/NiV with Al in the range of from a fraction of ⁇ 1 ⁇ to 2 ⁇ and relatively thin NiV in the range of ⁇ 0.1 ⁇ to 0.50 ⁇
  • pulsed laser ablation patterning instead of screen-printed patterned Al paste and furnace anneal
  • PVD provides much lower near-bulk Al resistivity of ⁇ 2.7 ⁇ , almost a factor of about 15x to lOOx lower than the cured Al paste resistivity, hence, reducing the required Al layer thickness to about a fraction of 1 ⁇ up to about 2 ⁇ (compared to about 15 ⁇ to 30+ ⁇ for Al paste)
  • PVD Al is also much more pure than Al paste (e.g., much less impurities such as Fe) and thus potentially enables higher Voc and higher resulting cell efficiency. PVD Al may reduce the overall Ml resistance and provide lower M2-M1 via plug/contact resistance thus reducing the number of required via holes drilled into the backplane, resulting in higher productivity for the backplane laser drilling process.
  • PVD Al/NiV and pulsed laser ablation instead of screen printed Al
  • the necessary patterning step for example in the case of laser ablation, also bears a risk of Al/NiV laser ablation damage and minority carrier lifetime degradation in the solar cell.
  • a PVD plus laser ablation toolset also carries a higher Capex cost compared to screen print with subsequent furnace cure.
  • the screen printed aluminum layer for Ml may be replaced with PVD Al/NiV followed by pulsed laser ablation of Al/NiV. It is also possible to combine processes, such as using a lower PVD layer for good and low contamination contact formation, followed by a screen printed thickening layer to provide a thicker landing pad layer for the laser via hole drill process to stop on. This second layer process may also serve as a mask for a subsequent etching and patterning process to remove the thinner PVD layer where it is not desired - thus the laser ablation process and associated risk of damaging the back surface passivation may be avoided.
  • the screen printed layer would serve as a mask for the PVD etching by choosing etches and metal combinations that allow for selective etching of the PVD layer at a higher rate than the screen printed layer.
  • the etching may be performed with a less selective chemistry and rely that the metal in the screen printed area is much thicker than the metal in the PVD only area. In the latter case, the etching needs to be timed suitably.
  • Ml layer may be incorporated into the disclosed process flows. For instance, it is also possible to deposit a very thin layer that may be transferred into a silicide using a rather low temperature process.
  • An example is nickel or cobalt and the formation of a nickel silicide or cobalt silicide.
  • Other materials, such as titanium and other refractory metals are also possible; however, nickel may be advantageous due to its low consumption of silicon and low silicidation reaction temperature.
  • the nickel silicide is only formed in the contact areas which are previously opened (oxide is removed), for example using a pulsed picoseconds or femtoseconds laser ablation process in the contact areas.
  • nickel silicide is formed only in the open areas where nickel is in contact with silicon. Afterwards, remaining unreacted nickel may be stripped from the dielectric region, forming localized self-aligned contacts. As contact resistance values with silicides may be relatively low, such a process may be used to lower the overall contact area percentage and thereby reduce the overall back surface recombination velocity (BSRV), which can lead to higher open circuit voltages and higher resulting cell efficiencies.
  • This silicidation may also be performed in conjunction with a local nickel deposition, for instance, using ink jet deposition of nickel dots which may be reacted, thereby removing the need of selectively wet etching unreacted nickel from other regions.
  • the presented process and resulting cell structure may utilize a flexible, CTE matched backplane to provide a cell design with increased flexibility, especially in conjunction with the thin or thinned absorber layer.
  • the absorber layer may already be thin (below about 80 ⁇ ), for instance formed as a deposited epitaxial thin-film growth onto a reusable template with a kerfless process, or may require thinning, for example, after lamination for the case of a thicker (approximately 100 to 180 ⁇ thick) starting CZ or otherwise crystalline wafer or when formed as a thicker deposited epitaxial growth onto a reusable template.
  • Cell flexibility lends itself to flexible module encapsulation concepts, for example glass free modules providing a very thin, lightweight and flexible module. These same flexible module attributes may also further reduce installation and overall balance of system (BOS) costs for such manufactured modules.
  • BOS system
  • backside structures emitter and base junction regions as well as the contact region opening for the Ml to make contact to the emitter and base contact regions
  • back surface recombination velocity is to be kept low for high performance IBC cells. Damage to the structured regions which may be caused by laser processing can be detrimental to the BSRV and with it to the attainable open circuit voltage performance.
  • the structuring of the back side relies on the selective removal of oxide by pulsed laser ablation, for example doped glasses from certain regions using a laser, much care is to be taken to reduce and/or avoid damage from the laser process. Pulsed picoseconds and
  • femtoseconds lasers may avoid such damage but may still leave some residual damage which can reduce the resulting cell efficiency.
  • Fig. 44A is a cross-sectional diagram showing direct oxide ablation using a ps laser of a BSG (or PSG) layer on a silicon layer.
  • Laser ablated opening 520 is formed by laser beam distribution 526 in BSG (or PSG) layer 522 exposing Si layer 524. Damaged Si regions may be formed in Si at glass to Si interfaces 528 and excess beam energy region 530.
  • Fig. 44B is a cross-sectional diagram showing ablation of a hardmask using a ps or ns laser and wet etch opening of a BSG (or PSG) layer on a silicon layer.
  • Laser ablated opening 548 is formed by laser beam distribution 546 in hard mask layer 540 on BSG (or PSG) layer 542 on silicon layer 544.
  • Hard mask layer 540 may be a temporary hard mask such as a resist or polymer or a permanent hard mask such as a-Si.
  • a wet etch then forms wet etch opening 552 exposing damage free region 550 in silicon layer 544.
  • the masking layer may be applied in the form of amorphous silicon on top of the deposited glass, in some instances in the same atmospheric pressure deposition tool, or alternatively using PECVD or PVD.
  • the thin (in the range of approximately 50 to about several hundred Angstroms thick) amorphous Si (a-Si) is then selectively ablated with the laser and provides a hard mask for the subsequent etching step.
  • the unablated a- Si in the untreated regions need not be removed, but merely oxidized as part of the subsequent furnace anneal step. This process may readily be implemented for the case of the selective emitter window and the base window opening processes.
  • the masking layer may for example also consist of a polymer such as resist or photoresist or other organic material.
  • the thickness of the polymer may be less than a micron and the application method may have a very high polymer or resist utilization rate, such as roller coating or spray coating.
  • a key requirement of the polymer or resist is that it adheres well to the glass and may sustain the oxide etching process using buffered or unbuffered HF.
  • the subsequent laser step in one embodiment, then ablates the resist or polymer, then the glass underneath is locally etched away, followed by stripping of the resist or polymer (in some instances in the same tool as the etch).
  • This method buys a large process margin for laser processing as the polymer may be ablated at a much lower laser fluence than even the a-Si or the glass, thereby resulting in undamaged contact regions.
  • This method also allows for the use of nanosecond lasers which are cheaper and cheaper to operate than picoseconds lasers. And this process may readily be implemented for the contact opening laser process step prior to Ml contacting, as the polymer or resist is removed after the glass etch.
  • the polymer or resist may also be photosensitive, for example with a positive photoresist action and the laser process only exposing the photoresist (rather than ablating it).
  • the ensuing wet step first develops the resist in a batch or inline bath, followed by the local glass etching, followed by the resist removal and cleanup step (in some instances all performed in one wet tool).
  • Figs. 45 through 49 show several representative process flow embodiments for the fabrication of a backplane-attached back contact solar cell wherein: (i) no post-lamination wet processing is performed, and (ii) the silicon wafer is not thinned beyond the thinning performed by the SDR and texture processes. These process flows result in back-contact solar cells with thicker absorber layers (typically in the range of about 100 ⁇ up to about 150 ⁇ ) as compared to earlier process flows.
  • the frontside passivation includes a thin thermal oxide underlayer in conjunction with a hydrogenated silicon nitride field-assisted passivation layer (also serving as anti-reflection coating or ARC layer).
  • the passivation layer may, for example, be a stack of PECVD hydrogenated amorphous silicon and silicon nitride (without the thin thermal oxide).
  • Figs. 45 through 49 are bulk CZ wafer back contact solar cell process flows with no selective emitter and utilizing a Top-Hat pulsed laser ablation with no laser damage removal process.
  • Fig. 45 is a process flow utilizing two APCVDs and three furnaces.
  • Figs. 46 through 48 are process flows utilizing two APCVDs and two furnaces.
  • Fig. 49 is a process flow utilizing one APCVDs and two furnaces.
  • While these process flows are shown without selective emitter formation, they may be extended to include selective emitter (for example by addition of one APCVD BSG and one pulsed laser ablation process steps). Key advantages of these process flow embodiments include:
  • FSF Doped front surface field
  • removing base and emitter doping agents after formation of solar cell back side base and emitter regions and subsequently deposit a backside passivation layer may be desirable to remove base and emitter doping agents after formation of solar cell back side base and emitter regions and subsequently deposit a backside passivation layer.
  • removing doping agents and residue for example by etching and referred to as etch back or strip etch
  • post base and emitter formation e.g., post dopant diffusion
  • the solar cell backside passivation layer is not subject to a thermal anneal for base/emitter formation (e.g., dopant drive-in), thus removing anneal temperature restraints for the passivation layer (resulting in increased passivation layer material selection options) and avoiding possible passivation layer damage caused during the base/emitter formation anneal (in some instances certain passivation layers are temperature sensitive, e.g., aluminum oxide, and may experience unfavorable effects during high temperature processing). Further, a dopant agent etch back, may also remove damage (e.g. laser damage) from the solar cell absorber itself caused during base/emitter region formation.
  • a thermal anneal for base/emitter formation e.g., dopant drive-in
  • damage e.g. laser damage
  • the base and emitter dopant etch strip methods described in detail herein provide for the low damage, high efficiency, and low cost fabrication of silicon back contact solar cells and particularly thin silicon back contact solar cells.
  • Etch strip processes may utilize a wet etching process to remove doping layer and include, but are not limited to, wet etch using aqueous HF or vapor HF, dilute KOH, etc.
  • these fabrication flows perform an annealing process for base and emitter region formation before backside passivation layer deposition (e.g., a backside passivation layer such as aluminum oxide, amorphous silicon, amorphous silicon and silicon oxide, aluminum oxide and silicon oxide, or aluminum oxide and silicon nitride).
  • doping oxides such as those shown as aluminum oxide shown as APCVD boron-doped aluminum oxide herein, may be doping oxides such as silicon oxide for example APCVD boron-doped silicon oxide depending on etchant.
  • passivation materials e.g., backside passivation dielectric may be aluminum oxide plus silicon oxide
  • dopants e.g., dopants
  • metallization materials and processes such as etching, annealing, deposition (e.g., atmospheric pressure vapor deposition APCVD, plasma enhanced chemical vapor deposition PECVD, atomic layer deposition ALD, etc.), and contact opening processes may be substituted with known materials and processes consistent with solar cell fabrication methods.
  • solar cell processing factors to consider when determining process flow include, but are not limited to: tool count, capital expenditure, fabrication complexity, temperature considerations. For example, with reference to Fig.
  • annealing may be performed.
  • an annealing step of approximately 350° to 450°C in, for example, forming gas, nitrogen, or a vacuum environment may be performed after frontside passivation (for example A1203 deposition).
  • this annealing may be performed:
  • Figs. 50 through 53 show solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a triple print dopant paste process for field emitter, base, and emitter formation;
  • Figs. 54 through 56 show solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a double print dopant paste process for base and emitter formation;
  • Figs. 50 through 53 show solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a triple print dopant paste process for field emitter, base, and emitter formation;
  • Figs. 54 through 56 show solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a double print dopant paste process for base and emitter formation;
  • Figs. 50 through 53 show solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a triple print dopant paste process for field emitter, base, and emitter formation;
  • 57 through 59 show solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a cascade process (deposition followed by patterning) forming field emitter, emitter, and base regions;
  • Figs. 61 and 62 show solar cell fabrication process flow embodiments for the formation of a back contact back junction solar cell utilizing a single cascade process and tunnel contacts;
  • Fig. 63 shows a solar cell fabrication process flow embodiment for the formation of a back contact back junction solar cell utilizing a single cascade process and tunnel contacts starting with an epitaxial thin film silicon substrate formation.
  • Figs. 50A through 50B are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a triple print dopant paste process for field emitter, base, and emitter formation.
  • three dopant pastes are pattern printed on the solar cell backside: a field emitter paste, an emitter paste, and a base window (paste).
  • dopant pastes may be inkjet or screen printed among other known pattern paste deposition methods in Tool 2.
  • dopant pastes may be silicon nano-particle pastes among other known paste compositions such as doped oxide paste.
  • Field emitter paste, emitter paste, and base window pastes may be concurrently printed in an inkjet tool and then concurrently annealed in a single furnace tool - thus concurrently forming field emitter, emitter, and base regions on the backside surface of the solar cell.
  • these pastes may be individually printed and annealed - in other words an annealing process after each individual dopant print.
  • the solar cell back surface is then wet etch stripped and cleaned to remove remaining dopant agent and doping agent residue.
  • a backside passivation layer is then deposited on the solar cell backside (shown as aluminum oxide but also be other passivation materials including aluminum oxide with silicon oxide). Base and emitter contacts are opened through the passivation layer to corresponding underlying base and emitter regions and additional solar cell fabrication steps may be performed.
  • Additional fabrication steps include the formation of a first level metallization layer (Ml), backplane lamination, an optional front surface thinning etch, texturization and/or clean, frontside passivation, backplane via hole formation, and the formation of a second level metallization layer (M2).
  • iCell scribing may be performed by laser processing or mechanical cutting processes.
  • Solar cell frontside processing may include fabrication steps consistent with the detailed flows described and steps may be deleted, added, or combined with known solar cell fabrication practice. Generally, the fabrication steps of Tools 12 to 15 in the following process flows may be combined or otherwise reduced.
  • Fig. 50B is a solar cell fabrication flow consistent with Fig. 50A with the silicon thinning etch, iCell cut, and texture etch and post texture clean steps performed in an alternative sequence and alternative tool combination.
  • Figs. 51A through 5 IB are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a triple print dopant paste process with an in-line furnace (e.g., in-line batch furnace) for base and emitter region formation in Tool 2.
  • Fig. 51 A is consistent with the flow of Fig. 50A with an in-line furnace anneal performed in Tool 2 along with dopant paste print.
  • Fig. 5 IB is consistent with the flow of Fig. 50B with an in-line furnace anneal performed in Tool 2 along with dopant paste print.
  • FIG. 52A through 52B are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a triple print dopant paste process with an in-line furnace for base and emitter region formation in Tool 2 and dual frontside surface passivation process in Tool 10 and Tool 11, respectively.
  • Fig. 52A is consistent with the flow of Fig. 51 A with a frontside passivation step performed in Tool 10.
  • Fig. 52B is consistent with the flow of Fig. 5 IB with a frontside passivation step performed in Tool 11.
  • Fig. 53 is a solar cell fabrication flow consistent with Fig. 52A with the iCell cut combined with second level metallization layer patterning in Tool 12.
  • Figs. 54A through 54B are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a double print dopant paste process for base and emitter formation.
  • two dopant pastes are pattern printed on the solar cell backside using Tool 2: an emitter paste and a base window (paste).
  • a field emitter is then deposited across the cell backside using Tool 3 APCVD.
  • Backside base and emitter regions are formed in an annealing process after which the remaining dopants are stripped and the backside surface is cleaned for the deposition of a backside passivation layer.
  • double print embodiments may reduce the amount of dopant paste used as compared to a triple print embodiment (i.e., two paste prints of base and emitter in a double print process as compared to three paste prints of field emitter, base, and emitter in a triple print process).
  • dopant pastes may be inkjet or screen printed among other known pattern paste deposition methods in Tool 2.
  • dopant pastes may be silicon nano-particle pastes among other known paste compositions such as doped oxide paste.
  • Fig. 54B is a consistent with the flow of Fig. 50B and having a double print of base and emitter paste in Tool 2 and field emitter formation in Tool 3.
  • Figs. 55A through 55B are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a double print dopant paste process for base and emitter region formation in Tool 2 and dual frontside surface passivation process in Tool 12 and Tool 13, respectively.
  • Fig. 55A is consistent with the flow of Fig. 54A with a frontside passivation step performed in Tool 12.
  • Fig. 55B is consistent with the flow of Fig. 54B with a frontside passivation step performed in Tool 13.
  • Fig. 56A is a solar cell fabrication flow consistent with Fig. 55A with the iCell cut combined with second level metallization layer patterning in Tool 14.
  • Fig. 56B is a solar cell fabrication flow consistent with Fig. 56A and having a separated double print with the addition of base window patterning. In some instances, this flow may be advantageous to reduce cross-doping of doping regions.
  • Emitter contact dopant paste is printed in Tool 2
  • field emitter is deposited in Tool 3
  • base windows are opened in Tool 4
  • base contact dopant paste is printed in Tool 5 thus physically separating the emitter contact dopant paste and based contact dopant paste by the
  • Figs. 57A through 57B are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a cascade process (deposition followed by patterning) forming field emitter, emitter, and base regions (shown in Tools 2 through 6).
  • the process flow of Fig. 57A shows an example of an APCVD cascade dry base flow with all dry AlOx and ns laser ablation processing for base and emitter region formation.
  • the cascade flows provided blanket deposit a field emitter dopant followed by patterning and blanket deposition of emitter and base dopants.
  • a concurrent annealing step shown in Fig.
  • 57A as Tool 4, simultaneously forms backside base and emitter regions process after which the remaining dopants are stripped and the backside surface is cleaned for the deposition of a backside passivation layer.
  • Considerations relating to this fabrication flow may include cost reduction as compared to a dopant paste based method, avoiding and/or reducing cross doping, an increase in the quantity of tools, and laser damage caused by laser ablation to open emitter and base solar cell backside surface regions for doping (for example Tool 3 and Tool 5 shown in Fig. 57A).
  • Fig. 57B is a consistent with the flow of Fig. 50B and having a cascade process (deposition followed by patterning) for field emitter, emitter, and base formation.
  • Figs. 58A through 58B are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing are solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a cascade process (deposition followed by patterning) forming field emitter, emitter, and base regions in Tools 2 through 6 and dual frontside surface passivation process in Tool 15 and Tool 16, respectively.
  • Fig. 58A is consistent with the flow of Fig. 57A with a frontside passivation step performed in Tool 15.
  • Fig. 58B is consistent with the flow of Fig. 57B with a frontside passivation step performed in Tool 16.
  • Fig. 59 is a solar cell fabrication consistent with Fig. 57A with the iCell cut combined with second level metallization layer patterning in Tool 17.
  • Fig. 60 is a solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a single cascade process (deposition followed by patterning) forming emitter and base regions (shown in Tools 2 through 4) and tunnel contacts (shown in Tool 8). Specifically, the process flow of Fig. 60 shows an example of an APCVD cascade single ablation tunnel contacts flow.
  • Fig. 61 is a solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a single cascade process (deposition followed by patterning) forming emitter regions only (shown in Tools 2 through 4) and tunnel contacts (shown in Tool 8).
  • Fig. 62 is a solar cell fabrication process flows for the formation of a back contact back junction solar cell utilizing a single cascade process (deposition followed by patterning) forming emitter and base regions (shown in Tools 2 through 4) and tunnel contacts (shown in Tool 8) consistent with the process flow of Fig. 60 and forming an epitaxial thin film substrate (as compared to the staring wafer of the fabrication flow shown in Fig. 60).
  • HF vapor etch in Tool 7 eliminates wet processing.
  • Al cap in Tool 10 may not be required.
  • the tunnel contact fabrication process flows of Figs. 60 through 62 may in some instances provide several advantages. For example: a minimum number of materials introduced into the solar cell structure and fabrication flow (as shown only A1203 used for surface and junction passivation) thus decreasing complexity; no selective emitter (i.e., non-selective emitters and no field emitter) for reduced process flow complexity and cost in the primary flow; high-quality rear surface passivation by stripping the doping layers and subsequently depositing a high-quality rear passivation comprising A1203; and highest thermal budget after backside passivation and contact junction passivation deposition may be the M2 PVD thermal budget ( ⁇ 325°C).
  • thin PVD Al may eliminate paste firing thermal budget risk to the rear side passivation. This has several major advantages and benefits including: high quality ohmic contacts to both n and p regions (superior to Ni inkjet print); ability to deposit tunnel aluminum oxide in situ in the PVD chamber, hence, no added tool for
  • heterojunction contacts tunnel A1203 is used for both n-type and p-type contacts
  • very low contact resistance and near-bulk resistivity of PVD Al enables reduction of the number of via holes improves capital efficiency (less number of via hole laser drilling tools)
  • no NiV capping layer may result in no requirement for metal laser ablation
  • highly reflective PVD Al is an excellent stopping layer for C02 via drill process
  • Al Ml patterned using simple screen print wet etch in dilute HC1.
  • the disclosed subject matter provides structures and methods for making self aligned contacts for back contact back junction solar cells.
  • the disclosed subject matter and corresponding figures provide low-damage, high-efficiency, and low- cost process flows for the formation of thin silicon solar cells using self aligned contacts for back contact back junction (e.g., interdigitated back contact IBC) solar cells.
  • the novel self aligned contact structures described may achieve higher solar cell conversion efficiency. Additionally, solar cell fabrication methods having minimal or reduced process steps for the formation of solar cell structures with self aligned contacts are described.
  • Fig. 63A is a cross- sectional diagram of a selective emitter solar cell with a self aligned contact structure having a dopant diffusion region with higher doping levels (e.g., greater than 1E18 cm-3) just below the metal to silicon absorber contact.
  • Self aligned contact structures may provide higher solar cell efficiency by having heavily doped regions (n and p type ) in silicon for improved metal/Si contact resistance and lower surface recombination velocity at metal/Si contact and by minimizing heavy doping areas (e.g., doping greater than 1E18 cm-2) in the solar cell thus reducing the overall saturation current density.
  • self aligned contact structure disclosed herein may also be formed by using
  • Fig. 63B is a cross-sectional diagram of a solar cell with a self aligned contact structure formed using hetero/tunneling contacts through a barrier layer in between metal and Si.
  • a self aligned structure An advantage of a self aligned structure is that heavy doping areas are limited to only under the contact where they are needed. If the contact open needs to be aligned to the heavy doping with non-self aligned contact structures, the heavy diffusions need to be much wider than the contact open to accommodate for alignment tolerances. As compared to non-self aligned contact structures, the self aligned contact structures provided may have higher efficiency because of two distinct reasons. First, heavy dopings may be deleterious when used under passivation - in other words heavy dopings are more and in some instances only useful when used under poor passivation such as metal. Thus, a self-aligned structure eliminates the areas of heavy doping under high quality passivation.
  • a self-aligned structure removes the outer nesting opening and minimizes and in some instances eliminates laser damage from this step. Further, in addition to efficiency advantages, the self-aligned structure may require less process steps and thus reduce cell cost.
  • Table 1 below shows a front-end process flow for the formation of a selective emitter solar cell having self aligned contacts and a field emitter - such as that shown in Fig. 63A - using a dopant paste step.
  • Table 1 Selective emitter solar cell having self aligned contacts with dopant paste and a field emitter.
  • Table 1 shows a process flow where self-aligned contact is used for making high efficiency back contact back junction solar cell. Shown, Step 1 is a saw damage removal step to remove damage from a wafer (e.g., a CZ wafer); however, the flows provided are equally applicable to an epitaxially formed silicon substrate processed while on template in which case Step 1 Saw Damage Removal is replace with a porous silicon and epitaxial silicon deposition step as described in detail herein.
  • a wafer e.g., a CZ wafer
  • the front-end processing described occurs on the exposed surface of the template attached epitaxial substrate after which the epitaxial substrate may be released (e.g., mechanical or wet etch release) from the template in back end processing.
  • the exemplary process flows provided are described in the context of fabrication high efficiency back contact back junction solar cells for descriptive purposes and one skilled in the art may combine, add or remove, alter, or move within an overall process flow the various processing steps disclosed. In other words, elements from each of the process flows described in the table provided herein may be combined together or with other known solar cell manufacturing methods.
  • the laser contact open shown in Step 3 in can be separated in two steps (for example as shown in Table 2) to form self aligned contacts only for base and emitter contacts separately; the dopant paste printing step shown in Step 4 may have additional third print of undoped paste on top of already printed dopant pastes (for example as shown in Fig. 8).
  • the wet etch step shown in Step 6 of Table 1 and which removes annealed dopant paste may be replaced by a dry HF vapor etch process or the removal Step 6 may be skipped (i.e., removed) entirely for an all-dry front-end process.
  • the laser contact open step shown in Step 6 of Table 1 may be replaced by an etch paste process comprising etch paste deposition, dry, and rinse for a laser free front-end process.
  • Table 2 below shows a front-end process flow for the formation of a selective emitter solar cell having self aligned contacts using dopant paste and using separate contact open steps.
  • Table 3 below shows a front-end process flow for the formation of a selective emitter solar cell having self aligned contacts with dopant paste and the application of a diffusion barrier.
  • the diffusion barrier deposition shown in Step 5 of Table 3 as an APCVD USG deposition may also be an undoped paste print.
  • Tables 2 and 3 may be used to reduce autodoping from dopant pastes during diffusion anneal.
  • Table 4 below shows a front-end process flow for the formation of a non abutted junction solar cell - such as that shown in Fig. 63C - having self aligned contacts with diffusion barrier dopant paste print.
  • Fig. 63C is a cross-sectional diagram of a non- abutted junction solar cell with a self aligned contact structure having a dopant diffusion region with higher doping levels (e.g., greater than 1E18 cm-3) just below the metal to silicon absorber contact.
  • Steps 2, 3, and, 4 of Table 4 may be replaced with two steps of APCVD boron doped silicon oxide (BSG1) deposition followed by picosecond (ps) C02 laser - an alternative embodiment referred to as self aligned contacts with dopant paste print and non abutted junction with boron doped silicon oxide by APCVD.
  • BSG1 boron doped silicon oxide
  • ps picosecond
  • Table 5 shows the fabrication process flow for a non selective emitter solar cell having self aligned contacts and using phosphorous dopant paste.
  • Table 6 shows the fabrication process flow for a non selective emitter solar cell having self aligned contacts and using phosphorus oxychloride POC13 (POC1). 1 Saw Damage Removal
  • Table 7 shows the fabrication process flow for a non selective emitter solar cell having self aligned passivated base contacts using dopant paste.
  • Table 8 below shows the fabrication process flow for solar cells having self aligned base tunneling/hetero junction contacts - such as those shown in Fig. 63B.
  • Table 9 below shows the fabrication process flow for solar cells having self aligned contacts without a heavy diffusion region below the base contact.
  • Table 10 below shows a front-end process flow for the formation of a solar cell having self aligned contacts with a field base - such as that shown in Fig. 63D.
  • Fig. 63D is a cross-sectional diagram of a solar cell with field base and a self aligned contact structure having a dopant diffusion region with higher doping levels (e.g., greater than IE 18 cm-3) just below the metal to silicon absorber contact.
  • the HF Vapor Step 6 in Table 10 and which removes annealed dopant paste may be replaced with a wet etch step. 1 Saw Damage Remova
  • Table 11 shows a front-end process flow for the formation of a solar cell having a field base self aligned contacts with etch paste and dopant paste prints - such as that shown in Fig. 63D
  • Figs. 64A through 64E is a process flow representation showing cross-sectional diagrams of solar cells at various steps during the fabrication of a abutted junction interdigitated back contact solar cell having self aligned contacts with dopant paste.
  • Fig. 64A shows an aluminum oxide (A1203) layer deposited (e.g., by APCVD) on a silicon substrate/wafer. The aluminum oxide layer may also have an undoped silicate glass layer.
  • a nanosecond (ns or ps) laser opens base and emitter contacts . This step may also include a wet etch to remove any oxide residue (e.g., aluminum silicon oxide residue).
  • Fig. 64A shows an aluminum oxide (A1203) layer deposited (e.g., by APCVD) on a silicon substrate/wafer.
  • the aluminum oxide layer may also have an undoped silicate glass layer.
  • a nanosecond (ns or ps) laser opens base and emitter contacts . This step may also include a wet
  • 64C dopant pastes are paste print in emitter and base regions followed by a diffusion anneal to drive -in/diffuse the dopants and form base and emitter regions.
  • Fig. 64D dopant pastes are stripped (e.g., by wet etch).
  • Fig. 64E metal is printed on the base and emitter regions and annealed resulting in minimal shunt risk.
  • Figs. 52A through 65G is a process flow representation showing cross-sectional diagrams of solar cells at various steps during the fabrication of a non abutted junction interdigitated back contact solar cell having self aligned contacts with dopant paste.
  • Fig. 65 A shows an aluminum oxide (A1203) layer deposited (e.g., by APCVD) on a silicon substrate/wafer. The aluminum oxide layer may also have an undoped silicate glass layer.
  • a nanosecond (ns) laser opens base contacts. This step may also include a wet etch to remove any oxide residue (e.g., aluminum silicon oxide residue).
  • Fig. 65 A shows an aluminum oxide (A1203) layer deposited (e.g., by APCVD) on a silicon substrate/wafer.
  • the aluminum oxide layer may also have an undoped silicate glass layer.
  • a nanosecond (ns) laser opens base contacts. This step may also include a wet etch to remove any oxide residue (e.g., aluminum silicon
  • a undoped silicate glass layer is deposited (e.g., by APCVD).
  • a pico second (ps) laser ablates base and emitter contact openings.
  • dopant pastes are paste print in emitter and base regions followed by a diffusion anneal to drive-in/diffuse the dopants and form base and emitter regions.
  • dopant pastes are stripped (e.g., by wet etch).
  • metal is printed on the base and emitter regions and annealed resulting in minimal shunt risk.
  • Figs. 66A through 66E is a process flow representation showing cross-sectional diagrams of solar cells at various steps during the fabrication of a non abutted junction interdigitated back contact solar cell having self aligned contacts with dopant paste using an undoped paste first.
  • Fig. 66A shows a undoped silicon oxide (Si02) paste printed on the desired based regions of a silicon substrate/wafer only.
  • a doped layer e.g., doped aluminum oxide layer A1203 or doped borosilicate glass layer BSG1
  • undoped silicate glass (USG) layer is deposited (e.g., by APCVD).
  • the undoped silicate glass layer may have a thickness three to four times thicker as compared to the undoped layer.
  • a pico second (ps) laser ablates base and emitter contact openings.
  • dopant pastes are paste print in emitter and base regions followed by a diffusion anneal to drive -in/diffuse the dopants and form base and emitter regions.
  • dopant pastes are stripped (e.g., by wet etch).
  • metal is printed on the base and emitter regions and annealed resulting in minimal shunt risk.
  • emitter or base contacts are opened sequentially (in either order) or simultaneously using various field dielectric removal techniques such as using lasers or wet etch or etch paste. And subsequently, depositing the dopant source in the opened contact, driving the dopant into silicon at high temperature, and selectively
  • the methods of manufacturing described may be further categorized by the source of the under-contact dopants. These can be from a dopant paste (for example phosphorous for n-type and Boron for p-type) or deposited films which incorporate dopants in them, for example APCVD deposited Boron or phosphorous doped Si02 films. Finally, a hybrid source where N+ and p+ dopant sources come from APCVD for one type and dopant paste for the other type of dopant. A further subcategory is defined by the technique to etch away/remove the dopant source which is applicable to both wafer and epitaxial based absorbers as well as dopant source categories (dopant paste, APCVC film, and hybrid dopant source).
  • dopant paste for example phosphorous for n-type and Boron for p-type
  • deposited films which incorporate dopants in them, for example APCVD deposited Boron or phosphorous doped Si02 films.
  • a hybrid source where
  • oxide based dopant sources such as doped Si02
  • either a wet process with HF can be used or a dry process using HF vapor phase etching may be deployed.
  • the field area is also Si02 then the wet HF selectivity is obtained as a heavily doped SiOx film may etche much faster than an undoped film.
  • the field area stack may contain an A1203 (e.g., deposited using APCVD as well). This film, once treated at high temperatures for example greater than 900°C, may have high selectivity to HF solution.
  • HF vapor also very selectively etch the dopant source.
  • both dopant sources may be screen printed dopant paste. If the contacts are open sequentially, then a deposited film for both contacts or hybrid sources can be utilized.
  • Table 12 shows a front-end self aligned contact fabrication flow which yields a separated junction and is accomplished using dopant pastes (for example, screen printed dopant pastes).
  • dopant pastes for example, screen printed dopant pastes.
  • the emitter doping is not abutting the base contact doping and is separated by the background bulk doping of the base.
  • Step 2 shows the deposition of the emitter followed by a cap.
  • the emitter source is shown to be an APCVD deposited boron doped A1203, it may also be a boron doped Si02 layer or another dopant source layer deposited using different means.
  • the first laser ablation (Step 3) is to open up the separation between emitter and base doping such that upon anneal, there is a separation between the junctions.
  • Step 5 is a contact open within the base window for base contact as well as a contact open for the emitter.
  • Both contacts are opened up in the same step - hence the method of printing the dopant source should be a selective print on top of these contacts such as screen printing of the dopant paste (as compared to a blanket deposition of a thin dopant sourced film).
  • the dopant source is either wet etched or etched selectively using HF vapor.
  • the etching step may be skipped (Step # 8).
  • the contacts can be opened sequentially.
  • either base or emitter contact is opened first and the corresponding paste is printed and dried.
  • the other contact is opened and the corresponding paste is printed and dried. Finally, both pastes are driven in at the same time. This alternative may avoid cross contamination in the
  • Steps 3 and 4 may be skipped and contacts can be directly opened for both base and emitter.
  • the field area may be capped by a thin film which is resistant to the dopant source etchant chemistry.
  • the dopant source is
  • the cap layer may be APCVD based A1203 (undoped or doped) or titanium oxide (Ti02) or amorphous silicon (a-Si).
  • Table 13 shows a front end separated junction self aligned solar cell process flow using only APCVD deposited films which serves as dopant sources. This flow follows the same steps as Table 12 (with all the variations described above) until Step 4. At Step 5, only one type of contact is opened first. In this case it is the emitter contact (for an n- type back contact cell). This is followed by an APCVD BSG film which is the dopant source for emitter contact doping (Step 6). Next, the base contact is opened and PSG is deposited using APCVD. In a variation, the sequence of emitter and base contact open can be reversed. An abutted version of the separated junction flow described in Table 13 skips/removes Steps 3 and 4 to create abutted junctions.
  • Table 14 below shows a front end separated junction self-aligned process flow using a hybrid approach.
  • one of the dopant source is a deposited APCVD film while the other type of dopant source is a printed dopant paste.
  • Step 5 of Table 14 the emitter contact is opened.
  • BSG is deposited in Step 6 and Step 7 opens base contact with a laser (note, although, the flow suggests using ps lasers, nano or femto second lasers with different wavelengths are not precluded as long as they meet the contact open requirements).
  • phosphorous based dopant paste is printed, dried in Step 8.
  • Step 9 is an anneal step to drive the dopants from the BSG and from the phosphorous paste to create under-contact doped areas, while step 10 removes the dopant sources based on either wet or HF vapor technique.
  • An abutted version of the separated junction flow described in Table 14 skips/removes Steps 3 and 4 to create abutted junctions.
  • Step 6 the sequence of BSG2 (Step 6) and phosphorous dopant paste (Step 8) is reversed. Base contact is opened first, followed by phosphorous paste. This is in turn followed emitter contact and BSG2 deposition and the remaining flow is similar.
  • the hybrid dopant sources are based on APCVD PSG and dopant paste boron such that the base contact is made with the APCVD deposited doped Si02 film while the emitter contact is made using boron based dopant paste.
  • This variation has further variations where the sequence of contact open and its accompanying dopant source has two possibilities.
  • Table 15 below is a front end process flow showing a variation of the hybrid approach of Table 14 where both dopant paste and doped dielectric films are used as a source of dopants for base and emitter under contact doping.
  • both emitter and the base contacts are separated by APCVD-PSG and diffusion anneal. This is done to reduce the risk of dopant co-diffusion during diffusion anneal.
  • Co-diffusion is a process when dopant source from base or emitter contact diffusion areas (phos or boron) from dopant paste (phos or boron) moves into other polarity (base or emitter) through gaseous phase. This process may avoided, for example, by putting a solid phase dopant sources
  • the paste is phosphorous and the base is opened first (for an n-type back contact cell) and in a variation the paste is the boron paste and the emitter is opened first.
  • a variation of the Table 15 process flow forms abutted junctions by skipping Steps 3 and 4 as shown in Table 16 below. As throughout this disclosure, the variations described in conjunction with Table 15 are equally applicable with the abutted junction flow.
  • the co-diffusion risk may be avoided by eliminating either APCVD-PSG or eliminating diffusion anneal.

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Abstract

L'invention concerne, selon un aspect, un procédé permettant de former des contacts auto-alignés pour des cellules solaires à jonction arrière et contact arrière à îlot monolithique.
PCT/US2014/072299 2013-12-23 2014-12-23 Contacts auto-alignés pour des cellules solaires à jonction arrière et contact arrière à îlot monolithique WO2015100392A2 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017216453B4 (de) 2017-09-18 2024-02-22 Robert Bosch Gmbh Kontaktanordnung mit einem Halbleiter und Verfahren zu deren Herstellung

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017216453B4 (de) 2017-09-18 2024-02-22 Robert Bosch Gmbh Kontaktanordnung mit einem Halbleiter und Verfahren zu deren Herstellung

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