WO2012159490A1 - 一种闪存错误预估模块及其预估方法 - Google Patents

一种闪存错误预估模块及其预估方法 Download PDF

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Publication number
WO2012159490A1
WO2012159490A1 PCT/CN2012/072955 CN2012072955W WO2012159490A1 WO 2012159490 A1 WO2012159490 A1 WO 2012159490A1 CN 2012072955 W CN2012072955 W CN 2012072955W WO 2012159490 A1 WO2012159490 A1 WO 2012159490A1
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flash
error
level
programming
flash memory
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PCT/CN2012/072955
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English (en)
French (fr)
Inventor
邢冀鹏
霍文捷
张�杰
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忆正科技（武汉）有限公司
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Application filed by 忆正科技（武汉）有限公司 filed Critical 忆正科技（武汉）有限公司
Priority to US14/119,121 priority Critical patent/US9047212B2/en
Priority to JP2014511714A priority patent/JP6048497B2/ja
Publication of WO2012159490A1 publication Critical patent/WO2012159490A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

Definitions

  • the present invention relates to the field of data storage, and in particular to a prediction technique for a flash memory error correction process. Background technique
  • a memory cell in a flash memory device records logic information by injecting electrons into the floating gate, and the memory cell also determines the logic held in the floating gate by reading the threshold voltage.
  • a flash device is erased many times, its device characteristics are degraded, resulting in a shortened programming time of the flash memory and an extended erase time.
  • Flash devices are also accompanied by various parasitic effects during operation, resulting in errors in the data stored in the flash device.
  • the main causes of error are: programming disturbance, read disturbance, pass disturbance and floating gate coupling effect.
  • the memory cells on the same bit line need to be connected with a higher pass voltage to make the flash memory cells turn on. Repeated writes can cause unexpected writes to the cells on the bit line, that is, through disturbances.
  • the flash array When the flash device performs multiple read operations, the flash array will be turned on repeatedly, accumulating electrons on the channel of the flash memory cell. If the accumulated electrons reach the write threshold of the flash memory cell, an accidental write operation will occur to the memory location of the flash memory.
  • the disturbance affects the correctness of the data stored by the SSD, and severe disturbances can also reduce the life of the flash device.
  • the floating gate coupling effect can also cause serious errors.
  • the density of the device continues to increase, causing a change in the floating gate threshold voltage of a single memory cell to affect the voltage of its adjacent cells, causing unexpected level shifts and errors.
  • a change in the floating gate voltage of a memory cell in the flash array can disturb the floating gate of the surrounding memory cells, causing the data stored in the surrounding memory cells to be accidentally flipped.
  • the technical problem to be solved by the present invention is to provide a flash memory error estimation module and a prediction method thereof, which provide a reliable calculation basis for the error correction algorithm of the flash memory and improve the error correction performance of the system.
  • the present invention firstly proposes a flash memory error estimation module, which is characterized in that the estimation module is mainly composed of a timer, a quantization index table, a storage page table, and an error index table.
  • the timer is used to record the programming time or erasing time of the flash memory, and the programming time or erasing time collected by the timer is used as an input of the quantization index;
  • the quantization index table is used to record a mapping relationship between a programming level and a programming time, a mapping relationship between an erasing level and an erasing time; an erasing level represents a life state of a flash block corresponding to the physical address, a programming level Representing the life state of the internal page of the flash block;
  • the storage page table includes a plurality of consecutive storage units, each of the consecutive storage units is configured to record an erase level and a programming level of a flash block, wherein an erase level of the flash block is saved at a beginning of the continuous storage unit.
  • the programming level of each page in the flash block is sequentially stored in the continuous storage unit;
  • the error index table includes a block error index table and a page fault index table, a block error index table records an erase level and a corresponding block error rate mapping relationship, a page error index table records a program level, and a corresponding page error rate. Mapping relationship;
  • the flash error estimation module receives the timing information sent by the flash controller, the enable signal or the R/B signal from the flash chip as an input, and outputs an error estimate to the error check module. Based on the above-mentioned flash error estimation module, the present invention also proposes a flash error estimation method of the flash error estimation module, which is characterized by comprising the following specific steps:
  • the timer of the estimation module collects the erasure time of the current flash operation block; when the flash memory is programmed, the programming time of the current flash operation page is acquired;
  • the estimation module quantizes the erase time to an erase level and quantizes the programming time to a program level.
  • the flash controller When the flash controller operates the flash memory, requesting the estimation module to perform an error estimation on the operated physical address; reading, by the estimation module, the programming level of the corresponding physical address and erasing from the storage page table The level, and the number of estimated errors converted to the corresponding page by the error index table, thereby completing the estimation operation.
  • the present invention utilizes specific physical signals in a flash memory device to pre-estimate the error rate of the flash memory to provide a suitable error estimate for the error correction algorithm of the flash memory. It is suitable for applications in which a flash memory device is used as a storage medium for a solid-state hard disk controller, a flash memory controller, etc., and the reliability of the flash memory device is greatly improved.
  • the most basic operating unit in a flash device is a page, and the flash controller can program or read the page; in a flash device, a plurality of pages form a block, and the smallest unit of the erase operation is a block in the flash device.
  • the flash controller records the time taken for the erase operation; when the page in the flash is programmed, the flash controller also monitors the programming time of the flash device.
  • the erase time and programming time in flash memory are related to the number of operations of the device. As the number of flash erases increases, the erase time becomes longer, as shown in Figure 1, and the programming time is gradually reduced, as shown in Figure 2.
  • the reason for this phenomenon is that the erase operation causes the physical characteristics of the flash memory to decay, causing the threshold voltage of the device to rise.
  • the raised threshold voltage causes the flash memory to be easier to program during operation, and the erase operation is more difficult.
  • the erase time and programming time of the flash block truly reflect the overall usage of the flash block.
  • the increased threshold voltage also means that the physical parasitics of the device will be more pronounced, resulting in a false increase in flash memory. Thus, errors in the I flash memory can be pre-empted by monitoring the erase time and programming time.
  • the estimation module is embedded in the flash controller, and the obtained estimation information is sent to the verification module in the flash controller.
  • the flash chip and the flash controller exchange data through the data bus and are controlled by the flash controller module of the flash controller; and a set of R/B signals in the interface of the flash chip are used to indicate the working state of the flash memory.
  • the level of the R/B signal will enter the active state, indicating flash The deposit is currently busy and will not respond to new operations.
  • the R/B signal will re-enter the inactive state, indicating that the flash is in an idle state.
  • the estimation module When the flash controller operates on the flash device, the estimation module counts the effective time of the R/B signal in the flash device to obtain the time overhead spent by the flash in programming or erasing operations to help estimate the module. Estimate errors in flash devices. The estimated error made by the estimation module is sent to the verification module, which verifies the error of the programming or erasing operation of the flash memory.
  • the estimation module can also perform timing in conjunction with the flash controller.
  • the flash controller can continually send a "read status" command to the flash to understand the operating state of the flash.
  • the flash controller will calculate the time spent by the flash memory during the erasing or programming operation according to the change status of the working state before and after the flash memory is completed, and send the obtained timing information to the estimation module, thereby helping the pre-processing.
  • the evaluation module completes the timing work.
  • the estimation module is mainly composed of a timer, a quantization index table, a storage page table, and an error index table, and its structure is as shown in FIG. 4.
  • the controller When the controller operates on the flash memory, the controller inputs an enable signal, activates the timer in the estimation module, and begins recording the effective working time of the flash memory.
  • the recorded programming time or erasing time is quantized into a program level or an erase level in the quantization index table and stored in the memory page table according to the physical address.
  • the controller needs to perform an error correction operation, the program level and the erasure level of the corresponding physical address are read from the memory page table, and the estimated number of errors is converted to the corresponding page by the error index table, thereby completing the estimation operation.
  • the program time or erase time collected during operation is not convenient to save. Therefore, the estimation module needs to quantify the programming time and the erase time, and quantize the continuous time into discrete time levels to facilitate the prediction module.
  • the collected data is indexed and saved.
  • the quantization process is implemented by a quantitative index table, as shown in Figure 5.
  • the program time or erase time collected by the timer is used as an input to the quantization index.
  • the quantization index records the mapping relationship between the programming level and the programming time, and the mapping relationship between the erasure level and the erasure time.
  • the quantization index will look up the quantization level corresponding to the input time, thus quantizing the time.
  • the quantized programming level and erasure level need to be saved in the manner shown in Figure 6. Erase, etc.
  • the level and programming level correspond to the physical address
  • the erasure level represents the lifetime of the flash block corresponding to the physical address
  • the programming level represents the page lifetime within the flash block.
  • the storage page table saves the erasure level of the block at the beginning of the storage unit corresponding to the physical address, and then stores the page table in which the program level of each page is sequentially stored in the storage unit. .
  • the estimation module needs to convert the programming level or erasure level of the physical address to the estimated number of errors for the block or page.
  • the estimated module error index table implements the conversion from time level to error number, as shown in Figure 7.
  • the error index table consists of two parts: a block error index and a page fault index. Block Error The index is responsible for converting the erase level of the block; the page fault index is responsible for translating the program level of the page. The contents of the error index table are previously completed by an offline experiment.
  • the flash controller gets the estimated error of the corresponding block as needed, or the estimated error of the page.
  • the estimation module When the flash controller operates on the flash memory, an error estimate of the physical address being manipulated is requested from the estimation module.
  • the operation flow of the estimation module for estimating operation is shown in Figure 8.
  • the prediction module After the prediction module starts working, it enters the timing step to capture the erase time of the current flash operation block when the flash is erased; when the flash is programmed, the programming time of the current flash operation page is acquired.
  • the quantization step is entered, and the estimation module queries the quantization index table, and the estimation module quantizes the erasure time into an erasure level, quantizes the programming time into a program level, and sets the current erasure level, the programming level, and the second.
  • the corresponding physical address is stored in the storage page table.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

本发明涉及数据存储领域，具体涉及到一种闪存纠错过程的预估技术。本发明提供了一种闪存错误预估模块及其错误预估方法，所述预估模块主要由计时器、量化索引表、存储页表以及错误索引表构成。所述闪存错误预估方法，建立擦写与编程的错误先验数据，利用闪存器件中特定的物理信号来预先估计闪存存储器的错误率，为闪存的纠错算法提供合适的错误估计。本发明适合应用于固态硬盘控制器、闪存控制器等以闪存器件为存储介质的场合中，提高闪存器件的可靠性。

Description

一种闪存错误预估模块及其预估方法 技术领域
本发明涉及数据存储领域， 具体涉及到一种闪存纠错过程的预估技术。 背景技术
闪存器件中的存储单元通过向浮栅中注入电子的方式来记录逻辑信息， 同 时存储单元还通过读取阀值电压来判断浮栅中保存的逻辑。 当闪存器件经过多 次地擦写之后， 其器件特性衰退， 导致闪存的编程时间缩短， 而擦除时间延长。
闪存器件在操作的过程中， 还伴随着各种寄生效应， 从而导致闪存器件保 存的数据发生错误。 其中， 最主要的错误原因为： 编程扰动、 读扰动、 通过扰 动以及浮栅耦合效应。 当闪存器件进行编程操作时， 闪存控制器将抬高字线
(Word l ine)上的电压， 这将导致字线上相邻的存储单元产生意外写动作， 即编 程扰动。 而在位线 (Bit l ine)方向上， 同一位线上的存储单元需要加上较高的 通过电压， 使闪存存储单元导通。 反复的写操作会导致位线上的单元发生意外 的写动作， 即通过扰动。 当闪存器件进行多次读操作时， 闪存阵列将会反复导 通， 在闪存存储单元的沟道上会累积电子。 若累积的电子达到闪存存储单元的 写阈值时， 会使闪存的存储单元发生意外写操作。 这里， 扰动会影响固态硬盘 保存的数据正确性， 严重的扰动还会降低闪存器件的使用寿命。 除此以外， 浮 栅耦合效应也会带来严重的错误。 当闪存工艺不断进步时， 器件的密度不断增 加， 从而导致单一存储单元的浮栅阀值电压的变化对其临近单元的电压产生影 响， 造成意外的电平移动， 产生错误。 闪存阵列中某一存储单元的浮栅电压变 化会对周围存储单元的浮栅造成扰动， 从而导致周围存储单元中保存的数据发 生意外翻转。
闪存器件中所存在的各种扰动和耦合效应严重干扰了闪存中所保存的数 据， 在实际使用的过程中需要纠错算法对闪存中存储的数据进行保护。 然而， 闪存控制器在利用诸如低密度校验编码等先进校验编码技术展开纠错之前， 必 须要对信道中的错误进行合理预估。 因而， 闪存控制器需要对闪存的错误预估 技术。 发明内容
本发明所要解决的技术问题是提供一种闪存错误预估模块及其预估方法， 为闪存的纠错算法提供可靠的计算依据， 提高系统的纠错性能。
为解决上述技术问题， 本发明首先提出了一种闪存错误预估模块， 其特 征在于， 所述预估模块主要由计时器、 量化索引表、 存储页表以及错误索引 表构成，
所述计时器用于记录闪存的编程时间或擦除时间， 计时器收集的编程时 间或擦除时间作为量化索引的输入；
所述量化索引表用于记录编程等级与编程时间之间的映射关系， 擦除等 级与擦除时间之间的映射关系； 擦除等级代表该物理地址所对应的闪存块的 寿命状态， 编程等级代表所述闪存块内部页的寿命状态；
所述存储页表包括若干个连续存储单元， 每个连续存储单元用于记录一 个闪存块的擦除等级、 编程等级， 其中， 该闪存块的擦除等级保存在所述连 续存储单元的开头， 该闪存块内各个页的编程等级依次存放在所述连续存储 单元内；
所述错误索引表包含块错误索引表和页错误索引表两个部分， 块错误索 引表记录擦除等级以及对应的块错误率的映射关系， 页错误索引表记录编程 等级以及对应的页错误率的映射关系；
所述闪存错误预估模块接收闪存控制器发来的计时信息、 使能信号或闪 存芯片发出的 R/B信号作为输入， 输出错误预估值到错误校验模块。 基于上述闪存错误预估模块，本发明还提出了该闪存错误预估模块的闪存错 误预估方法， 其特征在于， 包括以下具体步骤：
对闪存器件进行擦除和编程操作的压力实验， 记录擦除和编程的时间变 化以及闪存器件的错误的经验数据； 并建立所述量化索引表、 错误索引表， 作为预估模块进行错误预估的先验参照表；
所述预估模块的计时器采集当前闪存操作块的擦除时间； 在闪存进行编 程时， 采集当前闪存操作页的编程时间；
通过查询所述量化索引表， 预估模块将擦除时间量化为擦除等级， 将编 程时间量化为编程等级，
将当前擦除等级、 编程等级以及二者对应的物理地址， 保存在所述存储 页表中；
在闪存控制器对闪存进行操作时， 向所述预估模块请求对所操作的物理 地址进行错误预估； 由预估模块从所述存储页表中读取相应物理地址的编程 等级以及擦除等级， 并通过所述错误索引表转换为相应页的预估错误数目， 从而完成预估操作。
本发明利用闪存器件中特定的物理信号来预先估计闪存存储器的错误 率， 为闪存的纠错算法提供合适的错误估计。 适合应用于固态硬盘控制器、 闪存控制器等以闪存器件为存储介质的场合中， 大大提高了闪存器件的可靠 性。 附图说明
下面结合附图和具体实施方式对本发明的技术方案作进一步具体说明。 图 1. 闪存器件编程时间的变化规律。
图 2. 闪存器件擦除时间的变化规律。
图 3. 预估模块接口示意图。
图 4. 预估模块内部结构图。
图 5. 操作时间索引表。
图 6. 操作时间存储结构表。
图 7. 错误查询索引表。
图 8. 预估操作流程图。 具体实施方式
闪存器件中最基本的操作单元是页， 闪存控制器可以对页进行编程或者 读取操作； 在闪存器件内部由多个页又组成一个块， 擦除操作的最小单位是 闪存器件中的块。 当闪存器件中的块进行擦除操作时， 由闪存控制器记录擦 除操作所花费的时间； 当闪存中的页进行编程操作时， 闪存控制器还将监控 闪存器件的编程时间。
闪存中的擦除时间和编程时间与器件的操作次数存在关联性。 随着闪存 擦写次数的增加， 其擦除时间逐渐变长， 如图 1所示， 而编程时间则逐渐缩 短， 如图 2所示。 造成这种现象的原因在于： 擦写操作造成闪存物理特性衰 退， 使器件的阈值电压升高了。 升高的阈值电压会导致闪存在操作过程中， 编程操作更加容易， 而擦写操作更加困难。 闪存块的擦除时间和编程时间真 实地反映了闪存块的整体使用情况。 升高的阈值电压同时也意味着器件的物 理寄生效应会更加显著， 从而导致闪存的错误增加。 因而， 可以通过对擦除 时间和编程时间的监控来预须 I闪存中的错误。
在闪存控制器中采用擦除时间和编程时间进行预估之前， 需要事先了解 闪存器件擦除时间和编程时间的变化趋势， 以及擦除时间和编程时间与闪存 的错误的关联。 这个关联可以通过对闪存器件的压力实验实现。 在压力实验 中， 对闪存器件不断进行擦除和编程操作， 记录擦除和编程的时间变化情况 以及闪存器件的错误情况。 通过对经验数据收集、 整理和分析， 建立擦除和 编程时间变化的表格、 编程时间与错误率的对应表格， 以及擦除时间与错误 率的对应表格， 作为预估模块进行预估操作的先验参考数据。
如图 3所示的预估模块接口示意图， 预估模块嵌入于闪存控制器中， 并 将所得到的预估信息发送给闪存控制器中的校验模块。 闪存芯片与闪存控制 器之间通过数据总线进行数据交换， 并由闪存控制器的闪存接口模块进行控 制； 而在闪存芯片的接口中有一组 R/B信号用来指明闪存的工作状态。 当闪 存在进行编程以及擦除操作时， R/B信号的电平将会进入有效状态， 表明闪 存目前正处于忙碌状态， 不会响应新的操作。 当操作结束以后， R/B信号将 重新进入无效状态， 表明闪存进入空闲状态。 当闪存控制器对闪存器件进行 操作时， 由预估模块对闪存器件中 R/B信号的有效时间进行计时， 从而获得 闪存在编程或者擦除操作中所花费的时间开销， 以帮助预估模块对闪存器件 的错误进行预估。 预估模块作出的预估错误发送到检验模块， 检验模块对闪 存的编程或者擦除操作进行错误检验。
除了采用 R/B信号进行直接计时的方法以外， 预估模块还可以通过与闪 存控制器相配合的方式完成计时。 当闪存在进行擦除或者编程操作时， 闪存 控制器可以不断地向闪存发送 "读状态"命令， 以了解闪存的工作状态。 闪 存控制器将根据查闪存完成操作前后， 工作状态的变化状况， 统计出闪存在 擦除或者编程操作时所花费的时间开销， 并将所得到的计时信息， 发送给预 估模块， 从而帮助预估模块完成计时工作。
预估模块主要由计时器、 量化索引表、 存储页表以及错误索引表构成， 其结构如图 4所示。 当控制器对闪存进行操作时， 由控制器输入使能信号， 激活预估模块中的计时器， 开始对闪存的有效工作时间进行记录。 所记录的 编程时间或擦除时间， 将在量化索引表中量化为编程等级或擦除等级， 并根 据物理地址保存在存储页表中。 当控制器需要进行纠错操作时， 从存储页表 中读取相应物理地址的编程等级以及擦除等级， 并通过错误索引表转换为相 应页的预估错误数目， 从而完成预估操作。
在操作中所收集的编程时间或擦除时间不便于保存， 因此， 预估模块需 要对编程时间以及擦除时间进行量化操作， 将连续的时间量化为离散的时间 等级， 以方便预估模块将收集的数据进行索引和保存。 量化过程通过量化索 引表予以实现， 如图 5所示。 由计时器收集的编程时间或擦除时间作为量化 索引的输入。 量化索引中记录有编程等级与编程时间之间的映射关系， 以及 擦除等级与擦除时间之间的映射关系。 量化索引将会查找输入的时间所对应 的量化等级， 从而对时间进行了量化处理。
量化后的编程等级和擦除等级需要以图 6所示的方式予以保存。 擦除等 级与编程等级同物理地址相对应， 擦除等级代表物理地址所对应的闪存块的 使用寿命， 而编程等级则表征闪存块内部的页使用寿命。 当闪存的一个块内 部包含 256个页时， 则存储页表将块的擦除等级保存在该物理地址所对应存 储单元的开头， 接下来存储页表在该存储单元依次存放各个页的编程等级。
在闪存控制器对闪存进行操作时， 向预估模块请求对所操作的物理地址 的错误预估。 预估模块需要将该物理地址的编程等级或擦除等级转换为块或 页的预估错误数。 预估模块错误索引表实现时间等级到错误数的转换， 如图 7 所示。 错误索引表包含两个部分构成： 块错误索引和页错误索引。 块错误 索引负责将块的擦除等级进行转换； 页错误索引负责将页的编程等级进行转 换。 错误索引表中的内容事先通过离线实验完成。 闪存控制器根据需要获取 相应的块的预估错误， 或者是页的预估错误。
在闪存控制器对闪存进行操作时， 向所述预估模块请求对所操作的物理 地址的错误预估。 预估模块进行预估操作的操作流程如图 8所示。 在预估模 块开始工作以后， 进入计时步骤， 在闪存进行擦除时， 采集当前闪存操作块 的擦除时间； 在闪存进行编程时， 采集当前闪存操作页的编程时间。 计时完 成后， 进入量化步骤， 预估模块通过查询所述量化索引表， 预估模块将擦除 时间量化为擦除等级， 将编程时间量化为编程等级， 将当前擦除等级、 编程 等级以及二者对应的物理地址， 保存在所述存储页表中。 当控制器需要进行 纠错操作时，从所述存储页表中读取相应物理地址的编程等级以及擦除等级， 并通过所述错误索引表转换为相应页的预估错误数目， 从而完成预估操作。
最后所应说明的是， 以上具体实施方式仅用以说明本发明的技术方案而 非限制， 尽管参照较佳实施例对本发明进行了详细说明， 本领域的普通技术 人员应当理解， 可以对本发明的技术方案进行修改或者等同替换， 而不脱离 本发明技术方案的精神和范围， 其均应涵盖在本发明的权利要求范围当中。

Claims

权 利 要 求 书
1、一种闪存错误预估模块， 其特征在于， 所述预估模块主要由计时器、 量化索引表、 存储页表以及错误索引表构成，
所述计时器用于记录闪存的编程时间或擦除时间， 计时器收集的编程 时间或擦除时间作为量化索引的输入；
所述量化索引表用于记录编程等级与编程时间之间的映射关系， 擦除 等级与擦除时间之间的映射关系； 擦除等级代表该物理地址所对应的闪存 块的寿命状态， 编程等级代表所述闪存块内部页的寿命状态；
所述存储页表包括若干个连续存储单元， 每个连续存储单元用于记录 一个闪存块的擦除等级、 编程等级， 其中， 该闪存块的擦除等级保存在所 述连续存储单元的开头， 该闪存块内各个页的编程等级依次存放在所述连 续存储单元内；
所述错误索引表包含块错误索引表和页错误索引表两个部分， 块错误 索引表记录擦除等级以及对应的块错误率的映射关系， 页错误索引表记录 编程等级以及对应的页错误率的映射关系；
所述闪存错误预估模块接收闪存控制器发来的计时信息、 使能信号或 闪存芯片发出的 R/B信号作为输入， 输出错误预估值到错误校验模块。
2、 一种根据权利要求 1所述的闪存错误预估模块的闪存错误预估方法， 其特征在于， 包括以下具体步骤：
对闪存器件进行擦除和编程操作的压力实验， 记录擦除和编程的时间 变化以及闪存器件的错误的经验数据； 并建立所述量化索引表、 错误索引 表， 作为预估模块进行错误预估的先验参照表；
所述预估模块的计时器采集当前闪存操作块的擦除时间； 在闪存进行 编程时， 采集当前闪存操作页的编程时间；
通过查询所述量化索引表， 预估模块将擦除时间量化为擦除等级， 将 编程时间量化为编程等级， 将当前擦除等级、 编程等级以及二者对应的物理地址， 保存在所述存 储页表中；
在闪存控制器对闪存进行操作时， 向所述预估模块请求对所操作的物理 地址的错误预估； 由预估模块从所述存储页表中读取相应物理地址的编程 等级以及擦除等级，并通过所述错误索引表转换为相应页的预估错误数目， 从而完成预估操作。
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