WO2012155300A1 - 一种调试龙芯cpu和南北桥芯片的方法和装置 - Google Patents
一种调试龙芯cpu和南北桥芯片的方法和装置 Download PDFInfo
- Publication number
- WO2012155300A1 WO2012155300A1 PCT/CN2011/000875 CN2011000875W WO2012155300A1 WO 2012155300 A1 WO2012155300 A1 WO 2012155300A1 CN 2011000875 W CN2011000875 W CN 2011000875W WO 2012155300 A1 WO2012155300 A1 WO 2012155300A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- cpu
- debugging
- bus
- chip
- loongson cpu
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
Definitions
- the invention relates to a computer motherboard design. Specifically, a method and a device for debugging a Loongson CPU and a Northbridge and a Southbridge chip are provided, and a north-south bridge combination with a Loongson CPU is obtained. Background technique
- the Godson-3 series CPUs include 4 core 3A, 8 core 3B, 16 core 3C CPUs, and other series of CPUs developed in the future.
- the Godson-3 CPU is a general-purpose multi-core CPU. It adopts the MIPS architecture and can fully implement the functions of Intel and AMD X86 CPUs. Although it is slightly behind the X86 CPU in performance, it can be completely replaced in most areas. X86 CPU.
- Loongson 3A and 3B CPUs have been available, they have not solved the key problem of "use", that is, they have not found the north and south bridge chipsets and peripherals that are compatible with the Loongson CPU.
- the possibility of "Godson 3 CPU + SIS chipsets” and “Godson 3 CPU + NVIDIA company chipsets” was discussed, and the motherboard samples were developed, but it was not successful.
- the Godson 3 series CPU is limited to technical protection and cannot share the success of the X86 CPU, so bugs are inevitable.
- the conventional debugging method a chipset is used as a motherboard, and it takes at least 2 months to design and process a motherboard. If the debugging time is added, at least one motherboard is tried. Need to spend 6 Months of time are not only costly but also time consuming. Moreover, the current debugging method cannot debug multiple chipsets at the same time, and it is necessary to make a variety of different motherboards.
- FPGA Field Programmable Gate Array
- FPGA Field Programmable Gate Array
- a method for debugging a Loongson CPU and a North-South bridge chip comprising the following steps:
- the debugging Loongson CPU detects whether the stitch signal in the debugging device conforms to the user manual.
- the dragon core CPU pin signal has a bug, it can be adjusted to a standard signal in the debugging device. More preferably, the adjustment to the standard signal is implemented by writing a program in the debugging device.
- the program is written in the verilog language.
- the debugging device comprises an HT bus interface.
- the debugging device connects the Loongson CPU and the Northbridge chip through the HT bus interface.
- the debugging device is connected to the south bridge chip through the HT control line.
- the debugging device strobes the HT bus of the Loongson CPU and only one north bridge and one south bridge during debugging, and shields other north bridges and south bridge chips.
- the HT bus is successfully debugged, and if the connection is successful, the other pins are continuously debugged; if not, the next south bridge or the north bridge chip is strobed.
- the Loongson CPU will adopt a 16-bit HT bus operating mode.
- the Loongson CPU shields the high 8-bit HT control line in the 8bits*2 mode of operation during operation with the adapted south bridge chip.
- the Loongson CPU is connected to the South Bridge chip HT control line through a low 8-bit HT control line in operation with the adapted South Bridge chip. More preferably, the Loongson CPU shields the high 8-bit HT control line in the 8bi ts*2 mode of operation during operation with the adapted Northbridge chip.
- the Loongson CPU is connected to the Northbridge chip HT control line through a low 8-bit HT control line in operation with the adapted Northbridge chip.
- the Loongson CPU operates in a slave mode in operation with an adapted Northbridge chip.
- pins that are not explicitly defined and non-corresponding pins are introduced into the FPGA chip for debugging or connection.
- the undefined pin and the uncorrelated pin include an upper and lower electric timing signal and a configuration signal.
- the north bridge chip capable of adapting the Loongson series CPU comprises RS780, RS780C,
- Southbridge includes SB600,
- a device for debugging a Loongson CPU and a North-South bridge chip comprising an FPGA chip, an HT bus interface, and
- the HT bus interface switch the device is connected to the HT bus of the Loongson CPU and the Northbridge chip through the HT bus interface, and the device is connected to the South Bridge chip through the HT control line and the power-up and timing signal line.
- the Loongson CPU and the Northbridge chip are directly introduced into the FPGA chip.
- the device can shape the signal when there is a problem with the HT bus signal of the Loongson CPU.
- the shaping is implemented by writing a program in the veri log language on the FPGA chip.
- the HT bus and the south bridge HT control line of the Loongson CPU and the debugged North Bridge chip are turned on during debugging, and the HT bus of the remaining north and south bridge chips is turned off.
- the south bridge or the north bridge is unsuccessful, the next south bridge or north bridge chip HT bus switch is turned on.
- pins that are not explicitly defined and non-corresponding pins are introduced into the FPGA chip for debugging or connection.
- the undefined pin and the non-corresponding pin include a power up and down timing signal and a configuration signal.
- the device generally includes five HT interfaces, one of which is used to connect the Loongson CPU, and four of which are connected to the four Northbridge chips.
- the HT bus of the Loongson CPU does not satisfy the standard protocol, it can locate the problem of the signal and direct the advancement of the Loongson CPU.
- the isolation of the FPGA can shield the discovered bugs, so that the debugging can still proceed smoothly, instead of halfway, with great flexibility, saving time and cost.
- the FPGA can flexibly change its behavior to meet the design requirements, and it is very flexible without re-modifying the design.
- FPGA to write multiple sets of HT bus interfaces, multiple chipsets can be connected to the Loongson CPU, enabling multiple chipsets to be debugged simultaneously on one motherboard.
- the Loongson CPU needs to be debugged with a group of chipsets, the connection with other chipsets is broken, and the switching flexibility saves time and cost.
- the north bridge chip matched with the Godson 3 CPU includes RS780, RS780C, RS780D, RS780E, RS780G, RS780M, RS780MC, RX781, RS785G and RD790, and the south bridge includes SB700, SB710, SB750, SB600.
- Figure 1 is the Godson motherboard architecture
- Figure 3 shows the connection between the Godson CPU and the AMD chip reset and power management signals.
- the invention uses FPGA to write multiple sets of HT bus interfaces, and introduces important, undefined, and unreasonable signal lines to the FPGA, so that the Godson CPU Different chipsets of different companies are connected to the FPGA to realize debugging of multiple chipsets on one motherboard at the same time.
- the invention uses a debugging device including five HT interfaces as an example, and can debug four sets of north and south bridges at the same time.
- One of the HT interfaces is used to connect to the Loongson CPU, and the other four are connected to the Northbridge chip.
- the Southbridge chip is connected to the test unit via the HT control line. When a chip cannot be connected, the switch of the next chip can be turned on.
- connection signal lines data, address, control, and clock
- reset and initialization signal lines reset and initialization signal lines
- power management signal lines power management signal lines
- Godson 3 CPU and North Bridge are one-to-one correspondence, that is, there are 16 pairs of receiving differential signal lines, 2 pairs of receiving signals, clock differential pairs, 2 pairs of receiving control signals, and 16 pairs of differential signals. 2 pairs of transmit signal clock differential pairs, 2 pairs of transmit control signal differential pairs.
- the selected Northbridge HT bus complies with the standard HT bus protocol, but the HT bus of the Godson-3 CPU has some extra, special signals due to its unique design compared to the standard HT bus protocol. Correct processing of these special signals at the hardware layer and the protocol layer can not affect the normal working needs of the Loongson CPU itself, and is compatible with the North Bridge. It is a relatively important technical point.
- the signals PWROK, RESET#, LDTSTOP#, LDTREQ# have only one group, and the Godson HT bus interface signals have two groups corresponding to each other, they are HT—HI—POWEROK, HT HI—RSTn, HT_HI_LDT_STOPn, HT_HI_LDT_REQn, HT—LO—POWEROK, HT LO—RSTn, HT—LO—LDT—STOPn, HT—LO—LDT—REQn.
- These signals are specially made by Godson 3 The design characteristics of the CPU are determined.
- the Godson 3 CPU HT bus is 16-bit wide, but it has a unique design that can split the 16-bit wide bus into two independent 8-bit wide HT buses. Each 8-bit wide HT bus can be connected. Other CPUs or bridges. Signal HT_8x2 is used to determine whether to use HT 16bits or 2 discrete 8bits.
- HT—HI—HOSTMODE, HT—HI_RSTn, HT—HI_POWEROK, HT—HI—LDT—REQn, HT_Hl_LDT_STOPn are the signal lines of the high 8-bit HT bus
- HT—LO—HOSTMODE, HT—LO—RSTn, HT—LO—POWEROK, HT_LO—LDT—REQn, HT—LO_LDT—STOPn is the signal line of the low 8-bit HT bus. How to deal with these signals, how to interconnect with the North Bridge and the South Bridge is not standardized before the present invention, and the present invention introduces these signal lines into the FPGA.
- Godson-3 CPU and the Northbridge and Southbridge chips need to be introduced into the FPGA.
- This type of signal is mainly used to power up and down the timing signal line and configure the signal line.
- These signal lines include: 1) Godson No. 3 CPU system reset signal line SYSRESETN, PCI bus reset signal line PCI RESETN; 2) South bridge power-on signal line PWR_GOOD, North Bridge power-on signal line NB-PWRGD; 3) Module power-on enable signal and power OK signal PWRGOOD; 4) Godson 3 CPU configuration signal line GPIO signal line, memory clock frequency setting signal line, HT bus clock frequency setting signal line.
- the difficulty of the power-on and power-down sequence is: First, after the launch of the Godson 3 series CPU, there has been no practical verification, the CPU's own power-on and power-down sequence needs to be verified; Second, the Godson CPU—there is no matching North-South bridge chipset, how to and North-South The timing of the bridge's power-on and power-off is also unknown. By connecting the power module and the power-up and output timing control signals of the north and south bridge chips to the FPGA in this way, the timing of these signals can be adjusted as needed, and all attempts are made to meet the requirements.
- connection signal line of the HT bus of the Godson-3 CPU (40 pairs of differential pairs as described above) is introduced to the FPGA; the connection signal lines of the HT bus of different North Bridge chips of different companies are also introduced to the FPGA.
- HT bus special signal line HT-8x2 HT_HI_HOSTMODE, HT-HI-RSTn, HT-HI-POWEROK, HT-HI-LDT-REQn, HT-HI-LDT-STOPN, HT —LO—HOSTMODE, HT—LO—RSTn, HT—LO—POWEROK, HT LO—LDT—REQn, HT—LO_LDT—STOPn introduced to the FPGA
- Power-on and timing control signal lines are introduced to the FPGA. These signals include a) Godson-3 CPU system complex Bit signal line SYSRESETN, PCI bus reset signal line PCI-RESETN; b) South bridge power-on signal line PWR-GOOD, north bridge power-on signal line NB-PWRGD; c) power-on enable signal EN of each power supply module Power OK signal PWRGOOD;
- the configuration signal line is introduced to the FPGA.
- These signals include the Godson 3 CPU configuration signal line GPIO signal line, the memory clock frequency setting signal line, and the HT bus clock frequency setting signal line.
- the north bridge chip matched with the Godson 3 CPU includes RS780, RS780C, S780D, RS780E, RS780G, RS780M, RS780MC, RX781, S785G and RD790, and the south bridge includes SB700, SB710, SB750. , SB600 conclusions.
- the HT_8x2 signal is pulled down (Pull down), that is, the HT bus connected to the Godson 3 CPU and the AMD North Bridge is set to the 16-bit mode. Because the AMD North Bridge is a 16-bit HT bus, the Godson CPU needs to work with it.
- the interface signals of the high 8-bit HT bus (HT_HI_HOSTMODE, HT_HI_RSTn, HT_HI_POWEROK HT-HI-LDT-REQn, HT-HI-LDT-STOPn) are disabled by pulling low, and the protocol layer of the Godson CPU is set to use only the low 8bit.
- the interface signals of the HT bus (HT-LO-HOSTMODE, HT-LO-RSTn, HT-LO-POWEROK, HT-LO-LDT-REQn, HT-LO-LDT-STOPn) are controlled by the 16-bit HT bus. Because the Loongson CPU is in use with the AMD North Bridge interconnect, the 16bit HT bus is controlled as a whole.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Semiconductor Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/806,784 US9846625B2 (en) | 2011-05-16 | 2011-05-20 | Method and device for debugging a MIPS-structure CPU with southbridge and northbridge chipsets |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110126228.1 | 2011-05-16 | ||
CN201110126228.1A CN102214132B (zh) | 2011-05-16 | 2011-05-16 | 一种调试龙芯cpu和南北桥芯片的方法和装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012155300A1 true WO2012155300A1 (zh) | 2012-11-22 |
Family
ID=44745452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2011/000875 WO2012155300A1 (zh) | 2011-05-16 | 2011-05-20 | 一种调试龙芯cpu和南北桥芯片的方法和装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9846625B2 (zh) |
CN (1) | CN102214132B (zh) |
TW (1) | TWI516959B (zh) |
WO (1) | WO2012155300A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109614351A (zh) * | 2018-11-30 | 2019-04-12 | 中国人民解放军陆军工程大学 | 带有纠错和自动应答机制的并行总线串行互联扩展方法 |
US20210089419A1 (en) * | 2019-09-25 | 2021-03-25 | Alibaba Group Holding Limited | Debugging unit and processor |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102609040B (zh) * | 2012-01-12 | 2015-04-08 | 北京国基科技股份有限公司 | 一种面向加固的国产计算机及其安全bios工作方法 |
CN102768561B (zh) * | 2012-05-30 | 2015-02-04 | 曙光信息产业股份有限公司 | 一种双桥片主板冗余的设计方法 |
CN104298575B (zh) * | 2013-07-16 | 2018-08-03 | 鸿富锦精密电子(天津)有限公司 | 主板调试电路 |
CN104077220A (zh) * | 2014-06-10 | 2014-10-01 | 中标软件有限公司 | Mips架构操作系统内核的调试方法和装置 |
CN108536643A (zh) * | 2018-03-30 | 2018-09-14 | 西安微电子技术研究所 | 一种高性能计算平台 |
CN109657474B (zh) * | 2018-11-30 | 2023-07-11 | 江苏航天龙梦信息技术有限公司 | 兼容独立安全卡的主板控制时序及上电时序控制方法 |
CN111124488A (zh) * | 2019-12-11 | 2020-05-08 | 山东超越数控电子股份有限公司 | 一种基于龙芯处理器的Debian系统移植方法 |
CN111258949A (zh) * | 2020-01-20 | 2020-06-09 | 江苏龙威中科技术有限公司 | 一种基于龙芯3a+7a+fpga的异构计算机模块 |
CN111506466B (zh) * | 2020-04-24 | 2022-08-02 | 卡斯柯信号有限公司 | 一种用于关键电压的交互冗余监控系统及方法 |
CN112988659B (zh) * | 2021-05-07 | 2021-07-20 | 湖南华自信息技术有限公司 | Pcie桥片冗余主板、设计方法以及计算机存储介质 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1818883A (zh) * | 2005-02-07 | 2006-08-16 | 中国科学院计算技术研究所 | 一种用于测试mips处理器的设备 |
US20070294055A1 (en) * | 2006-06-16 | 2007-12-20 | Via Technologies, Inc. | Debug device for detecting bus transmission and method thereof |
US20080005378A1 (en) * | 2006-05-19 | 2008-01-03 | Intel Corporation | Chipset determinism for improved validation |
US7319947B1 (en) * | 1999-12-22 | 2008-01-15 | Intel Corporation | Method and apparatus for performing distributed simulation utilizing a simulation backplane |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW514791B (en) * | 2001-05-28 | 2002-12-21 | Via Tech Inc | Structure, method and related control chip for accessing device of computer system with system management bus |
JP2006510967A (ja) * | 2002-12-18 | 2006-03-30 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Jtag機能を備えている複数の集積回路を有するシステムにおけるコードのダウンロード |
US7676600B2 (en) * | 2003-04-23 | 2010-03-09 | Dot Hill Systems Corporation | Network, storage appliance, and method for externalizing an internal I/O link between a server and a storage controller integrated within the storage appliance chassis |
US7565566B2 (en) * | 2003-04-23 | 2009-07-21 | Dot Hill Systems Corporation | Network storage appliance with an integrated switch |
CN100386709C (zh) * | 2003-06-06 | 2008-05-07 | 中国科学院计算技术研究所 | 一种龙芯-1cpu的网络计算机主板系统的复位方法 |
TW200401188A (en) * | 2003-09-16 | 2004-01-16 | Via Tech Inc | Debug device and method thereof |
US8000322B2 (en) * | 2004-07-30 | 2011-08-16 | Hewlett-Packard Development Company, L.P. | Crossbar switch debugging |
US7941585B2 (en) * | 2004-09-10 | 2011-05-10 | Cavium Networks, Inc. | Local scratchpad and data caching system |
CN1265264C (zh) * | 2004-09-21 | 2006-07-19 | 威盛电子股份有限公司 | 协调南北桥电路与cpu于不同节能状态的电路及方法 |
US7257654B1 (en) * | 2004-11-09 | 2007-08-14 | Advanced Micro Devices, Inc. | PCI bridge device configured for using JTAG scan for writing internal control registers and outputting debug state |
US7478299B2 (en) * | 2006-08-14 | 2009-01-13 | International Business Machines Corporation | Processor fault isolation |
US8074131B2 (en) * | 2009-06-30 | 2011-12-06 | Intel Corporation | Generic debug external connection (GDXC) for high integration integrated circuits |
US8661302B2 (en) * | 2010-11-17 | 2014-02-25 | Advanced Micro Devices, Inc. | Enhanced debug/test capability to a core reset process |
CN101989222B (zh) * | 2010-11-22 | 2012-10-03 | 连云港杰瑞深软科技有限公司 | 一种龙芯仿真器终端 |
US20120150474A1 (en) * | 2010-12-09 | 2012-06-14 | Advanced Micro Devices, Inc. | Debug state machine cross triggering |
-
2011
- 2011-05-16 CN CN201110126228.1A patent/CN102214132B/zh active Active
- 2011-05-20 WO PCT/CN2011/000875 patent/WO2012155300A1/zh active Application Filing
- 2011-05-20 US US13/806,784 patent/US9846625B2/en active Active
-
2012
- 2012-05-15 TW TW101117228A patent/TWI516959B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7319947B1 (en) * | 1999-12-22 | 2008-01-15 | Intel Corporation | Method and apparatus for performing distributed simulation utilizing a simulation backplane |
CN1818883A (zh) * | 2005-02-07 | 2006-08-16 | 中国科学院计算技术研究所 | 一种用于测试mips处理器的设备 |
US20080005378A1 (en) * | 2006-05-19 | 2008-01-03 | Intel Corporation | Chipset determinism for improved validation |
US20070294055A1 (en) * | 2006-06-16 | 2007-12-20 | Via Technologies, Inc. | Debug device for detecting bus transmission and method thereof |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109614351A (zh) * | 2018-11-30 | 2019-04-12 | 中国人民解放军陆军工程大学 | 带有纠错和自动应答机制的并行总线串行互联扩展方法 |
CN109614351B (zh) * | 2018-11-30 | 2022-05-24 | 中国人民解放军陆军工程大学 | 带有纠错和自动应答机制的并行总线串行互联扩展方法 |
US20210089419A1 (en) * | 2019-09-25 | 2021-03-25 | Alibaba Group Holding Limited | Debugging unit and processor |
US11755441B2 (en) * | 2019-09-25 | 2023-09-12 | Alibaba Group Holding Limited | Debugging unit and processor |
Also Published As
Publication number | Publication date |
---|---|
CN102214132B (zh) | 2014-07-02 |
US20140157051A1 (en) | 2014-06-05 |
TWI516959B (zh) | 2016-01-11 |
US9846625B2 (en) | 2017-12-19 |
TW201248422A (en) | 2012-12-01 |
CN102214132A (zh) | 2011-10-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2012155300A1 (zh) | 一种调试龙芯cpu和南北桥芯片的方法和装置 | |
US8656220B2 (en) | System-on-chip and debugging method thereof | |
CN107907814B (zh) | 一种提高芯片量产测试效率的方法 | |
WO2011009409A1 (zh) | Jtag设备及实现jtag数据传输的方法 | |
CN107066746B (zh) | 基于i2c接口通过cpld来实现pca9555功能的方法 | |
US10509595B2 (en) | System and method for communication in a semiconductor device | |
CN101420328A (zh) | 远程升级现场可编程门阵列的系统、接口卡及方法 | |
CN111901164A (zh) | Ocp nic网卡的适配控制方法、装置、设备及系统 | |
CN104102160A (zh) | 一种can总线信号收发解析工具 | |
WO2016184170A1 (zh) | Smi接口器件的调试装置及方法、存储介质 | |
CN111008102A (zh) | Fpga加速卡高速接口si测试控制装置、系统及方法 | |
CN203250308U (zh) | 内嵌于芯片的usb转jtag调试装置 | |
CN108153626B (zh) | 一种usb、串口复用与安全隔离系统 | |
CN107329863B (zh) | 一种基于COMe的测量仪器通用硬件平台 | |
JP2024508592A (ja) | Usbインタフェースの多重化方法、回路、電子機器及び記憶媒体 | |
CN115344105A (zh) | 接口复用的芯片和芯片的调试系统 | |
CN204028612U (zh) | 一种can总线信号收发工具 | |
CN103440194B (zh) | 一种调试龙芯cpu和南北桥芯片的装置 | |
CN209433397U (zh) | 多路usb信号切换装置 | |
Lin et al. | Design and implementation of OTG communication system terminal based on USB | |
CN207504888U (zh) | 多路车载CAN Note数据分析仪 | |
CN113485768B (zh) | 一种phy参数配置装置及ssd | |
TWI699101B (zh) | 基於邊界掃描的在線級聯加載韌體系統及其方法 | |
CN210428435U (zh) | 一种基于zigbee的无线控制多路SWD调试器 | |
CN202230470U (zh) | 一种调试龙芯cpu和南北桥芯片的装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11865548 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13806784 Country of ref document: US |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205N DATED 22/01/2014) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11865548 Country of ref document: EP Kind code of ref document: A1 |