WO2012148641A2 - Uv assisted silylation for recovery and pore sealing of damaged low k films - Google Patents

Uv assisted silylation for recovery and pore sealing of damaged low k films Download PDF

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WO2012148641A2
WO2012148641A2 PCT/US2012/032203 US2012032203W WO2012148641A2 WO 2012148641 A2 WO2012148641 A2 WO 2012148641A2 US 2012032203 W US2012032203 W US 2012032203W WO 2012148641 A2 WO2012148641 A2 WO 2012148641A2
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substrate
exposing
dielectric film
processing chamber
radiation
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WO2012148641A3 (en
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Bo Xie
Alexandros T. Demos
Kang Sub Yim
Thomas Nowak
Kelvin Chan
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Applied Materials Inc
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Applied Materials Inc
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Priority to KR1020137029732A priority patent/KR20140010449A/en
Priority to CN2012800121151A priority patent/CN103430291A/en
Publication of WO2012148641A2 publication Critical patent/WO2012148641A2/en
Publication of WO2012148641A3 publication Critical patent/WO2012148641A3/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/093Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/095Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by irradiating with electromagnetic or particle radiation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/093Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H10P14/6532Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • H10P14/6538Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light by exposure to UV light
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/665Porous materials

Definitions

  • the methods described generally relate to repairing and lowering the dielectric constant of low k films used in semiconductor fabrication.
  • the dielectric constant (k) of dielectric films in semiconductor fabrication is continually decreasing as device scaling continues. Minimizing integration damage on low dielectric constant (low k) films is important to be able to continue decreasing feature sizes. However, as feature sizes shrink, improvement in the resistive capacitance and reliability of dielectric films becomes a serious challenge.
  • Embodiments according to the present invention generally relate to methods for repairing and lowering the dielectric constant of low k films for semiconductor fabrication.
  • One method of repairing a damaged low k dielectric film includes alternatingly exposing a dielectric film to ultraviolet (UV) radiation and a silylation compound at least two times.
  • UV ultraviolet
  • Another method includes exposing a dielectric film to a silylation compound, depositing a layer of silicon oxide onto the dielectric film, and exposing the dielectric film and silicon oxide layer to ultraviolet (UV) radiation.
  • UV ultraviolet
  • Figures 1 A-1 F illustrate a dielectric layer during various stages of processing.
  • Figure 2A illustrates the increase of a dielectric film's water contact angle as compared to the water contact angle of damaged dielectric films (as control) using the treatment processes described.
  • Figure 2B illustrates the decrease of a dielectric film's dielectric constant (k value) as compared to the dielectric constant (k value) of damaged dielectric films and undamaged dielectric films (as positive and negative controls) using the treatment processes described herein.
  • Figure 2C illustrates the results under FTIR (Fourier Transformed InfraRed Spectroscopy) showing the reduction of hydrogen bonded silanol groups of dielectric films treated with one or more treatment and repairing processes described herein as compared to the FTIR spectroscopy of a damaged dielectric films (as negative control).
  • FTIR Fast Transformed InfraRed Spectroscopy
  • Embodiments described generally relate to methods for repairing and lowering the dielectric constant (k-value) of low k films used in semiconductor fabrication.
  • Figure 1A illustrates a dielectric film 100 deposited onto a structure 101 .
  • the structure 101 may be a substrate, such as, for example, a silicon wafer, or a previously formed layer, such as, for example, a metallization or interconnect layer.
  • the dielectric film 100 may be a porous silicon containing low k film, such as, for example, Si0 2 , SiOC, SiON, SiCOH, SiOCN, or other related films.
  • the dielectric film 100 may have pores 102 formed therein.
  • Figure 1 B illustrates the dielectric film 100 after having been planarized and etched to form features, e.g., 104, into the dielectric film 100.
  • the dielectric film 100 may have been planarized by a chemical mechanical planarization (CMP) process, for example.
  • CMP chemical mechanical planarization
  • the dielectric film 100 may have been etched by masking a portion of the dielectric film 100, contacting the unmasked portion of the dielectric film 100 with a plasma formed from hydrofluoric acid (HF) vapor, and ashing away the mask using a plasma formed from oxygen (0 2 ) gas or C0 2 gas, for example.
  • HF hydrofluoric acid
  • the processes of planarization, ashing, and etching of the dielectric film 100 introduce hydrogen and/or water into the dielectric film 100 causing Si-OH groups to form, for example, which make the dielectric film 100 hydrophilic.
  • the hydrophilic property of the dielectric film 100 causes the pores 102 to fill with water which creates an undesirable effect, such that the water laden pores are then identified as being damaged pores 103.
  • the presence of both Si-OH groups and damaged pores 103 undesirably increase the k-value of the dielectric film 100 and locations where there is a presence of Si-OH or damaged pores 103 are considered to be damaged.
  • Figure 1 C illustrates the dielectric film 100 after having been repaired by one or more processes, which are described below.
  • the repair processes decrease the k-value of the dielectric film 100 by removing the water from the damaged pores 103, thereby creating repaired pores 105, and by converting the Si-OH groups in the dielectric film 100 into hydrophobic Si-0-Si(CH 3 ) 3 groups, for example.
  • the hydrophobic Si-0-Si(CH 3 ) 3 groups assist in driving water out of the damaged pores 103.
  • the dielectric constant (k value) of damaged dielectric films repaired using the treatment processes described is significantly decreased when compared to the dielectric constant (k value) of unrepaired damaged dielectric films and to the dielectric constant (k value) of undamaged dielectric films (as positive and negative controls, respectively).
  • the resulting repaired dielectric films show an increase in water contact angle when compared to the water contact angle of damaged dielectric films (used as a control) after using the treatment and repairing processes described herein.
  • FTIR Fastier Transformed InfraRed Spectroscopy
  • the number of hydrogen bonded silanol groups present in damaged dielectric films have been significantly reduced after treating the damaged dielectric films with one or more of the repair processes as described below (as compared to the FTIR spectroscopy of an unrepaired damaged dielectric film as negative control).
  • a damaged dielectric film 100 may be repaired by a vapor phase silylation process.
  • the vapor phase silylation process comprises contacting the dielectric film 100 with a vaporized silylation compound to create the Si-0-Si(CH 3 ) 3 groups in the dielectric film 100. Vaporizing the silylation compound allows the silylation compound to penetrate deeply into the dielectric film 100.
  • the silylation compound may be hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH 3 -Si-(OCH 3 ) 3 ), dimethyldimethoxysilane (DMDMS) ((CH 3 ) 2 -Si-(OCH 3 ) 2 ), methyltrimethoxysilane (MTMS) ((CH 3 ) 3 -Si-OCH 3 ), phenyltrimethoxysilane (PTMOS) (C 6 H 5 -Si-(OCH 3 ) 3 ), phenyldimethylchlorosilane (PDMCS) (C 6 H 5 -Si-(CH 3 ) 2 -CI), dimethylaminotrimethylsilane (
  • the vapor phase silylation process may be conducted by placing the dielectric film 100 into a processing chamber, vaporizing the silylation compound, and causing the vaporized silylation compound to flow into the processing chamber.
  • the silylation compound may alternatively be vaporized in the processing chamber.
  • the silylation compound may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber.
  • a carrier gas such as He, may be used to assist the introduction of the silylation compound into the processing chamber.
  • a catalyst such as water, may be added during the vapor phase silylation process.
  • the vapor phase silylation process may be conducted at a processing chamber pressure between about 50 mTorr and about 500 Torr, such as 6 Torr, a dielectric film temperature between about 100 °C and about 400 °C, such as 385 °C, a silylation compound flow rate between about 0.5 g/min and about 5 g/min, such as 1 g/min, and a processing time between about 1 min and about 10 min, such as 3 min.
  • the processing chamber pressure may vary during the vapor phase silylation process, for example, between about 50 Torr and about 500 Torr.
  • the dielectric film 100 may be repaired by using an ultra-violet (UV) cure process.
  • the UV cure process comprises exposing the dielectric film 100 to UV radiation to remove water from the damaged pores and to create the Si-0-Si(CH 3 ) 3 groups in the dielectric film 100 described above.
  • the UV cure process may be conducted by placing the dielectric film 100 into a processing chamber and causing the dielectric film 100 to be exposed to a source of UV radiation, with sufficient energy to drive initiate and drive the process.
  • the UV radiation source may be a UV lamp, for example.
  • the UV radiation source may be positioned outside of the processing chamber having an inert gas environment, such as He or Ar, for example, and a quartz window through which the UV radiation may pass.
  • the processing chamber may also include a microwave source to heat the dielectric film 100 prior to or concurrently with the exposure of the dielectric film 100 to the UV radiation.
  • the UV cure process may also be conducted using a plasma to simulate UV radiation wavelengths.
  • the plasma may be formed by coupling RF power to a treatment gas such as He, Ar, 0 2 , and N 2 .
  • the UV cure process may be conducted at a processing chamber pressure between about 1 Torr and about 100 Torr, such as 6 Torr, a dielectric film temperature between about 20 °C and about 400 °C, such as 385 °C, a process chamber environment (non-treatment) gas flow rate between about 8 slm and about 24 slm, such as 16 slm, a treatment gas flow rate between about 2 slm and about 20 slm, such as 12 slm, a RF power between about 50 W and about 1000 W, such as 500W, an RF power frequency of 13.56 MHz, a processing time between about 10 sec and about 180 sec, such as 60 sec, a UV irradiance between about 100 W/m 2 and about 2000 W/m 2 , such as 1500 W/m 2 , and using UV wavelengths between about 100 nm and about 400 nm.
  • the UV cure process described above acts to repair the damaged pores 103 in the sidewalls of the features, e.g.,
  • the dielectric film 100 may be repaired using the vapor phase silylation process described above followed by the UV cure process also described above, or vice versa.
  • the two processes may also be conducted in- situ and in the same chamber.
  • the processing chamber may contain a showerhead and a quartz window, which may be integrated into a single component.
  • the dielectric film 100 may be repaired using a process including a UV cure followed by vapor phase silylation which is then followed by an additional UV cure.
  • the 3-phase process operates to remove water from the damaged pores 103 so that the silylation compound can penetrate and repair the damaged pores 103.
  • the initial UV cure removes water from the surface of the dielectric film 100 and from the sidewalls of the features, e.g., 104, the vapor phase silylation recovers the hydrophobicity of the film, and the additional UV cure completes the repair of the dielectric film 100.
  • the process may be conducted in a single processing chamber or multiple processing chambers.
  • the dielectric film 100 may be repaired by an in- situ pulsed silylation and UV cure process.
  • the in-situ pulsed silylation and UV cure process may be conducted by placing the dielectric film 100 into a processing chamber and alternatingly exposing the dielectric film 100 to UV radiation and then into contact with a silylation compound.
  • a source of UV radiation may be exposed to the dielectric film 100 for between about 5 seconds and about 10 seconds and then cut off from the exposure.
  • a liquid or vaporized silylation compound such as one of the silylation compounds mentioned above, may be controlled to flow into the processing chamber for between about 5 seconds and about 10 seconds to contact the dielectric film 100 and then the flow may be stopped.
  • the two steps of the in-situ pulsed silylation and UV cure process may be repeated as needed to achieve the desired repair of the dielectric film 100.
  • the two steps of the in-situ pulsed silylation and UV cure process may be repeated, e.g., repeated for 2 times, 3 times, 10 times, etc. It should be understood that either step may begin the repair procedure and be followed by the other step.
  • the silylation compound may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber, the UV radiation source may be a UV lamp positioned outside of the processing chamber, and the processing chamber may have a quartz window through which UV radiation may pass.
  • the in-situ pulsed silylation and UV cure process may be conducted at a processing chamber pressure between about 1 Torr and about 500 Torr, such as 6 Torr , a dielectric film temperature between about 100 °C and about 400 °C, such as 385 °C, a silylation compound flow rate between about 0.5 g/min and about 5 g/min, such as 1 g/min, a total processing time between about 10 sec and about 600 sec, such as 180 sec, a UV irradiance between about 100 W/m 2 and about 2000 W/m 2 , such as 1500 W/m 2 , and using UV wavelengths between about 100 nm and about 400 nm.
  • the dielectric film 100 may be repaired by an in- situ silylation and UV cure process.
  • the in-situ silylation and UV cure process may be conducted by placing the dielectric film 100 into a processing chamber, causing the continuous flow of a liquid or vaporized silylation compound, such as one of the silylation compounds mentioned above, into the processing chamber to contact the dielectric film 100, and simultaneously exposing the dielectric film 100 to pulsed UV radiation.
  • the silylation compound may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber, the UV radiation source may be a UV lamp positioned outside of the processing chamber, and the processing chamber may have a quartz window through which UV radiation may pass.
  • the in-situ silylation and UV cure process may be conducted at a processing chamber pressure between about 1 Torr and about 500 Torr, such as 6 Torr, a dielectric film temperature between about 100 °C and about 400 °C, such as 385 °C, a silylation compound flow rate between about 0.5 g/min and about 5 g/min, such as 1 g/min, a total processing time between about 10 sec and about 600 sec, such as 180 sec, a UV irradiance between about 100 W/m 2 and about 2000 W/m 2 , such as 1500 W/m 2 , and using UV wavelengths between about 100 nm and about 400 nm.
  • a processing chamber pressure between about 1 Torr and about 500 Torr, such as 6 Torr, a dielectric film temperature between about 100 °C and about 400 °C, such as 385 °C, a silylation compound flow rate between about 0.5 g/min and about 5 g/min, such as 1 g/min, a total
  • the dielectric film 100 may be repaired by 3-phase procedure including a silylation process, a low temperature conformal silicon oxide deposition process, and a UV cure process.
  • the silylation and UV cure processes may be similar to those initially described above.
  • the low temperature conformal silicon oxide deposition process is an atomic layer deposition (ALD) type process for depositing very thin layers.
  • ALD atomic layer deposition
  • a conformal seed layer is deposited onto the dielectric film 100 by positioning the dielectric film 100 in a processing chamber and exposing the dielectric film 100 to a plasma formed from a silicon-containing precursor.
  • the conformal seed layer is then treated with a plasma formed from an oxygen- containing precursor, thereby forming a silicon oxide layer on the dielectric film 100. This process may be repeated until a desired thickness of silicon oxide is formed.
  • Suitable silicon-containing precursors may include octamethylcyclotetrasiloxane (OMCTS), methyldiethoxysilane (MDEOS), bis(tertiary- butylamino)silane (BTBAS), tridimethylaminosilane (TriDMAS), silane, disilane, dichlorosilane, trichlorosilane, dibromosilane, silicon tetrachloride, silicon tetrabromide, or combinations thereof.
  • the silicon-containing plasma is provided at about 50 W to about 3000 W of RF power at a frequency of 13.56 MHz and/or 350KHz.
  • the RF power may be provided to a showerhead, i.e., a gas distribution assembly, and/or a substrate support in the chamber.
  • the spacing between the showerhead and the substrate support may be greater than about 230 mils, such as between about 350 mils and about 800 mils.
  • the silicon-containing precursor may optionally include carrier gases, such as helium, nitrogen, oxygen, nitrous oxide, and argon.
  • carrier gases such as helium, nitrogen, oxygen, nitrous oxide, and argon.
  • the silicon-containing precursor may be introduced at flow rates between about 5 seem and about 1000 seem.
  • An optional carrier gas, e.g., helium may be introduced at flow rates of between about 100 seem and about 20000 seem.
  • the ratio of the flow rate of the silicon-containing precursor, e.g., octamethylcyclotetrasiloxane, to the flow rate of the carrier gas, e.g., helium is about 1 :1 or greater, such as between about 1 :1 and about 1 :100.
  • the processing chamber pressures may be greater than about 5 mTorr, such as between about 1 .8 Torr and about 10 Torr, and the temperatures of the dielectric film 100 may be between about 125°C and about 580°C, more particularly, the temperatures are between about 200°C and about 400°C, while the silicon-containing precursor is flowing into the processing chamber to deposit the conformal seed layer.
  • the silicon-containing precursor may be controlled to flow into the chamber for a process time sufficient to deposit a layer having a thickness of between about 5 A and about 2000 A.
  • the silicon-containing precursor may be controlled to flow into the chamber for between about 0.1 seconds and about 120 seconds.
  • Suitable oxygen-containing precursors may include oxygen (0 2 ) gas or nitrous oxide (N 2 0).
  • the oxygen-containing precursor may be introduced into the chamber at flow rates of between about 100 and about 20000 seem.
  • the oxygen- containing precursor may be controlled to flow into the chamber for a process time such as between about 0.1 seconds and about 120 seconds.
  • the oxygen plasma may be provided by applying a RF power of between about 50 W and about 3000 W in the chamber at a frequency of 13.56 MHz and/or 350KHz.
  • the chamber pressure may be between about 5 mTorr and about 10 Torr, and the temperature of the dielectric film 100 may be between about 125°C and about 580°C while the oxygen- containing precursor is flowing into the chamber.
  • a suitable processing chamber for the carbon-containing plasma process is the PRODUCER® SNOW PECVD chamber, commercially available from Applied Materials, Inc., located in Santa Clara, CA.
  • the 3-phase procedure described above advantageously seals the damaged pores which may have been cracked during the etching, ashing, or planarization processes discussed above.
  • the dielectric film 100 may be repaired by a carbon-containing plasma process.
  • the carbon-containing plasma process may be conducted by placing the dielectric film 100 in a processing chamber, causing a carbon-containing precursor gas, such as a hydrocarbon precursor gas, to flow into the processing chamber, coupling RF power to the carbon-containing precursor gas to form a plasma, and contacting the dielectric film 100 with the carbon-containing plasma.
  • the carbon-containing precursor gas may include ethylene, acetylene, butadiene, alpha-terpinene (A-TRP), methane, bicycloheptadiene (BCHD), or other related compounds.
  • the carbon-containing precursor gas may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber.
  • a suitable processing chamber for the carbon-containing plasma process is the PRODUCER® PECVD chamber, commercially available from Applied Materials, Inc., located in Santa Clara, CA.
  • the carbon-containing plasma process may be conducted at a processing chamber pressure between 1 Torr and 50 Torr, such as 10 Torr, a dielectric film temperature between about 20 °C and about 400 °C, such as 300 °C, a carbon-containing precursor gas flow rate between about 10 seem and about 5000 seem, such as 1000 seem, a RF power between about 10 W and about 1000 W, such as 300 W, a RF frequency between 0.01 MHz and 300 MHz, such as 13.56 MHz, and a processing time between about 5 sec and about 600 sec, such as 60 sec.
  • FIGs 2A-2C illustrate the benefits of using the repair process described above.
  • the water contact angles of various dielectric films are shown.
  • An undamaged dielectric film generally exhibits high water contact angle, e.g., about 102.5 degree as shown in data column 7 of Figure 2A, and is relatively hydrophobic.
  • a damaged dielectric film generally exhibits lower water contact angle, as compared to that of an undamaged dielectric film.
  • the water contact angles of two exemplary damaged dielectric films as shown in data columns 1 and 3 of Figure 2A are 7.5 degree and 13 degree, and thus the damaged dielectric films are more hydrophilic.
  • Data column 2 of Figure 2A shows one example of a water contact angle of a damaged dielectric film having been restored to at least about 82.6 degree, after using one vapor phase silylation process as described above on the damaged dielectric film whose pre-repair condition is shown in data column 1 .
  • Data column 4 of Figure 2A shows another example of a water contact angle of a damaged dielectric film having been restored to at least about 76.2 degree, after using another vapor phase silylation process as described above on the damaged dielectric film whose pre-repair condition is shown in data column 3.
  • Data column 5 of Figure 2A shows another example of a water contact angle of a damaged dielectric film having been restored to at least about 28.92 degree, after using a UV cure process as described above on the damaged dielectric film whose pre-repair condition is shown in data column 3.
  • data column 6 of Figure 2A shows another example of a restored water contact angle of a damaged dielectric film having been restored to at least about 96.3 degree, after using another vapor phase silylation process and ⁇ n- situ UV cure process simultaneously as described above on the damaged dielectric film whose pre-repair condition is shown in data column 3.
  • the restored water contact angle of the repaired dielectric film of data column 6 is surprisingly much better than the examples as shown in data columns 2, 4 and 5 and is comparatively close to the water contact angle (102.5 degree) of the undamaged dielectric film of data column 7.
  • the results in Figure 2A illustrate the increase of a dielectric film's water contact angle using the treatment processes described herein, as compared to the water contact angle of damaged dielectric films (used as a control).
  • FIG. 2B the dielectric constants (k values) of various dielectric films are shown.
  • An undamaged low-k dielectric film generally exhibits a low dielectric constant.
  • a low k undamaged dielectric film has a k value of 2.21 as shown in data column 10
  • the undamaged low-k dielectric film may be damaged by various different treatments, which change (transform) the dielectric film into damaged dielectric films with k values of 2.62, as one example of a damaged dielectric film in data column 1 , and 2.52 as another example of a damaged dielectric film in data column 5.
  • some post-deposition treatment processes can damage low-k dielectric films and the dielectric constants (k values) of resulting damaged dielectric films are 10% to 20% higher than the dielectric constant of the undamaged dielectric film.
  • Data columns 2 and 6 of Figure 2B show examples of the dielectric constants of damaged dielectric films having been restored to at least about 2.54 and about 2.43, after using one vapor phase silylation process as described above on the examples of the damaged dielectric films whose pre-repair conditions are shown in data columns 1 and 5 (k value of 2.62 and 2.52), respectively.
  • the k values of 2.54 and 2.43 of the repaired dielectric films in data column 2 and 6 are still too high, as compared to the k value of 2.21 of the undamaged dielectric film in data column 10.
  • the results demonstrate that the vapor phase silylation process repairs the dielectric constants of the damaged dielectric films and lowers the dielectric constant values of the damaged dielectric films between about 2% and about 6%.
  • Data column 7 of Figure 2B shows one example of the dielectric constant of a damaged dielectric film having been repaired to at least about 2.45, after using a UV cure process as described above on the example of the damaged dielectric film whose pre-repair condition is shown in data column 5.
  • the results show that the UV cure process is comparable with the silylation process in restoring the k-value of the damaged dielectric film, generally showing a lowering of the dielectric constants of the damaged dielectric films between about 2% and about 6%.
  • Data columns 3 and 8 of Figure 2B shows two examples of using a vapor phase silylation process and a UV cure process consecutively on the damaged dielectric films whose pre-repair condition is shown in data columns 1 and 5, respectively.
  • the consecutive combined treatments by silylation and UV cure processes restore and repair the damaged dielectric films and lower the k-value of the damaged dielectric films.
  • the resulting k values of 2.4 and 2.36 of the repaired dielectric films, as shown in data columns 3 and 8 are lower than the k values of 2.54, 2.43, and 3.45 of the repaired dielectric films in data columns 2, 6, and 7, which use only a single treatment step of either a silylation process or a UV cure process.
  • the multistep in-situ treatment of a substrate can be, for example, simultaneously exposing the substrate to a vapor phase silylation process and an in-situ UV cure process for a predetermined processing time without taking the substrate out of the process chamber.
  • Another example is simultaneously exposing the substrate to an in-situ pulsed silylation and UV cure process, e.g., exposing the substrate to a vapor phase silylation compound for a predetermined processing time (e.g., continuously or in short 5-10 second pulses) and to an in-situ UV cure process for another processing time (e.g., continuously or in short 5-10 second pulses).
  • a predetermined processing time e.g., continuously or in short 5-10 second pulses
  • an in-situ UV cure process for another processing time (e.g., continuously or in short 5-10 second pulses).
  • Data columns 4 and 9 of Figure 2B show the results of two examples of using an in-situ vapor phase silylation and UV cure process (e.g., treating substrates with damaged dielectric films whose pre-repair conditions are shown in data columns 1 and 5 simultaneously with a vapor phase silylaiton compound and UV radiation).
  • the dielectric constants (k-values) of the repaired dielectric films are about 2.38 and about 2.32 as shown in data columns 4 and 9, as compared to the dielectric constants 2.62 and 2.52 of the starting damaged dielectric films in data columns 1 and 5, respectively.
  • the results in data columns 4 and 9 show that the in-situ silylation and UV cure process is better than the consecutive combined silylaiton and UV cure process, generally lowering the dielectric constants of the damaged dielectric films between about 6% and about 20%.
  • the in-situ vapor phase silylation and UV cure process can not only lower the dielectric constant of a damaged dielectric film, it can repair and restore the damaged dielectric film to an extent that the dielectric constant value is comparable to the original k-value of 2.21 of the undamaged dielectric film.
  • Figures 2C illustrates a plot of results of FTIR (Fourier Transformed InfraRed Spectroscopy) showing the reduction of hydrogen bonded silanol groups of dielectric films treated with one or more treatment/repairing processes described herein as compared to the FTIR spectroscopy of a damaged dielectric films (used as negative control).
  • the dotted line illustrates the FTIR results of a damaged dielectric film (establishing a negative control level), showing high absorption at wave number around 3000 (cm "1 ) to 3500 (cm "1 ) and indicating high numbers of Si-OH bonds.
  • the long and short dashed line illustrates the FTIR results of a repaired dielectric film using a silylation process described above, showing reduced Si-OH bonds as compared to the damaged negative control level.
  • the solid line illustrates the FTIR results of a repaired dielectric film using a in-situ silylation and UV cure process described above, showing reduced S-OH bonds as compared to the FTIR results of the single silylation treatment process (the dashed line) and the damaged negative control (the dotted line).
  • the significant decrease in the absorption around wave number 3000 (cm "1 ) to 3500 (cm "1 ) indicates a reduced number of Si-OH bonds, e.g., the Si-OH bonds may be converted into Si-0-Si(CH 3 ) 3 and other bonds.
  • a diffusion barrier 106 may be deposited into the features, e.g., 104, of the dielectric film 100 and a metal material 107, such as, for example, copper or a copper alloy, may be deposited into the features, e.g., 104, as seen in Figure 1 D. It may be necessary to planarize the metal material 107 and remove any oxides from the metal material 107 that may form during planarization. Common metal oxide removal techniques involve the use of hydrogen or ammonia plasmas. The planarization and/or metal oxide removal processes may re-damage the surface of the dielectric film 100, as seen in Figure 1 E. The dielectric film 100 may be repaired using any of the repair processes described above, as seen in Figure 1 F.

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Abstract

Methods for the repair of damaged low k films are provided. Damage to the low k films occurs during processing of the film such as during etching, ashing, and planarization. The processing of the low k film causes water to store in the pores of the film and further causes hydrophilic compounds to form in the low k film structure. Repair processes incorporating ultraviolet (UV) radiation and silylation compounds remove the water from the pores and further remove the hydrophilic compounds from the low k film structure.

Description

UV ASSISTED SILYLATION FOR RECOVERY AND PORE SEALING
OF DAMAGED LOW K FILMS
BACKGROUND OF THE INVENTION
Field of the Invention
[0001] The methods described generally relate to repairing and lowering the dielectric constant of low k films used in semiconductor fabrication.
Description of the Related Art
[0002] The dielectric constant (k) of dielectric films in semiconductor fabrication is continually decreasing as device scaling continues. Minimizing integration damage on low dielectric constant (low k) films is important to be able to continue decreasing feature sizes. However, as feature sizes shrink, improvement in the resistive capacitance and reliability of dielectric films becomes a serious challenge.
[0003] Current techniques for the etching or ashing of dielectric films involve process chemistries which create water (H20) as a byproduct. The water byproduct can be introduced into the deposited dielectric films, thereby increasing the k value of the dielectric film. Also, current techniques for the removal of copper oxides (CuO) and chemical mechanical planarization (CMP) residues involve the use of ammonia (NH3) or hydrogen (H2) plasmas. Removal of the copper oxides and CMP residues are necessary to improve the electromigration (EM) of the metallization structures and the time dependent dielectric breakdown (TDDB) of the inter level dielectric (ILD) films. However, exposing low k films to NH3 and H2 plasmas modifies the film structure and increases the k value. Present repair techniques involve liquid phase silylation or use of supercritical C02. However, such techniques have not proven effective for repairing sidewall damage of recessed features in the films.
[0004] Thus, a method for repairing dielectric films to lower the k value is necessary to improve efficiency and allow for smaller device sizes. SUMMARY OF THE INVENTION
[0005] Embodiments according to the present invention generally relate to methods for repairing and lowering the dielectric constant of low k films for semiconductor fabrication.
[0006] One method of repairing a damaged low k dielectric film includes alternatingly exposing a dielectric film to ultraviolet (UV) radiation and a silylation compound at least two times.
[0007] Another method includes exposing a dielectric film to a silylation compound, depositing a layer of silicon oxide onto the dielectric film, and exposing the dielectric film and silicon oxide layer to ultraviolet (UV) radiation.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope, the description may suggest to other equally effective embodiments.
[0009] Figures 1 A-1 F illustrate a dielectric layer during various stages of processing.
[0010] Figure 2A illustrates the increase of a dielectric film's water contact angle as compared to the water contact angle of damaged dielectric films (as control) using the treatment processes described.
[0011] Figure 2B illustrates the decrease of a dielectric film's dielectric constant (k value) as compared to the dielectric constant (k value) of damaged dielectric films and undamaged dielectric films (as positive and negative controls) using the treatment processes described herein.
[0012] Figure 2C illustrates the results under FTIR (Fourier Transformed InfraRed Spectroscopy) showing the reduction of hydrogen bonded silanol groups of dielectric films treated with one or more treatment and repairing processes described herein as compared to the FTIR spectroscopy of a damaged dielectric films (as negative control).
DETAILED DESCRIPTION
[0013] Embodiments described generally relate to methods for repairing and lowering the dielectric constant (k-value) of low k films used in semiconductor fabrication.
[0014] Figure 1A illustrates a dielectric film 100 deposited onto a structure 101 . The structure 101 may be a substrate, such as, for example, a silicon wafer, or a previously formed layer, such as, for example, a metallization or interconnect layer. The dielectric film 100 may be a porous silicon containing low k film, such as, for example, Si02, SiOC, SiON, SiCOH, SiOCN, or other related films. The dielectric film 100 may have pores 102 formed therein.
[0015] Figure 1 B illustrates the dielectric film 100 after having been planarized and etched to form features, e.g., 104, into the dielectric film 100. The dielectric film 100 may have been planarized by a chemical mechanical planarization (CMP) process, for example. The dielectric film 100 may have been etched by masking a portion of the dielectric film 100, contacting the unmasked portion of the dielectric film 100 with a plasma formed from hydrofluoric acid (HF) vapor, and ashing away the mask using a plasma formed from oxygen (02) gas or C02 gas, for example.
[0016] The processes of planarization, ashing, and etching of the dielectric film 100 introduce hydrogen and/or water into the dielectric film 100 causing Si-OH groups to form, for example, which make the dielectric film 100 hydrophilic. The hydrophilic property of the dielectric film 100 causes the pores 102 to fill with water which creates an undesirable effect, such that the water laden pores are then identified as being damaged pores 103. The presence of both Si-OH groups and damaged pores 103 undesirably increase the k-value of the dielectric film 100 and locations where there is a presence of Si-OH or damaged pores 103 are considered to be damaged. The locations damaged from planarization and etching are usually localized to an upper portion of the dielectric film 100 and to the sidewalls of the features, e.g., 104, as shown in Figure 1 B. [0017] Figure 1 C illustrates the dielectric film 100 after having been repaired by one or more processes, which are described below. The repair processes decrease the k-value of the dielectric film 100 by removing the water from the damaged pores 103, thereby creating repaired pores 105, and by converting the Si-OH groups in the dielectric film 100 into hydrophobic Si-0-Si(CH3)3 groups, for example. The hydrophobic Si-0-Si(CH3)3 groups assist in driving water out of the damaged pores 103. The dielectric constant (k value) of damaged dielectric films repaired using the treatment processes described (thus becoming repaired dielectric films) is significantly decreased when compared to the dielectric constant (k value) of unrepaired damaged dielectric films and to the dielectric constant (k value) of undamaged dielectric films (as positive and negative controls, respectively).
[0018] In addition, the resulting repaired dielectric films show an increase in water contact angle when compared to the water contact angle of damaged dielectric films (used as a control) after using the treatment and repairing processes described herein. Further, when using FTIR (Fourier Transformed InfraRed Spectroscopy) to analyze the bonding properties of repaired dielectric films, the number of hydrogen bonded silanol groups present in damaged dielectric films have been significantly reduced after treating the damaged dielectric films with one or more of the repair processes as described below (as compared to the FTIR spectroscopy of an unrepaired damaged dielectric film as negative control).
[0019] In one embodiment, a damaged dielectric film 100 may be repaired by a vapor phase silylation process. The vapor phase silylation process comprises contacting the dielectric film 100 with a vaporized silylation compound to create the Si-0-Si(CH3)3 groups in the dielectric film 100. Vaporizing the silylation compound allows the silylation compound to penetrate deeply into the dielectric film 100. The silylation compound may be hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH3-Si-(OCH3)3), dimethyldimethoxysilane (DMDMS) ((CH3)2-Si-(OCH3)2), methyltrimethoxysilane (MTMS) ((CH3)3-Si-OCH3), phenyltrimethoxysilane (PTMOS) (C6H5-Si-(OCH3)3), phenyldimethylchlorosilane (PDMCS) (C6H5-Si-(CH3)2-CI), dimethylaminotrimethylsilane (DMATMS) ((CH3)2-N-Si-(CH3)3), bis(dimethylamino)dimethylsilane (BDMADMS), or other compounds containing Si, H, and C.
[0020] The vapor phase silylation process may be conducted by placing the dielectric film 100 into a processing chamber, vaporizing the silylation compound, and causing the vaporized silylation compound to flow into the processing chamber. The silylation compound may alternatively be vaporized in the processing chamber. The silylation compound may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber. A carrier gas, such as He, may be used to assist the introduction of the silylation compound into the processing chamber. Additionally, a catalyst, such as water, may be added during the vapor phase silylation process. The vapor phase silylation process may be conducted at a processing chamber pressure between about 50 mTorr and about 500 Torr, such as 6 Torr, a dielectric film temperature between about 100 °C and about 400 °C, such as 385 °C, a silylation compound flow rate between about 0.5 g/min and about 5 g/min, such as 1 g/min, and a processing time between about 1 min and about 10 min, such as 3 min. The processing chamber pressure may vary during the vapor phase silylation process, for example, between about 50 Torr and about 500 Torr.
[0021 ] In another embodiment, the dielectric film 100 may be repaired by using an ultra-violet (UV) cure process. The UV cure process comprises exposing the dielectric film 100 to UV radiation to remove water from the damaged pores and to create the Si-0-Si(CH3)3 groups in the dielectric film 100 described above. The UV cure process may be conducted by placing the dielectric film 100 into a processing chamber and causing the dielectric film 100 to be exposed to a source of UV radiation, with sufficient energy to drive initiate and drive the process. The UV radiation source may be a UV lamp, for example. The UV radiation source may be positioned outside of the processing chamber having an inert gas environment, such as He or Ar, for example, and a quartz window through which the UV radiation may pass. The processing chamber may also include a microwave source to heat the dielectric film 100 prior to or concurrently with the exposure of the dielectric film 100 to the UV radiation. The UV cure process may also be conducted using a plasma to simulate UV radiation wavelengths. The plasma may be formed by coupling RF power to a treatment gas such as He, Ar, 02, and N2. The UV cure process may be conducted at a processing chamber pressure between about 1 Torr and about 100 Torr, such as 6 Torr, a dielectric film temperature between about 20 °C and about 400 °C, such as 385 °C, a process chamber environment (non-treatment) gas flow rate between about 8 slm and about 24 slm, such as 16 slm, a treatment gas flow rate between about 2 slm and about 20 slm, such as 12 slm, a RF power between about 50 W and about 1000 W, such as 500W, an RF power frequency of 13.56 MHz, a processing time between about 10 sec and about 180 sec, such as 60 sec, a UV irradiance between about 100 W/m2 and about 2000 W/m2, such as 1500 W/m2, and using UV wavelengths between about 100 nm and about 400 nm. The UV cure process described above acts to repair the damaged pores 103 in the sidewalls of the features, e.g., 104.
[0022] In another embodiment, the dielectric film 100 may be repaired using the vapor phase silylation process described above followed by the UV cure process also described above, or vice versa. The two processes may also be conducted in- situ and in the same chamber. For example, the processing chamber may contain a showerhead and a quartz window, which may be integrated into a single component.
[0023] In another embodiment, the dielectric film 100 may be repaired using a process including a UV cure followed by vapor phase silylation which is then followed by an additional UV cure. The 3-phase process operates to remove water from the damaged pores 103 so that the silylation compound can penetrate and repair the damaged pores 103. The initial UV cure removes water from the surface of the dielectric film 100 and from the sidewalls of the features, e.g., 104, the vapor phase silylation recovers the hydrophobicity of the film, and the additional UV cure completes the repair of the dielectric film 100. The process may be conducted in a single processing chamber or multiple processing chambers.
[0024] In another embodiment, the dielectric film 100 may be repaired by an in- situ pulsed silylation and UV cure process. The in-situ pulsed silylation and UV cure process may be conducted by placing the dielectric film 100 into a processing chamber and alternatingly exposing the dielectric film 100 to UV radiation and then into contact with a silylation compound. For example, in one portion of the in-situ pulsed silylation and UV cure process, a source of UV radiation may be exposed to the dielectric film 100 for between about 5 seconds and about 10 seconds and then cut off from the exposure. In another portion of the in-situ pulsed silylation and UV cure process, a liquid or vaporized silylation compound, such as one of the silylation compounds mentioned above, may be controlled to flow into the processing chamber for between about 5 seconds and about 10 seconds to contact the dielectric film 100 and then the flow may be stopped. The two steps of the in-situ pulsed silylation and UV cure process may be repeated as needed to achieve the desired repair of the dielectric film 100. For example, the two steps of the in-situ pulsed silylation and UV cure process may be repeated, e.g., repeated for 2 times, 3 times, 10 times, etc. It should be understood that either step may begin the repair procedure and be followed by the other step. The silylation compound may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber, the UV radiation source may be a UV lamp positioned outside of the processing chamber, and the processing chamber may have a quartz window through which UV radiation may pass. The in-situ pulsed silylation and UV cure process may be conducted at a processing chamber pressure between about 1 Torr and about 500 Torr, such as 6 Torr , a dielectric film temperature between about 100 °C and about 400 °C, such as 385 °C, a silylation compound flow rate between about 0.5 g/min and about 5 g/min, such as 1 g/min, a total processing time between about 10 sec and about 600 sec, such as 180 sec, a UV irradiance between about 100 W/m2 and about 2000 W/m2, such as 1500 W/m2, and using UV wavelengths between about 100 nm and about 400 nm.
[0025] In another embodiment, the dielectric film 100 may be repaired by an in- situ silylation and UV cure process. The in-situ silylation and UV cure process may be conducted by placing the dielectric film 100 into a processing chamber, causing the continuous flow of a liquid or vaporized silylation compound, such as one of the silylation compounds mentioned above, into the processing chamber to contact the dielectric film 100, and simultaneously exposing the dielectric film 100 to pulsed UV radiation. The silylation compound may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber, the UV radiation source may be a UV lamp positioned outside of the processing chamber, and the processing chamber may have a quartz window through which UV radiation may pass. The in-situ silylation and UV cure process may be conducted at a processing chamber pressure between about 1 Torr and about 500 Torr, such as 6 Torr, a dielectric film temperature between about 100 °C and about 400 °C, such as 385 °C, a silylation compound flow rate between about 0.5 g/min and about 5 g/min, such as 1 g/min, a total processing time between about 10 sec and about 600 sec, such as 180 sec, a UV irradiance between about 100 W/m2 and about 2000 W/m2, such as 1500 W/m2, and using UV wavelengths between about 100 nm and about 400 nm.
[0026] In another embodiment, the dielectric film 100 may be repaired by 3-phase procedure including a silylation process, a low temperature conformal silicon oxide deposition process, and a UV cure process. The silylation and UV cure processes may be similar to those initially described above. The low temperature conformal silicon oxide deposition process is an atomic layer deposition (ALD) type process for depositing very thin layers. In the low temperature conformal silicon oxide deposition process, a conformal seed layer is deposited onto the dielectric film 100 by positioning the dielectric film 100 in a processing chamber and exposing the dielectric film 100 to a plasma formed from a silicon-containing precursor. The conformal seed layer is then treated with a plasma formed from an oxygen- containing precursor, thereby forming a silicon oxide layer on the dielectric film 100. This process may be repeated until a desired thickness of silicon oxide is formed.
[0027] Suitable silicon-containing precursors may include octamethylcyclotetrasiloxane (OMCTS), methyldiethoxysilane (MDEOS), bis(tertiary- butylamino)silane (BTBAS), tridimethylaminosilane (TriDMAS), silane, disilane, dichlorosilane, trichlorosilane, dibromosilane, silicon tetrachloride, silicon tetrabromide, or combinations thereof. The silicon-containing plasma is provided at about 50 W to about 3000 W of RF power at a frequency of 13.56 MHz and/or 350KHz. The RF power may be provided to a showerhead, i.e., a gas distribution assembly, and/or a substrate support in the chamber. The spacing between the showerhead and the substrate support may be greater than about 230 mils, such as between about 350 mils and about 800 mils.
[0028] The silicon-containing precursor may optionally include carrier gases, such as helium, nitrogen, oxygen, nitrous oxide, and argon. The silicon-containing precursor may be introduced at flow rates between about 5 seem and about 1000 seem. An optional carrier gas, e.g., helium, may be introduced at flow rates of between about 100 seem and about 20000 seem. The ratio of the flow rate of the silicon-containing precursor, e.g., octamethylcyclotetrasiloxane, to the flow rate of the carrier gas, e.g., helium, is about 1 :1 or greater, such as between about 1 :1 and about 1 :100. The processing chamber pressures may be greater than about 5 mTorr, such as between about 1 .8 Torr and about 10 Torr, and the temperatures of the dielectric film 100 may be between about 125°C and about 580°C, more particularly, the temperatures are between about 200°C and about 400°C, while the silicon-containing precursor is flowing into the processing chamber to deposit the conformal seed layer.
[0029] The silicon-containing precursor may be controlled to flow into the chamber for a process time sufficient to deposit a layer having a thickness of between about 5 A and about 2000 A. For example, the silicon-containing precursor may be controlled to flow into the chamber for between about 0.1 seconds and about 120 seconds.
[0030] Suitable oxygen-containing precursors may include oxygen (02) gas or nitrous oxide (N20). The oxygen-containing precursor may be introduced into the chamber at flow rates of between about 100 and about 20000 seem. The oxygen- containing precursor may be controlled to flow into the chamber for a process time such as between about 0.1 seconds and about 120 seconds. The oxygen plasma may be provided by applying a RF power of between about 50 W and about 3000 W in the chamber at a frequency of 13.56 MHz and/or 350KHz. The chamber pressure may be between about 5 mTorr and about 10 Torr, and the temperature of the dielectric film 100 may be between about 125°C and about 580°C while the oxygen- containing precursor is flowing into the chamber. A suitable processing chamber for the carbon-containing plasma process is the PRODUCER® SNOW PECVD chamber, commercially available from Applied Materials, Inc., located in Santa Clara, CA. The 3-phase procedure described above advantageously seals the damaged pores which may have been cracked during the etching, ashing, or planarization processes discussed above.
[0031 ] In another embodiment, the dielectric film 100 may be repaired by a carbon-containing plasma process. The carbon-containing plasma process may be conducted by placing the dielectric film 100 in a processing chamber, causing a carbon-containing precursor gas, such as a hydrocarbon precursor gas, to flow into the processing chamber, coupling RF power to the carbon-containing precursor gas to form a plasma, and contacting the dielectric film 100 with the carbon-containing plasma. The carbon-containing precursor gas may include ethylene, acetylene, butadiene, alpha-terpinene (A-TRP), methane, bicycloheptadiene (BCHD), or other related compounds. The carbon-containing precursor gas may be introduced into the processing chamber through a showerhead positioned at an upper portion of the processing chamber. A suitable processing chamber for the carbon-containing plasma process is the PRODUCER® PECVD chamber, commercially available from Applied Materials, Inc., located in Santa Clara, CA. The carbon-containing plasma process may be conducted at a processing chamber pressure between 1 Torr and 50 Torr, such as 10 Torr, a dielectric film temperature between about 20 °C and about 400 °C, such as 300 °C, a carbon-containing precursor gas flow rate between about 10 seem and about 5000 seem, such as 1000 seem, a RF power between about 10 W and about 1000 W, such as 300 W, a RF frequency between 0.01 MHz and 300 MHz, such as 13.56 MHz, and a processing time between about 5 sec and about 600 sec, such as 60 sec.
[0032] Figures 2A-2C illustrate the benefits of using the repair process described above. In Figures 2A, the water contact angles of various dielectric films are shown. An undamaged dielectric film generally exhibits high water contact angle, e.g., about 102.5 degree as shown in data column 7 of Figure 2A, and is relatively hydrophobic. A damaged dielectric film generally exhibits lower water contact angle, as compared to that of an undamaged dielectric film. For example, the water contact angles of two exemplary damaged dielectric films as shown in data columns 1 and 3 of Figure 2A are 7.5 degree and 13 degree, and thus the damaged dielectric films are more hydrophilic.
[0033] Data column 2 of Figure 2A shows one example of a water contact angle of a damaged dielectric film having been restored to at least about 82.6 degree, after using one vapor phase silylation process as described above on the damaged dielectric film whose pre-repair condition is shown in data column 1 . Data column 4 of Figure 2A shows another example of a water contact angle of a damaged dielectric film having been restored to at least about 76.2 degree, after using another vapor phase silylation process as described above on the damaged dielectric film whose pre-repair condition is shown in data column 3. Data column 5 of Figure 2A shows another example of a water contact angle of a damaged dielectric film having been restored to at least about 28.92 degree, after using a UV cure process as described above on the damaged dielectric film whose pre-repair condition is shown in data column 3.
[0034] In addition, data column 6 of Figure 2A shows another example of a restored water contact angle of a damaged dielectric film having been restored to at least about 96.3 degree, after using another vapor phase silylation process and \n- situ UV cure process simultaneously as described above on the damaged dielectric film whose pre-repair condition is shown in data column 3. The restored water contact angle of the repaired dielectric film of data column 6 is surprisingly much better than the examples as shown in data columns 2, 4 and 5 and is comparatively close to the water contact angle (102.5 degree) of the undamaged dielectric film of data column 7. The results in Figure 2A illustrate the increase of a dielectric film's water contact angle using the treatment processes described herein, as compared to the water contact angle of damaged dielectric films (used as a control).
[0035] In Figures 2B, the dielectric constants (k values) of various dielectric films are shown. An undamaged low-k dielectric film generally exhibits a low dielectric constant. , In one example, a low k undamaged dielectric film has a k value of 2.21 as shown in data column 10, and the undamaged low-k dielectric film may be damaged by various different treatments, which change (transform) the dielectric film into damaged dielectric films with k values of 2.62, as one example of a damaged dielectric film in data column 1 , and 2.52 as another example of a damaged dielectric film in data column 5. Thus, some post-deposition treatment processes can damage low-k dielectric films and the dielectric constants (k values) of resulting damaged dielectric films are 10% to 20% higher than the dielectric constant of the undamaged dielectric film.
[0036] Data columns 2 and 6 of Figure 2B show examples of the dielectric constants of damaged dielectric films having been restored to at least about 2.54 and about 2.43, after using one vapor phase silylation process as described above on the examples of the damaged dielectric films whose pre-repair conditions are shown in data columns 1 and 5 (k value of 2.62 and 2.52), respectively. The k values of 2.54 and 2.43 of the repaired dielectric films in data column 2 and 6 are still too high, as compared to the k value of 2.21 of the undamaged dielectric film in data column 10. The results demonstrate that the vapor phase silylation process repairs the dielectric constants of the damaged dielectric films and lowers the dielectric constant values of the damaged dielectric films between about 2% and about 6%.
[0037] Data column 7 of Figure 2B shows one example of the dielectric constant of a damaged dielectric film having been repaired to at least about 2.45, after using a UV cure process as described above on the example of the damaged dielectric film whose pre-repair condition is shown in data column 5. The results show that the UV cure process is comparable with the silylation process in restoring the k-value of the damaged dielectric film, generally showing a lowering of the dielectric constants of the damaged dielectric films between about 2% and about 6%.
[0038] Data columns 3 and 8 of Figure 2B shows two examples of using a vapor phase silylation process and a UV cure process consecutively on the damaged dielectric films whose pre-repair condition is shown in data columns 1 and 5, respectively. The consecutive combined treatments by silylation and UV cure processes restore and repair the damaged dielectric films and lower the k-value of the damaged dielectric films. In addition, by using the consecutive combined treatments by silylation and UV cure processes, the resulting k values of 2.4 and 2.36 of the repaired dielectric films, as shown in data columns 3 and 8, are lower than the k values of 2.54, 2.43, and 3.45 of the repaired dielectric films in data columns 2, 6, and 7, which use only a single treatment step of either a silylation process or a UV cure process.
[0039] Further, it has been found that using multistep, or simultaneously performed in-situ treatments of a substrate having a damaged dielectric film thereon inside a process chamber can restore and repair the damaged dielectric films much better than using only the single treatment step process. The multistep in-situ treatment of a substrate can be, for example, simultaneously exposing the substrate to a vapor phase silylation process and an in-situ UV cure process for a predetermined processing time without taking the substrate out of the process chamber. Another example is simultaneously exposing the substrate to an in-situ pulsed silylation and UV cure process, e.g., exposing the substrate to a vapor phase silylation compound for a predetermined processing time (e.g., continuously or in short 5-10 second pulses) and to an in-situ UV cure process for another processing time (e.g., continuously or in short 5-10 second pulses).
[0040] Data columns 4 and 9 of Figure 2B show the results of two examples of using an in-situ vapor phase silylation and UV cure process (e.g., treating substrates with damaged dielectric films whose pre-repair conditions are shown in data columns 1 and 5 simultaneously with a vapor phase silylaiton compound and UV radiation). The dielectric constants (k-values) of the repaired dielectric films are about 2.38 and about 2.32 as shown in data columns 4 and 9, as compared to the dielectric constants 2.62 and 2.52 of the starting damaged dielectric films in data columns 1 and 5, respectively. The results in data columns 4 and 9 show that the in-situ silylation and UV cure process is better than the consecutive combined silylaiton and UV cure process, generally lowering the dielectric constants of the damaged dielectric films between about 6% and about 20%. The in-situ vapor phase silylation and UV cure process can not only lower the dielectric constant of a damaged dielectric film, it can repair and restore the damaged dielectric film to an extent that the dielectric constant value is comparable to the original k-value of 2.21 of the undamaged dielectric film. [0041] Figures 2C illustrates a plot of results of FTIR (Fourier Transformed InfraRed Spectroscopy) showing the reduction of hydrogen bonded silanol groups of dielectric films treated with one or more treatment/repairing processes described herein as compared to the FTIR spectroscopy of a damaged dielectric films (used as negative control). In Figure 2C, the dotted line illustrates the FTIR results of a damaged dielectric film (establishing a negative control level), showing high absorption at wave number around 3000 (cm"1) to 3500 (cm"1) and indicating high numbers of Si-OH bonds. The long and short dashed line illustrates the FTIR results of a repaired dielectric film using a silylation process described above, showing reduced Si-OH bonds as compared to the damaged negative control level.
[0042] In Figure 2C, the solid line illustrates the FTIR results of a repaired dielectric film using a in-situ silylation and UV cure process described above, showing reduced S-OH bonds as compared to the FTIR results of the single silylation treatment process (the dashed line) and the damaged negative control (the dotted line). The significant decrease in the absorption around wave number 3000 (cm"1) to 3500 (cm"1) indicates a reduced number of Si-OH bonds, e.g., the Si-OH bonds may be converted into Si-0-Si(CH3)3 and other bonds.
[0043] After the dielectric film 100 has been repaired, subsequent processes may be performed to continue the fabrication of the semiconductor substrate. For example, a diffusion barrier 106 may be deposited into the features, e.g., 104, of the dielectric film 100 and a metal material 107, such as, for example, copper or a copper alloy, may be deposited into the features, e.g., 104, as seen in Figure 1 D. It may be necessary to planarize the metal material 107 and remove any oxides from the metal material 107 that may form during planarization. Common metal oxide removal techniques involve the use of hydrogen or ammonia plasmas. The planarization and/or metal oxide removal processes may re-damage the surface of the dielectric film 100, as seen in Figure 1 E. The dielectric film 100 may be repaired using any of the repair processes described above, as seen in Figure 1 F.
[0044] The repair processes described effectively lower the k-value of the damaged dielectric films thus enabling the continued scaling of semiconductor device features. [0045] While the foregoing is directed to the embodiments described, other and further embodiments according to the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1 . A method of repairing a damaged dielectric film, comprising:
placing a substrate having the damaged dielectric film thereon into a processing chamber;
vaporizing a silylation compound into a flow of a vaporized silylation compound;
exposing the substrate to the flow of the vaporized silylation compound in the processing chamber for a first processing time while in-situ exposing the substrate to ultraviolet (UV) radiation for a second period of time in the same processing chamber having the substrate disposed therein without taking the substrate out of the processing chamber.
2. The method of claim 1 , further comprising flowing one or more inert gases into the processing chamber.
3. The method of claim 1 , further comprising:
forming a plasma in the processing chamber from at least one of He, Ar, 02, or N2 gas.
4. The method of claim 1 , further comprising:
heating the substrate having the damaged dielectric film thereon to a substrate temperature of between about 100 °C and about 400 °C prior to or concurrently with exposing the substrate to the flow of the vaporized silylation compound.
5. The method of claim 1 , wherein the substrate is exposed to the flow of the vaporized silylation compound prior to or concurrently with in-situ exposing the substrate to ultraviolet (UV) radiation.
6. The method of claim 1 , wherein the silylation compound is vaporized into a vapor phase prior to or after flowing into the processing chamber.
7. The method of claim 1 , wherein the silylation compound is selected from the group consisting of hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH3-Si-(OCH3)3), dimethyldimethoxysilane (DMDMS) ((CH3)2-Si-(OCH3)2), methyltrimethoxysilane (MTMS) ((CH3)3-Si-OCH3), phenyltrimethoxysilane (PTMOS) (C6H5-Si-(OCH3)3), phenyldimethylchlorosilane (PDMCS) (C6H5-Si-(CH3)2-CI), dimethylaminotrimethylsilane (DMATMS) ((CH3)2-N- Si-(CH3)3), bis(dimethylamino)dimethylsilane (BDMADMS), and combinations thereof.
8. The method of claim 1 , wherein the first processing time is between about 10 seconds and about 600 seconds.
9. The method of claim 1 , wherein the UV radiation is generated from a UV radiation source at an UV wavelength of between about 100 nm and about 400 nm and at an UV radiation power of between about 100 W/m2 and about 2000 W/m2.
10. The method of claim 1 , further comprising:
exposing the substrate to an UV cure process prior to exposing the substrate to the flow of the vaporized silylation compound in the processing chamber while in- situ exposing the substrate to ultraviolet (UV) radiation.
1 1 . The method of claim 1 , wherein exposing the substrate to the flow of the vaporized silylation compound in the processing chamber while in-situ exposing the substrate to ultraviolet (UV) radiation comprises:
continuously exposing the substrate to the flow of the vaporized silylation compound for the first processing time while in-situ exposing the substrate to ultraviolet (UV) radiation in pulses, each pulse being between about 5 seconds and about 10 seconds.
12. The method of claim 1 , wherein exposing the substrate to the flow of the vaporized silylation compound in the processing chamber while in-situ exposing the substrate to ultraviolet (UV) radiation comprises:
alternatingly exposing the substrate to the vaporized silylation compound for a pulse of between 5 seconds and 10 seconds and to the ultraviolet (UV) radiation for a pulse of between 5 seconds and 10 seconds; and
repeating the alternatingly exposing the substrate to the flow of the vaporized silylation compound and the ultraviolet (UV) radiation.
13. The method of claim 1 , further comprising:
depositing a layer of silicon oxide onto the substrate having the damaged dielectric film thereon, wherein depositing the layer of silicon oxide comprises:
forming a plasma from a silicon-containing precursor to deposit a silicon-containing compound onto the substrate; and
exposing the substrate having the deposited silicon-containing compound to an oxygen-containing plasma;
14. The method of claim 13, wherein the silicon-containing precursor comprises octamethylcyclotetrasiloxane (OMCTS), methyldiethoxysilane (MDEOS), bis(tertiary- butylamino)silane (BTBAS), tridimethylaminosilane (TriDMAS), silane, disilane, dichlorosilane, trichlorosilane, dibromosilane, silicon tetrachloride, or silicon tetrabromide.
15. The method of claim 13, wherein exposing the substrate to the oxygen- containing plasma comprises:
forming a plasma from an oxygen-containing precursor selected from the group consisting of 02, N20, and combinations thereof.
PCT/US2012/032203 2011-04-25 2012-04-04 Uv assisted silylation for recovery and pore sealing of damaged low k films Ceased WO2012148641A2 (en)

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US20120270339A1 (en) 2012-10-25
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KR20140010449A (en) 2014-01-24
US8492170B2 (en) 2013-07-23

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