CN104752317B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN104752317B CN104752317B CN201310731501.2A CN201310731501A CN104752317B CN 104752317 B CN104752317 B CN 104752317B CN 201310731501 A CN201310731501 A CN 201310731501A CN 104752317 B CN104752317 B CN 104752317B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor substrate is provided, sequentially forms etching stopping layer and porous low k dielectric layer on a semiconductor substrate；Copper metal interconnection structure is formed in porous low k dielectric layer；Copper metal diffusion impervious layer is formed in the side wall and bottom deposit of copper metal interconnection structure；Last handling process is implemented to Semiconductor substrate, to repair the porous low k dielectric layer to sustain damage, and lifts the mechanical strength of porous low k dielectric layer；Copper metal interconnection layer is filled in copper metal interconnection structure.According to the present invention, after deposition forms copper metal diffusion impervious layer, last handling process is implemented to Semiconductor substrate, the porous low k dielectric layer to be formed and be sustained damage during copper metal interconnection structure can be repaired, the mechanical strength of porous low k dielectric layer is lifted, avoids the decline of device performance.
Description
Technical field
The present invention relates to semiconductor fabrication process, is avoided when forming copper metal interconnection structure in particular to one kind porous
The method that low k dielectric sustains damage.
Background technology
With the continuous reduction of dimensions of semiconductor devices, the influence of the capacitive crosstalk between copper metal interconnection layer is increasingly aobvious
Write.In order to solve the problems, such as capacitive crosstalk, it is a kind of solution well that porous low k dielectric layer is arranged between copper metal interconnection layer
The certainly mode of problem.
For the logic circuit in semiconductor devices, the number of plies of copper metal interconnection layer reaches several layers or even ten several layers,
Each layer of copper metal interconnection layer is respectively formed in corresponding copper metal interconnection structure.As shown in Figure 1A, formed with front-end devices
Semiconductor substrate 100 on formed with the etching stopping layer 101 and porous low k dielectric layer 102 being laminated from bottom to top, pass through dry method
It is etched in formed with the copper metal interconnection structure 103 connected with the front-end devices in porous low k dielectric layer 102, it is by through hole
103a and groove 103b is formed.Then, wet-cleaning is implemented, to remove residue and impurity caused by the etching.Then, such as
Shown in Figure 1B, copper metal diffusion impervious layer is formed in the side wall of copper metal interconnection structure 103 and bottom by physical vapour deposition (PVD)
104.Then, copper metal Seed Layer and copper metal interconnection layer are sequentially formed.
Mechanical strength for porous low k dielectric layer 102 is poor, therefore, in above-mentioned technical process, the dry method erosion of implementation
Quarter, wet-cleaning and physical vapour deposition (PVD) all can cause to damage to porous low k dielectric layer 102, and then change porous low k dielectric layer
102 k values（Dielectric constant）, cause the decline of device performance.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate, etching stopping layer and porous low k dielectric layer are sequentially formed on the semiconductor substrate；In the porous low k dielectric layer
Middle formation copper metal interconnection structure；Copper metal diffusion barrier is formed in the side wall and bottom deposit of the copper metal interconnection structure
Layer；Last handling process is implemented to the Semiconductor substrate, to repair the porous low k dielectric layer to sustain damage, and lifts institute
State the mechanical strength of porous low k dielectric layer.
Further, the implementation steps of the last handling process include：The Semiconductor substrate is placed in DEMS atmosphere,
The porous low k dielectric layer to be sustained damage when forming the copper metal interconnection structure to repair；It is real to the Semiconductor substrate
Ultraviolet light or infrared irridiation processing are applied, so that the dielectric constant of the porous low k dielectric layer is returned to form the copper metal
Numerical value before interconnection structure；Argon plasma bombardment processing is implemented to the Semiconductor substrate, is situated between with lifting the porous low k
The mechanical strength of electric layer.
Further, the flow of the DEMS is 100-5000sccm, and temperature is 100-500 DEG C.
Further, the power of the ultraviolet light irradiation is more than 100W, wavelength 150-400nm, the infrared irridiation
Power is 50-3000W, wavelength is more than 400nm.
Further, the power of argon plasma bombardment is 100-3000W, pressure 0.1-10Torr, described argon etc.
The flow of gas ions is 100-3000sccm.
Further, the step of forming the copper metal interconnection structure includes：Formed on the porous low k dielectric layer under
And the cushion and hard mask layer of upper stacking；The groove being used as in the copper metal interconnection structure is formed in the hard mask layer
Pattern first opening, to expose the cushion；Formed in the cushion and the porous low k dielectric layer and be used as institute
State the second opening of the pattern of the through hole in copper metal interconnection structure；Using the hard mask layer as mask, delay with described in step etching
Layer and the porous low k dielectric layer are rushed, to form the copper metal interconnection structure in the porous low k dielectric layer.
Further, after the etching terminates, in addition to the etching exposed by the copper metal interconnection structure is removed
The step of stop-layer and implementation etching post processing.
Further, after implementing the last handling process, it is additionally included in the copper metal interconnection structure and fills copper metal
The step of interconnection layer.
Further, before implementing the filling, in addition to copper metal seed is formed on the copper metal diffusion impervious layer
The step of layer.
Further, after implementing the filling, in addition to cmp is performed until exposing the porous low k dielectric
The step of layer
According to the present invention, after deposition forms the copper metal diffusion impervious layer, after Semiconductor substrate implementation
Processing procedure, can repair the porous low k dielectric layer to be formed and be sustained damage during the copper metal interconnection structure, and lifting is porous
The mechanical strength of low k dielectric, avoid the decline of device performance.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A shows the device after the copper metal interconnection structure that connection front-end devices layer is formed according to prior art
Schematic cross sectional view；
Figure 1B shows the device formed in the copper metal interconnection structure shown in figure ia after copper metal diffusion impervious layer
The schematic cross sectional view of part；
Fig. 2A-Fig. 2 H are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view；
Fig. 3 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Formation copper metal interconnection structure when avoid the method that porous low k dielectric layer sustains damage.Obviously, execution of the invention and unlimited
Due to the specific details that the technical staff of semiconductor applications is familiar with.Presently preferred embodiments of the present invention is described in detail as follows, but
In addition to these detailed descriptions, the present invention can also have other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
[exemplary embodiment]
Below, reference picture 2A- Fig. 2 H and Fig. 3 are mutual to describe method formation copper metal according to an exemplary embodiment of the present invention
The key step that porous low k dielectric layer sustains damage is avoided when linking structure.
Reference picture 2A- Fig. 2 H, it illustrated therein is method according to an exemplary embodiment of the present invention and implement the step of institute successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, using chemical vapor deposition method in Semiconductor substrate 200
On sequentially form etching stopping layer 201, porous low k dielectric layer 202, cushion 203 and hard mask layer 204.
On semiconductor substrate 200 formed with front-end devices, to put it more simply, being not shown in legend.The front-end devices
Refer to the back end fabrication for implementing semiconductor devices（BEOL）The device formed before, herein not to the specific of front-end devices
Structure is defined.The front-end devices include grid structure, and as an example, grid structure includes from bottom to top layer successively
Folded gate dielectric and gate material layers.In the both sides of grid structure formed with side wall construction, half in side wall construction both sides
It is channel region between source/drain region formed with source/drain region in conductor substrate 200；In the top of grid structure and source/drain region
On formed with self-aligned silicide.
Material preferred SiCN, SiC or SiN of etching stopping layer 201, its as subsequent etch porous low k dielectric layer 202 with
While forming the etching stopping layer of the throughhole portions for the copper metal interconnection structure for connecting the front-end devices wherein, it can hinder
The copper metal for being only formed at the copper metal interconnection structure is diffused into interlayer dielectric layer where the front-end devices.
The formation of porous low k dielectric layer 202 comprises the following steps：Low k dielectric is deposited on etching stopping layer 201, its
Constituent material can be selected from this area it is common there is low k-value（Dielectric constant is less than 4.0）Material, including but not limited to k values
For 2.6-2.9 silicate compound (Hydrogen Silsesquioxane, referred to as HSQ), the HOSP that k values are 2.8TM
（The advanced low-k materials of the mixture based on organic matter and Si oxide of Honeywell companies manufacture）And k values are
2.65 SiLKTM（A kind of advanced low-k materials of Dow Chemical companies manufacture）Etc.；Using ultraviolet irradiation or add
The methods of hot, makes low k dielectric porous, to form porous low k dielectric layer 202, due to needing to implement porous process, therefore,
, it is necessary to add pore creating material precursor during low k dielectric is deposited, such as C10H16(ATRP)。
Cushion 203 includes transition material the layer 203a and TEOS stacked gradually from bottom to top（Tetraethyl orthosilicate）Layer
203b, transition material layer 203a effect are the adhesive force between the constituent material and TEOS for increasing porous low k dielectric layer 202,
TEOS layers 203b effect is the copper metal being filled in follow-up grinding in the copper metal interconnection structure for connecting the front-end devices
When avoid mechanical stress from causing to damage to the porous structure of porous low k dielectric layer 202.Transition material layer 203a constituent material
Including SiN, SiC or SiOC.
Hard mask layer 204 includes the metal hard mask layer 204a and oxide hard-mask layer stacked gradually from bottom to top
204b, the structure of this double-deck hard mask layer can ensure Dual graphing or the craft precision of multiple graphical, ensure in
The depth of whole figures and the uniformity of side wall profile formed needed for hard mask layer 204, i.e., will first have different characteristic chi
Very little pattern is formed in oxide hard-mask layer 204b, then using oxide hard-mask layer 204b as mask etch metal hard mask
Layer 204a makes the figure of required formation in hard mask layer 204.Metal hard mask layer 204a constituent material includes TiN, BN
Or its combination, preferably TiN；Oxide hard-mask layer 204b constituent material includes SiO2, SiON etc., and require its relative to
Metal hard mask layer 204a constituent material has preferable etching selectivity.
Then, as shown in Figure 2 B, the first opening 205 is formed in hard mask layer 204, to expose the cushion 203 of lower section.
The pattern of the throughhole portions of first opening, the 205 corresponding copper metal interconnection structure for connecting the front-end devices, it can be wrapped
Include multiple figures with different characteristic size.
According to the situation of the figure of required formation, need to implement the patterning process of the through-hole pattern twice or repeatedly, every time
Implementation comprises the following steps：ODL layers are sequentially formed on oxide hard-mask layer 204b（Organic dielectric layer）, BARC layer（Bottom
Portion's ARC）With PR layers（Photoresist layer）；Photoetching, development treatment are carried out to PR layers, to form through-hole pattern in PR layers；
Using the PR layers of patterning as mask, BARC layer, ODL layers and oxide hard-mask layer 204b are etched successively, in oxide hardmask
Through-hole pattern is formed in layer 204b；PR layers, BARC layer and the ODL layers of patterning are removed using techniques such as ashing.Finally, with it
The oxide hard-mask layer 204b of through-hole pattern needed for middle formation whole is mask, etches metal hard mask layer 204a, completes the
The making of one opening 205.
Then, as shown in Figure 2 C, it is mask with the hard mask layer 204 with the first opening 205, etch buffer layers successively
203 and porous low k dielectric layer 202, until exposing etching stopping layer 201.Institute is implemented using anisotropic dry method etch technology
Etching is stated, the etching forms the copper metal interconnection structure for connecting the front-end devices after terminating in porous low k dielectric layer 202
Through hole 207a.
Then, as shown in Figure 2 D, the second opening 206 is formed in hard mask layer 204, to expose the cushion 203 of lower section.
The pattern of the trench portions of second opening, the 206 corresponding copper metal interconnection structure for connecting the front-end devices, it can be wrapped
Include multiple figures with different characteristic size.
According to the situation of the figure of required formation, need to implement the patterning process of the channel patterns twice or repeatedly, every time
Implementation comprises the following steps：Another ODL layers, another BARC layer and another PR are sequentially formed on oxide hard-mask layer 204b
Layer；Photoetching, development treatment are carried out to another PR layers, to form channel patterns in another PR layers；With another PR layers of patterning
For mask, another BARC layer, another ODL layers and oxide hard-mask layer 204b are etched successively, in oxide hard-mask layer 204b
Middle formation channel patterns；Another PR layers, another BARC layer and another ODL layers of patterning are removed using techniques such as ashing.Finally,
Using the oxide hard-mask layer 204b for forming channel patterns needed for whole wherein as mask, metal hard mask layer 204a is etched,
Complete the making of the second opening 206.
Then, as shown in Figure 2 E, it is mask with the hard mask layer 204 with the second opening 206, etch buffer layers successively
203 and porous low k dielectric layer 202, the etching is implemented using anisotropic dry method etch technology, the etching terminate after
The groove 207b for the copper metal interconnection structure for connecting the front-end devices is formed in porous low k dielectric layer 202.
Next, the etching stopping layer 201 exposed by through hole 207a is removed, so that the copper metal interconnection structure and institute
State front-end devices connection.In the present embodiment, the removal of the etching stopping layer 201 is implemented using dry method etch technology.Then,
Etching last handling process is implemented using wet clean process, to remove residuals and impurity caused by foregoing etching process.
The technical process for being previously formed the copper metal interconnection structure for connecting the front-end devices is only dual damascene process
In one kind, those skilled in the art should know, form the dual damascene process of the copper metal interconnection structure
Other embodiment is also applicable, such as is initially formed the trench portions of the copper metal interconnection structure and re-forms the copper metal
The throughhole portions of interconnection structure, will not be repeated here its detailed implementation steps.
Then, as shown in Figure 2 F, copper metal diffusion barrier is formed in the side wall and bottom deposit of copper metal interconnection structure 207
Layer 208.In the present embodiment, it is described to be deposited as physical vapour deposition (PVD).The material of copper metal diffusion impervious layer 208 is metal, gold
Belong to nitride or its combination, preferably Ta and TaN combination or Ti and TiN combination.
Next, last handling process is implemented to Semiconductor substrate 200, to repair the porous low k dielectric layer to sustain damage
202, and lift the mechanical strength of porous low k dielectric layer 202.In the present embodiment, the last handling process comprises the following steps：
First, Semiconductor substrate 200 is placed in DEMS（A kind of silicone glass precursor, chemical formula are）Atmosphere
In, the porous low k dielectric layer 202 that sustains damage when forming copper metal interconnection structure 207 to repair, DEMS flow is 100-
5000sccm, temperature are 100-500 DEG C；Then, implement ultraviolet light to Semiconductor substrate 200 or infrared irridiation is handled, so that
The dielectric constant of porous low k dielectric layer 202 is returned to the numerical value before forming copper metal interconnection structure 207, the ultraviolet light spoke
According to power be more than 100W, wavelength 150-400nm, the power of the infrared irridiation is 50-3000W, wavelength is more than
400nm；Finally, argon is implemented to Semiconductor substrate 200（Ar）Plasma bombardment processing, to lift porous low k dielectric layer 202
Mechanical strength, the power that the argon plasma bombards is 100-3000W, the stream of pressure 0.1-10Torr, argon plasma
Measure as 100-3000sccm, wherein, Torr represents millimetres of mercury, and sccm represents cc/min.
Then, as shown in Figure 2 G, copper metal interconnection layer 209 is filled in copper metal interconnection structure 207.In the present embodiment
In, the filling is implemented using electroplating technology.In order to strengthen between copper metal interconnection layer 209 and copper metal diffusion impervious layer 208
Tack, before implementing the filling, copper metal Seed Layer is initially formed on copper metal diffusion impervious layer 208, to put it more simply,
It is not shown in figure.
Then, as illustrated in figure 2h, cmp is performed, until expose porous low k dielectric layer 202, in the process,
Hard mask layer 204 and cushion 203 are removed.
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed, next, can pass through
Subsequent technique completes the making of whole semiconductor devices.According to the present invention, sunk in the side wall of copper metal interconnection structure 207 and bottom
Product is formed after copper metal diffusion impervious layer 208, implements last handling process to Semiconductor substrate 200, can repair to form copper gold
Belong to the porous low k dielectric layer 202 to be sustained damage during interconnection structure 207, the mechanical strength of lifting porous low k dielectric layer 202, avoid
The decline of device performance.
Reference picture 3, the flow chart for the step of method according to an exemplary embodiment of the present invention is implemented successively is illustrated therein is,
For schematically illustrating the flow of whole manufacturing process.
In step 301, there is provided Semiconductor substrate, sequentially form etching stopping layer and porous low k on a semiconductor substrate
Dielectric layer；
In step 302, copper metal interconnection structure is formed in porous low k dielectric layer；
In step 303, copper metal diffusion impervious layer is formed in the side wall and bottom deposit of copper metal interconnection structure；
In step 304, last handling process is implemented to Semiconductor substrate, to repair the porous low k dielectric layer to sustain damage,
And lift the mechanical strength of porous low k dielectric layer；
In step 305, copper metal interconnection layer is filled in copper metal interconnection structure.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, sequentially forms etching stopping layer and porous low k dielectric layer on the semiconductor substrate；
Copper metal interconnection structure is formed in the porous low k dielectric layer；
Copper metal diffusion impervious layer is formed in the side wall and bottom deposit of the copper metal interconnection structure；
Last handling process is implemented to the Semiconductor substrate, to repair the porous low k dielectric layer to sustain damage, and lifts institute
The mechanical strength of porous low k dielectric layer is stated,
Wherein, the implementation steps of the last handling process include：The Semiconductor substrate is placed in DEMS atmosphere, to repair
Form the porous low k dielectric layer to be sustained damage during the copper metal interconnection structure；The Semiconductor substrate is implemented ultraviolet
Light or infrared irridiation processing, so that the dielectric constant of the porous low k dielectric layer is returned to and to form the copper metal and mutually link
Numerical value before structure；Argon plasma bombardment processing is implemented to the Semiconductor substrate, to lift the porous low k dielectric layer
Mechanical strength.
2. according to the method for claim 1, it is characterised in that the flow of the DEMS is 100-5000sccm, and temperature is
100-500℃。
3. according to the method for claim 1, it is characterised in that the power of the ultraviolet light irradiation is more than 100W, wavelength is
150-400nm, the power of the infrared irridiation is 50-3000W, wavelength is more than 400nm.
4. according to the method for claim 1, it is characterised in that the power of the argon plasma bombardment is 100-3000W,
Pressure is 0.1-10Torr, and the flow of the argon plasma is 100-3000sccm.
5. according to the method for claim 1, it is characterised in that the step of forming the copper metal interconnection structure includes：
The cushion and hard mask layer being laminated from bottom to top are formed on the porous low k dielectric layer；Formed and used in the hard mask layer
Make the first opening of the pattern of the groove in the copper metal interconnection structure, to expose the cushion；In the cushion and
The second opening of the pattern for the through hole being used as in the copper metal interconnection structure is formed in the porous low k dielectric layer；With described
Hard mask layer is mask, with cushion described in step etching and the porous low k dielectric layer, with the porous low k dielectric layer
Form the copper metal interconnection structure.
6. according to the method for claim 5, it is characterised in that after the etching terminates, in addition to removal passes through institute
The step of stating etching stopping layer and the implementation etching post processing that copper metal interconnection structure exposes.
7. according to the method for claim 1, it is characterised in that after implementing the last handling process, be additionally included in described
The step of copper metal interconnection layer is filled in copper metal interconnection structure.
8. according to the method for claim 7, it is characterised in that before implementing the filling, be additionally included in the copper metal
The step of copper metal Seed Layer is formed on diffusion impervious layer.
9. according to the method for claim 7, it is characterised in that after implementing the filling, in addition to perform chemical machinery
Grinding is until the step of exposing the porous low k dielectric layer.
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| TW201243948A (en) * | 2011-04-25 | 2012-11-01 | Applied Materials Inc | UV assisted silylation for recovery and pore sealing of damaged low k films |
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| CN103474342A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing damaged dielectric layer |
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