CN106971973B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

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CN106971973B
CN106971973B CN201610021334.6A CN201610021334A CN106971973B CN 106971973 B CN106971973 B CN 106971973B CN 201610021334 A CN201610021334 A CN 201610021334A CN 106971973 B CN106971973 B CN 106971973B
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layer
copper metal
hard mask
low
hole
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CN106971973A (en
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胡敏达
周俊卿
何其旸
张海洋
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the method comprises the following steps: providing a semiconductor substrate, and sequentially forming an etching stop layer, a low-k dielectric layer and a hard mask layer on the semiconductor substrate; forming a groove and a through hole for filling a copper metal interconnection layer in the low-k dielectric layer; performing a pretreatment process on the groove and the through hole to repair the appearance of the groove and the through hole and round the top corner parts of the groove and the through hole; a post-etching treatment process is performed to remove etching residues and impurities. According to the invention, the quality of the formed copper metal interconnection layer can be improved, and the performance of the device is further improved.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to a semiconductor manufacturing process, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
In back end of line (BEOL) of semiconductor devices, a dual damascene process is typically used to form a copper interconnect layer in a semiconductor device.
In order to improve the implementation precision of the dual damascene process, a hard mask stack structure needs to be formed on the low-k dielectric layer before forming the trench and the via hole for filling the copper metal interconnection layer in the low-k dielectric layer. The existing hard mask laminated structure is composed of a buffer layer and a hard mask layer which are laminated from bottom to top, wherein the buffer layer has the function of avoiding mechanical stress from damaging a porous structure of a low-k dielectric layer when a filled copper metal interconnection layer is ground subsequently, the hard mask layer is composed of a metal hard mask layer and an oxide hard mask layer which are laminated from bottom to top, and the double-layer hard mask layer structure can ensure the process precision of double patterning or multiple patterning.
The dual damascene process is usually performed by etching the buffer layer and the low-k dielectric layer (i.e. simultaneously etching the buffer layer and the low-k dielectric layer) by an All-in-one Etch (All-in-one Etch) process to form trenches and vias in the low-k dielectric layer for filling the copper metal interconnection layer. When the integrated etching is carried out, because the low-k dielectric layer has weaker mechanical strength, the residual stress in the metal hard mask layer can distort the shapes of the groove and the through hole with high depth-to-width ratio, and further the filling of a subsequent copper metal interconnection layer is influenced.
Therefore, a method is needed to solve the above problems.
Disclosure of Invention
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, and sequentially forming an etching stop layer, a low-k dielectric layer and a hard mask layer on the semiconductor substrate; forming a groove and a through hole for filling a copper metal interconnection layer in the low-k dielectric layer; performing a pretreatment process on the groove and the through hole to repair the appearance of the groove and the through hole and round the top corner parts of the groove and the through hole; a post-etching treatment process is performed to remove etching residues and impurities.
In one example, the preprocessing process includes: silicon sputtered by the plasma bombardment electrode is attached to the side walls and the bottoms of the grooves and the through holes to form spin-coating silicon layers so as to repair the appearances of the grooves and the through holes; using CF4And bombarding the hard mask layer to round the top corner parts of the groove and the through hole so as to be beneficial to filling of a subsequent copper metal interconnection layer.
In one example, the CF4The technological parameters of bombardment include: the temperature is 40-80 ℃, the pressure is 20-80mTorr, the low-frequency power is 0W, the high-frequency power is 200-2Or He/H2The volume ratio of the carrier gas component is 6:1-10:1, the carrier gas and the CF4The total flow rate of (1) is 600-2000 sccm.
In one example, a buffer layer is formed between the low-k dielectric layer and the hard mask layer.
In one example, the post-etch treatment process is performed using a wet clean process.
In one example, after the post-etch treatment process is performed, a step of filling the trench and the via with a copper metal interconnection layer is further included.
In one embodiment, the present invention also provides a semiconductor device manufactured by the above method.
In one embodiment, the present invention also provides an electronic apparatus including the semiconductor device.
According to the invention, the quality of the formed copper metal interconnection layer can be improved, and the performance of the device is further improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A-1B are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention;
fig. 2 is a flowchart of steps performed in sequence by a method according to a first exemplary embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the back end of the line process of the semiconductor device, a dual damascene process is usually used to form a copper interconnect layer in the semiconductor device. In order to improve the implementation precision of the dual damascene process, a hard mask stack structure needs to be formed on the low-k dielectric layer before forming the trench and the via hole for filling the copper metal interconnection layer in the low-k dielectric layer. The existing hard mask laminated structure is composed of a buffer layer and a hard mask layer which are laminated from bottom to top, wherein the buffer layer has the function of avoiding mechanical stress from damaging a porous structure of a low-k dielectric layer when a filled copper metal interconnection layer is ground subsequently, the hard mask layer is composed of a metal hard mask layer and an oxide hard mask layer which are laminated from bottom to top, and the double-layer hard mask layer structure can ensure the process precision of double patterning or multiple patterning.
The dual damascene process is typically performed by etching the buffer layer and the low-k dielectric layer (i.e., simultaneously etching the buffer layer and the low-k dielectric layer) using an integrated etching process to form trenches and vias in the low-k dielectric layer for filling the copper metal interconnect layer. When the integrated etching is carried out, because the low-k dielectric layer has weaker mechanical strength, the residual stress in the metal hard mask layer can distort the shapes of the groove and the through hole with high depth-to-width ratio, and further the filling of a subsequent copper metal interconnection layer is influenced.
In order to solve the above problem, as shown in fig. 2, the present invention provides a method of manufacturing a semiconductor device, the method including:
in step 201, providing a semiconductor substrate, and sequentially forming an etch stop layer, a low-k dielectric layer and a hard mask layer on the semiconductor substrate;
in step 202, forming a trench and a via in the low-k dielectric layer for filling the copper metal interconnection layer;
in step 203, performing a pretreatment process on the trench and the via hole to repair the topography of the trench and the via hole and round top corner portions of the trench and the via hole;
in step 204, a post-etch treatment process is performed to remove etch residues and impurities.
According to the manufacturing method of the semiconductor device, the groove and the through hole are subjected to a pretreatment process, the shapes of the groove and the through hole are repaired, the copper metal diffusion barrier layer and the copper metal seed layer which are formed subsequently can be better attached to the side walls and the bottoms of the groove and the through hole, the corner parts of the top ends of the groove and the through hole are rounded, the process window of the copper metal interconnection layer which is filled subsequently is expanded, the quality of the formed copper metal interconnection layer is improved, and the performance of the device is improved.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
[ exemplary embodiment one ]
Referring to fig. 1A-1B, there are shown schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.
First, as shown in fig. 1A, a semiconductor substrate 100 is provided, and an etch stop layer 101, a low-k dielectric layer 102, a buffer layer 103, and a hard mask layer 104 covering the semiconductor substrate 100 are sequentially formed on the semiconductor substrate 100 using a chemical vapor deposition process.
A front-end device is formed on the semiconductor substrate 100, and is not shown in the drawing for simplicity. The front-end device refers to a device formed before the back-end process is performed, and the specific structure of the front-end device is not limited herein.
The material of the etch stop layer 101 includes SiCN, SiC, SiN, BN, etc., which serves as an etch stop layer for subsequently etching the low-k dielectric layer 102 to form an upper copper metal interconnect structure therein while preventing copper in the lower copper metal interconnect layer from diffusing into the upper dielectric layer (e.g., the low-k dielectric layer 102).
The formation of the low-k dielectric layer 102 includes the steps of: a low-k dielectric layer is deposited on the etch stop layer 101, and the material of which can be selected from materials with low-k value (dielectric constant less than 4.0) commonly used in the art, including but not limited to silicate compounds (HSQ) with k value of 2.6-2.9, HOSP with k value of 2.8TM(Low dielectric constant material based on a mixture of organic and silicon oxides manufactured by Honeywell Corp.) and SiLK with a k value of 2.65TM(a low dielectric constant material manufactured by Dow Chemical Co., Ltd.), and the like; the low-k dielectric layer 102 is made porous by uv irradiation or heating, and a pore former precursor, such as C, is added during the deposition of the low-k dielectric layer 102 because the porous process is performed10H16(ATRP)。
The buffer layer 103 may include a bottom-up stacked OMCTS (octamethylcyclotetrasiloxane) layer that functions as a transition material layer between the low-k dielectric material and TEOS to increase adhesion therebetween, and a TEOS layer that functions to prevent mechanical stress from damaging the porous structure of the low-k dielectric material during subsequent polishing of the filled copper interconnect metal.
The hard mask layer 104 may include a metal hard mask layer and an oxide hard mask layer stacked from bottom to top, and the structure of the double-layer hard mask layer can ensure the process precision of double patterning or multiple patterning, and ensure the consistency of the depth and sidewall profile of all patterns to be formed in the hard mask layer 104, i.e., patterns with different feature sizes are formed in the oxide hard mask layer, and then the metal hard mask layer is etched to form the patterns to be formed in the hard mask layer 104 by using the oxide hard mask layer as a mask. The metal hard mask layer 104a is made of a material including Ti, TiN, BN, AlN, CuN, or any combination thereof, preferably TiN; oxidation by oxygenThe hard mask layer is made of SiO2SiON, etc., and requires a better etch selectivity with respect to the constituent material of the metal hardmask layer.
Next, as shown in fig. 1B, a copper metal interconnect structure 106 is formed in the low-k dielectric layer 102, and the etch stop layer 101 exposed through the copper metal interconnect structure 106 is removed, so that the copper metal interconnect structure 106 is in communication with the front-end devices formed on the semiconductor substrate 100.
The process of forming the copper metal interconnection structure 106 communicating with the front-end device may adopt a dual damascene process, such as an All-in-one Etch (All-in-one Etch) process, which includes the following process steps:
first, a first opening serving as a first pattern 106a in the copper metal interconnect structure 106 is formed in the hard mask layer 104 to expose the underlying buffer layer 103. The first opening may include a plurality of patterns with different feature sizes, and the patterning process of the first pattern 106a is performed two or more times according to the pattern to be formed, each of the processes including the following steps: sequentially forming an ODL layer (organic medium layer), a BARC layer (bottom anti-reflection coating) and a PR layer (photoresist layer) on the oxide hard mask layer; performing photolithography and development treatment on the PR layer to form a first pattern 106a in the PR layer; taking the patterned PR layer as a mask, sequentially etching the BARC layer, the ODL layer and the oxide hard mask layer to form a first pattern 106a in the oxide hard mask layer; and removing the patterned PR layer, the BARC layer and the ODL layer by ashing and the like. And finally, etching the metal hard mask layer by taking the oxide hard mask layer in which all the required first patterns 106a are formed as a mask, thereby finishing the manufacture of the first opening.
Next, a second opening, which may also include a plurality of patterns having different feature sizes, is formed in the buffer layer 103 and the low-k dielectric layer 102 to serve as a second pattern 106b in the copper metal interconnect structure 106. The patterning process of the second pattern 106b is performed two or more times according to the condition of the pattern to be formed, each of which includes the steps of: forming an ODL layer, a BARC layer and a PR layer in sequence on the semiconductor substrate 200 to cover the first opening; performing photolithography and development treatment on the PR layer to form a second pattern 106b in the PR layer; sequentially etching the BARC layer, the ODL layer, the buffer layer 103 and a part of the low-k dielectric layer 102 by using the patterned PR layer as a mask, and forming a second pattern 106b in the buffer layer 103 and the low-k dielectric layer 102; and removing the patterned PR layer, the BARC layer and the ODL layer by ashing and the like.
Finally, the buffer layer 103 and the low-k dielectric layer 102 are simultaneously etched by using the hard mask layer 104 as a mask, so as to form the copper metal interconnection structure 106 in the low-k dielectric layer 102, i.e., simultaneously form the first pattern 106a and the second pattern 106b (e.g., trench and via) in the copper metal interconnection structure 106. The integration etching is terminated when the etch stop layer 101 is exposed. As an example, the removal of the etch stop layer 101 is performed using a dry etching process.
A pretreatment process is performed on the copper metal interconnect structure 106 before the copper metal interconnect layer is filled in the formed copper metal interconnect structure 106.
The pretreatment process comprises the following steps: silicon sputtered by the plasma bombardment electrode is attached to the side wall and the bottom of the copper metal interconnection structure 106 to form a spin-coating silicon layer so as to repair the appearance of the copper metal interconnection structure 106; using CF4Bombarding the hard mask layer 104 to round the top corner part of the copper metal interconnection structure 106 to facilitate the subsequent filling of the copper metal interconnection layer, wherein the temperature is 40-80 ℃, the pressure is 20-80mTorr, the low-frequency power is 0W, the high-frequency power is 200-600W, and the carrier gas is Ar/H2Or He/H2The volume ratio of carrier gas component is 6:1-10:1, carrier gas and CF4The total flow rate of (1) is 600-2000 sccm.
And then, performing an etching post-treatment process to remove residues and impurities generated in the etching process, and ensuring the deposition quality of the copper metal diffusion barrier layer and the copper metal seed layer during subsequent deposition. The post-etch treatment may be performed using a conventional wet clean process.
To this end, the process steps performed by the method according to the first exemplary embodiment of the present invention are completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device.
Compared with the prior art, according to the method provided by the invention, before the copper metal interconnection layer is filled in the formed copper metal interconnection structure 106, the pretreatment process is carried out on the copper metal interconnection structure 106, the appearance of the copper metal interconnection structure 106 is repaired, simultaneously, the subsequently formed copper metal diffusion barrier layer and the copper metal seed layer can be better attached to the side wall and the bottom of the copper metal interconnection structure 106, the top corner part of the copper metal interconnection structure 106 is rounded, simultaneously, the process window of the subsequently filled copper metal interconnection layer is expanded, the quality of the subsequently formed copper metal interconnection layer is further improved, and the performance of the device is improved.
[ second exemplary embodiment ]
First, a semiconductor device obtained by the process steps implemented by the method according to the first exemplary embodiment of the present invention is provided, as shown in fig. 1B, including: the semiconductor substrate 100 has an isolation structure formed in the semiconductor substrate 100, and various well structures (wells), for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure.
The front-end devices formed on the semiconductor substrate 100 are not shown in the drawings for simplicity. The front-end device refers to a device formed before the back-end process is performed, and the specific structure of the front-end device is not limited herein.
An etch stop layer 101, a low-k dielectric layer 102, a buffer layer 103, and a hard mask layer 104 stacked from bottom to top formed on a semiconductor substrate 100; a copper metal interconnect structure 106 formed in the low-k dielectric layer 102 for filling a copper metal interconnect layer, the copper metal interconnect structure 106 comprising a first pattern 106a and a second pattern 106 b.
Then, the fabrication of the whole semiconductor device is completed through the following processes, including: the copper metal interconnect layer is formed in the copper metal interconnect structure 106 by performing a chemical mechanical polishing process to make the surface of the copper metal interconnect layer flush with the surface of the hard mask layer 104 using any suitable process technique known to those skilled in the art, such as an electroplating process followed by a chemical mechanical polishing process.
Before forming the copper metal interconnection layer, a copper metal diffusion barrier layer and a copper metal seed layer are required to be sequentially formed on the bottom and the side wall of the copper metal interconnection structure 106, the copper metal diffusion barrier layer can prevent copper in the copper metal interconnection layer from diffusing into the low-k dielectric layer 102, and the copper metal seed layer can enhance the adhesion between the copper metal interconnection layer and the copper metal diffusion barrier layer.
The copper metal diffusion barrier layer and the copper metal seed layer may be formed by any suitable process known to those skilled in the art, such as physical vapor deposition, sputtering, or chemical vapor deposition, and the copper metal diffusion barrier layer may be formed of a metal, a metal nitride, or a combination thereof, such as a combination of Ta and TaN or a combination of Ti and TiN.
Repeating the steps to form a plurality of interconnected metal layers; and forming a metal bonding pad for wire bonding in the subsequent device packaging process.
[ exemplary embodiment III ]
The present invention also provides an electronic device including the semiconductor device according to the second exemplary embodiment of the present invention. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device. The electronic device has better performance due to the use of the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (7)

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, and sequentially forming an etching stop layer, a low-k dielectric layer and a hard mask layer on the semiconductor substrate;
forming a groove and a through hole for filling a copper metal interconnection layer in the low-k dielectric layer;
performing a pretreatment process on the groove and the through hole to repair the appearance of the groove and the through hole and round the top corner parts of the groove and the through hole;
performing a post-etching treatment process to remove etching residues and impurities; wherein the pre-processing process comprises: and silicon sputtered by the plasma bombardment electrode is attached to the side walls and the bottoms of the grooves and the through holes to form a spin-coating silicon layer so as to repair the appearances of the grooves and the through holes.
2. The method of claim 1, wherein the preprocessing process further comprises: using CF4And bombarding the hard mask layer to round the top corner parts of the groove and the through hole so as to be beneficial to filling of a subsequent copper metal interconnection layer.
3. The method of claim 1, wherein a buffer layer is formed between the low-k dielectric layer and the hard mask layer.
4. The method of claim 1, wherein the post-etch treatment process is performed using a wet clean process.
5. The method of claim 1, further comprising the step of filling the trench and via with a copper metal interconnect layer after performing the post-etch treatment process.
6. A semiconductor device manufactured by the method of any one of claims 1 to 5.
7. An electronic device, characterized in that the electronic device comprises the semiconductor device according to claim 6.
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