WO2012145977A1 - 半导体器件及其编程方法 - Google Patents

半导体器件及其编程方法 Download PDF

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Publication number
WO2012145977A1
WO2012145977A1 PCT/CN2011/078327 CN2011078327W WO2012145977A1 WO 2012145977 A1 WO2012145977 A1 WO 2012145977A1 CN 2011078327 W CN2011078327 W CN 2011078327W WO 2012145977 A1 WO2012145977 A1 WO 2012145977A1
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Prior art keywords
via structure
silicon via
semiconductor substrate
fuse
interconnect
Prior art date
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PCT/CN2011/078327
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English (en)
French (fr)
Inventor
钟汇才
梁擎擎
赵超
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/321,852 priority Critical patent/US20130037859A1/en
Publication of WO2012145977A1 publication Critical patent/WO2012145977A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a programming method thereof. Background technique
  • the 3D package vertically packs two or more integrated circuits in the same chip, which can reduce the occupied space.
  • the commonly used substrate for carrying integrated circuits often has a through-silicon via structure (TSV, Through). -Silicon- Vias ).
  • TSV through-silicon via structure
  • -Silicon- Vias By using a through silicon via structure instead of a traditional edge connection for 3D packaging, more logic can be integrated into a small device footprint.
  • the through silicon via structure can effectively shorten the critical path, reduce the delay, and increase the device speed.
  • the forming method of the through silicon via structure mainly comprises: forming a through via on the semiconductor substrate, and filling therein a connection nail formed by connecting the interconnection line in the semiconductor substrate, and then connecting the nail through the connecting nail
  • the interconnect structure on the other wafer or another chip is connected to implement a 3D package.
  • the prior art through-silicon via structure is mainly formed based on a copper interconnection process, and FIGS. 1 to 5 show
  • a semiconductor substrate 10 is provided, on which semiconductor devices such as MOS transistors may be formed, and interconnection structures such as plugs, interconnects, and the like may also be formed.
  • the upper surface of the semiconductor substrate 10 is etched to form an opening 11.
  • a barrier layer 12 is formed covering the bottom of the opening, the sidewall, and the semiconductor substrate The upper surface of 10, and then metal copper 13 is formed on the barrier layer 12 by electroplating to fill the opening, and further includes forming a seed layer on the surface of the barrier layer 12 before forming the metal copper 13. ).
  • the metal copper and the barrier layer 12 overlying the semiconductor substrate 10 are planarized to expose the upper surface of the semiconductor substrate 10 to form the connecting studs 13a.
  • the semiconductor substrate 10 is thinned from the lower surface thereof to expose the connecting stud 13a so that the opening becomes a through hole penetrating the entire semiconductor substrate 10, completing the formation of the through silicon via structure. process.
  • the through silicon via structures formed in the prior art are generally electrically connected to a predetermined interconnection line in the semiconductor substrate, and then the predetermined interconnection is performed through the through silicon via structure when performing 3D packaging.
  • the wires are electrically connected to interconnect structures on other substrates. Since the connection relationship between the through-silicon via structure and the interconnect line is fixed, it is difficult to make corresponding changes according to the needs of the actual application, and the application flexibility is low.
  • the problem solved by the present invention is to provide a semiconductor device and a programming method thereof, which improve the flexibility of the through-silicon via structure application.
  • the present invention provides a semiconductor device comprising: a semiconductor substrate having interconnect lines formed therein; a through silicon via structure extending through the semiconductor substrate;
  • a programmable device that can switch between on and off states through which the through silicon via structure A programmable device is coupled to the interconnect.
  • the programmable device is a capacitor formed in the semiconductor substrate or on the semiconductor substrate, an upper plate thereof is electrically connected to the through-silicon via structure, and a lower plate and the interconnection are Line electrical connection.
  • the through silicon via structure is divided into a first portion and a second portion, wherein the first portion is connected to the upper plate of the capacitor, and the second portion is connected to the lower plate of the capacitor, the interconnect line and the The first portion or the second portion of the through silicon via structure is electrically connected.
  • the programmable device is a fuse or an anti-fuse formed in the semiconductor substrate or on the semiconductor substrate, one end of which is electrically connected to the through-silicon via structure, and the other end thereof is The interconnect is electrically connected.
  • the fuse or antifuse splits the through silicon via structure into a first portion and a second portion, wherein the first portion is connected to one end of the fuse or the antifuse, and the second portion is coupled to the fuse or The other end of the antifuse is connected, and the interconnect is electrically connected to the first or second portion of the through silicon via structure.
  • the programmable device is a floating gate MOS transistor formed in the semiconductor substrate, and a source and a drain thereof are electrically connected to the through silicon via structure and the interconnection, respectively.
  • the programmable device is a microprocessor (CPU), a logic control device controlled by a Field-Programmable Gate Array (FPGA), and a Programmable Logic Controller (PLC). Or Micro Control Unit (MCU).
  • CPU microprocessor
  • FPGA Field-Programmable Gate Array
  • PLC Programmable Logic Controller
  • MCU Micro Control Unit
  • the present invention also provides a programming method of the above semiconductor device, comprising: The row is programmed to electrically connect or disconnect the through silicon via structure to the interconnect.
  • the embodiment of the present invention has the following advantages:
  • the semiconductor device of the embodiment of the invention the through silicon via structure is connected to the interconnection line in the semiconductor substrate through the programmable device, thereby being able to pass the
  • the programming of the programming device to achieve the on or off between the through silicon via structure and the interconnect line is beneficial to improve flexibility in practical applications.
  • the programmable device in this embodiment may be a capacitor, a fuse, or an anti-fuse, which may be formed in a semiconductor substrate or a semiconductor substrate, or may be embedded in a through-silicon via structure. Further, the programmable device further It may be a floating gate MOS transistor formed in a semiconductor substrate.
  • the above programmable devices can be formed by a common semiconductor processing process, and thus have good industrial applicability.
  • 1 to 5 are schematic cross-sectional views showing a method of forming a through silicon via structure in the prior art
  • FIG. 6 is a cross-sectional structural view showing an embodiment of a semiconductor device of the present invention.
  • Figure 7 is a cross-sectional structural view showing another embodiment of the semiconductor device of the present invention.
  • Figure 8 is a schematic diagram showing the logical structure of an embodiment of a semiconductor device of the present invention.
  • the through-silicon via structure formed in the semiconductor substrate in the prior art is often fixedly connected to a predetermined interconnection line, and has low flexibility in practical use.
  • the through silicon via structure is connected to the interconnection line in the semiconductor substrate through the programmable device, so that the through silicon via structure and the interconnection line can be realized by programming the programmable device.
  • the continuity or disconnection is beneficial to improve the flexibility in the actual application process.
  • the programmable device in this embodiment may be a capacitor, a fuse, or an anti-fuse, which may be formed in a semiconductor substrate or a semiconductor substrate, or may be embedded in a through-silicon via structure.
  • the programmable device further It may be a floating gate MOS transistor formed in a semiconductor substrate.
  • the above programmable devices can be formed by a common semiconductor processing process, and thus have good industrial applicability.
  • FIG. 6 is a cross-sectional structural view of an embodiment of a semiconductor device of the present invention, comprising: a semiconductor substrate 20 having interconnect lines 22a formed therein; a through silicon via structure 21 extending through the semiconductor substrate 20; A programmable device 23 that switches between the on and off states, the through silicon via structure 21 being connected to the interconnect 22a by the programmable device 23.
  • the programmable device 23 is a capacitor, a fuse, an antifuse or a floating gate MOS transistor (floating gate MOS) formed on the semiconductor substrate 20 or on the surface of the semiconductor substrate 20.
  • Transistor floating gate MOS
  • the above capacitors, fuses, anti-fuse, and MOS transistors with floating gates can be formed by conventional semiconductor processing in the process of forming the interconnections 22a, and have good industrial availability.
  • the semiconductor substrate 20 may be a silicon substrate, a silicon substrate, a ⁇ -V element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or other semiconductors known to those skilled in the art.
  • the interconnection line 22a may be a copper interconnection, an aluminum interconnection, or the like, and is electrically connected to a device such as the MOS transistor through an interconnection structure such as a via hole or a contact hole.
  • the programmable device 23 and interconnects 22a, 22b may be located in the same dielectric layer or in different dielectric layers.
  • the programmable device 23 is a capacitor, a fuse or an antifuse formed on the surface of the semiconductor substrate 20, through the wires distributed on the semiconductor substrate 20 and the through silicon via structure 21 Electrical connection, since the programmable device 23 is located on the surface of the semiconductor substrate 20, the manufacturing process is more compact.
  • the through silicon via structure 21 is The upper plate is electrically connected, and the interconnect 22a is electrically connected to the lower plate.
  • the upper plate and the lower plate are insulated to disconnect the through silicon via structure 21 and the interconnect 22a, and the through silicon via structure is used in subsequent applications such as 3D packaging.
  • 21 Idle not used for interconnection between semiconductor substrates.
  • a breakdown voltage may be applied between the upper and lower plates of the capacitor such that the capacitor is turned on after being turned on, that is, the through silicon via structure 21 and the interconnect 22a are turned on.
  • the electrical connection between the interconnect 22a and the other semiconductor substrate can be realized by the through silicon via structure 21 in practical applications such as subsequent 3D packaging.
  • the programmable device 23 is a fuse or an anti-fuse
  • the The through silicon via structure 21 is electrically connected to one end of a fuse or an antifuse
  • the interconnect 22a is electrically connected to the other end of the fuse or the antifuse.
  • the fuse is turned on, and the anti-fuse is turned off, so that the through-silicon via structure 21 and the interconnect 22a are also turned on or off correspondingly.
  • a programming current may be applied to the fuse or antifuse such that the fuse is turned off, or the antifuse is turned on, thereby correspondingly between the through silicon via structure 21 and the interconnect 22a. Turn off or turn on. Therefore, the through silicon via structure 21 and the interconnect 22a can be turned on or off flexibly according to the needs of practical applications.
  • the programmable device 23 is a MOS transistor with a floating gate, specifically a MOS transistor with a floating gate used in a memory such as an EPROM, an EEPROM, or a FLASH
  • the floating gate is One end of the source or the drain of the MOS transistor is electrically connected to the through silicon via structure 21, and the other end of the source or drain is electrically connected to the interconnect 22a.
  • electrons can be injected or erased in the floating gate, thereby switching between the on and off states between the source and the drain of the floating gate MOS transistor, that is, the through silicon via structure 21 It is turned on or off with the interconnect 22a.
  • the method includes: a semiconductor substrate 30 having interconnect lines 32a formed therein; and a through silicon via structure 31.
  • a semiconductor substrate 30 having interconnect lines 32a formed therein; and a through silicon via structure 31.
  • the semiconductor substrate 30 Through the semiconductor substrate 30; a programmable device 33 that can switch between on and off states, the through silicon via structure 31 being connected to the interconnect line 32a through the programmable device 33.
  • the programmable device 33 is a capacitor, a fuse or an anti-fuse embedded in the through silicon via structure 31.
  • MOS transistors and interconnection lines 32a, 32b may also be formed in the semiconductor substrate 30. and many more.
  • the capacitive, fuse or anti-fuse programmable device 33 divides the through silicon via structure 31 into a first portion 31a and a second portion 31b, wherein the first portion 31a is connected to the upper plate of the capacitor, and the second portion 31b is The lower plate of the capacitor is connected, or the first portion 31a is connected to one end of the fuse or the antifuse, and the second portion 31b is connected to the other end of the fuse or the antifuse.
  • the interconnecting portion 32a is electrically connected to the first portion 31a of the through-silicon via structure 31 or the second portion 31b is electrically connected to the first portion 31a.
  • the second portion is connected to the first portion 31a.
  • 31b is connected to other semiconductor substrates.
  • the through-silicon via structure 31 (specifically, the second portion 31b in this embodiment) and the interconnect line 32 can be guided by programming a capacitor, a fuse or an anti-fuse. Turn on or off to increase flexibility in actual use.
  • the programmable device may also be a single microprocessor located in the semiconductor substrate or on the semiconductor substrate, an FPGA controlled logic control device, a programmable logic controller or a micro control unit, etc.
  • a device with logic control function realizes switching between the through-silicon via structure and the interconnection state through logic control or programming, thereby improving the flexibility in practical applications.
  • FIG. 8 is a schematic diagram showing the logic structure of a semiconductor device according to an embodiment of the present invention, including: a plurality of interconnect lines 42; a through silicon via structure 41; a programmable device 43, through which the through silicon via structure 41 is passed through the programmable device 43
  • the interconnects 42 are connected, and the programmable device can be a capacitor, a fuse, an anti-fuse or a MOS transistor with a floating gate.
  • the present invention also provides a programming method of the above semiconductor device. Referring to FIG. 8, the programmable device 43 is programmed to electrically connect or disconnect the through-silicon via structure 41 and the interconnect 42 to improve Flexibility in practical applications.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

一种半导体器件及其编程方法，所述半导体器件包括：半导体基底，所述半导体基底中形成有互连线；穿硅通孔结构，贯穿所述半导体基底；还包括可切换导通和关断状态的可编程器件，所述穿硅通孔结构通过所述可编程器件与所述互连线相连。本发明有利于提高穿硅通孔结构在实际应用中的灵活度。

Description

半导体器件及其编程方法
本申请要求于 2011 年 4 月 29 日提交中国专利局、 申请号为 201110112295.8、 发明名称为"半导体器件及其编程方法"的中国专利申请的优 先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体技术领域， 特别涉及一种半导体器件及其编程方法。 背景技术
3D封装将两片或更多的集成电路垂直堆叠封装在同一芯片中， 从而可以 减少占用的空间， 在 3D封装中， 常用的承载集成电路的村底往往具有穿硅通 孔结构 （TSV, Through-Silicon- Vias ) 。 通过采用穿硅通孔结构来取代传统的 边缘连线来进行 3D封装， 可以在一个小的器件封装（footprint ) 中集成更多的 逻辑功能。 此外， 采用穿硅通孔结构可以有效的缩短关键路径（critical path ) , 减小延迟， 提高器件速度。 穿硅通孔结构的形成方法主要包括： 在半导体基底上形成贯穿的通孔， 并 在其中填充形成连接釘（nail ) , 该连接釘与半导体基底中的互连线相连， 之 后通过连接釘与另一晶圓或另一芯片上的互连结构相连， 从而实现 3D封装。 现有技术的穿硅通孔结构主要是基于铜互连工艺形成的，图 1至图 5示出了
参考图 1 , 提供半导体基底 10, 所述半导体基底 10上可以形成有半导体器 件， 如 MOS晶体管， 此外也可以形成有互连结构， 如栓塞、 互连线等。 参考图 2, 对所述半导体基底 10的上表面进行刻蚀， 形成开口 11。 参考图 3 , 形成阻挡层 12, 覆盖所述开口的底部、 侧壁和所述半导体基底 10的上表面，之后在所述阻挡层 12上通过电镀法形成金属铜 13 ,填充所述开口， 在形成金属铜 13之前还包括在所述阻挡层 12的表面上形成籽晶层（ seed layer )。
参考图 4, 对覆盖在半导体基底 10上的金属铜和阻挡层 12进行平坦化， 至 暴露出所述半导体基底 10的上表面， 形成连接釘 13a。
参考图 5 , 从所述半导体基底 10的下表面对其进行减薄， 至暴露出所述连 接釘 13a, 使得所述开口成为贯穿整个半导体基底 10的通孔， 完成穿硅通孔结 构的形成过程。
现有技术中形成的穿硅通孔结构一般都是与半导体基底中预设的互连线 电连接的， 之后在进行 3D封装时， 通过该穿硅通孔结构将所述预设的互连线 与其他基底上的互连结构进行电连接。由于穿硅通孔结构与互连线之间的连接 关系是固定的，难以根据实际应用的需求进行相应的改变，应用的灵活度较低。
关于穿硅通孔结构的更多详细描述，请参考专利号为 7,683,459和 7,633,165 的美国专利。 发明内容
本发明解决的问题是提供一种半导体器件及其编程方法，提高穿硅通孔结 构应用的灵活度。
为解决上述问题， 本发明提供了一种半导体器件， 包括： 半导体基底， 所述半导体基底中形成有互连线； 穿硅通孔结构， 贯穿所述半导体基底；
还包括可切换导通和关断状态的可编程器件，所述穿硅通孔结构通过所述 可编程器件与所述互连线相连。
可选地，所述可编程器件为形成于所述半导体基底中或所述半导体基底上 的电容，其上极板与所述穿硅通孔结构电连接，其下极板与所述互连线电连接。
所述穿硅通孔结构分割为第一部分和第二部分，其中第一部分与所述电容的上 极板相连， 第二部分与所述电容的下极板相连， 所述互连线与所述穿硅通孔结 构的第一部分或第二部分电连接。
可选地，所述可编程器件为形成于所述半导体基底中或所述半导体基底上 的熔丝或反熔丝， 其一端与所述穿硅通孔结构电连接， 其另一端与所述互连线 电连接。
所述熔丝或反熔丝将所述穿硅通孔结构分割为第一部分和第二部分，其中第一 部分与所述熔丝或反熔丝的一端相连，第二部分与所述熔丝或反熔丝的另一端 相连， 所述互连线与所述穿硅通孔结构的第一部分或第二部分电连接。
可选地， 所述可编程器件为形成于所述半导体基底中的带浮栅的 MOS晶 体管， 其源极和漏极分别与所述穿硅通孔结构和互连线电连接。
可选地，所述可编程器件为微处理器（ CPU )、受现场可编程门阵列（ FPGA, Field-Programmable Gate Array ) 控制的逻辑控制器件、 可编程逻辑控制器 ( PLC, Programmable Logic Controller )或微控制单元（ MCU )。
本发明还提供了上述半导体器件的编程方法， 包括： 对所述可编程器件进 行编程， 以使所述穿硅通孔结构与所述互连线电连接或断开。 与现有技术相比， 本发明的实施例有如下优点： 本发明实施例的半导体器件中，穿硅通孔结构通过可编程器件与半导体基 底中的互连线相连，从而能够通过对该可编程器件的编程来实现穿硅通孔结构 与互连线之间的通或者断， 有利于提高在实际应用过程中的灵活度。 本实施例中的可编程器件可以是电容、 熔丝、反熔丝， 既可以形成于半导 体基底中或半导体基底上， 也可以嵌于穿硅通孔结构中， 此外， 所述可编程器 件还可以是形成于半导体基底中的带浮栅的 MOS晶体管。 上述可编程器件都 可以采用常用的半导体加工工艺来形成， 因而具有 ί艮好的工业实用性。 附图说明
通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1 至图 5是现有技术的一种穿硅通孔结构的形成方法的剖面结构示意 图；
图 6是本发明半导体器件的一个实施例的剖面结构示意图；
图 7是本发明半导体器件的另一个实施例的剖面结构示意图；
图 8是本发明半导体器件的实施例的逻辑结构示意图。
具体实施方式
现有技术中形成于半导体基底中的穿硅通孔结构往往与预设的互连线固 定连接， 在实际使用时的灵活度较低。 本发明实施例的半导体器件中，穿硅通孔结构通过可编程器件与半导体基 底中的互连线相连，从而能够通过对该可编程器件的编程来实现穿硅通孔结构 与互连线之间的通或者断， 有利于提高在实际应用过程中的灵活度。 本实施例中的可编程器件可以是电容、 熔丝、反熔丝， 既可以形成于半导 体基底中或半导体基底上， 也可以嵌于穿硅通孔结构中， 此外， 所述可编程器 件还可以是形成于半导体基底中的带浮栅的 MOS晶体管。 上述可编程器件都 可以采用常用的半导体加工工艺来形成， 因而具有 ί艮好的工业实用性。 为使本发明的上述目的、特征和优点能够更为明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
在以下描述中阐述了具体细节以便于充分理解本发明。但是本发明能够以 多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明 内涵的情况下做类似推广。 因此本发明不受下面公开的具体实施方式的限制。 图 6是本发明半导体器件的一个实施例的剖面结构示意图， 包括： 半导体 基底 20, 所述半导体基底 20中形成有互连线 22a; 穿硅通孔结构 21 , 贯穿所 述半导体基底 20; 可切换导通和关断状态的可编程器件 23 , 所述穿硅通孔结 构 21通过所述可编程器件 23与所述互连线 22a相连。 本实施例中， 所述可编 程器件 23 为形成于半导体基底 20 中或半导体基底 20表面上的电容、 熔丝 ( fuse ), 反熔丝 （antifuse ) 或带浮栅的 MOS 晶体管 （floating gate MOS transistor )。 上述电容、 熔丝、 反熔丝以及带浮栅的 MOS晶体管可以在形成互 连线 22a的过程中， 采用常规的半导体加工工艺一并形成， 具有艮好的工业可 用性。 所述半导体基底 20可以是硅村底、 错硅村底、 ΠΙ - V族元素化合物村底、 碳化硅村底或其叠层结构， 或绝缘体上硅结构， 或本领域技术人员公知的其他 半导体材料村底， 其中可以形成有 MOS 晶体管等器件， 所述半导体基底 20 还可以包括覆盖在 MOS晶体管等器件上的多层介质层， 所述介质层中形成有 互连线 22a、 互连线 22b等。 所述互连线 22a可以是铜互连线、 铝互连线等， 通过通孔、 接触孔等互连结构与所述 MOS晶体管等器件相电连接。 所述可编 程器件 23和互连线 22a、 22b可以位于同一层介质层中， 也可以位于不同的介 质层中。 在一优选的实施例中， 所述可编程器件 23 为形成于半导体基底 20 表面上的电容、 熔丝或反熔丝， 通过分布于半导体基底 20上的导线与所述穿 硅通孔结构 21电连接， 由于可编程器件 23位于半导体基底 20的表面， 因而 其制造工艺更加筒单。
根据具体实施例的不同， 若可编程器件 23为包括上极板、 下极板以及位 于上极板和下极板之间的介质层的电容， 则所述穿硅通孔结构 21与所述上极 板电连接， 所述互连线 22a与所述下极板电连接。 在常规状态下， 所述上极板 和下极板之间绝缘， 使得穿硅通孔结构 21和互连线 22a之间断开， 则在后续 进行 3D封装等应用时， 该穿硅通孔结构 21 闲置， 不用于半导体基底之间的 互连。 此外， 可以在所述电容的上极板和下极板之间施加一击穿电压， 使得该 电容击穿后导通， 也即使得穿硅通孔结构 21和互连线 22a之间导通， 则在后 续 3D封装等实际应用时， 可以通过该穿硅通孔结构 21实现互连线 22a与其 他半导体基底之间的电连接。
根据具体实施例的不同， 若所述可编程器件 23为熔丝或反熔丝， 则所述 穿硅通孔结构 21与熔丝或反熔丝的一端电连接， 互连线 22a与熔丝或反熔丝 的另一端电连接。 在常规状态下， 所述熔丝导通， 所述反熔丝关断， 使得穿硅 通孔结构 21和互连线 22a之间也相应的导通或关断。 此外， 可以在所述熔丝 或反熔丝上施加一编程电流， 使得熔丝关断， 或使得反熔丝导通， 从而使得穿 硅通孔结构 21和互连线 22a之间也相应的关断或导通。 从而可以 ^据实际应 用的需要灵活的将穿硅通孔结构 21与互连线 22a导通或关断。
根据具体实施例的不同， 若所述可编程器件 23为带浮栅的 MOS晶体管， 具体可以是 EPROM、 EEPROM、 FLASH等存储器中所采用的带浮栅的 MOS 晶体管， 则所述带浮栅的 MOS晶体管的源极或漏极中的一端与穿硅通孔结构 21 电连接， 源极或漏极中的另一端与互连线 22a电连接。 通过编程， 可以在 浮栅中注入电子或将电子擦除， 从而实现带浮栅的 MOS晶体管的源极和漏极 之间的导通和关断状态的切换， 也即将穿硅通孔结构 21与互连线 22a导通或 关断。
图 7示出了本发明半导体器件的另一个实施例的剖面结构示意图， 如图 7 所示， 包括： 半导体基底 30, 所述半导体基底 30中形成有互连线 32a; 穿硅 通孔结构 31 , 贯穿所述半导体基底 30; 可切换导通和关断状态的可编程器件 33 , 所述穿硅通孔结构 31通过所述可编程器件 33与所述互连线 32a相连。 本 实施例中， 所述可编程器件 33为嵌于所述穿硅通孔结构 31中的电容、熔丝或 反熔丝。
所述半导体基底 30的材料请参见上述实施例的描述， 这里不再赘述。 所 述半导体基底 30中也可以形成有 MOS晶体管等器件， 以及互连线 32a、 32b 等等。
所述电容、熔丝或反熔丝的可编程器件 33将穿硅通孔结构 31分割为第一 部分 31a和第二部分 31b, 其中第一部分 31a与电容的上极板相连， 第二部分 31b与电容的下极板相连， 或者第一部分 31a与熔丝或反熔丝的一端相连， 第 二部分 31b与熔丝或反熔丝的另一端相连。 互连线 32a与穿硅通孔结构 31的 第一部分 31a电连接或第二部分 31b电连接， 本实施例中具体和第一部分 31a 相连， 在后续进行 3D封装等应用时， 所述第二部分 31b与其他半导体基底相 连。
与前述实施例类似的， 通过对电容、 熔丝或反熔丝的编程， 可以使得穿硅 通孔结构 31 (本实施例中具体为其中的第二部分 31b ) 与互连线 32之间导通 或关断， 提高实际使用中的灵活度。
在其他实施例中，所述可编程器件还可以是位于所述半导体基底中或半导 体基底上的筒单的微处理器、受 FPGA控制的逻辑控制器件、可编程逻辑控制 器或微控制单元等具有逻辑控制功能的器件，通过逻辑控制或编程， 实现穿硅 通孔结构与互连线之间的导通和关断状态的切换， 提高实际应用中的灵活度。
图 8示出了本发明实施例的半导体器件的逻辑结构示意图， 包括： 多条互 连线 42; 穿硅通孔结构 41 ; 可编程器件 43 , 穿硅通孔结构 41通过可编程器 件 43与互连线 42相连， 所述可编程器件可以是电容、 熔丝、反熔丝或带浮栅 的 MOS晶体管等。 本发明还提供了上述半导体器件的编程方法， 参考图 8, 对所述可编程器件 43进行编程， 使得所述穿硅通孔结构 41与互连线 42之间 电连接或断开， 从而提高实际应用中的灵活度。 本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何 本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法 和技术内容对本发明技术方案做出可能的变动和修改， 因此， 凡是未脱离本发 改、 等同变化及修饰， 均属于本发明技术方案的保护范围。

Claims

权 利 要 求
1. 一种半导体器件， 包括：
半导体基底， 所述半导体基底中形成有互连线；
穿硅通孔结构， 贯穿所述半导体基底；
其特征在于， 还包括可切换导通和关断状态的可编程器件， 所述穿硅通孔 结构通过所述可编程器件与所述互连线相连。
2. 根据权利要求 1所述的半导体器件， 其特征在于， 所述可编程器件为形成 于所述半导体基底中或所述半导体基底上的电容，其上极板与所述穿硅通孔结 构电连接， 其下极板与所述互连线电连接。
3. 根据权利要求 1所述的半导体器件， 其特征在于， 所述可编程器件为嵌于 所述穿硅通孔结构中的电容，所述电容将所述穿硅通孔结构分割为第一部分和 第二部分， 其中第一部分与所述电容的上极板相连， 第二部分与所述电容的下 极板相连， 所述互连线与所述穿硅通孔结构的第一部分或第二部分电连接。
4. 根据权利要求 1所述的半导体器件， 其特征在于， 所述可编程器件为形成 于所述半导体基底中或所述半导体基底上的熔丝或反熔丝，其一端与所述穿硅 通孔结构电连接， 其另一端与所述互连线电连接。
5. 根据权利要求 1所述的半导体器件， 其特征在于， 所述可编程器件为内嵌 于所述穿硅通孔结构中的熔丝或反熔丝，所述熔丝或反熔丝将所述穿硅通孔结 构分割为第一部分和第二部分， 其中第一部分与所述熔丝或反熔丝的一端相 连， 第二部分与所述熔丝或反熔丝的另一端相连， 所述互连线与所述穿硅通孔 结构的第一部分或第二部分电连接。
6. 根据权利要求 1所述的半导体器件， 其特征在于， 所述可编程器件为形成 于所述半导体基底中的带浮栅的 MOS晶体管， 其源极和漏极分别与所述穿硅 通孔结构和互连线电连接。
7. 根据权利要求 1所述的半导体器件， 其特征在于， 所述可编程器件为位于 所述半导体基底中或所述半导体基底上的微处理器、受现场可编程门阵列控制 的逻辑控制器件、 可编程逻辑控制器或微控制单元。
8. 一种对权利要求 1至 7中任一项所述的半导体器件的编程方法， 其特征在 于， 包括： 对所述可编程器件进行编程， 以使所述穿硅通孔结构与所述互连线 电连接或断开。
PCT/CN2011/078327 2011-04-29 2011-08-12 半导体器件及其编程方法 Ceased WO2012145977A1 (zh)

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