WO2012139382A1 - 硅纳米线晶体管器件可编程阵列及其制备方法 - Google Patents

硅纳米线晶体管器件可编程阵列及其制备方法 Download PDF

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WO2012139382A1
WO2012139382A1 PCT/CN2011/082465 CN2011082465W WO2012139382A1 WO 2012139382 A1 WO2012139382 A1 WO 2012139382A1 CN 2011082465 W CN2011082465 W CN 2011082465W WO 2012139382 A1 WO2012139382 A1 WO 2012139382A1
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nanowire
silicon
gate
region
channel
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French (fr)
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黄如
邹积彬
王润声
樊捷闻
刘长泽
王阳元
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Peking University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/383—Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0195—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3462—Nanowires

Definitions

  • the invention belongs to the field of CMOS very large scale integrated circuit (ULSI) manufacturing technology, and particularly relates to a silicon nanowire metal-Oxide-Silicon Field Effect Transistor (SNW MOSFET) hexagonal programmable array (Hexagonal Programmable Array). And its preparation method.
  • ULSI very large scale integrated circuit
  • SNW MOSFET silicon nanowire metal-Oxide-Silicon Field Effect Transistor
  • Hexagonal Programmable Array hexagonal programmable array
  • Semiconductor devices are important components in the manufacture of electronic products.
  • the replacement of semiconductor devices has advanced the development of semiconductor technology and advances in the semiconductor industry, especially for CPU and memory of central processing units. Since the end of the last century, the chip manufacturing process has developed rapidly, from micron level to today's technology less than 32nm.
  • the gate control capability of the conventional planar tube device is gradually reduced, the device characteristics are degraded, and the short channel effect is affected.
  • the gate oxide thickness is at most a few nanometers or even less than one nanometer. Such a thin gate oxide thickness can cause severe gate leakage current, which deteriorates device performance, reliability, and greatly increases device power consumption. If the junction depth is reduced by process technology, it will not only bring great challenges to the process realization. On the other hand, due to the inevitable experience of many thermal processes in the whole process of device fabrication, it will bring about the manufacture of shallow junctions. A lot of difficulties.
  • multi-gate device structures such as dual gate, triple gate and fence devices to improve the gate control capability of the device.
  • the fence structure has the strongest gate control capability, because the entire channel is surrounded by the gate.
  • the nanowire structure in the fence structure becomes the most promising device structure. Because this kind of fence structure is beneficial to the increase of device mobility and reliability, nanowire devices are the most ideal device structure under the condition that the field effect transistor features are reduced to nanometer scale.
  • the purpose of the embodiments of the present invention is to make up for the blank of the prior art, and provide an optimization scheme based on nanowire transistor manufacturing for the traditional process, forming a hexagonal programmable array, greatly improving the integration degree of the nanowire device, and facilitating programming. , to achieve ultra-large scale, ultra-high integration of digital / analog and digital-analog hybrid circuits.
  • a hexagonal programmable array based on a silicon nanowire FET (shown in FIG. 1), comprising a nanowire device, a nanowire device connection region, and a gate connection region, wherein the nanowire devices are arranged in a hexagonal shape to form a programming Unit, a common nanowire device is shared between adjacent programming units, and a middle portion of each programming unit is a hollow region, and the nanowire device (see FIG. 2) is a silicon nanowire field effect transistor hexagonal programmable array.
  • the core part has a cylindrical structure.
  • the nanowire device includes a silicon nanowire channel, a gate dielectric layer, and a gate region.
  • the gate dielectric layer encapsulates the silicon nanowire channel, and the gate region encapsulates the gate dielectric layer.
  • the lengths of the silicon nanowire channel, the gate dielectric layer, and the gate region are uniform, ranging from 5 nanometers to 1 micrometer.
  • the channel radius of the silicon nanowire ranges from 3 nm to 100 nm.
  • the doping concentration of the silicon nanowire channel is less than
  • the thickness of the gate dielectric layer is in the range of 0.5 nm to 10 nm.
  • the thickness of the gate region ranges from 10 nm to 500 nm.
  • the nanowire device is connected to the nanowire device connection region, and each silicon nanowire connection region is connected to three nanowire devices, which provides a basis for high-density, multi-nanowire device interconnection. Since the nanowire device connection region is located on both sides of the nanowire device.
  • the nanowire device connection region can serve as the source or drain of the nanowire device at the same time, and the definition of the specific source and drain is defined by the user.
  • the size of the nanowire device connection region depends on the nanowire channel size/process conditions, and the size ratio is shown in FIGS.
  • the circuit structure of the N-type and P-type nanowire devices is the doping concentration of the nanowire device is less than 10 15 cm - 3 , undoped or equivalent Not doped.
  • the nanowire device connection region can be doped at a high concentration with a doping concentration of 10 18 ⁇ 10 2 ° cm 3 .
  • the gate connection region provides a connection for the gate region of the nanowire device, allowing a plurality of nanowire devices to form a common gate structure.
  • the silicon nanowire field effect transistor hexagonal programmable array of the embodiment of the invention is based on the original nanowire fabrication technology. In the CMOS process, the following steps are specifically included:
  • step (4) a grid mask can be used.
  • step (5) After the gate connection region is formed in step (5), a mask is additionally added, and the hexagonal programmable array region is doped at a high concentration with a doping concentration of 10 18 to 10 2 ° cm -3 .
  • RTA rapid thermal annealing
  • the interconnected nanowire channel in the former needs to be gated to achieve the equivalent of a "transmission gate”, and the interconnection channel in the latter does not need to be used. Gate control, only inject high-concentration magazines. Therefore, the (4) steps of the CMOS process and the N/PM0S process may be different.
  • the silicon nanowire field effect transistor hexagonal programmable array is suitable for high speed and high integration digital/analog circuits, and digital-analog hybrid circuits. Because it omits the bulk source-drain contact of traditional nanowire devices, it saves area. Compared with the traditional planar tube programmable gate array FPGA, while achieving the suppression of the short trench effect, it also saves a considerable area and can achieve ultra-high integration.
  • each interconnected node (nanowire device connection region) of the hexagonal nanowire interconnection network structure connects three device channels, and there are three devices between the two farthest nodes of each unit, thus realizing complex control interconnection control Logic, which is not available in traditional forms of arrays.
  • FIG. 1 is a top plan view of a hexagonal programmable array of silicon nanowire field effect transistors introduced in an embodiment of the present invention. In the picture:
  • the two grids are shown in the figure, which can be composed of two materials, realize NM0S and PM0S), 5-silicon wafer, and 6-block.
  • Figure 2 is a schematic diagram of a single nanowire device on the left. In the figure: Because there are more, my changes below are not revised. 7-Nanowire device connection region, 8-silicon wafer cutout, 9-nm device gate region.
  • Figure 2 is a schematic cross-sectional view of a single nanowire device on the right side, in which:
  • Figure 3 shows the first hard mask with a reticle or a square. (In the figure, a circle is taken as an example. If it is a square, the critical effect of exposure can also be used to expose the pattern).
  • Figure 3 shows the first hard mask with a reticle or a square. (In the figure, a circle is taken as an example. If it is a square, the critical effect of exposure can also be used to expose the pattern).
  • Fig. 4 is a circular pattern etched after exposure, and the nanowire silicon strip is oxidized and thinned to make it float, and the cross section is formed into a circular shape as shown in the right side of Fig. 2.
  • Figure 5 is a deposition of a gate connection region after thermal oxidation at a high temperature to form a gate dielectric layer. The portion overlying the nanowire channel is the gate region. After this you can define partitions and isolate some unwanted connections.
  • Figure 6 shows a 4-tube CMOS using two basic hexagonal cells. Schematic diagram of NAND gate:
  • 20-N nanowire devices 21-P nanowire devices, 22- normally open tubes for interconnection, 23-intercepted nanowires, gates for 24-N nanowire devices, 25-P nanowire devices Grid, 26- normally open tube gate (equivalent to transmission), 27-input signal A, 28-input signal B, 29- normally open tube input (VDD or GND, depending on the type of normally open tube).
  • Figure 7 shows the CMOS NAND gate circuit diagram, corresponding to the various devices and signals in Figure 6:
  • FIG. 1 is a top plan view of a hexagonal programmable array of silicon nanowire field effect transistors introduced in an embodiment of the present invention.
  • the structure is different from that of a conventional conventional nanowire field effect transistor.
  • the structure of the nanowire device has changed.
  • Conventional nanowire devices generally include: a nanowire channel, a gate region, a source region, and a drain region.
  • the source and drain regions of conventional nanowire devices occupy a very large area.
  • the nanowire devices in the hexagonal array described in this patent completely abandon the traditional source and drain, and the area is small and can be used.
  • this greatly reduces the redundant area between the channel and the channel of the nanowire device.
  • the core area is saved by at least 8/9.
  • the interleaved circular reticle provides the possibility of forming such a nanowire network: the interlaced reticle forms a nanowire device connection region that is thicker than the nanowire channel.
  • the nanowire trench The channel can be suspended, and the process conditions can be controlled: The appropriate oxidation temperature, such as 950 degrees, time, such as 10 seconds, so that the nanowire device connection area is not suspended, there is a silicon support underneath the entire network.
  • the silicon nanowire field effect transistor hexagonal programmable array is simple in process, and only a single silicon wafer cutout can be defined to realize a large number of nanowires. Equivalent to a lithography pattern to implement three nanowire devices, efficient use of lithography. This is especially true when using E-Beam Lithography.
  • each interconnected node (nanowire device connection region) of the hexagonal nanowire interconnection network structure connects three device channels, and there are three devices between the two farthest nodes of each unit, thus realizing complex control interconnection control Logic, this is biography
  • An array of systems is not available.
  • the above various differences are beneficial to improve the performance and working efficiency of the nanowire field effect transistor. Therefore, the silicon nanowire field effect transistor hexagonal programmable array is suitable for high-speed and high-integration digital/analog circuits, and digital-analog hybrid circuits.
  • a silicon wafer having a doping concentration of less than 10 15 cm -3 is selected, and a silicon wafer hollow region is defined by an interleaved hard mask.
  • the area of the interlaced pattern is smaller than the expected area of the hollow area of the silicon wafer, and may be circular or square or hexagonal, and the effect of exposing a slightly larger circular shape is achieved by the proximity effect during exposure.
  • the typical interleaved pattern basic unit area range is: 10 nm X 10 nm ⁇ 2. 5 ⁇ m X 2. 5 ⁇ m.
  • the interlaced reticle forms the nanowire device connection region thicker than the nanowire channel, in the oxidation reduction
  • the nanowires can be suspended, and the connection region of the nanowire device is not suspended.
  • the silicon support underneath supports the entire network.
  • the N-gate and P-gate connections are defined by two other hard masks.
  • the gate is defined and the type of device covered by the gate is also defined.
  • a nanowire device gate connection region is then deposited.
  • the N-type gate and the P-type gate need to be made of different materials. If you want to form NM0S, the N-type gate is implanted with phosphorus P/arsenic As. If you want to form PM0S, the P-type gate is implanted with boron B.
  • Figure 6 shows an embodiment comprising two hexagonal programming units, which actually use nine nanowire devices, two of which are N-type nanowire devices, two P-type nanowire devices, and the remaining five nanowires.
  • the device is used as an interconnect.
  • the 29-N type nanowire device and the 30-P type nanowire device are respectively gated by a 33-N type nanowire device and gated by a 34-P type nanowire device. Controlled, using different material gates and silicon work function difference to control the threshold voltage, to achieve the purpose of forming different types of nanowire devices.
  • the above described detailed description of the silicon nanowire field effect transistor hexagonal programmable array provided by the present invention is not limited to the present invention. Various modifications and refinements may be made within the spirit and scope of the invention, and the scope of the invention is defined by the scope of the claims.

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Description

硅纳米线晶体管器件可编程阵列及其制备方法 技术领域
本发明属于 CMOS超大规模集成电路（ULSI)制造技术领域， 特别涉及一种硅纳米线场 效应晶体管（ Silicon Nanowire Metal-Oxide-Silicon Field Effect Transistor, SNW MOSFET)六边 形可编程阵列 （Hexagonal Programmable Array)及其制备方法。 背景技术
半导体器件是制造电子产品的重要元件。 半导体器件的更新换代推进了半导体技术的发 展和半导体工业的进步， 特别是对中央处理器 CPU和存储器的性能提升。 从上世纪末开始， 芯片制造工艺发展十分迅速， 先后从微米级别， 一直发展到今天小于 32nm的技术。
随着器件特征尺寸进入 45纳米或更小，传统平面管器件的栅控能力逐渐减小，器件特性 衰退， 饱受短沟道效应的影响。 在传统器件设计中栅氧厚度至多为几纳米甚至小于一纳米， 如此薄的栅氧厚度会带来严重的栅泄漏电流， 从而恶化器件的性能， 可靠性以及大幅度增加 器件的功耗； 同时， 如果通过工艺技术减小结深， 不仅会给工艺实现方面带来巨大的挑战， 另一方面， 由于在器件制备的整个过程中， 将不可避免的经历许多热过程， 为制造浅结带来 很多的困难。
为了解决上述一系列问题， 器件设计者提出了多栅器件结构例如双栅， 三栅和围栅器件 来提高器件的栅控能力。 在众多器件结构中， 围栅结构具有最强的栅控能力， 因为整个沟道 被栅包围， 当沟道长度缩小到纳米尺度时， 围栅结构中的纳米线结构成为最有潜力的器件结 构， 因为这种围栅结构有利于器件迁移率和可靠性的提高， 因此纳米线器件成为在场效应晶 体管特征尺寸缩小到纳米尺度条件下的最为理想的器件结构。
同时， 摩尔定律指出： 集成电路上可容纳的晶体管数目， 每隔 18个月增加一倍， 集成电 路的性能也将提升一倍。 随着半导体器件的特征尺寸不断减小， 制约摩尔定律的主要因素从 器件工作区的大小进而转向诸如源漏面积、 引线等其他方面。 在传统纳米线制造工艺中， 源 区（source)漏区（drain)会占有相当大的面积，它们等效为器件栅控有效沟道工作区（channel) 的两倍大小。 这无疑成为制约集成电路集成度进一歩提高的一个非常重要因素。 因此如何节 约此部分面积，优化硅纳米线器件版图设计， 己经成为当前高密度集成电路设计的重要课题。 发明内容
本发明实施例的目的是弥补现有技术的空白， 针对传统工艺， 提供一种基于纳米线晶体 管制造的优化方案， 形成六边形可编程阵列， 大幅度提高纳米线器件集成度， 方便编程使用， 实现超大规模， 超高集成度的数字 /模拟和数模混合电路。
本发明实施例的技术方案如下：
一种基于硅纳米线场效应晶体管的六边形可编程阵列 （如图 1所示）， 包括纳米线器件、 纳米线器件连接区和栅连接区， 纳米线器件以六边形排列构成一编程单元， 相邻编程单元之 间共用一个公共的纳米线器件， 每个编程单元的中间部分为镂空区， 所述纳米线器件 （见图 2 )为硅纳米线场效应晶体管六边形可编程阵列的核心部分， 呈圆柱形结构。纳米线器件包括 硅纳米线沟道、 栅介质层、 栅区。 栅介质层包裹硅纳米线沟道， 栅区包裹栅介质层。 硅纳米 线沟道、 栅介质层、 栅区的长度取值一致， 范围是 5纳米〜 1微米。
所述硅纳米线沟道半径取值范围是 3 纳米〜 100 纳米。 硅纳米线沟道的掺杂浓度小于
1015cm— 3， 不掺杂或等效为不掺杂。
所述栅介质层厚度取值范围是 0. 5纳米〜 10纳米。
所述栅区厚度取值范围是 10纳米〜 500纳米。
纳米线器件与纳米线器件连接区相连接， 每个硅纳米线连接区连接 3个纳米线器件， 为 高密度、 多纳米线器件互联提供了基础。 由于纳米线器件连接区位于纳米线器件两侧。 纳米 线器件连接区可同时作为此纳米线器件的源或漏， 具体源漏的定义使用者自己定义。 同时纳 米线器件连接区下面存在一个硅支架， 支撑整个纳米线器件网络。 纳米线器件连接区尺寸依 纳米线沟道尺寸 /工艺条件取值， 其尺寸比例如图 1， 2所示。 对于 CMOS工艺， 同时具有 N型和 P型纳米线器件的电路结构来讲， 纳米线器件连接区掺杂浓度小于 1015cm— 3， 不掺杂或等效为 不掺杂。 对于单独的匪 OS工艺或 PMOS工艺， 全部器件为同种类型， 可对纳米线器件连接区进 行高浓度掺杂， 掺杂浓度为 1018〜102°cm_3。
栅连接区为纳米线器件的栅区提供连接， 使多根纳米线器件可以形成共栅结构。
本发明实施例硅纳米线场效应晶体管六边形可编程阵列是基于原有纳米线制作技术。 在 CMOS工艺下， 具体包括以下步骤：
( 1 ) 选取初始浓度很低的硅片 （掺杂浓度小于 1015cm— 3)， 利用硬掩模定义硅片镂空区；
( 2 ) 去掉（1 ) 中硬掩模， 进行氧化减薄纳米线硅条， 形成悬浮的硅纳米线网络； 交错的掩 模版形成的纳米线器件连接区较纳米线沟道粗， 在氧化减薄这个工艺步骤中， 纳米线 可以实现悬空，而纳米线器件连接区并没有悬空， 它下面存在硅支架同支撑整个网络。 ( 3 ) 湿法腐蚀掉形成的二氧化硅， 进行热氧化形成一层致密二氧化硅栅介质；
( 4 ) 利用另两片硬掩模分别对 N型栅和 P型栅连接进行定义； 这里用户自定义， 可编程控 制；
( 5 ) 淀积材料， 制作栅连接区；
( 6 ) 利用另一块掩模版定义一些隔断图形， 用作隔断一些不需要连接的部分； 利用刻蚀技 术使这些连接部分断开； 可编程控制； （此步骤可选， 如无需隔断则略去此步骤）
( 7 ) 最后进入常规 CMOS后道工序。
在匪 OS或 PM0S工艺下， 需作出以下修改：
步骤 （4) 中用一块栅掩模版即可。
步骤 （5 ) 中制作栅连接区后， 要额外增加一块掩模版， 对六边形可编程阵列区域进行高 浓度掺杂， 掺杂浓度为 1018〜102°cm— 3。 之后快速热退火（RTA) ， 将杂志驱入纳米线器件连接 区和其他作为互联线用的纳米线沟道。
这里需注意， 对于 CMOS工艺和 N/PM0S工艺来讲， 前者中作为互联的纳米线沟道需要制 作栅控制， 达到等效于 "传输门" 的目的， 而后者中的互联作用沟道不需要栅控制， 仅注入 高浓度杂志即可。 因此 CMOS工艺和 N/PM0S工艺的 （4 ) 步骤可能有不同。
与现有技术相比， 本发明实施例的作用是- 硅纳米线场效应晶体管六边形可编程阵列适合应用于高速高集成度的数字 /模拟电路， 和 数模混合电路。 由于其略去了传统纳米线器件的大块源漏接触， 十分节省面积。 与传统平面 管可编程门阵列 FPGA比较， 在达到抑制短沟效应的同时， 也节省了相当大的面积， 可以达到 超高集成度。 同时， 六边形纳米线互联网络结构每个互联节点 （纳米线器件连接区） 连接三 个器件沟道，每个单元最远的两个节点间存在 3个器件， 因此可实现复杂控制互联控制逻辑， 这是传统形式的阵列所不能提供的。 附图说明
图 1是本发明实施例中介绍的硅纳米线场效应晶体管六边形可编程阵列的俯视面示意图。 图中：
1-纳米线器件的抽象棍棒式示意图， 2-硅片镂空区， 3-纳米线器件连接区， 4-栅连接区
(图中为两种栅， 可为两种材料构成， 实现 NM0S和 PM0S ) ， 5-硅片， 6-隔断。
图 2是左侧为单个纳米线器件示意图， 图中： 因为较多， 以下我的改动不加修订标记了。 7-纳米线器件连接区， 8-硅片镂空区， 9-纳米线器件的栅区。
图 2是右侧为单个纳米线器件剖面示意图， 图中：
10-硅纳米线沟道， 11-栅介质层， 12-栅区。
图 3为第一次硬掩模， 掩模版为圆形或方形。 （图中以圆形为例， 如为方形， 利用曝光的 临界效应， 也可以将图形曝圆）。 图 3中：
13-圆形掩模版， 14-硅片。
图 4为曝光后刻蚀出圆形图形， 并且氧化减薄纳米线硅条， 使之悬空， 同时使之剖面形 成如图 2右侧图中的圆形。 图 4中：
15-硅片镂空区， 16-纳米线沟道， 17-硅片。
图 5为在高温热氧化形成栅介质层后， 淀积形成栅连接区。 覆盖在纳米线沟道上的部分 为栅区。 在这之后可以定义隔断， 隔断某些不想要的连接。
18-栅连接区， 19-隔断。以下改动用修订。 图 6为利用两个基本六边形单元制作 4管 CMOS 与非门的示意图：
20-N型纳米线器件， 21-P型纳米线器件， 22-常开管用做互联， 23-被隔断的纳米线， 24-N 型纳米线器件的栅， 25-P 型纳米线器件的栅， 26-常开管的栅 （等效为传输们）， 27-输入信 号 A， 28-输入信号 B， 29-常开管输入 （VDD或 GND， 视常开管类型而定）。
图 7为 CMOS与非门电路图， 对应图 6中各种器件和信号：
30-N型纳米线器件， 31-P型纳米线器件， 32-输入信号 A， 33-输入信号 B， 34-节点 0 GND, 35-节点 1， 36-节点 2 输出， 37-节点 3 VDD。 具体实施方式
下面结合附图和具体实施方式对本发明实施例作进一步详细描述：
图 1 为本发明实施例中介绍的硅纳米线场效应晶体管六边形可编程阵列的俯视面示意 图。 其结构与一般的常规纳米线场效应晶体管区别在于- 首先纳米线器件结构有所变化， 传统的纳米线器件大体包括： 纳米线沟道， 栅区， 源区 和漏区。 为了打通孔制作互联引线， 传统纳米线器件的源区和漏区占用非常大的面积， 本专 利所介绍的六边形阵列中的纳米线器件， 完全抛弃传统源漏， 用面积很小且可作为互联节点 的纳米线器件连接区替代， 这样极大地减小了纳米线器件沟道与沟道之间冗余面积。 对于相 同功能的电路结构， 其核心面积节省至少 8/9。 另外， 交错的圆形掩模版也为形成这种纳米 线网络提供了可能： 交错的掩模版形成的纳米线器件连接区较纳米线沟道粗， 在氧化减薄这 个工艺步骤中， 纳米线沟道可以实现悬空， 而可控制工艺条件： 适当氧化温度， 如 950度、 时间， 如 10秒等， 使纳米线器件连接区并没有悬空， 它下面存在硅支架支撑整个网络。
其次，硅纳米线场效应晶体管六边形可编程阵列的工艺简单，只需定义一次硅片镂空区， 就可以实现众多纳米线。 等效为一个光刻图形实现三根纳米线器件， 高效地利用光刻技术。 这在使用电子束光刻 （E-Beam Lithography ) 时尤为明显。
同时， 六边形纳米线互联网络结构每个互联节点 （纳米线器件连接区）连接三个器件沟 道， 每个单元最远的两个节点间存在 3个器件， 因此可实现复杂控制互联控制逻辑， 这是传 统形式的阵列所不能提供的。 上述各种区别有利于提高纳米线场效应晶体管的性能和工作效 率。所以，硅纳米线场效应晶体管六边形可编程阵列适合应用于高速高集成度的数字 /模拟电 路， 和数模混合电路。
下面以 CMOS工艺下的硅纳米线场效应晶体管六边形可编程阵列制作与非门为例说明主 要制作流程：
( 1 ) 选取掺杂浓度小于 1015cm— 3的硅片， 利用交错式硬掩模定义硅片镂空区。 如图 3所 示。此歩骤中， 交错式图形面积要小于预计的硅片镂空区面积， 可以为圆形或方形或六边形， 利用曝光时的临近效应达到曝光出稍大圆形的目的。典型的交错式图形基本单元面积范围是： 10纳米 X 10纳米〜 2. 5微米 X 2. 5微米。
( 2 ) 去掉 （1 ) 中硬掩模， 进行氧化减薄纳米线硅条， 形成悬浮的硅纳米线网络； 交错 的掩模版形成的纳米线器件连接区较纳米线沟道粗， 在氧化减薄这个工艺步骤中， 纳米线可 以实现悬空， 而纳米线器件连接区并没有悬空， 它下面存在硅支架同支撑整个网。
( 3 )湿法腐蚀掉形成的二氧化硅， 进行热氧化形成一层致密二氧化硅栅介质。 如图 7所 示。 （此时硅上都有一层二氧化硅， 未在图中标出） 。
( 4)利用另两片硬掩模分别对 N型栅和 P型栅连接进行定义， 定义栅的同时， 也定义了 栅所覆盖器件的类型。 然后淀积生成纳米线器件栅连接区。 此步骤中 N型栅和 P型栅需采用 不同材料， 如想要形成 NM0S, 则 N型栅采用磷 P/砷 As注入， 如想要形成 PM0S， P型栅采用 硼 B注入。
( 5 )利用另一块掩模版定义一些隔断图形， 隔断一些不需要连接的部分； 利用刻蚀技术 使这些连接部分断开。
后面的工艺流程和常规硅纳米线 M0S晶体管完全一样。先后进行：平坦化，淀积隔离层， 光刻外围输入输出引线孔， 淀积金属， 光刻引线， 钝化等等。
图 6所示包括两个六边形编程单元的实施例， 该编程阵列实际用到 9根纳米线器件，其 中 2根 N型纳米线器件，两根 P型纳米线器件，其余 5根纳米线器件用作互连。参考图 7， 29-N 型纳米线器件和 30-P型纳米线器件分别由 33-N型纳米线器件的栅和 34-P型纳米线器件的栅 所控制， 利用不同材料栅与硅的功函数差控制阈值电压， 达到形成不同类型纳米线器件的目 的。 以上通过详细实例描述了本发明所提供的硅纳米线场效应晶体管六边形可编程阵列， 上 面描述的应用场景和实施例， 并非用于限定本发明， 任何本领域技术人员， 在不脱离本发明 的精神和范围内， 可以做各种的更动和润饰， 因此本发明的保护范围视权利要求范围界定。

Claims

权 利 要 求
1、一种基于硅纳米线场效应晶体管的六边形可编程阵列，其特征在于，包括纳米线器件、 纳米线器件连接区和栅连接区， 所述纳米线器件呈圆柱形结构， 包括硅纳米线沟道、 栅介质 层和栅区， 栅介质层包裹硅纳米线沟道， 栅区包裹栅介质层， 其中， 硅纳米线沟道、 栅介质 层和栅区的长度取值一致， 范围是 5纳米〜 1微米， 纳米线器件以六边形排列构成一编程单 元， 相邻编程单元之间共用一个公共的纳米线器件， 每个编程单元的中间部分为镂空区， 纳 米线器件连接区为 3个纳米线器件之间的连接节点， 该纳米线器件连接区与纳米器件的沟道 连接， 同时作为纳米线器件的源或漏， 纳米线器件连接区固定在一个硅支架上， 栅连接区为 纳米线器件的栅区提供连接， 使多根纳米线器件形成共栅结构。
2、 如权利要求 1所述的基于硅纳米线场效应晶体管的六边形可编程阵列， 其特征在于， 所述硅纳米线沟道半径取值范围是 3纳米〜 100纳米，硅纳米线沟道的掺杂浓度小于 1015cm— 3， 不掺杂或等效为不掺杂。
3、 如权利要求 1所述的基于硅纳米线场效应晶体管的六边形可编程阵列， 其特征在于， 所述栅介质层厚度取值范围是 0. 5纳米〜 10纳米。
4、 如权利要求 1所述的基于硅纳米线场效应晶体管的六边形可编程阵列， 其特征在于， 所述栅区厚度取值范围是 10纳米〜 500纳米。
5、 一种制备如权利要求 1所述的六边形可编程阵列的方法， 具体包括以下步骤-
1)选取掺杂浓度小于 1015cm— 3的硅片， 利用硬掩模定义硅片镂空区；
2)去掉 1 ) 中硬掩模， 进行氧化减薄纳米线硅条， 形成悬浮的硅纳米线网络； 交错的掩 模版形成的纳米线器件连接区较沟道区粗， 在氧化减薄这个工艺步骤中， 纳米线可以实现悬 空， 而纳米线器件连接区并没有悬空， 它下面存在硅支架同支撑整个网络；
3)湿法腐蚀掉形成的二氧化硅， 进行热氧化形成一层致密二氧化硅栅介质；
4)利用另两片硬掩模分别对 N型栅和 P型栅连接进行定义；
5)淀积材料， 制作栅连接区； 6)最后进入常规 CMOS后道工序。
6、 如权利要求 5所述的制备方法， 其特征在于， 利用另一块掩模版定义隔断图形， 利 用刻蚀技术断开不需要连接的纳米线器件。
7、 如权利要求 5所述的制备方法， 其特征在于， 步骤 5 ) 中制作栅连接区后， 额外增 加一块掩模版， 对六边形可编程阵列区域进行高浓度掺杂， 掺杂浓度为 1018〜102°cm— 3， 之后 快速热退火， 将杂质驱入纳米线器件连接区和其他作为互联线用的区域。
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