WO2012139356A1 - 一种sigma-delta调制器 - Google Patents
一种sigma-delta调制器 Download PDFInfo
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- WO2012139356A1 WO2012139356A1 PCT/CN2011/079023 CN2011079023W WO2012139356A1 WO 2012139356 A1 WO2012139356 A1 WO 2012139356A1 CN 2011079023 W CN2011079023 W CN 2011079023W WO 2012139356 A1 WO2012139356 A1 WO 2012139356A1
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- integrator
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- delta
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
- H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
- H03M3/44—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with provisions for rendering the modulator inherently stable
- H03M3/446—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with provisions for rendering the modulator inherently stable by a particular choice of poles or zeroes in the z-plane, e.g. by positioning zeroes outside the unit circle, i.e. causing the modulator to operate in a chaotic regime
- H03M3/448—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with provisions for rendering the modulator inherently stable by a particular choice of poles or zeroes in the z-plane, e.g. by positioning zeroes outside the unit circle, i.e. causing the modulator to operate in a chaotic regime by removing part of the zeroes, e.g. using local feedback loops
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
- H03M3/438—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path
- H03M3/452—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a higher order loop filter in the feedforward path with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input
Definitions
- the invention belongs to the field of signal processing, and in particular relates to a sigma-delta modulator.
- Analog-to-Digital Converter It plays a very important role in signal processing, and requires a large number of digital-to-analog converters in the fields of digital audio, digital television, image coding and frequency synthesis. As the size and bias of VLSIs continue to decrease, the accuracy and dynamic range of analog devices continue to decrease, enabling high resolution ADC is a challenge.
- the high-order multi-bit sigma-delta ADC is widely used in practice because it does not require a sample-and-hold circuit and has a small circuit scale and high resolution.
- Sigma-delta Since the birth of the modulation technology in the 1960s, after several years of development, it has become one of the mainstream technologies for implementing high-performance analog-to-digital conversion interface circuits in very large-scale integrated circuit systems. in short, The sigma-delta modulator converts a continuous time, continuous amplitude input signal into a discrete time, discrete amplitude output sequence.
- Sigma-delta modulator Sigma-delta modulator
- SDM Sigma-delta modulator
- the quantization noise is pushed to the high frequency end, and the quantization noise is double suppressed, so that the signal-to-noise ratio of the data converter can be significantly improved, and high-precision analog-to-digital conversion can be realized.
- the sigma-delta modulator is mainly composed of an A/D converter and a D/A
- the converter consists of a series of integrators.
- the number of integrators determines the order of the sigma-delta modulator. For example, if there are three integrators connected in series in a single loop modulator, then this single loop sigma-delta
- the modulator is called a single-loop third-order sigma-delta modulator.
- the main performance indicators of the Sigma-delta modulator are: Dynamic Range, DR ), Signal-to-Noise Ratio (SNR), Signal-to-Noise Distortion Ratio (Signal-to-Noise Distortion Ratio, SNDR ), Effective Number of Bit (ENOB), and Overload Level (OL).
- the Z domain expressions of the output signals of the first integrator 102, the second integrator 104, and the third integrator 106 are as follows (1), (2), (3)
- x(z) is the Z-domain expression of the input signal
- a 5 and a 6 are the feedback gain coefficients of the gain amplifier 109 and the gain amplifier 110, respectively.
- E(z) is the Z-domain expression of the quantization error.
- the first integrator 102 the second integrator 104, and the third integrator 106
- the output is not only related to the quantization error, but also to the input signal x(z).
- the stability of the modulation is seriously affected, thereby greatly limiting the dynamic range of the input signal.
- the purpose of embodiments of the present invention is to solve the sigma-delta existing in the prior art.
- the modulator increases the power consumption of the circuit and seriously affects the stability of the modulation.
- the problem that the dynamic range of the input signal is narrow is to provide a sigma-delta modulator. Can reduce distortion, improve stability and dynamic range of the input signal.
- a sigma-delta modulator comprising:
- a second gain amplifier a third gain amplifier, a digital to analog converter, and a sequentially connected subtractor, a first adder, a first integrator, a second integrator, a first gain amplifier, a second adder, a quantizer;
- a forward input end of the subtractor is connected to another input end of the second adder, and an output end of the first integrator is further connected to the second adder via the second gain amplifier
- An output end of the quantizer is connected to an inverting input end of the subtractor via the digital-to-analog converter, and an output end of the second integrator is further connected to the third gain amplifier The other input of an adder.
- a second gain amplifier through a second gain amplifier, a third gain amplifier, a digital to analog converter, and a sequentially connected subtractor, a first adder, a first integrator, a second integrator, a first gain amplifier, a second adder, a quantizer
- the forward input end of the subtractor is connected to the other input end of the second adder, and the output end of the first integrator is further connected to the other input end of the second adder via the second gain amplifier, and the output end of the quantizer is digital
- the analog converter is connected to the inverting input of the subtractor, and the output of the second integrator is further connected to the other input end of the first adder via the third gain amplifier, thereby realizing a kind
- the sigma-delta modulator which only processes quantization noise, reduces distortion, improves stability, and dynamic range of the input signal.
- FIG. 1 is a schematic structural diagram of a third-order sigma-delta modulator provided by the prior art
- FIG. 2 is a schematic structural diagram of a second-order sigma-delta modulator according to an embodiment of the present invention
- FIG. 3 is a schematic structural diagram of a third-order sigma-delta modulator according to an embodiment of the present invention.
- FIG. 4 is a third-order sigma-delta provided by an embodiment of the present invention. Schematic diagram of the voltage range of the third integrator, the first integrator, and the second integrator output of the modulator;
- Figure 5 is the traditional third-order sigma-delta shown in Figure 1.
- FIG. 6 is a third-order sigma-delta provided by an embodiment of the present invention.
- Figure 7 is the traditional third-order sigma-delta shown in Figure 1.
- FIG. 8 is a schematic structural diagram of a delay integrator according to an embodiment of the present invention.
- FIG. 9 is a schematic structural diagram of a fourth-order sigma-delta modulator according to an embodiment of the present invention.
- the output of the quantizer is digital-to-analog converter
- the DAC is connected to the inverting input of the subtractor, and the output of the second integrator is further connected to the other input of the first adder via the third gain amplifier, thereby realizing a sigma-delta Modulator, each integrator only processes quantization noise.
- FIG. 2 shows a second-order sigma-delta provided by an embodiment of the present invention.
- the structure of the modulator is shown only for the sake of convenience in the description of the embodiment of the present invention.
- the sigma-delta The modulator can be used in a data processing device, such as a digital audio processing device, a digital television, an image encoding device, a frequency synthesizing device, etc., and can be a software unit, a hardware unit, or a combination of hardware and software running in the devices. As a stand-alone pendant integrated into these data processing devices or in the application system of these data processing devices.
- the The sigma-delta modulator includes a second gain amplifier 208, a third gain amplifier 210, a digital to analog converter 209, and a sequentially connected subtractor 201, a first adder 202 a first integrator 203, a second integrator 204, a first gain amplifier 205, a second adder 206, a quantizer 207, and a forward input of the subtractor 201 connected to the second adder
- the output of the first integrator 203 is further connected to a further input of the second adder 206 via the second gain amplifier 208
- the output of the quantizer 207 is subjected to a digital-to-analog converter (DAC) 209 is connected to the inverting input of the subtractor 201
- the output of the second integrator 204 is further connected to the first adder 202 via the third gain amplifier 210.
- the second adder 206 has three inputs.
- All the feedforward signals are accumulated by the second adder 206, and the accumulated signals are sent to the quantizer 207. Quantization is performed; the quantized signal is used as an output, and the other circuit is converted into an analog signal by a digital-to-analog converter 209; the converted analog signal is fed back to the subtractor 201 The inverting input is subtracted from the original analog input signal.
- the quantizer 207 is a uniform quantizer 207. That is, the value range of the input signal is divided by equal distance. If the quantizer 207 is an n-bit quantizer 207, then the range of the input signal is equally divided by n equal parts.
- the digital-to-analog converter 209 converts the digital signal into an analog signal, and then feeds the converted analog signal back to the subtractor 201 The reverse input.
- the digital to analog converter 209 can be a voltage scaling digital to analog converter 209, a charge scaling digital to analog converter 209, or a current scaling digital to analog converter 209.
- a charge scaling type digital-to-analog converter 209 can be employed to further improve the accuracy of the sigma-delta modulator.
- the modulator further includes at least one gain amplifier, and corresponding to each of the gain amplifiers connected to the subtractor 201 and the first adder 202 At least one integrator between the outputs of each integrator is further coupled to an input of the second adder 206 via a gain amplifier.
- FIG. 3 shows a third-order sigma-delta provided by an embodiment of the present invention.
- the structure of the modulator is shown only for the sake of convenience in the description of the embodiment of the present invention.
- the subtractor 201 and the first adder 202 A third integrator 211 is added between them, and the output of the third integrator 211 is further connected to an input of the second adder 206 via the fourth gain amplifier 212.
- the second adder 206 The input is 4 .
- the Z-domain expressions output by the third integrator 211, the first integrator 203, and the second integrator 204 are as follows:
- X(z) is the Z-domain expression of the input signal.
- the feedback gain coefficient; E(z) is the Z-domain expression of the quantization error.
- the sigma-delta modulator provided by the embodiment of the present invention can effectively solve the quantizer 207 when the analog input signal is large.
- the problem of overloading keeps the system in a stable state, thus effectively expanding the dynamic range of the analog input signal.
- FIG. 4 shows a third integrator 211 and a first integrator of a third-order sigma-delta modulator according to an embodiment of the present invention.
- FIG. 5 shows the first integrator 203 and the second integrator of the conventional third-order sigma-delta modulator shown in FIG.
- the simulation conditions are specifically: oversampling rate is 16 , oversampling frequency is 24MHz, full scale relative level (dB full Scale , dBFS ) is -3dB , the signal band is 1MHz , and the signal input frequency is 146480Hz
- the abscissa in the simulation diagram is the output voltage of the integrator, and the ordinate is the number of times the corresponding output voltage appears.
- the third-order sigma-delta provided by the embodiment of the present invention
- the voltage range of each integrator output of the modulator is significantly smaller than the voltage range of each integrator output of the conventional third-order sigma-delta modulator shown in Figure 1. Similarly, for other orders sigma-delta Similar simulation results can be obtained with the modulator.
- the quantizer 207 is a uniform quantizer 207; a digital to analog converter 209. It may be a voltage scaling digital to analog converter 209, a charge scaling digital to analog converter 209 or a current scaling digital to analog converter 209.
- FIG. 6 and 7 respectively show a third-order sigma-delta modulator provided by an embodiment of the present invention and FIG. 1
- Figure 6 and 7 simulation conditions and Figures 4 and 5 The simulation conditions are the same; fast Fourier transform (FFT) is performed by adding the final output of the modulator to the Hamming window. After taking the square of the modulus value and taking the logarithm, the relationship between the frequency and the power spectral density shown in Figures 6 and 7 can be obtained.
- FFT fast Fourier transform
- the traditional third-order sigma-delta The modulator is unstable due to the excessive amplitude of the input signal, which causes the performance of the modulator to drastically decrease; however, the third-order sigma-delta provided by the embodiment of the present invention
- the modulator overcomes the instability problem, expands the dynamic range of the input signal, and improves the signal-to-noise ratio. In general, when the input signal overloads the modulator, the input signal is considered to be relatively large. Similarly, for other orders Similar simulation results can be obtained with the sigma-delta modulator.
- the integrators such as the first integrator 203, the second integrator 204, and the third integrator 211 in the sigma-delta modulator are delay integrators.
- the delay integrator is sequentially connected by an adder 801, a unit delayer 802, and a limiter 803. Composition.
- the limiter 803 is used to limit the output voltage of the integrator to a certain range to prevent sigma-delta
- the input amplitude of the quantizer 207 in the modulator is too large, causing the quantizer 207 to be overloaded.
- the input signal to be processed is first transferred to an input port of the adder 801; the output port of the adder 801 and the unit delay unit
- the input port of the 802 is connected; the output signal of the unit delay unit 802 is directly input to the limiter 803; one output signal of the limiter 803 is fed back to the adder 801
- the other port is the output of the unit delay 802.
- This closed loop forms an integrator whose system transfer function is:
- FIG. 9 shows a fourth-order sigma-delta provided by an embodiment of the present invention.
- the structure of the modulator is shown only for the sake of convenience in the description of the embodiment of the present invention.
- the subtractor 201 and the first adder 202 A fourth integrator 213 is added between them, and the output of the fourth integrator is further connected to an input of the second adder 206 via the fifth gain amplifier 214.
- the input of the second adder 206 is 5 One.
- the fourth integrator 213 can be connected between the subtractor 201 and the third integrator 211, as shown in FIG. 9, or can be connected to the third integrator 211 and the first adder 202. Between the third integrator 211 and the fourth integrator 213 in Fig. 9, the position can be exchanged.
- Each integrator, quantizer 207, digital to analog converter 209 The implementation of the above is as described above and will not be described again.
- the output end of the quantizer is connected to the inverting input terminal of the subtractor via a digital-to-analog converter, and the output end of the second integrator is further connected to the other input end of the first adder via a third gain amplifier, thereby realizing a kind With sigma-delta modulators, each integrator only processes quantization noise, which reduces distortion, improves stability, and the dynamic range of the input signal.
- the modulator further includes at least one gain amplifier and at least one integrator connected to each of the gain amplifiers connected between the subtractor and the first adder, and the output ends of the integrators are respectively connected to the second adder via the gain amplifier One input to achieve third order and above Sigma-delta modulator.
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Abstract
本发明适用于信号处理领域，提供了一种sigma-delta调制器，包括：第二增益放大器、第三增益放大器、数模转换器，以及顺序连接的减法器、第一加法器、第一积分器、第二积分器、第一增益放大器、第二加法器、量化器；所述减法器的正向输入端接所述第二加法器的另一输入端，所述第一积分器的输出端还经所述第二增益放大器后接所述第二加法器的再一输入端，所述量化器的输出端经所述数模转换器接所述减法器的反向输入端，所述第二积分器的输出端还经所述第三增益放大器后接所述第一加法器的另一输入端。在本发明中，通过各积分器只处理量化噪声，实现了一种sigma-delta调制器，能减少了失真、提高稳定性及输入信号的动态范围。
Description
本发明属于信号处理领域，尤其涉及一种 sigma-delta 调制器。
模数转换器（ Analog-to-Digital Converter ， ADC
）在信号处理中起了一个非常重要的作用，在数字音频、数字电视、图像编码及频率合成等领域都需要大量的数模转换器。由于超大规模集成电路的尺寸和偏压不断减少，模拟器件的精度和动态范围也不断降低，实现高分辨率的
ADC 是一种挑战。而高阶多位 sigma-delta ADC 由于不需要采样保持电路，电路规模小，可以实现较高的分辨率，因此在实际中得到广泛的应用。
sigma-delta
调制技术自二十世纪六十年代诞生以来，经过若干年的发展，现已成为超大规模集成电路系统中实现高性能模数转换接口电路的主流技术之一。简而言之，
sigma-delta 调制器用以将一连续时间，连续幅度的输入信号转换成为一离散时间，离散幅度的输出序列。基于 sigma-delta 调制技术的
sigma-delta 调制器（ sigma-delta modulator ， SDM
），结合应用过采样技术和噪声整形技术相结合，把量化噪声推到高频端，对量化噪声进行双重抑制，从而能显著的提高数据转换器的信噪比、实现高精度模数转换。
sigma-delta 调制器主要由一个 A/D 转换器、一个 D/A
转换器和一系列串联积分器组成。积分器的个数决定了 sigma-delta 调制器的阶数。如：单环路调制器中有三个积分器串联，则此单环路 sigma-delta
调制器就称为单环路三阶 sigma-delta 调制器。 Sigma-delta 调制器的主要性能指标有：动态范围（ Dynamic Range, DR
）、信噪比（ Signal-to-Noise Ratio ， SNR ）、信噪失真比（ Signal-to-Noise Distortion Ratio ，
SNDR ）、有效位数（ Effective Number of Bit,ENOB ）、以及过载度（ Overload Level, OL ）。
传统单环路三阶多比特 sigma-delta 调制器的结构示意图如图 1
所示。其中，输入的模拟信号馈送到第一减法器 101 的一个输入端口；第一减法器 101 的输出端口与第一积分器 102 的输入端口进行相连；第一积分器 101
的输出端口与第二减法器 103 的一个输入端口相连；第二减法器 103 的输出端口与第二积分器 104 的输入端口相连；第二积分器 104
的输出端口与第三减法器 105 的一个输入端口相连；第三减法器 105 的输出端口与第三积分器 106 的输入端口相连；第三积分器 106 的输出端口与量化器
107 的输入端口相连；量化器 107 的一路输出作为数字信号输出，而另一路输出则送入到 DAC108 ； DAC108
把转换后的模拟信号分为三路；一路模拟信号反馈回到第一减法器 101 的另一个输入端口；一路模拟信号通过增益系数为 a5 的增益放大器 109
后反馈回第二减法器 103 的另一个输入端口；一路模拟信号通过增益系数为 a6 的增益放大器 110 后反馈回第三减法器 105 的另一个输入端口。
第一积分器 102 、第二积分器 104 和第三积分器 106 输出信号的 Z 域表达式分别如下述
(1) 、(2) 、 (3) 式：
其中， x(z) 为输入信号的 Z 域表达式； a5 、
a6 分别为增益放大器 109 和增益放大器 110 的反馈增益系数。 E(z) 为量化误差的 Z 域表达式。
从上述表达式中可以看出，第一积分器 102 、第二积分器 104 和第三积分器 106
的输出不仅与量化误差有关，还与输入信号 x(z) 有关。当输入信号较大时，会严重影响调制的稳定性，从而大大限制了输入信号的动态范围。
现有技术存在的 sigma-delta
调制器在输入信号较大时，会增加电路的功耗、严重影响调制的稳定性，输入信号的动态范围较窄 。
本发明实施例的目的旨在解决现有技术存在的 sigma-delta
调制器在输入信号较大时，会增加电路的功耗、严重影响调制的稳定性，输入信号的动态范围较窄 的问题，在于提供一种 sigma-delta 调制器
，能减少了失真、提高稳定性及输入信号的动态范围。
本发明实施例是这样实现的，一种 sigma-delta 调制器，包括：
第二增益放大器、第三增益放大器、数模转换器，以及顺序连接的减法器、第一加法器、第一积分器、第二积分器、第一增益放大器、第二加法器、量化器；
所述减法器的正向输入端接所述第二加法器的另一输入端，所述第一积分器的输出端还经所述第二增益放大器后接所述第二加法器的再一输入端，所述量化器的输出端经所述数模转换器接所述减法器的反向输入端，所述第二积分器的输出端还经所述第三增益放大器后接所述第一加法器的另一输入端。
在本发明中，通过
第二增益放大器、第三增益放大器、数模转换器，以及顺序连接的减法器、第一加法器、第一积分器、第二积分器、第一增益放大器、第二加法器、量化器，减法器的正向输入端接第二加法器的另一输入端，第一积分器的输出端还经第二增益放大器后接第二加法器的再一输入端，量化器的输出端经数模转换器接减法器的反向输入端，第二积分器的输出端还经第三增益放大器后接第一加法器的另一输入端，实现了一种
sigma-delta调制器，各积分器只处理量化噪声， 能减少了失真、提高稳定性及输入信号的动态范围。
图 1 是现有技术提供的三阶 sigma-delta 调制器的结构示意图；
图 2 是本发明 实施例提供的 二阶 sigma-delta 调制器的结构示意图；
图 3 是本发明 实施例提供的 三阶 sigma-delta 调制器的结构示意图；
图 4 是本发明实施例提供的三阶 sigma-delta
调制器的第三积分器、第一积分器和第二积分器输出的电压范围仿真示意图；
图 5 是图 1 所示的传统三阶 sigma-delta
调制器的第一积分器、第二积分器和第三积分器输出的电压范围仿真示意图；
图 6 是本发明实施例提供的三阶 sigma-delta
调制器在输入模拟信号幅度比较大的情况下输出的数字信号的信噪比的仿真示意图；
图 7 是图 1 所示的传统三阶 sigma-delta
调制器在输入模拟信号幅度比较大的情况下输出的数字信号的信噪比的仿真示意图；
图 8 是本发明实施例提供的延时积分器的结构示意图；
图 9 是本发明 实施例提供的 四阶 sigma-delta 调制器的结构示意图。
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本发明实施例中，通过第二增益放大器、第三增益放大器、数模转换器，以及顺序连接的减法器、第一加法器、第一积分器、第二积分器、第一增益放大器、第二加法器、量化器，减法器的正向输入端接第二加法器的另一输入端，第一积分器的输出端还经第二增益放大器后接第二加法器的再一输入端，量化器的输出端经数模转换器（
DAC ）接减法器的反向输入端，第二积分器的输出端还经第三增益放大器后接第一加法器的另一输入端，实现了一种 sigma-delta
调制器，各积分器只处理量化噪声 。
图 2 示出了本发明实施例提供的二阶 sigma-delta
调制器的结构，为了便于说明仅示出了与本发明实施例相关的部分。
该 sigma-delta
调制器可以用于数据处理设备，例如数字音频处理设备、数字电视、图像编码设备、频率合成设备等，可以是运行于这些设备内的软件单元、硬件单元或者软硬件相结合的单元，也可以作为独立的挂件集成到这些数据处理设备中或者运行于这些数据处理设备的应用系统中。其中，该
sigma-delta 调制器包括第二增益放大器 208 、第三增益放大器 210 、数模转换器 209 ，以及顺序连接的减法器 201 、第一加法器 202
、第一积分器 203 、第二积分器 204 、第一增益放大器 205 、第二加法器 206 、量化器 207 ，减法器 201 的正向输入端接第二加法器
206 的另一输入端，第一积分器 203 的输出端还经第二增益放大器 208 后接第二加法器 206 的再一输入端，量化器 207 的输出端经数模转换器（
DAC ） 209 接减法器 201 的反向输入端，第二积分器 204 的输出端还经第三增益放大器 210 后接第一加法器 202
的另一输入端。这里，第二加法器 206 的输入端为 3 个。
这样，即将实现了：
1 、将模拟输入信号前馈到量化器 207 前的第二加法器 206 的输入端；
2 、将第一积分器 203 和第二积分器 204 的输出经增益放大器 208 、 205
后前馈到量化器 207 前的第二加法器 206 的另外两个输入端；
3 、 将最后一个积分器（即第二放大器）的输出经第三增益放大器 210
后反馈到上一个积分器（即第一放大器）前的第一加法器 202 的输入端；
4 、通过第二加法器 206 将所有的前馈信号进行累加，并把累加后的信号送入到量化器 207
进行量化；量化后的信号一路作为输出，另一路则经过数模转换器 209 把数字信号转换为模拟信号；转换后的模拟信号反馈回减法器 201
的反向输入端，与原模拟输入信号相减。
在本发明实施例中，量化器 207 为均匀量化器 207
，即把输入信号的取值域按等距离分割。假如，量化器 207 为 n 比特量化器 207 ，那么输入信号的取值域则按 n 等份进行等距离分割。
数模转换器 209 将数字信号转换为模拟信号，然后把转换后的模拟信号反馈回减法器 201
的反向输入端。数模转换器 209 可以为电压定标型数模转换器 209 、电荷定标型数模转换器 209 或电流定标型数模转换器 209 。
由于电荷定标型数模转换器 209
的精度较高，作为本发明的一个优选实施例，可以采用的电荷定标型数模转换器 209 ，以进一步提高 sigma-delta 调制器的精度。
对于三阶及以上的 sigma-delta
调制器，还包括至少一个增益放大器，以及分别对应各增益放大器的连接于减法器 201 与第一加法器 202
之间的至少一个积分器，各积分器的输出端还分别经增益放大器后接第二加法器 206 的一输入端。
图 3 示出了本发明实施例提供的三阶 sigma-delta
调制器的结构，为了便于说明仅示出了与本发明实施例相关的部分。
在二阶 sigma-delta 调制器的基础上，在减法器 201 与第一加法器 202
之间增加了第三积分器 211 ，且第三积分器 211 的输出端还经第四增益放大器 212 后接第二加法器 206 的一输入端。这里，第二加法器 206
的输入端为 4 个。第三积分器 211 、第一积分器 203 和第二积分器 204 输出的 Z 域表达式如下：
其中， X(z) 为输入信号的 Z 域表达式。
分别为前馈增益系数，
为反馈增益系数； E(z) 分别为量化误差的 Z 域表达式。
从表达式 (4) 、 (5) 、 (6) 中可以看出，第一积分器 203 、第二积分器 204
和第三积分器 211 的输出并不包含输入信号 X(z)
，只与量化误差有关，即各积分器只处理量化噪声，这大大降低了各积分器的电压输出范围，能有效防止由于过载问题而产生的系统不稳定性。
另外，本发明实施例提供的 sigma-delta 调制器能有效解决当模拟输入信号较大时量化器 207
过载的问题，使系统处于稳定状态，从而有效的扩大了模拟输入信号的动态范围。
图 4 示出了本发明实施例提供的三阶 sigma-delta 调制器的第三积分器 211 、第一积分器
203 和第二积分器 204 输出的电压范围仿真示意图；图 5 示出了图 1 所示的传统三阶 sigma-delta 调制器的第一积分器 203 、第二积分器
204 和第三积分器 211 输出的电压范围仿真示意图。其中，仿真条件具体为：过采样率为 16 ，过采样频率为 24MHz ，满度相对电平（ dB full
scale ， dBFS ）为 -3dB ，信号频带为 1MHz ，信号输入频率为 146480Hz
；仿真示意图中的横坐标为积分器的输出电压，纵坐标为相应输出电压出现的次数。从图 4 、 5 中可以看出，本发明实施例提供的三阶 sigma-delta
调制器的各积分器输出的电压范围明显小于图 1 所示的传统三阶 sigma-delta 调制器的各积分器输出的电压范围。同样，对于其他阶 sigma-delta
调制器也可以得到类似的仿真结果。
同样，在本发明实施例中，量化器 207 为均匀量化器 207 ；数模转换器 209
可以为电压定标型数模转换器 209 、电荷定标型数模转换器 209 或电流定标型数模转换器 209 。
图 6 、 7 分别示出了本发明实施例提供的三阶 sigma-delta 调制器与图 1
所示的传统三阶 sigma-delta 调制器在输入模拟信号幅度比较大的情况下，输出的数字信号的信噪比的仿真示意图。图 6 、 7 的仿真条件与图 4 、 5
的仿真条件相同；通过把调制器的最后输出加汉明窗后做快速傅里叶变换（ Fast Fourier Transform ， FFT
）后取模值的平方，再取对数，即可得到图 6 、 7 所示的频率与功率谱密度的关系。从图 6 、 7 可以看出：传统三阶 sigma-delta
调制器由于输入信号幅度过大 ，而导致调制器不稳定，从而使调制器的性能急剧下降；然而本发明实施例提供的三阶 sigma-delta
调制器，克服了不稳定性问题，使输入信号的动态范围扩大，信噪比得到提升。一般来说，当输入信号使调制器过载时，则认为输入信号比较大。同样，对于其他阶
sigma-delta 调制器也可以得到类似的仿真结果。
为了进一步提高 sigma-delta 调制器的稳定性，作为本发明的一个优选实施例，
sigma-delta 调制器中的第一积分器 203 、第二积分器 204 和第三积分器 211 等积分器为延时积分器。
具体地，如图 8 所示，延时积分器由顺序连接的加法器 801 、单位延时器 802 和限幅器 803
组成。
限幅器 803 的作用是将积分器的输出电压限制在某个特定的范围内，以防止 sigma-delta
调制器中量化器 207 的输入幅度过大，而导致量化器 207 过载。
所需处理的输入信号首先传送到加法器 801 的一个输入端口；加法器 801 的输出端口与单位延时单元
802 的输入端口进行连接；单位延时单元 802 的输出信号直接输入到限幅器 803 ；限幅器 803 的一路输出信号反馈回加法器 801
的另一个端口，而另一路输出则作为单位延时器 802 的输出信号。这个闭环回路就组成了一个积分器，积分器的系统传输函数为：：
其中， X(Z) 为输入信号， Y(Z) 为输出信号。
图 9 示出了本发明实施例提供的四阶 sigma-delta
调制器的结构，为了便于说明仅示出了与本发明实施例相关的部分。
在三阶 sigma-delta 调制器的基础上，在减法器 201 与第一加法器 202
之间增加了第四积分器 213 ，且第四积分器的输出端还经第五增益放大器 214 后接第二加法器 206 的一输入端。这里，第二加法器 206 的输入端为 5
个。该第四积分器 213 可以连接于减法器 201 与第三积分器 211 之间，即如图 9 所示，也可以连接于第三积分器 211 与第一加法器 202
之间，即图 9 中的第三积分器 211 与第四积分器 213 交换位置即可。各积分器、量化器 207 、数模转换器 209
等的实现如上所述，不再赘述。
在本发明实施例中，通过第二增益放大器、第三增益放大器、数模转换器，以及顺序连接的减法器、第一加法器、第一积分器、第二积分器、第一增益放大器、第二加法器、量化器，减法器的正向输入端接第二加法器的另一输入端，第一积分器的输出端还经第二增益放大器后接第二加法器的再一输入端，量化器的输出端经数模转换器接减法器的反向输入端，第二积分器的输出端还经第三增益放大器后接第一加法器的另一输入端，实现了一种
sigma-delta 调制器，各积分器只处理量化噪声， 能减少了失真、提高稳定性及输入信号的动态范围。
进一步地， sigma-delta
调制器还包括至少一个增益放大器以及分别对应各增益放大器的连接于减法器与第一加法器之间的至少一个积分器，各积分器的输出端还分别经增益放大器后接第二加法器的一输入端，以实现三阶及以上的
sigma-delta 调制器。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
Claims (9)
- 一种 sigma-delta 调制器，其特征在于，所述 sigma-delta 调制器包括：第二增益放大器、第三增益放大器、数模转换器，以及顺序连接的减法器、第一加法器、第一积分器、第二积分器、第一增益放大器、第二加法器、量化器；所述减法器的正向输入端接所述第二加法器的另一输入端，所述第一积分器的输出端还经所述第二增益放大器后接所述第二加法器的再一输入端，所述量化器的输出端经所述数模转换器接所述减法器的反向输入端，所述第二积分器的输出端还经所述第三增益放大器后接所述第一加法器的另一输入端。
- 如权利要求 1 所述的 sigma-delta 调制器，其特征在于，所述的 sigma-delta 调制器还包括至少一个增益放大器，以及分别对应各所述增益放大器的连接于所述减法器与所述第一加法器之间的至少一个积分器，各所述积分器的输出端还分别经增益放大器后接第二加法器的一输入端。
- 如权利要求 2 所述的 sigma-delta 调制器，其特征在于，所述至少一个增益放大器为第四增益放大器，所述至少一个积分器为第三积分器，所述第三积分器的输出端还经所述第四增益放大器后接所述第二加法器的一输入端。
- 如权利要求 3 所述的 sigma-delta 调制器，其特征在于， sigma-delta 调制器还包括第五增益放大器和第四积分器，第四积分器连接于所述减法器与所述第一加法器之间，且所述第四积分器的输出端还经所述第五增益放大器后接所述第二加法器的一输入端。
- 如权利要求 1 至 4 任一项所述的 sigma-delta 调制器，其特征在于，所述量化器为均匀量化器。
- 如权利要求 1 至 4 任一项所述的 sigma-delta 调制器，其特征在于，所述数模转换器为电压定标型数模转换器、电荷定标型数模转换器或电流定标型数模转换器。
- 如权利要求 1 所述的 sigma-delta 调制器，其特征在于，所述第一积分器、第二积分器为延时积分器。
- 如权利要求 2 所述的 sigma-delta 调制器，其特征在于，所述至少一个积分器为至少一个延时积分器。
- 如权利要求 7 或 8 所述的 sigma-delta 调制器，其特征在于，所述延时积分器由顺序连接的加法器、单位延时器和限幅器组成。
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| CN102545901B (zh) * | 2012-02-21 | 2015-06-17 | 北京工业大学 | 基于逐次比较量化器的二阶前馈Sigma-Delta调制器 |
| CN102638268B (zh) * | 2012-04-19 | 2015-02-18 | 北京工业大学 | 基于逐次比较量化器的三阶前馈Sigma-Delta调制器 |
| US8779957B2 (en) * | 2012-08-02 | 2014-07-15 | Qualcomm Incorporated | Low distortion feed-forward delta-sigma modulator |
| US9054733B2 (en) * | 2013-06-12 | 2015-06-09 | Microchip Technology Incorporated | Quantization noise coupling delta sigma ADC with a delay in the main DAC feedback |
| WO2015066879A1 (zh) * | 2013-11-07 | 2015-05-14 | 深圳大学 | Sigma-delta调制器 |
| CN104883190B (zh) * | 2014-02-28 | 2018-10-16 | 山东共达电声股份有限公司 | 一种包含自适应增量调制的高精度模数转换器 |
| JP5958884B2 (ja) * | 2014-03-20 | 2016-08-02 | カシオ計算機株式会社 | Ｄ／ａ変換装置、ｄ／ａ変換方法及び電子楽器 |
| CN106788444A (zh) * | 2016-12-12 | 2017-05-31 | 浙江大学 | 同时实现无杂散、高信噪失真比的低通σδ调制器 |
| CN113848380B (zh) * | 2021-10-22 | 2023-10-20 | 深圳市兆驰数码科技股份有限公司 | 功率检测电路及方法、直流和相位的检测系统及方法 |
| CN114499536A (zh) * | 2022-03-31 | 2022-05-13 | 深圳市爱普特微电子有限公司 | 用于Sigma-DeltaADC的过载处理方法和系统 |
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| US7450047B1 (en) * | 2007-09-06 | 2008-11-11 | National Semiconductor Corporation | Sigma-delta modulator with DAC resolution less than ADC resolution and increased dynamic range |
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