WO2012132692A1 - 並列処理システム及び並列処理システムの動作方法 - Google Patents
並列処理システム及び並列処理システムの動作方法 Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17331—Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
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- the present invention relates to a parallel processing system and an operation method of the parallel processing system.
- a parallel processing system may be used to speed up the computation processing by a computer.
- processing is executed in parallel by a plurality of computers (computers).
- a parallel processing system a shared memory type parallel processing system and a distributed memory type parallel processing system are known.
- FIG. 1A is a conceptual diagram showing an example of a shared memory type parallel processing system.
- the parallel processing system 100 includes a plurality of computers 102 (102-1 to 102-n) and a shared memory 101.
- a plurality of processes are assigned to a plurality of computers 102 (102-1 to 102-n).
- Each of the plurality of computers 102 executes the assigned process by accessing the shared memory 101.
- FIG. 1B is a conceptual diagram showing an example of a distributed memory type parallel processing system.
- the parallel processing system 100 includes a plurality of computers 102-1 to 102-n.
- Each computer 102 is provided with a distributed memory 103 (103-1 to 103-n).
- Each computer 102 executes assigned processing by accessing its own distributed memory 103.
- this parallel processing system 100 in order to make the data stored in the distributed memory 103 coincide among a plurality of computers 102, synchronous processing is required.
- each computer 102 executes the next assigned process.
- Patent Document 1 Japanese Patent No. 2559918 discloses a distributed memory type computer having a configuration in which a plurality of independently operating computers are connected. This distributed memory type computer has a synchronization request register means for each of the computers independently making a synchronization request and holding a synchronization request signal, a synchronization judgment means for judging that there is a request from the synchronization request registers of all computers, Synchronous distribution means for distributing the determination results to all computers, synchronous detection register means for detecting synchronization based on the distributed determination results, and independently provided in each computer, the processing in each computer is executed as prescribed.
- Status request register means for requesting status indicating whether or not, and holding a status request signal, status determination means for determining whether there is a request from the status request register of all computers, and status for distributing the determination results to all computers According to the distribution means, the determination result distributed by the status distribution means and the determination result distributed by the synchronization means.
- the status detection register means for status detection Te can detect the status of all computers when the synchronization is established in all computers.
- an object of the present invention is to provide a parallel processing system and an operation method of the parallel processing system that can improve the processing performance without providing a complicated control function.
- the parallel processing system includes a plurality of computers that are connected to each other via a network and execute a plurality of processes in a distributed manner.
- Each of the plurality of computers includes an arithmetic processing unit that executes assigned processing, a local memory group having a first area and a second area, and an input / output control circuit.
- the arithmetic processing unit executes processing using the first area as an access destination address in a first period, and executes processing using the second area as an access destination address in a second period following the first period.
- the input / output control circuit includes an updating unit that updates the data stored in the local memory group to the latest data by performing communication between the plurality of computers.
- the update unit is configured to update the data stored in the first area in the second period.
- each computer since each computer executes the process assigned with the local memory group as the access destination, there is no memory access contention.
- processing is executed in the first period with the first area as the access destination.
- the process is executed with the second area as the access destination.
- the data stored in the first area is updated in the second period. That is, in the second period, the execution of the process using the second area as the access destination and the updating of the first area are performed in parallel.
- it is not necessary to stop execution of processing in each computer. Therefore, the processing performance in the parallel processing system can be improved.
- the operation method of the parallel processing system is an operation method of the parallel processing system including a plurality of computers connected to each other via a network.
- Each of the plurality of computers includes an arithmetic processing unit that executes assigned processing, a local memory group having a first area and a second area, and an input / output control circuit.
- the operation method includes a step in which the arithmetic processing unit executes processing in the first period using the first area as an access destination address, and the arithmetic processing unit performs the processing in the second period following the first period.
- the step of executing the process using the second area as the access destination address and the input / output control circuit communicate with each other so that the data stored in the local memory group becomes the latest data. Updating.
- the updating step includes a step of updating data stored in the first area in the second period.
- a parallel processing system and an operation method of the parallel processing system that can improve processing performance without providing a complicated control function are provided.
- FIG. 1 It is a conceptual diagram which shows an example of a shared memory type parallel processing system.
- 1 is a conceptual diagram illustrating an example of a distributed memory type parallel processing system.
- 1 is a schematic diagram showing a parallel processing system according to a first embodiment. It is a conceptual diagram which shows the memory space of CPU in each computer. It is a figure for demonstrating the operation
- FIG. 2 is a schematic diagram showing the parallel processing system 1 according to the present embodiment.
- the parallel processing system 1 includes a plurality of computers (computers) 2-1 to 2-n, which are connected to each other via a network 3 so as to be accessible to each other. Yes.
- the program executed by the parallel processing system 1 includes a plurality of processes. A plurality of processes are allocated to be distributed to a plurality of computers 2-1 to 2-n and executed in parallel.
- Each of the plurality of computers 2-1 to 2-n has a CPU 4 (arithmetic processing unit), a local memory group 5, and an input / output control circuit 6.
- a timer circuit 10 is provided in at least one of the plurality of computers 2-1 to 2-n. In the present embodiment, a timer circuit 10 is provided in the computer 2-1.
- the CPU 4 (arithmetic processing unit), the local memory group 5, the input / output control circuit 6, and the timer circuit 10 are connected to each other via a bus. In each computer 2, the CPU 4 executes assigned processing using data stored in the local memory group 5.
- the timer circuit 10 has a function of generating a timer signal and supplying it to a plurality of computers 2-1 to 2-n.
- the timer circuit 10 has a predetermined time set in advance.
- the timer circuit 10 generates a timer signal and supplies it to the CPU 4 and the input / output control circuit 6 every time the specified time elapses.
- the timer signal supplied to the input / output control circuit 6 is supplied to other computers (2-2 to 2-n) via the network 3. In other computers (2-2 to 2-n), a timer signal is supplied to the CPU 4 via the input / output control circuit 6.
- the local memory group 5 has a first area and a second area.
- FIG. 3 is a conceptual diagram showing the memory space of the CPU 4 in each computer 2. As shown in FIG. 3, in the memory space, the first area and the second area are allocated to different areas.
- a plurality of partial areas are set in each of the first area and the second area.
- the plurality of partial areas are set so as to correspond to the plurality of computers 2-1 to 2-n.
- the CPU 4 executes the assigned process using either the first area or the second area as the access destination address, and writes the execution result of the assigned process in the partial area corresponding to the own computer. For example, in the computer 2-1, the CPU 4 writes the execution result of the assigned process in the partial area 1 of the first area or the second area (the partial area corresponding to the computer 2-1).
- the CPU 4 is configured to switch the access destination area between the first area and the second area each time a timer signal is acquired. That is, the CPU 4 switches the access destination area every time the specified time elapses.
- the input / output control circuit 6 is connected to the network 3 and has a function of transmitting / receiving data to / from another computer 2. As shown in FIG. 2, the input / output control circuit 6 includes an update unit 7.
- the updating unit 7 has a function of performing communication between a plurality of computers 2 and updating the data stored in the local memory group 5 so as to become the latest data.
- FIG. 4 is a diagram for explaining an operation method of the parallel processing system 1.
- FIG. 4 shows the relationship between time and processing for the first area and the second area.
- the time when the timer circuit 10 first generates the timer signal is shown as time t0.
- the time when the timer signal is supplied next to time t0 is shown as time t1.
- the time when the timer signal is supplied next to time t1 is shown as time t2.
- the time when the timer signal is supplied next to time t2 is shown as time t3.
- the CPU 4 executes the assigned process with the first area as the access destination.
- the CPU 4 switches the access destination to the second area. That is, during the period from the time t1 to the time t2 (second period), the CPU 4 executes the assigned process with the second area as the access destination.
- the timer signal is supplied at time t2
- the CPU 4 switches the access destination to the first area again.
- the CPU 4 executes the process using the first area as the access destination, similarly to the period from the time t0 to the time t1.
- the update unit 7 of the input / output control circuit 6 updates the data stored in the second area.
- the update unit 7 updates the data stored in the first area.
- the update unit 7 updates the data stored in the second area.
- the update unit 7 updates the data stored in the second area during the period (first period) in which the CPU 4 executes the process assigned with the first area as the access destination. . In addition, the update unit 7 updates the data stored in the first area during the period (second period) in which the CPU 4 executes the process assigned with the second area as the access destination.
- FIG. 5A is a diagram for explaining an operation example in the first period.
- FIG. 5A shows operating states of the computer 2-1, the computer 2-2, and the computer 2-3.
- the CPU 4 executes the assigned process using the first area.
- the processing result is written in the partial area 1 (the partial area corresponding to the computer 2-1) of the first area in the computer 2-1.
- the processing result is written in the partial area 2 of the first area (the partial area corresponding to the computer 2-2).
- the processing result is stored in the partial area 3 of the first area (the partial area corresponding to the computer 2-3).
- the data stored in the second area is updated by the update unit 7.
- FIG. 5B is a diagram for describing an operation example in the second period.
- the update unit 7 updates the data stored in the first area. That is, as shown in FIG. 5B, the data written in the partial area 1 of the first area of the computer 2-1 is transferred to the partial area 1 of the first area of each of the computers 2-2 and 2-3. Copied. Similarly, the data written in the partial area 2 of the first area of the computer 2-2 is copied to the partial area 2 of the first area of each of the computers 2-1 and 2-3. Similarly, the data written in the partial area 3 of the first area of the computer 2-3 is copied to the partial area 3 of the first area of each of the computers 2-1 and 2-2.
- the data stored in the first area in each computer 2 is updated so as to become the latest data.
- the CPU 4 executes the assigned process using the second area.
- the CPU 4 writes the execution result of the process in the partial area 1 of the second area.
- the execution result of the process is written in the partial area 2 of the second area.
- the execution result of the process is written in the partial area 3 of the second area.
- Data written to the second area of each computer 2 is copied to the second area of another computer in the next first period.
- each computer 2 can execute the process assigned by the stand-alone and does not need to perform the synchronization process.
- the processing performance can be improved without mounting a complicated control function for the synchronous processing.
- the local memory group 5 may be provided with three or more areas.
- the other area is updated during the period in which the process assigned using the one area is executed. Even if such a configuration is adopted, the same effect as in the present embodiment can be obtained.
- the first area and the second area are allocated to different memory elements. That is, in each computer 2, the local memory group 5 includes a first memory element and a second memory element, a first area is allocated to the first memory element, and a second area is allocated to the second memory element. Preferably it is assigned. If such a configuration is adopted, the CPU 4 only needs to access the first memory element in the first period, and only needs to access the second memory element in the second period. Therefore, it is possible to completely separate the operation when the CPU 4 accesses each memory element and the operation when the update unit 7 accesses each memory element. The memory access operation by the CPU 4 and the memory access operation by the updating unit 7 do not conflict, and the processing performance can be further improved.
- FIG. 6 is a schematic diagram showing the parallel processing system 1 according to the present embodiment. As shown in FIG. 6, in the present embodiment, a specified time changing unit 9 is added to the input / output control circuit 6. About another point, since the structure similar to 1st Embodiment is employable, detailed description is abbreviate
- the default time changing unit 9 has a function of changing the specified time set in the timer circuit 10. For example, when the default time change unit 9 obtains a default time change instruction from the user via an input device (not shown) connected to the network, the default time change unit 9 determines the timer circuit 10 based on the default time change instruction. Change the setting. In the subsequent operation, the length of each of the first period and the second period becomes the predetermined time after the change.
- the parallel processing system 1 it is possible to set an optimal specified time according to the form of the program executed in the parallel processing system 1. For example, it is possible to cope with complicated processing by extending the specified time. In addition, by shortening the specified time, it is possible to improve the real time property of the processing.
- each computer 2 is configured such that the CPU 4 can switch the partial area in which the execution result of the process is written to another partial area. Since the other points can be the same as those of the above-described embodiment, detailed description thereof is omitted.
- FIG. 7 is an explanatory diagram for explaining an operation method of the parallel processing system 1 according to the present embodiment.
- each computer 2 is provided with a plurality of partial areas in each of the first area and the second area so as to correspond to all the computers 2.
- FIG. 7 schematically shows the configuration of the computer 2-1.
- the CPU 4 writes the execution result of the process in the partial area (partial area 1) corresponding to the own computer.
- an instruction is given to the CPU 4 of each computer 2 to change the write destination partial area.
- This instruction is given by, for example, an input device (not shown) connected to the network 1.
- the CPU 4 rewrites the partial area to which the processing result is written.
- the partial area to be written to is switched from the partial area 1 to the partial area n. This makes it possible for the computer 2-1 to function as the computer 2-n.
- each computer 2 can be made to function as another computer connected to the network 1 by changing the partial area where the processing result is written. Therefore, even when the number of computers 1 connected to the network 1 is changed, the parallel processing system 1 can be operated without contradiction. In the parallel processing system 1, it becomes possible to easily provide redundancy and expandability.
- the update unit 7 performs an update process so that a copy operation is executed between a plurality of computers 2 by a relay operation.
- FIG. 8 is an explanatory diagram for explaining an example of the update process.
- the number of computers 2 connected to the network 1 is three.
- FIG. 8 shows the state of the first area in each of the computer 2-1, the computer 2-2, and the computer 2-3.
- the processing result a is written in the partial area 1 of the computer 2-1 and the processing result b is written in the partial area 2 of the computer 2-2 in the first period. It is assumed that the processing result c is written in the partial area 3 (shaded portion in the figure).
- the data (processing result a) written in the partial area 1 is copied from the computer 2-1 to the computer 2-2.
- the data (processing result a and processing result b) written in the partial area 1 and the partial area 2 are copied from the computer 2-2 to the computer 2-3.
- the data (processing results b and c) written in the partial area 2 and the partial area 3 are copied from the computer 2-3 to the computer 2-1.
- the data (processing result c) written in the partial area 3 is copied from the computer 2-1 to the computer 2-2.
- data stored in the local memory group 5 is copied (sequentially) so as to be relayed between a plurality of computers 2. Therefore, even if the number of computers 2 connected to the network 1 is changed, the data stored in the local memory group 5 can be easily unified in all the computers 2.
Abstract
Description
図2は、本実施形態に係る並列処理システム1を示す概略図である。図2に示されるように、並列処理システム1は、複数の計算機(コンピュータ)2-1~2-nを備えており、これらは、ネットワーク3を介して互いにアクセス可能になるように接続されている。並列処理システム1により実行されるプログラムには、複数の処理が含まれている。複数の処理は、複数の計算機2-1~2-nに分散するように割り当てられ、並列的に実行される。
機2-3の各々の第1領域の部分領域2に、コピーされる。同様に、計算機2-3の第1領域の部分領域3に書き込まれたデータが、計算機2-1及び計算機2-2の各々の第1領域の部分領域3に、コピーされる。これにより、各計算機2において第1領域に格納されたデータが、最新のデータになるように更新される。一方、CPU4は、第2領域を利用して、割り当てられた処理を実行する。図5Bに示される例では、計算機2-1において、CPU4が、第2領域の部分領域1に、処理の実行結果を書き込む。また、計算機2-2においては、第2領域の部分領域2に、処理の実行結果が書き込まれる。計算機2-3においては、第2領域の部分領域3に、処理の実行結果が書き込まれる。各計算機2の第2領域に書き込まれたデータは、次の第1期間において、他の計算機の第2領域にコピーされる。
続いて、第2の実施形態について説明する。図6は、本実施形態に係る並列処理システム1を示す概略図である。図6に示されるように、本実施形態では、入出力制御回路6に、規定時間変更部9が追加されている。その他の点については、第1の実施形態と同様の構成を採用することができるので、詳細な説明は省略する。
続いて、第3の実施形態について説明する。本実施形態では、各計算機2において、CPU4が、処理の実行結果を書き込む部分領域を、他の部分領域に切り替えることができるように構成されている。その他の点については、既述の実施形態と同様とすることができるので、詳細な説明は省略する。
続いて、第4の実施形態について説明する。本実施形態においては、更新部7の動作が工夫されている。その他の点については、第1の実施形態と同様とすることができるので、詳細な説明は省略する。
Claims (8)
- ネットワークを介して互いにアクセス可能に接続され、複数の処理を分散して実行する、複数の計算機、
を具備し、
前記複数の計算機の各々は、
割り当てられた処理を実行する演算処理装置と、
第1領域及び第2領域を有する、ローカルメモリ群と、
入出力制御回路とを備え、
前記演算処理装置は、
第1期間において、前記第1領域をアクセス先アドレスとして処理を実行し、
前記第1期間に続く第2期間において、前記第2領域をアクセス先アドレスとして処理を実行し、
前記入出力制御回路は、前記複数の計算機間で通信を行なうことにより、前記ローカルメモリ群に格納されたデータを最新のデータになるように更新する、更新部を備え、
前記更新部は、前記第2期間において、前記第1領域に格納されたデータを更新するように構成されている
並列処理システム。 - 請求項1に記載された並列処理システムであって、
前記入出力制御回路は、更に、前記第1期間の長さを変更する、規定時間変更部を有している
並列処理システム。 - 請求項1又は2に記載された並列処理システムであって、
前記第1領域及び前記第2領域は、それぞれ、前記複数の計算機の全てに対応する複数の部分領域を有しており、
前記各計算機において、前記演算処理装置は、処理の実行結果を、前記複数の部分領域のうちの対応する部分領域に書き込む
並列処理システム。 - 請求項3に記載された並列処理システムであって、
前記演算処理装置は、処理の実行結果の書込み先となる部分領域を他の部分領域に変更することが可能となるように、構成されている
並列処理システム。 - 請求項1乃至4のいずれかに記載された並列処理システムであって、
前記更新部は、前記第2期間において、前記複数の計算機間で前記1領域に格納されたデータがリレーされるように、前記第1領域に格納されたデータを次の計算機にコピーし、前記第1領域の更新を行なう
並列処理システム。 - ネットワークを介して互いにアクセス可能に接続され、複数の処理を分散して実行する、複数の計算機、
を具備し、
前記複数の計算機の各々は、
割り当てられた処理を実行する演算処理装置と、
複数の領域を有する、ローカルメモリ群と、
入出力制御回路とを備え、
前記演算処理装置は、
前記複数の領域のうちのいずれかの領域をアクセス先として処理を実行し、
予め定められた規定時間が経過するたびに、アクセス先を、前記複数の領域のうちの他の領域に切り替え、
前記入出力制御回路は、前記複数の計算機間で通信を行なうことにより、前記ローカルメモリ群に格納されたデータを最新のデータになるように更新する、更新部を備え、
前記更新部は、前記演算処理装置が前記複数の領域のうちの一の領域をアクセス先として処理を実行している間に、前記複数の領域のうちの他の領域に格納されたデータを更新する
並列処理システム。 - ネットワークを介して互いにアクセス可能に接続された、複数の計算機、
を具備し、
前記複数の計算機の各々は、
割り当てられた処理を実行する演算処理装置と、
第1領域及び第2領域を有する、ローカルメモリ群と、
入出力制御回路とを備える
並列処理システムの動作方法であって、
前記演算処理装置が、第1期間において、前記第1領域をアクセス先アドレスとして処理を実行するステップと、
前記演算処理装置が、前記第1期間に続く第2期間において、前記第2領域をアクセス先アドレスとして処理を実行するステップと、
前記入出力制御回路が、前記複数の計算機間で通信を行なうことにより、前記ローカルメモリ群に格納されたデータを最新のデータになるように更新するステップと、
を具備し、
前記更新するステップは、前記第2期間において、前記第1領域に格納されたデータを更新するステップを含んでいる
並列処理システムの動作方法。 - ネットワークを介して互いにアクセス可能に接続された、複数の計算機、
を具備し、
前記複数の計算機の各々は、
割り当てられた処理を実行する演算処理装置と、
複数の領域を有する、ローカルメモリ群と、
入出力制御回路とを備える
並列処理システムの動作方法であって、
前記演算処理装置が、前記複数の領域のうちのいずれかの領域をアクセス先として処理を実行するステップと、
前記演算処理装置が、予め定められた規定時間が経過するたびに、アクセス先を、前記複数の領域のうちの他の領域に切り替えるステップと、
前記入出力制御回路が、前記複数の計算機間で通信を行なうことにより、前記ローカルメモリ群に格納されたデータを最新のデータになるように更新するステップと、
を具備し、
前記更新するステップは、前記演算処理装置が前記複数の領域のうちの一の領域をアクセス先として処理を実行している間に、前記複数の領域のうちの他の領域に格納されたデータを更新するステップを含んでいる
並列処理システムの動作方法。
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US10747546B2 (en) * | 2017-06-19 | 2020-08-18 | Mitsubishi Electric Corporation | Distributed allocation device, distributed allocation system, and distributed allocation method |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63238653A (ja) * | 1986-11-27 | 1988-10-04 | Nippon Telegr & Teleph Corp <Ntt> | データ処理装置とその処理方法 |
JPH03105583A (ja) * | 1989-09-20 | 1991-05-02 | Fujitsu Ltd | 並列データ処理方式 |
JPH04114262A (ja) * | 1990-09-05 | 1992-04-15 | Fujitsu Ltd | 高速データ処理装置 |
JP2559918B2 (ja) | 1990-06-14 | 1996-12-04 | 富士通株式会社 | 並列計算機における同期制御方式 |
JP2001084229A (ja) * | 1999-09-10 | 2001-03-30 | Ricoh Co Ltd | Simd型プロセッサ |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69032259T2 (de) | 1989-09-20 | 1998-08-13 | Fujitsu Ltd | Paralleldatenverarbeitungsanlage |
JPH07271744A (ja) * | 1994-03-31 | 1995-10-20 | Matsushita Electric Ind Co Ltd | 並列計算機 |
JPH0981532A (ja) * | 1995-09-08 | 1997-03-28 | Fujitsu Ltd | 分散記憶型並列計算機 |
JP3644158B2 (ja) * | 1996-11-15 | 2005-04-27 | 株式会社日立製作所 | 並列計算機におけるデータ送受信方法 |
JP4260962B2 (ja) | 1999-02-10 | 2009-04-30 | 住友電気工業株式会社 | 多重逆反射体とその製造方法 |
RU2202123C2 (ru) * | 2001-06-06 | 2003-04-10 | Бачериков Геннадий Иванович | Параллельная вычислительная система с программируемой архитектурой |
EP2192495A1 (de) * | 2008-11-11 | 2010-06-02 | Thomson Licensing | Verfahren zur Bearbeitung von Daten mittels Dreifach-Pufferung |
JP4990322B2 (ja) * | 2009-05-13 | 2012-08-01 | 株式会社日立製作所 | データ移動管理装置及び情報処理システム |
-
2011
- 2011-03-29 JP JP2011073163A patent/JP5680466B2/ja active Active
-
2012
- 2012-02-24 US US14/008,023 patent/US9774671B2/en active Active
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- 2012-02-24 EP EP12763064.8A patent/EP2693343B1/en active Active
- 2012-02-24 RU RU2013143837/08A patent/RU2559723C2/ru active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63238653A (ja) * | 1986-11-27 | 1988-10-04 | Nippon Telegr & Teleph Corp <Ntt> | データ処理装置とその処理方法 |
JPH03105583A (ja) * | 1989-09-20 | 1991-05-02 | Fujitsu Ltd | 並列データ処理方式 |
JP2559918B2 (ja) | 1990-06-14 | 1996-12-04 | 富士通株式会社 | 並列計算機における同期制御方式 |
JPH04114262A (ja) * | 1990-09-05 | 1992-04-15 | Fujitsu Ltd | 高速データ処理装置 |
JP2001084229A (ja) * | 1999-09-10 | 2001-03-30 | Ricoh Co Ltd | Simd型プロセッサ |
Non-Patent Citations (1)
Title |
---|
See also references of EP2693343A4 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2689433C1 (ru) * | 2018-06-14 | 2019-05-28 | Российская Федерация, от имени которой выступает ФОНД ПЕРСПЕКТИВНЫХ ИССЛЕДОВАНИЙ | Вычислительный модуль и способ обработки с использованием такого модуля |
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