WO2012132229A1 - MANUFACTURING METHOD FOR TRENCH-TYPE SiC SEMICONDUCTOR DEVICE - Google Patents
MANUFACTURING METHOD FOR TRENCH-TYPE SiC SEMICONDUCTOR DEVICE Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
Abstract
In a trench MOSFET, the voltage resistance of the gate insulating film is lowered by the electric field concentration at trench corners. When the thickness of the gate insulating film is increased in order to suppress this reduction, the ON resistance increases, and it is difficult to establish both a low ON resistance and a high voltage resistance when the thickness of the gate insulating film in a trench is constant. Therefore, a bottom-up-fill optical CVD film (6b) is used in a portion of the gate insulating film in the trench. Thus, the gate insulating film on the bottom surface is thicker than the gate insulating film on the side surfaces. Specifically, a trench-type SiC-MOSFET is manufactured by means of: a step for forming a trench in an SiC substrate; a step for forming the insulating film (6b) in the bottom of the trench by means of optical CVD; and a step for forming a gate electrode (7) above the insulating film.
Description
本発明は、トレンチ型ＳｉＣ半導体装置の製造方法に関する。
The present invention relates to a method of manufacturing a trench type SiC semiconductor device.
シリコンカーバイド（ＳｉＣ）は、シリコン（Ｓｉ）よりも絶縁破壊電界が約１０倍大きいため、耐圧を維持するドリフト層を薄く、かつ不純物濃度を高くすることができ、ＳｉＣは大電力用の電界効果型トランジスタ（ＭＯＳＦＥＴ）の抵抗、すなわち損失を低減できる材料である。そのため、次世代の高耐圧・低損失スイッチングデバイスとしてＳｉＣを用いたＭＯＳＦＥＴが注目されている。しかもＳｉＣ基板に形成した溝（トレンチ）の側面をＭＯＳ界面あるいはチャネルとするトレンチ型ＭＯＳＦＥＴは、従来のＳｉＣ基板表面をＭＯＳ界面あるいはチャネルとするＭＯＳＦＥＴよりも損失が低減できる構造として期待されている。
Since silicon carbide (SiC) has a dielectric breakdown electric field about 10 times larger than that of silicon (Si), the drift layer for maintaining the breakdown voltage can be made thin and the impurity concentration can be increased. SiC is a field effect for high power. It is a material that can reduce the resistance, that is, the loss of a type transistor (MOSFET). For this reason, MOSFETs using SiC have attracted attention as next-generation high withstand voltage / low loss switching devices. In addition, a trench MOSFET in which a side surface of a groove (trench) formed in a SiC substrate has a MOS interface or channel is expected to have a structure capable of reducing loss as compared with a conventional MOSFET having a SiC substrate surface as a MOS interface or channel.
ここで、従来のトレンチ型のパワーＭＯＳＦＥＴの動作原理を図１４を用いて説明する。図において、符号１はｎ＋ドレイン、２はｎ－ドリフト層、３はｐ型ベース領域、４はｐ＋コンタクト領域、５はｎ＋ソース、６（６ａ、ｃ）はゲート絶縁膜、７はゲート電極、８はソース／ゲート間を電気的に絶縁するための層間絶縁膜、９はソース電極、１０はドレイン電極である。ドレイン電極１０とソース電極９との間に電圧が印加された状態で、ゲート電極７に正の電圧が印加されると、ベース層３の表層、すなわちトレンチの側壁表面に電子の反転層が形成される。その結果、ドレイン電極１０からドレイン領域１、ドリフト層２、ソース領域５を経て、ソース電極１０に電流が流れる。
Here, the operation principle of a conventional trench type power MOSFET will be described with reference to FIG. In the figure, reference numeral 1 is an n + drain, 2 is an n − drift layer, 3 is a p-type base region, 4 is a p + contact region, 5 is an n + source, 6 (6a, c) is a gate insulating film, 7 is A gate electrode, 8 is an interlayer insulating film for electrically insulating the source / gate, 9 is a source electrode, and 10 is a drain electrode. When a positive voltage is applied to the gate electrode 7 in a state where a voltage is applied between the drain electrode 10 and the source electrode 9, an electron inversion layer is formed on the surface layer of the base layer 3, that is, the side wall surface of the trench. Is done. As a result, a current flows from the drain electrode 10 to the source electrode 10 through the drain region 1, the drift layer 2, and the source region 5.
本デバイスに望まれる特性は、ゲート電極７に所望の電圧を印加したときにドレイン電流が大きいことである。ドレイン電流は、反転層の電子密度が高いほど大きくなる。反転層電子密度はゲート絶縁膜が薄いほど高くなり、ゲート絶縁膜が薄いほど、ドレイン電流は大きくなる。しかし、ゲート絶縁膜が薄くなるほど耐圧限界が低くなる。特に、トレンチ型ＭＯＳＦＥＴの場合、トレンチの底部側面の角部において電界が集中するために、トレンチ角部のゲート絶縁膜の耐圧が問題になる。
The characteristic desired for this device is that the drain current is large when a desired voltage is applied to the gate electrode 7. The drain current increases as the electron density of the inversion layer increases. The inversion layer electron density is higher as the gate insulating film is thinner, and the drain current is larger as the gate insulating film is thinner. However, the withstand voltage limit decreases as the gate insulating film becomes thinner. In particular, in the case of a trench MOSFET, the electric field concentrates at the corner of the bottom side surface of the trench, so that the breakdown voltage of the gate insulating film at the corner of the trench becomes a problem.
この問題を回避する方法として、ＳｉＣ基板の酸化速度が面方位に依存することを利用し、トレンチ底面のゲート絶縁膜をトレンチ側面のゲート絶縁膜よりも厚くする方法が提案されている（特許文献１）。すなわち、六方晶のＳｉＣ（０００１）カーボン面を表面とし、そこにトレンチを形成し、ＳｉＣトレンチ面を酸化すると、底面のカーボン面の酸化速度が側面のＳｉＣ面の酸化速度よりも大きいために、底面のゲート絶縁膜を側面のゲート絶縁膜よりも厚くすることができる。
As a method for avoiding this problem, a method has been proposed in which the gate insulating film on the bottom surface of the trench is made thicker than the gate insulating film on the side surface of the trench by utilizing the fact that the oxidation rate of the SiC substrate depends on the plane orientation (Patent Literature). 1). That is, when a hexagonal SiC (0001) carbon surface is the surface, a trench is formed there, and the SiC trench surface is oxidized, the oxidation rate of the bottom carbon surface is greater than the oxidation rate of the side SiC surface. The bottom gate insulating film can be made thicker than the side gate insulating film.
特許文献１の発明によるトレンチの底面と側面のゲート絶縁膜の厚さを変える方法では、酸化速度の差に依存しゲート絶縁膜の厚さが決まるため、側面と底面のゲート絶縁膜の厚さを独立して制御するのは困難であった。特に、ゲート絶縁膜がある程度厚くなり酸化速度に面方位の依存性が無くなると、酸化速度がゲート絶縁膜中の酸素の拡散速度で決まるようになり、底面と側面でゲート絶縁膜の厚さの差をある一定以上に大きくするのは困難であった。また、酸化膜厚さをある程度以上厚くすると、界面準位が増えるため、移動度の劣化が顕著になり、オン抵抗の低減という観点から酸化膜は一定の厚さに抑制することが有効であることがわかってきた。すなわち、面方位依存の酸化レートの差により、側面と底面の絶縁膜厚さに所望の差をつけることは、高い耐圧とオン抵抗の低減との両立という観点から望ましくない。また、段差に対してほぼ均一な膜厚分布が得られる化学気相成長などによる堆積膜を組み合わせても、側面と底面の絶縁膜厚さを独立して制御することは不可能である。したがって、Ｃ面にトレンチを形成し、面方位依存の酸化により、側面に対して底面の絶縁膜を厚くする方法ではオン抵抗の低減と高耐圧の両立は困難である。
In the method of changing the thickness of the gate insulating film on the bottom and side surfaces of the trench according to the invention of Patent Document 1, the thickness of the gate insulating film is determined depending on the difference in oxidation rate. It was difficult to control them independently. In particular, when the gate insulating film becomes thicker to some extent and the surface orientation does not depend on the oxidation rate, the oxidation rate is determined by the diffusion rate of oxygen in the gate insulating film. It was difficult to increase the difference beyond a certain level. Further, when the oxide film thickness is increased to a certain extent, the interface state increases, so that the mobility is significantly deteriorated, and it is effective to suppress the oxide film to a certain thickness from the viewpoint of reducing the on-resistance. I understand that. That is, it is not desirable to give a desired difference in the insulating film thickness between the side surface and the bottom surface due to the difference in oxidation rate depending on the plane orientation from the viewpoint of achieving both high breakdown voltage and reduced on-resistance. In addition, even if a deposited film obtained by chemical vapor deposition or the like that provides a substantially uniform film thickness distribution with respect to the step is combined, it is impossible to independently control the insulating film thickness on the side surface and the bottom surface. Therefore, it is difficult to achieve both a reduction in on-resistance and a high breakdown voltage by a method in which a trench is formed in the C-plane and the insulating film on the bottom surface is thickened with respect to the side surface by surface orientation-dependent oxidation.
一方、底面のゲート絶縁膜を側面のゲート絶縁膜よりも厚くする方法として、エッチバックを利用する方法が提案されている（特許文献２）。この方法では、トレンチを形成した後に、トレンチを絶縁膜で覆い、平坦化と絶縁膜のエッチバックによりトレンチの底部にだけ絶縁膜を残した上で、トレンチに対しＳｉＣを酸化、あるいは化学気相成長などで堆積することでゲート絶縁膜を形成している。ところが、この方法ではプラズマでエッチバックを行うため、ＳｉＣトレンチ側面にプラズマによる損傷が入る。また、エッチング後にはエッチングの副生成物がＳｉＣトレンチ側面に付着していると考えられるため、エッチバック後には希フッ酸などでトレンチ側面の損傷層を除去したり、副生成物を除去したりする必要がある。その除去には通常希フッ酸などによる処理が不可欠である。希フッ酸などを用いてトレンチ面からエッチングの副生成物を除去するときに、底面の絶縁膜にピンホールが形成される可能性がある。このピンホールは耐圧を低下させる要因になる。このように、エッチバックを用いて底面の絶縁膜を厚くする方法でも、オン抵抗の低減と高耐圧の両立は困難である。
On the other hand, as a method of making the gate insulating film on the bottom surface thicker than the gate insulating film on the side surface, a method using etch back has been proposed (Patent Document 2). In this method, after the trench is formed, the trench is covered with an insulating film, and the insulating film is left only at the bottom of the trench by planarization and etching back of the insulating film, and then SiC is oxidized or chemical vapor deposited on the trench. A gate insulating film is formed by depositing by growth or the like. However, since this method etches back with plasma, the side surface of the SiC trench is damaged by the plasma. In addition, it is considered that etching by-products are attached to the side surfaces of the SiC trench after the etching. Therefore, after etching back, the damaged layer on the side surfaces of the trench is removed with dilute hydrofluoric acid, or by-products are removed. There is a need to. Usually, treatment with dilute hydrofluoric acid is indispensable for the removal. When etching by-products are removed from the trench surface using dilute hydrofluoric acid or the like, pinholes may be formed in the bottom insulating film. This pinhole becomes a factor of lowering the withstand voltage. Thus, it is difficult to achieve both a reduction in on-resistance and a high breakdown voltage even by a method in which the insulating film on the bottom surface is thickened by using etch back.
そこで本発明の目的はオン抵抗の低減と高耐圧を両立させる方法を提供することである。
Therefore, an object of the present invention is to provide a method for achieving both a reduction in on-resistance and a high breakdown voltage.
上記課題を解決する本願発明の代表的なものを挙げると以下のとおりである。本願発明は、ＳｉＣ基板に対し、トレンチを形成する工程と、トレンチの底に絶縁膜を光ＣＶＤで形成する工程と、絶縁膜の上方にゲート電極を形成する工程とを備えるトレンチ型ＳｉＣ半導体装置の製造方法である。
Typical examples of the present invention for solving the above problems are as follows. The present invention relates to a trench type SiC semiconductor device comprising a step of forming a trench with respect to an SiC substrate, a step of forming an insulating film on the bottom of the trench by photo-CVD, and a step of forming a gate electrode above the insulating film. It is a manufacturing method.
また、別の本願発明は、ＳｉＣ基板に対し、トレンチを形成する工程と、トレンチの側面及び底面に、酸化又は酸窒化、若しくは、熱ＣＶＤにより第一絶縁膜を形成する工程と、トレンチの底面に光ＣＶＤにより第二絶縁膜を形成する工程と、第一および第二絶縁膜の上方にゲート電極を形成する工程とを備えるトレンチ型ＳｉＣ半導体装置の製造方法である。
Another invention of the present application includes a step of forming a trench in a SiC substrate, a step of forming a first insulating film on the side and bottom surfaces of the trench by oxidation, oxynitridation, or thermal CVD, and a bottom surface of the trench. A method of manufacturing a trench type SiC semiconductor device comprising: a step of forming a second insulating film by photo-CVD, and a step of forming a gate electrode above the first and second insulating films.
また、別の本願発明は、ＳｉＣ基板に対し、トレンチを形成する工程と、トレンチの側面及び底面に、酸化又は酸窒化により第一絶縁膜を形成する工程と、トレンチの底面であって、第一絶縁膜の上方に、光ＣＶＤにより第二絶縁膜を形成する工程と、トレンチの側面及び底面であって、第二絶縁膜の上方に、熱ＣＶＤにより第三の絶縁膜を形成する工程と、第三絶縁膜の上方にゲート電極を形成する工程とを備えるトレンチ型ＳｉＣ半導体装置の製造方法である。
Another invention of the present application is a step of forming a trench in an SiC substrate, a step of forming a first insulating film on the side and bottom surfaces of the trench by oxidation or oxynitriding, and a bottom surface of the trench, Forming a second insulating film by photo-CVD above one insulating film; forming a third insulating film by thermal CVD on the side and bottom surfaces of the trench and above the second insulating film; And a step of forming a gate electrode above the third insulating film.
上記方法により、トレンチの上面に対して、トレンチの底面の膜堆積速度が大きな光ＣＶＤを用いて成膜された絶縁膜をトレンチの底近傍のみに選択的に配備し、この膜と酸化膜又は酸窒化膜、若しくは、トレンチの上面に対してトレンチの底面の膜厚がほぼ一定の堆積膜を組み合わせることにより、トレンチ側面のゲート絶縁膜の厚さとトレンチ底面の絶縁膜厚さを独立に制御できる。
By the above method, an insulating film formed using photo-CVD with a large film deposition rate on the bottom surface of the trench with respect to the upper surface of the trench is selectively provided only near the bottom of the trench, and this film and the oxide film or By combining an oxynitride film or a deposited film with a substantially constant thickness on the bottom surface of the trench with respect to the top surface of the trench, the thickness of the gate insulating film on the side surface of the trench and the insulating film thickness on the bottom surface of the trench can be controlled independently. .
本願発明により、オン抵抗の低減と高耐圧を実現するトレンチ型ＳｉＣ半導体装置を製造することができる。
According to the present invention, a trench type SiC semiconductor device that realizes a reduction in on-resistance and a high breakdown voltage can be manufactured.
本発明の実施例１によるトレンチ型ＳｉＣ－ＭＯＳＦＥＴの断面図を図１により説明する。図において、符号１はｎ＋ドレイン、２はｎ－ドリフト層、３はｐ型ベース領域、４はｐ＋コンタクト領域、５はｎ＋ソース、６ａは酸化又は酸窒化によって形成されたゲート絶縁膜、６ｂは光ＣＶＤによってトレンチ底部に堆積された絶縁膜、６ｃは主として熱エネルギーを利用して化学反応を促進させる化学気相成長（以下、熱ＣＶＤという）によって堆積された絶縁膜６ｃ、７はゲート電極、８はソース／ゲート間を電気的に絶縁するための層間絶縁膜、９はソース電極、１０はドレイン電極である。
A cross-sectional view of a trench type SiC-MOSFET according to Example 1 of the present invention will be described with reference to FIG. In the figure, reference numeral 1 denotes an n + drain, 2 denotes an n − drift layer, 3 denotes a p-type base region, 4 denotes a p + contact region, 5 denotes an n + source, and 6a denotes a gate insulating film formed by oxidation or oxynitridation. , 6b is an insulating film deposited on the bottom of the trench by photo-CVD, 6c is an insulating film 6c, 7 deposited by chemical vapor deposition (hereinafter referred to as thermal CVD) that promotes a chemical reaction mainly using thermal energy. A gate electrode, 8 is an interlayer insulating film for electrically insulating the source / gate, 9 is a source electrode, and 10 is a drain electrode.
本トレンチ型ＳｉＣ－ＭＯＳＦＥＴにおいては、ゲート絶縁膜６は、酸化又は酸窒化によって形成されたゲート絶縁膜６ａと光ＣＶＤによってトレンチ底部に堆積された絶縁膜６ｂと熱ＣＶＤによって堆積された絶縁膜６ｃの３種の絶縁膜を組み合わせて構成されている。チャネルとなる側面のゲート絶縁膜は酸化又は酸窒化によって形成されたゲート絶縁膜６ａと熱ＣＶＤによって堆積された絶縁膜６ｃを積層で構成させ、一方、底面のゲート絶縁膜は６ａと６ｃの絶縁膜と光ＣＶＤによってトレンチ底部に堆積された絶縁膜６ｂの積層で構成されている。したがって、トレンチ側面のゲート絶縁膜の厚さはトレンチ底面のゲート絶縁膜の厚さよりも薄くなっている。
In this trench type SiC-MOSFET, the gate insulating film 6 includes a gate insulating film 6a formed by oxidation or oxynitridation, an insulating film 6b deposited at the bottom of the trench by photo-CVD, and an insulating film 6c deposited by thermal CVD. These three types of insulating films are combined. The gate insulating film on the side surface serving as a channel is formed by stacking a gate insulating film 6a formed by oxidation or oxynitridation and an insulating film 6c deposited by thermal CVD, while the gate insulating film on the bottom surface is an insulation between 6a and 6c. It is composed of a stack of a film and an insulating film 6b deposited on the bottom of the trench by photo-CVD. Therefore, the thickness of the gate insulating film on the side surface of the trench is thinner than the thickness of the gate insulating film on the bottom surface of the trench.
ゲート絶縁膜６aは基板を１０００度以上に保ちつつ、酸素（Ｏ２）と水蒸気(Ｈ２Ｏ)、又は水素（Ｈ２）と酸化窒素（Ｎ２ＯあるいはＮＯ）の混合ガスを用いて酸化又は酸窒化して形成された膜であり、トレンチ側面における厚さが５ｎｍである。６ｃはＳｉＣ基板温度を７５０度に保った状態で、シラン（ＳｉＨ４）と酸化窒素（Ｎ２ＯあるいはＮＯ）を原料として供給することにより、化学気相成長により堆積した膜であり、トレンチ側面の厚さが６０ｎｍである。
The gate insulating film 6a is oxidized using a mixed gas of oxygen (O 2 ) and water vapor (H 2 O) or hydrogen (H 2 ) and nitrogen oxide (N 2 O or NO) while keeping the substrate at 1000 ° C. or more. Alternatively, it is a film formed by oxynitriding, and the thickness on the side surface of the trench is 5 nm. 6c is a film deposited by chemical vapor deposition by supplying silane (SiH 4 ) and nitrogen oxide (N 2 O or NO) as raw materials while keeping the SiC substrate temperature at 750 ° C. The thickness is 60 nm.
一方、６ｂは光ＣＶＤで堆積した膜で、底面における膜厚は１００ｎｍである。この膜６ｂは、真空紫外光を照射するランプを備えたＣＶＤ装置にトレンチを形成したＳｉＣ基板を導入し、ＣＶＤ装置に所定の原料ガスを導入することで形成される。具体的には、真空容器中に膜を堆積したいトレンチを加工したＳｉＣ基板を配備し、ＳｉＣ基板の温度を１００度以下に保ち、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙ ｏｒｔｈｏｓｉｌｉｃａｔｅ）を原料ガスとして供給するとともに、１７２ｎｍの波長のＸｅ２のエキシマ光をＳｉＣ基板に照射することによってトレンチの底面に絶縁膜を堆積したものである。原料ガスのＴＥＯＳにはエチル基が多く含まれているが、真空紫外光を照射されるとＳｉ－Ｏの結合が切れ、流動性を持った分子がトレンチの底面に堆積すると考えられている。したがって、トレンチ内においては、トレンチの側面には実質的には絶縁膜が堆積することなく、底面に選択的に絶縁膜が堆積する。結果として、トレンチの底面にのみ絶縁膜を堆積することができる。
On the other hand, 6b is a film deposited by photo-CVD, and the film thickness at the bottom is 100 nm. This film 6b is formed by introducing a SiC substrate having a trench formed in a CVD apparatus provided with a lamp for irradiating vacuum ultraviolet light, and introducing a predetermined source gas into the CVD apparatus. Specifically, an SiC substrate with a trench processed to deposit a film in a vacuum vessel is provided, the temperature of the SiC substrate is kept at 100 ° C. or less, TEOS (Tetrahethy orthosilicate) is supplied as a source gas, and a wavelength of 172 nm An insulating film is deposited on the bottom surface of the trench by irradiating the SiC substrate with Xe2 excimer light. The source gas TEOS contains a lot of ethyl groups, but it is considered that when irradiated with vacuum ultraviolet light, Si—O bonds are broken and molecules having fluidity are deposited on the bottom surface of the trench. Therefore, in the trench, the insulating film is selectively deposited on the bottom surface without substantially depositing the insulating film on the side surface of the trench. As a result, an insulating film can be deposited only on the bottom surface of the trench.
このようにトレンチ（溝）あるいは穴の底に対して選択的に堆積する手法をボトムアップフィルと呼ぶ。上記の例では、ＴＥＯＳを原料ガスとしたボトムアップフィルの例を示したが、ＯＭＣＴＳ（Ｏｃｔｏｍｅｔｈｙｌ ｃｙｃｌｏｔｅｔｒａｓｉｌｏｘａｎｅ）、ＢＴＢＡＳ（Ｂｉｓ（Ｔｅｒｔｉａｒｙ ｂｕｔｙｌ ａｍｉｎｏ）ｓｉｌａｎｅ）、ＨＭＤＳＯ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌｏｘａｎｅ）、ＭＨＤＳＡ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌａｚａｎｅ）、ＨＭＣＴＳＮ（Ｈｅｘａｍｅｔｈｙｌ ｃｙｃｌｏｔｒｉｓｉｌａｚａｎｅ）等を用いてもボトムアップフィルの絶縁膜堆積が可能である。また、真空紫外光の光源としては、Ｘｅ２のエキシマランプ、水銀ランプ、ＸｅＣｌ、ＫｒＦ、ＡｒＦのエキシマレーザ、Ｆ２、Ａｒ２のレーザなどを用いてもよいが、ランプの寿命などを考えると、Ｘｅ２のエキシマランプを用いるのが実用的である。
This method of selectively depositing on the bottom of a trench or a hole is called bottom-up fill. In the above example, an example of bottom-up fill using TEOS as a raw material gas has been shown. The bottom-up fill insulating film can be deposited using HMCTSN (Hexamethyl cyclotrisilazane) or the like. Further, as a vacuum ultraviolet light source, an Xe2 excimer lamp, a mercury lamp, XeCl, KrF, ArF excimer lasers, F2, Ar2 lasers, etc. may be used. It is practical to use an excimer lamp.
選択的にトレンチの底面に堆積する絶縁膜６ｂ厚さは５０ないし１００ｎｍである。光ＣＶＤ法は、化学気相成長法による膜堆積なので、トレンチの底面の膜厚は、原料ガスの濃度、全圧、プロセス時間を制御することで、５ｎｍ以下の精度での堆積膜厚制御は十分に可能である。また、絶縁膜６ｂの主成分は珪素、酸素、窒素、水素である。一般に、酸化珪素の耐圧は他の固体酸化物の耐圧に比べて高いことが知られており、絶縁膜６ｂは酸化珪素に加え、原料ガスに含まれる窒素、炭素、水素を主成分とするのが望ましい。
The thickness of the insulating film 6b selectively deposited on the bottom surface of the trench is 50 to 100 nm. Since the photo-CVD method is film deposition by chemical vapor deposition, the film thickness at the bottom of the trench can be controlled with a precision of 5 nm or less by controlling the concentration of the source gas, the total pressure, and the process time. It is possible enough. The main components of the insulating film 6b are silicon, oxygen, nitrogen, and hydrogen. In general, it is known that the breakdown voltage of silicon oxide is higher than that of other solid oxides, and the insulating film 6b is mainly composed of nitrogen, carbon, and hydrogen contained in a source gas in addition to silicon oxide. Is desirable.
以上のような絶縁膜形成方法により、トレンチ側面のゲート絶縁膜の厚さに対しトレンチ底面の絶縁膜を厚くすることが可能になる。具体的には、トレンチ底面のゲート絶縁膜の膜厚は、トレンチ側面のゲート絶縁膜の膜厚よりも５０ｎｍ以上厚くすることができる。さらに望ましくは、１００ｎｍ以上厚くすることができる。本手法では、トレンチの側面のゲート絶縁膜の厚さとトレンチ底面の絶縁膜の厚さを独立して制御することができるので、トレンチ側面のゲート絶縁膜は一様な電界に対して信頼性が確保できる程度に薄くし、トレンチ底面のゲート絶縁膜は集中電界を緩和するのに必要なだけ厚くすることができる。したがって、反転層の電子濃度を高く保ちつつ、すなわちチャネルのオン抵抗を小さく保ちつつ、絶縁耐性の高いトレンチ型ＳｉＣ－ＭＯＳＦＥＴが実現できる。特に光ＣＶＤによるボトムアップフィルの絶縁膜に関しては、チャネルの移動度などに悪影響を及ぼす不純物元素や正負の電荷が含まれていてもかまわない。なぜなら、チャネル底部の絶縁膜は絶縁耐性を高めるために必要な絶縁膜であり、トレンチ型ＳｉＣ－ＭＯＳＦＥＴのチャネル抵抗には影響を及ぼさないためである。実際に、同じＴＥＯＳを原料ガスとして堆積される絶縁膜でも光ＣＶＤで堆積されるＳｉＯは熱ＣＶＤで堆積されるＳｉＯよりも密度が低い。ただし、熱処理後には６ＭＶ／ｃｍ以上の絶縁破壊耐性を持つことが実験的に確かめられている。
By the insulating film forming method as described above, the insulating film on the bottom surface of the trench can be made thicker than the thickness of the gate insulating film on the side surface of the trench. Specifically, the thickness of the gate insulating film on the bottom surface of the trench can be made 50 nm or more thicker than the thickness of the gate insulating film on the side surface of the trench. More desirably, the thickness can be increased to 100 nm or more. In this method, since the thickness of the gate insulating film on the side surface of the trench and the thickness of the insulating film on the bottom surface of the trench can be controlled independently, the gate insulating film on the side surface of the trench is reliable against a uniform electric field. The gate insulating film on the bottom of the trench can be made as thick as necessary to alleviate the concentrated electric field. Therefore, a trench type SiC-MOSFET with high insulation resistance can be realized while keeping the electron concentration of the inversion layer high, that is, keeping the channel on-resistance small. In particular, the bottom-up fill insulating film formed by photo-CVD may contain impurity elements and positive and negative charges that adversely affect channel mobility and the like. This is because the insulating film at the bottom of the channel is an insulating film necessary for enhancing the insulation resistance and does not affect the channel resistance of the trench type SiC-MOSFET. Actually, even in an insulating film deposited using the same TEOS as a source gas, SiO deposited by photo-CVD has a lower density than SiO deposited by thermal CVD. However, it has been experimentally confirmed that it has a dielectric breakdown resistance of 6 MV / cm or more after the heat treatment.
次に、図１のトレンチ型ＳｉＣ－ＭＯＳＦＥＴを製造する方法を図２～図１１を用いて示す。まず、ｎ型の六方晶系ＳｉＣ基板の（０００１）Ｓｉ面を表面とし、基板の裏面に高濃度のリン（Ｐ）あるいは砒素（Ａｓ）をイオン注入により導入し、表面側にｐ型のＳｉＣのベース層３をエピタキシャル成長させる（図２）。次に、パターニングとイオン注入と１７００度程度の熱処理により、ｐ型のエピタキシャル層３の表面に高濃度のｎ型領域５および高濃度のｐ型領域４を形成する（図３）。トレンチを形成するためのハードマスクとして、絶縁膜８を堆積し、トレンチの形成するためのリソグラフィーを行い、所望の位置にのみレジスト４１を残す（図４）。このレジスト４１を用いて、絶縁膜８とＳｉＣをエッチングし、形成されたトレンチの底面をドリフト層２内に存在させ、アッシングによりレジスト４１を除去する（図５）。エッチングによる損傷層を除去するため、ＳｉＣトレンチの表面を酸化し、表面酸化膜を希フッ酸などで除去する。次にＳｉＣの表面を１０００度ないし１３００度の温度で酸化又は酸窒化する。このときに形成する酸化膜６ａ又は酸窒化膜６ａは１０ｎｍ以下、望ましくは５ｎｍがよい（図６）。
Next, a method for manufacturing the trench type SiC-MOSFET of FIG. 1 will be described with reference to FIGS. First, the (0001) Si surface of an n-type hexagonal SiC substrate is used as the front surface, and high-concentration phosphorus (P) or arsenic (As) is introduced into the back surface of the substrate by ion implantation. The base layer 3 is epitaxially grown (FIG. 2). Next, a high-concentration n-type region 5 and a high-concentration p-type region 4 are formed on the surface of the p-type epitaxial layer 3 by patterning, ion implantation, and heat treatment at about 1700 degrees (FIG. 3). As a hard mask for forming the trench, an insulating film 8 is deposited, and lithography for forming the trench is performed to leave the resist 41 only at a desired position (FIG. 4). Using this resist 41, the insulating film 8 and SiC are etched, the bottom surface of the formed trench is present in the drift layer 2, and the resist 41 is removed by ashing (FIG. 5). In order to remove the damaged layer by etching, the surface of the SiC trench is oxidized, and the surface oxide film is removed with dilute hydrofluoric acid or the like. Next, the surface of SiC is oxidized or oxynitrided at a temperature of 1000 to 1300 degrees. The oxide film 6a or oxynitride film 6a formed at this time is 10 nm or less, preferably 5 nm (FIG. 6).
次に、光ＣＶＤにより絶縁膜６ｂを堆積する（図７）。この光ＣＶＤにおいては、原料ガスと照射する光の波長を適切に選択し、基板温度、原料ガス供給時間などの条件を制御することで、トレンチや穴の底に対して選択的に所望の膜を堆積することが可能である。すなわち、トレンチの側面には膜を堆積することなく、トレンチの底面に膜を堆積することが可能である。たとえば、ＣＶＤ反応室に図６のようなトレンチが形成されたＳｉＣ基板を配備し、原料ガスのＴＥＯＳを導入し、１７２ｎｍの波長の光を照射すると、トレンチの底に選択的にＳｉＯ膜が堆積する。この膜の堆積速度は、導入する原料ガスの濃度や圧力などで制御できる。トレンチの底に選択的に膜を堆積する方法としては、ＳＯＧ（Ｓｐｉｎ ｏｎ Ｇｌａｓｓ）と呼ばれる塗布膜を利用することも考えられる。ただし、１００ｎｍ程度あるいはそれ以下の厚さの塗布膜を制御性良く塗布するのは困難である。さらに、塗布で形成される絶縁膜は光ＣＶＤで形成される絶縁膜比べて、残留不純物が多い。そのため、その後の熱処理において、膜が収縮し、不純物を多く放出し、すでに形成した絶縁膜６ａの表面に不純物を導入する原因となり好ましくない。したがって、光ＣＶＤによって底面にのみ厚い絶縁膜を堆積する必要がある。
Next, an insulating film 6b is deposited by photo-CVD (FIG. 7). In this photo-CVD, the source gas and the wavelength of light to be irradiated are appropriately selected, and conditions such as the substrate temperature and the source gas supply time are controlled, so that a desired film can be selectively applied to the bottom of the trench or hole. Can be deposited. That is, it is possible to deposit a film on the bottom surface of the trench without depositing a film on the side surface of the trench. For example, when a SiC substrate having a trench as shown in FIG. 6 is installed in a CVD reaction chamber, a source gas TEOS is introduced, and light having a wavelength of 172 nm is irradiated, a SiO film is selectively deposited on the bottom of the trench. To do. The deposition rate of this film can be controlled by the concentration or pressure of the introduced source gas. As a method for selectively depositing a film on the bottom of the trench, it is conceivable to use a coating film called SOG (Spin on Glass). However, it is difficult to apply a coating film having a thickness of about 100 nm or less with good controllability. Further, the insulating film formed by coating has more residual impurities than the insulating film formed by photo-CVD. Therefore, in the subsequent heat treatment, the film shrinks and releases a large amount of impurities, which is not preferable because it introduces impurities into the surface of the already formed insulating film 6a. Therefore, it is necessary to deposit a thick insulating film only on the bottom surface by photo-CVD.
光ＣＶＤによりトレンチの底に選択的に絶縁膜を堆積したのちに、熱エネルギーを利用した化学気相成長（熱ＣＶＤ）により、絶縁膜６ｃを堆積する（図８）。このとき、基板の温度を８００度に保ち、原料ガスをシラン（ＳｉＨ４）と一酸化に窒素（Ｎ２Ｏ）を導入して、酸化シリコン膜を３０ｎｍないし１００ｎｍ堆積させる。光ＣＶＤで堆積した膜には、カーボンなどの不純物が含まれており、通常、その後の熱処理により、内包する不純物などを除去し、膜を焼き締める必要があるが、熱ＣＶＤの間に、不純物が除去され、絶縁膜６ｂが焼き締められる。なお、熱ＣＶＤの代わりにプラズマＣＶＤで絶縁膜６ｃを形成することも考えられるが、プラズマＣＶＤは熱ＣＶＤに比べ、膜の均一性が悪いので熱ＣＶＤで絶縁膜６ｃを形成し、トレンチ側面の絶縁膜の膜厚の均一性を確保する必要がある。
After an insulating film is selectively deposited on the bottom of the trench by photo-CVD, an insulating film 6c is deposited by chemical vapor deposition (thermal CVD) using thermal energy (FIG. 8). At this time, the temperature of the substrate is kept at 800 ° C., the source gas is silane (SiH 4 ) and nitrogen (N 2 O) is introduced into the monoxide to deposit a silicon oxide film of 30 nm to 100 nm. Films deposited by photo-CVD contain impurities such as carbon, and it is usually necessary to remove the encapsulated impurities and bake the film by subsequent heat treatment. Is removed, and the insulating film 6b is baked. Although it is conceivable that the insulating film 6c is formed by plasma CVD instead of thermal CVD, since the uniformity of the film is poorer than that by thermal CVD, the insulating film 6c is formed by thermal CVD and the trench side surface is formed. It is necessary to ensure the uniformity of the thickness of the insulating film.
次に、ＣＶＤ法により多結晶シリコン７と必要に応じて絶縁膜９１を堆積する（図９）。リソグラフィーとエッチングにより、ゲート電極７のパターニングを行い、ゲート電極７を形成する（図１０）。この後、ゲート電極７表面に絶縁分離用の層間絶縁膜１１を堆積する（図１１）。
Next, a polycrystalline silicon 7 and an insulating film 91 are deposited if necessary by the CVD method (FIG. 9). The gate electrode 7 is patterned by lithography and etching to form the gate electrode 7 (FIG. 10). Thereafter, an insulating interlayer 11 is deposited on the surface of the gate electrode 7 (FIG. 11).
そして、リソグラフィーとエッチングにより、層間絶縁膜１１、ゲート絶縁膜６ａ、６ｃ、絶縁膜８を加工し、ｐ＋コンタクト領域４及びｎ＋ソース領域５が表出するコンタクトホールを形成し、シリサイド反応によりソース電極９を形成する（図示せず）。層間絶縁膜１１に対し別のパターンでリソグラフィーとエッチングを行い、ゲートのためのコンタクトホールを形成し、ｎ＋基板１の裏面にドレイン電極１０を形成する（図示せず）。
Then, the interlayer insulating film 11, the gate insulating films 6a and 6c, and the insulating film 8 are processed by lithography and etching to form contact holes in which the p + contact region 4 and the n + source region 5 are exposed. A source electrode 9 is formed (not shown). Lithography and etching are performed on the interlayer insulating film 11 in a different pattern to form a contact hole for the gate, and a drain electrode 10 is formed on the back surface of the n + substrate 1 (not shown).
以上のように、トレンチ内に光ＣＶＤにより形成された絶縁膜を用いることで、トレンチ底面のゲート絶縁膜を側面より厚く形成できるので、オン抵抗の低減と高耐圧を実現するトレンチ型ＳｉＣ半導体装置を製造することができる。また、この光ＣＶＤにより形成された絶縁膜を形成した後の工程で、当該絶縁膜をエッチバックしていないので、エッチバックの際に生じるトレンチ側壁の損傷も生じることがない。
As described above, since the gate insulating film on the bottom of the trench can be formed thicker than the side surface by using the insulating film formed by photo-CVD in the trench, the trench type SiC semiconductor device that realizes a reduction in on-resistance and a high breakdown voltage. Can be manufactured. In addition, since the insulating film is not etched back in the process after the insulating film formed by the photo-CVD is formed, the trench side wall that occurs during the etch back is not damaged.
実施例１では、ゲート絶縁膜は酸化膜あるいは酸窒化膜６ａ、光ＣＶＤにより堆積した絶縁膜６ｂ、熱ＣＶＤにより堆積した絶縁膜６ｃの順に積層した絶縁膜であったが、実施例２では別の形態について説明する。
In the first embodiment, the gate insulating film is an insulating film in which an oxide film or oxynitride film 6a, an insulating film 6b deposited by photo-CVD, and an insulating film 6c deposited by thermal CVD are stacked in this order. Will be described.
別の形態として、図１２に図示するように、酸化膜又は酸窒化膜６ａ、熱ＣＶＤによる堆積した絶縁膜６ｃ、光ＣＶＤにより堆積した絶縁膜６ｂの順に積層したりすることもできる。重要なのは、光ＣＶＤにより堆積した絶縁膜６ｂと、酸化膜又は酸窒化膜６ａと、熱ＣＶＤにより堆積した絶縁膜６ｃとを適宜組み合わせることにより、トレンチの側面のゲート絶縁膜に対し、トレンチの底面のゲート絶縁膜が厚くなるようにトレンチ型ＳｉＣ－ＭＯＳＦＥＴを製造することである。
As another form, as shown in FIG. 12, an oxide film or oxynitride film 6a, an insulating film 6c deposited by thermal CVD, and an insulating film 6b deposited by photo-CVD can be laminated in this order. What is important is that the insulating film 6b deposited by photo-CVD, the oxide film or oxynitride film 6a, and the insulating film 6c deposited by thermal CVD are appropriately combined, so that the bottom surface of the trench is made to the gate insulating film on the side surface of the trench. The trench type SiC-MOSFET is manufactured so that the gate insulating film becomes thicker.
製造方法において、図２～１１と違うのは、ゲート絶縁膜の形成方法である。すなわち図１２では、まず、酸化又は酸窒化による絶縁膜６ａを形成し、その後、熱ＣＶＤにより絶縁膜６ｃを堆積し、光ＣＶＤにより絶縁膜６ｂを堆積させる。絶縁膜６ｂを堆積後には、４００度以上の酸化雰囲気での熱処理を施したのちに、ゲート電極７を堆積する。
In the manufacturing method, the difference from FIGS. 2 to 11 is the method of forming the gate insulating film. That is, in FIG. 12, first, the insulating film 6a is formed by oxidation or oxynitridation, and then the insulating film 6c is deposited by thermal CVD, and the insulating film 6b is deposited by optical CVD. After the insulating film 6b is deposited, the gate electrode 7 is deposited after heat treatment in an oxidizing atmosphere of 400 ° C. or more.
また、別の形態として、図１３に図示するように、酸化膜又は酸窒化膜６ａの代わりに熱ＣＶＤにより堆積した絶縁膜６ｂを、光ＣＶＤにより堆積した絶縁膜６ｂの上下に積層したりしてもよい。重要なのは、光ＣＶＤにより堆積した絶縁膜６ｂと熱ＣＶＤにより堆積した絶縁膜６ｃを適宜組み合わせることにより、トレンチの側面のゲート絶縁膜に対し、トレンチの底面のゲート絶縁膜が厚くなるようにトレンチ型ＳｉＣ－ＭＯＳＦＥＴを製造することである。
As another form, as shown in FIG. 13, insulating films 6b deposited by thermal CVD instead of the oxide film or oxynitride film 6a may be stacked on and under the insulating film 6b deposited by photo-CVD. May be. What is important is that the insulating film 6b deposited by optical CVD and the insulating film 6c deposited by thermal CVD are appropriately combined so that the gate insulating film on the bottom surface of the trench becomes thicker than the gate insulating film on the side surface of the trench. It is to manufacture a SiC-MOSFET.
なお、熱ＣＶＤの中には、二種類以上の原料ガスを交互に供給して、原子層毎に膜を堆積させる原子層堆積法を含んでもよい。高い耐圧を維持しつつ、閾値電圧を制御するために金属酸化物からなる絶縁膜を原子層堆積法により堆積してもよい。
Note that thermal CVD may include an atomic layer deposition method in which two or more source gases are alternately supplied to deposit a film for each atomic layer. In order to control the threshold voltage while maintaining a high breakdown voltage, an insulating film made of a metal oxide may be deposited by an atomic layer deposition method.
製造方法において、図２～１１と違うのは、ゲート絶縁膜の形成方法である。すなわち図１３では、図６における酸化又は酸窒化による絶縁膜６ａを熱ＣＶＤにより形成される絶縁膜６ｃで置き換えればよい。
In the manufacturing method, the difference from FIGS. 2 to 11 is the method of forming the gate insulating film. That is, in FIG. 13, the insulating film 6a formed by oxidation or oxynitriding in FIG. 6 may be replaced with an insulating film 6c formed by thermal CVD.
また、図示はしないが、熱酸化膜６ａを形成し、熱ＣＶＤ膜６ｃを堆積し、次に光ＣＶＤ膜６ｂを堆積し、さらに別の熱ＣＶＤ膜６ｃ２を堆積するなどして４層の絶縁膜構造としてもよい。
Although not shown, four layers of insulation are formed by forming a thermal oxide film 6a, depositing a thermal CVD film 6c, then depositing a photo-CVD film 6b, and further depositing another thermal CVD film 6c2. A film structure may be used.
以上のような絶縁膜形成方法により、実施例１と同様に、トレンチ側面のゲート絶縁膜の厚さに対しトレンチ底面の絶縁膜を厚くすることが可能になる。具体的には、トレンチ底面のゲート絶縁膜の膜厚は、トレンチ側面のゲート絶縁膜の膜厚よりも５０ｎｍ以上厚くすることができる。さらに望ましくは、１００ｎｍ以上厚くすることができる。本手法では、トレンチの側面のゲート絶縁膜の厚さとトレンチ底面の絶縁膜の厚さを独立して制御することができるので、トレンチ側面のゲート絶縁膜は一様な電界に対して信頼性が確保できる程度に薄くし、トレンチ底面のゲート絶縁膜は集中電界を緩和するのに必要なだけ厚くすることができる。したがって、反転層の電子濃度を高く保ちつつ、すなわちチャネルのオン抵抗を小さく保ちつつ、絶縁耐性の高いトレンチ型ＳｉＣ－ＭＯＳＦＥＴが実現できる。また、この光ＣＶＤにより形成された絶縁膜を形成した後の工程で、当該絶縁膜をエッチバックしていないので、エッチバックの際に生じるトレンチ側壁の損傷も生じることがない。
By the insulating film forming method as described above, the insulating film on the bottom surface of the trench can be made thicker than the gate insulating film on the side surface of the trench as in the first embodiment. Specifically, the thickness of the gate insulating film on the bottom surface of the trench can be made 50 nm or more thicker than the thickness of the gate insulating film on the side surface of the trench. More desirably, the thickness can be increased to 100 nm or more. In this method, since the thickness of the gate insulating film on the side surface of the trench and the thickness of the insulating film on the bottom surface of the trench can be controlled independently, the gate insulating film on the side surface of the trench is reliable against a uniform electric field. The gate insulating film on the bottom of the trench can be made as thick as necessary to alleviate the concentrated electric field. Therefore, a trench type SiC-MOSFET with high insulation resistance can be realized while keeping the electron concentration of the inversion layer high, that is, keeping the channel on-resistance small. In addition, since the insulating film is not etched back in the process after the insulating film formed by the photo-CVD is formed, the trench side wall that occurs during the etch back is not damaged.
以上、実施例１及び２について説明した。これらから分かるように、本願発明で重要なことは、トレンチ内のゲート絶縁膜の一部をボトムアップフィルによって形成すること、すなわち、光ＣＶＤによる堆積膜６ｂによって形成することである。
In the above, Example 1 and 2 were demonstrated. As can be seen from the above, what is important in the present invention is that a part of the gate insulating film in the trench is formed by bottom-up fill, that is, formed by the deposited film 6b by photo-CVD.
１：ｎ＋型ドレイン、
２：ｎ－型ドリフト層、
３：ｐ型ベース領域、
４：ｐ＋型コンタクト領域、
５：ｎ＋型ソース領域、
６：ゲート絶縁膜、
６ａ：酸化あるいは酸窒化で形成するゲート絶縁膜
６ｂ：光ＣＶＤで堆積するゲート絶縁膜
６ｃ：熱ＣＶＤで堆積するゲート絶縁膜
７：ゲート電極、
８：層間絶縁膜、
９：ソース電極、
１０：ドレイン電極
１１：層間絶縁膜
４１：トレンチ加工用のレジストパターン
９１：絶縁膜 1: n + type drain,
2: n − type drift layer,
3: p-type base region,
4: p + type contact region,
5: n + type source region,
6: Gate insulating film,
6a:gate insulating film 6b formed by oxidation or oxynitridation: gate insulating film 6c deposited by photo-CVD: gate insulating film 7 deposited by thermal CVD: gate electrode,
8: Interlayer insulating film,
9: source electrode,
10: drain electrode 11: interlayer insulating film 41: resistpattern 91 for trench processing: insulating film
２：ｎ－型ドリフト層、
３：ｐ型ベース領域、
４：ｐ＋型コンタクト領域、
５：ｎ＋型ソース領域、
６：ゲート絶縁膜、
６ａ：酸化あるいは酸窒化で形成するゲート絶縁膜
６ｂ：光ＣＶＤで堆積するゲート絶縁膜
６ｃ：熱ＣＶＤで堆積するゲート絶縁膜
７：ゲート電極、
８：層間絶縁膜、
９：ソース電極、
１０：ドレイン電極
１１：層間絶縁膜
４１：トレンチ加工用のレジストパターン
９１：絶縁膜 1: n + type drain,
2: n − type drift layer,
3: p-type base region,
4: p + type contact region,
5: n + type source region,
6: Gate insulating film,
6a:
8: Interlayer insulating film,
9: source electrode,
10: drain electrode 11: interlayer insulating film 41: resist
Claims (19)
- ＳｉＣ基板に対し、トレンチを形成する工程と、
前記トレンチの底に絶縁膜を光ＣＶＤで形成する工程と、
前記絶縁膜の上方にゲート電極を形成する工程とを備えることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 Forming a trench in the SiC substrate;
Forming an insulating film at the bottom of the trench by photo-CVD;
Forming a gate electrode above the insulating film. A method of manufacturing a trench type SiC semiconductor device. - 請求項１において、
前記光ＣＶＤの原料ガスは、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌ ｏｒｔｈｏｓｉｌｉｃａｔｅ）、ＯＭＣＴＳ（Ｏｃｔｏｍｅｔｈｙｌ ｃｙｃｌｏｔｅｔｒａｓｉｌｏｘａｎｅ）、ＢＴＢＡＳ（Ｂｉｓ（Ｔｅｒｔｉａｒｙ ｂｕｔｙｌ ａｍｉｎｏ）ｓｉｌａｎｅ）、ＨＭＤＳＯ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌｏｘａｎｅ）、ＭＨＤＳＡ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌａｚａｎｅ）、若しくは、ＨＭＣＴＳＮ（Ｈｅｘａｍｅｔｈｙｌ ｃｙｃｌｏｔｒｉｓｉｌａｚａｎｅ）のいずれかであることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 1,
Raw material gas in the light CVD is, TEOS (Tetraethyl orthosilicate), OMCTS (Octomethyl cyclotetrasiloxane), BTBAS (Bis (Tertiary butyl amino) silane), HMDSO (Hexamethyl disiloxane), MHDSA (Hexamethyl disilazane), or, HMCTSN (Hexamethyl cyclotrisilazane) A method of manufacturing a trench type SiC semiconductor device, wherein - 請求項１において、
前記光ＣＶＤでは、真空紫外光を用いることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 1,
In the photo-CVD, vacuum ultraviolet light is used. A method for manufacturing a trench type SiC semiconductor device. - 請求項１において、
前記絶縁膜を形成する工程の後の工程で、前記絶縁膜は、前記トレンチ内においてエッチバックされないことを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 1,
A method of manufacturing a trench type SiC semiconductor device, wherein the insulating film is not etched back in the trench in a step subsequent to the step of forming the insulating film. - 請求項１において、
前記ゲート電極のゲート絶縁膜が前記トレンチの側面及び底面に形成され、前記ゲート絶縁膜は前記絶縁膜を含み、
前記トレンチの底面のゲート絶縁膜の膜厚は、前記トレンチの側面のゲート絶縁膜の膜厚よりも５０ｎｍ以上厚いことを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 1,
A gate insulating film of the gate electrode is formed on a side surface and a bottom surface of the trench, and the gate insulating film includes the insulating film;
The trench type SiC semiconductor device manufacturing method, wherein the thickness of the gate insulating film on the bottom surface of the trench is 50 nm or more thicker than the thickness of the gate insulating film on the side surface of the trench. - 請求項１において、
前記ＳｉＣ基板にはＭＯＳＦＥＴのｎ型ドレイン層と前記ｎ型ドレイン層とｐｎ接合するｐ型ベース領域とが設けられ、
前記ゲート電極の下端は前記ｐｎ接合よりも前記ＳｉＣ基板の裏面側に位置することを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 1,
The SiC substrate is provided with an n-type drain layer of a MOSFET and a p-type base region that pn-joins with the n-type drain layer,
A method of manufacturing a trench type SiC semiconductor device, wherein a lower end of the gate electrode is located on a back side of the SiC substrate with respect to the pn junction. - 請求項１において、
前記絶縁膜を形成する工程は、真空紫外光を照射するランプを備えたＣＶＤ装置に前記トレンチを形成したＳｉＣ基板を導入し、前記ＣＶＤ装置に所定の原料ガスを導入することで前記絶縁膜を形成する工程であることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 1,
In the step of forming the insulating film, the SiC substrate in which the trench is formed is introduced into a CVD apparatus provided with a lamp that irradiates vacuum ultraviolet light, and the insulating film is formed by introducing a predetermined source gas into the CVD apparatus. A method of manufacturing a trench type SiC semiconductor device, characterized by being a forming step. - ＳｉＣ基板に対し、トレンチを形成する工程と、
前記トレンチの側面及び底面に、酸化又は酸窒化、若しくは、熱ＣＶＤにより第一絶縁膜を形成する工程と、
前記トレンチの底面に光ＣＶＤにより第二絶縁膜を形成する工程と、
前記第一および第二絶縁膜の上方にゲート電極を形成する工程とを備えることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 Forming a trench in the SiC substrate;
Forming a first insulating film on the side and bottom surfaces of the trench by oxidation, oxynitridation, or thermal CVD;
Forming a second insulating film on the bottom surface of the trench by photo-CVD,
Forming a gate electrode above the first and second insulating films. A method of manufacturing a trench type SiC semiconductor device. - 請求項８において、
前記光ＣＶＤの原料ガスは、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌ ｏｒｔｈｏｓｉｌｉｃａｔｅ）、ＯＭＣＴＳ（Ｏｃｔｏｍｅｔｈｙｌ ｃｙｃｌｏｔｅｔｒａｓｉｌｏｘａｎｅ）、ＢＴＢＡＳ（Ｂｉｓ（Ｔｅｒｔｉａｒｙ ｂｕｔｙｌ ａｍｉｎｏ）ｓｉｌａｎｅ）、ＨＭＤＳＯ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌｏｘａｎｅ）、Ｍ
ＨＤＳＡ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌａｚａｎｅ）、若しくは、ＨＭＣＴＳＮ（Ｈｅｘａｍｅｔｈｙｌ ｃｙｃｌｏｔｒｉｓｉｌａｚａｎｅ）のいずれかであることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 8,
The source gases for the photo-CVD are TEOS (Tetraethyl orthosilicate), OMCTS (Octomoethyl cyclotetrasiloxane), BTBAS (Bis (Tertiary Butylamino) silane), HMDSO (Hexamethyldisiloxane), HMDSO (Hexamethyldisiloxane).
A method for manufacturing a trench type SiC semiconductor device, which is either HDSA (Hexamethyl disilazane) or HMCTSN (Hexamethyl cyclotrisilazane). - 請求項８において、
前記光ＣＶＤでは、真空紫外光を用いることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 8,
In the photo-CVD, vacuum ultraviolet light is used. A method for manufacturing a trench type SiC semiconductor device. - 請求項８において、
前記第一および第二絶縁膜を形成する工程の後の工程で、前記第一および第二絶縁膜は、前記トレンチ内においてエッチバックされないことを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 8,
A method of manufacturing a trench SiC semiconductor device, wherein the first and second insulating films are not etched back in the trench in a step subsequent to the step of forming the first and second insulating films. - 請求項８において、
前記ゲート電極のゲート絶縁膜が前記トレンチの側面及び底面に形成され、前記ゲート絶縁膜は前記第一および第二絶縁膜を含み、
前記トレンチの底面のゲート絶縁膜の膜厚は、前記トレンチの側面のゲート絶縁膜の膜厚よりも５０ｎｍ以上厚いことを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 8,
A gate insulating film of the gate electrode is formed on a side surface and a bottom surface of the trench, and the gate insulating film includes the first and second insulating films;
The trench type SiC semiconductor device manufacturing method, wherein the thickness of the gate insulating film on the bottom surface of the trench is 50 nm or more thicker than the thickness of the gate insulating film on the side surface of the trench. - 請求項８において、
前記ＳｉＣ基板にはＭＯＳＦＥＴのｎ型ドレイン層と前記ｎ型ドレイン層とｐｎ接合するｐ型ベース領域とが設けられ、
前記ゲート電極の下端は前記ｐｎ接合よりも前記ＳｉＣ基板の裏面側に位置することを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 8,
The SiC substrate is provided with an n-type drain layer of a MOSFET and a p-type base region that pn-joins with the n-type drain layer,
A method of manufacturing a trench type SiC semiconductor device, wherein a lower end of the gate electrode is positioned on a back side of the SiC substrate with respect to the pn junction. - 請求項８において、
前記第二絶縁膜を形成する工程は、真空紫外光を照射するランプを備えたＣＶＤ装置に前記トレンチを形成したＳｉＣ基板を導入し、前記ＣＶＤ装置に所定の原料ガスを導入することで前記絶縁膜を形成する工程であることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 8,
The step of forming the second insulating film includes introducing the SiC substrate having the trench into a CVD apparatus equipped with a lamp that irradiates vacuum ultraviolet light, and introducing the predetermined source gas into the CVD apparatus. A method of manufacturing a trench type SiC semiconductor device, characterized by being a step of forming a film. - ＳｉＣ基板に対し、トレンチを形成する工程と、
前記トレンチの側面及び底面に、酸化又は酸窒化により第一絶縁膜を形成する工程と、
前記トレンチの底面であって、前記第一絶縁膜の上方に、光ＣＶＤにより第二絶縁膜を形成する工程と、
前記トレンチの側面及び底面であって、前記第二絶縁膜の上方に、熱ＣＶＤにより第三の絶縁膜を形成する工程と、
前記第三絶縁膜の上方にゲート電極を形成する工程とを備えることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 Forming a trench in the SiC substrate;
Forming a first insulating film on the side and bottom surfaces of the trench by oxidation or oxynitriding;
Forming a second insulating film by photo-CVD at the bottom of the trench and above the first insulating film;
Forming a third insulating film by thermal CVD on the side and bottom surfaces of the trench and above the second insulating film;
Forming a gate electrode above the third insulating film. A method of manufacturing a trench type SiC semiconductor device. - 請求項１５において、
前記光ＣＶＤの原料ガスは、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌ ｏｒｔｈｏｓｉｌｉｃａｔｅ）、ＯＭＣＴＳ（Ｏｃｔｏｍｅｔｈｙｌ ｃｙｃｌｏｔｅｔｒａｓｉｌｏｘａｎｅ）、ＢＴＢＡＳ（Ｂｉｓ（Ｔｅｒｔｉａｒｙ ｂｕｔｙｌ ａｍｉｎｏ）ｓｉｌａｎｅ）、ＨＭＤＳＯ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌｏｘａｎｅ）、ＭＨＤＳＡ（Ｈｅｘａｍｅｔｈｙｌ ｄｉｓｉｌａｚａｎｅ）、若しくは、ＨＭＣＴＳＮ（Ｈｅｘａｍｅｔｈｙｌ ｃｙｃｌｏｔｒｉｓｉｌａｚａｎｅ）のいずれかであることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 15,
Raw material gas in the light CVD is, TEOS (Tetraethyl orthosilicate), OMCTS (Octomethyl cyclotetrasiloxane), BTBAS (Bis (Tertiary butyl amino) silane), HMDSO (Hexamethyl disiloxane), MHDSA (Hexamethyl disilazane), or, HMCTSN (Hexamethyl cyclotrisilazane) A method of manufacturing a trench type SiC semiconductor device, wherein - 請求項１５において、
前記光ＣＶＤでは、真空紫外光を用いることを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 15,
In the photo-CVD, vacuum ultraviolet light is used. A method for manufacturing a trench type SiC semiconductor device. - 請求項１５において、
前記第一絶縁膜、前記第二絶縁膜及び前記第三絶縁膜を形成する工程の後の工程で、前記第一絶縁膜、前記第二絶縁膜及び前記第三絶縁膜は、前記トレンチ内においてエッチバックされないことを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 15,
In a step after the step of forming the first insulating film, the second insulating film, and the third insulating film, the first insulating film, the second insulating film, and the third insulating film are formed in the trench. A method of manufacturing a trench type SiC semiconductor device, wherein the trench type SiC semiconductor device is not etched back. - 請求項１５において、
前記ゲート電極のゲート絶縁膜が前記トレンチの側面及び底面に形成され、前記ゲート絶縁膜は前記第一絶縁膜、前記第二絶縁膜及び前記第三絶縁膜を含み、
前記トレンチの底面のゲート絶縁膜の膜厚は、前記トレンチの側面のゲート絶縁膜の膜厚よりも５０ｎｍ以上厚いことを特徴とするトレンチ型ＳｉＣ半導体装置の製造方法。 In claim 15,
A gate insulating film of the gate electrode is formed on a side surface and a bottom surface of the trench, and the gate insulating film includes the first insulating film, the second insulating film, and the third insulating film;
The trench type SiC semiconductor device manufacturing method, wherein the thickness of the gate insulating film on the bottom surface of the trench is 50 nm or more thicker than the thickness of the gate insulating film on the side surface of the trench.
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| JP2016143788A (en) * | 2015-02-03 | 2016-08-08 | 住友電気工業株式会社 | Manufacturing method of silicon carbide semiconductor device |
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