KR100539159B1 - Transistor in a semiconductor device and a method of manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, wherein the gate insulating film is formed into a laminated structure of a nitride-based insulating film and a high dielectric insulating film containing hafnium or zirconium, thereby further reducing the electrical thickness of the gate oxide film. The leakage current through the gate insulating film can be reduced, and in the case of the nMOS transistor, the reliability of the device is prevented from being degraded by the hot carrier flowing into the gate oxide film.In the case of the pMOS transistor, impurities injected into the gate are transferred to the channel region. Disclosed are a transistor of a semiconductor device and a method of manufacturing the same that can prevent diffusion.

Description

Transistor in a semiconductor device and a method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, and more particularly to a transistor of a semiconductor device and a method of manufacturing the same for reducing the electrical thickness of the gate insulating film and preventing leakage current through the gate insulating film.

In general, a transistor of a semiconductor device includes a gate electrode and a source / drain formed on a semiconductor substrate at both edges of the gate electrode, and a gate oxide film is formed between the gate electrode and the semiconductor substrate.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to the prior art.

Referring to FIG. 1A, an nMOS region is formed by an ion implantation process after forming an isolation layer 102 in an isolation region of a semiconductor substrate 101 in which an nMOS region in which an nMOS transistor is to be formed and a pMOS region in which a pMOS transistor is to be formed are defined, respectively. The p well 103a is formed in the semiconductor substrate 101 of the semiconductor substrate 101, and the n well 103b is formed in the semiconductor substrate 101 of the pMOS region, respectively. On the other hand, the p well 103a and the n well 103b are each subjected to an ion implantation process for adjusting the threshold voltage of the transistor to be formed in a subsequent process.

Referring to FIG. 1B, after removing the natural oxide film or the remaining oxide film formed on the semiconductor substrate 101 with a hydrofluoric acid-based cleaning solution, the gate oxide film 104 and the polysilicon layer 105 are disposed on the entire structure including the nMOS region and the pMOS region. To form sequentially. In this case, the gate oxide film 104 may be grown using hydrogen and oxygen gas.

Referring to FIG. 1C, the gate oxide film 104 and the polysilicon layer 105 in FIG. 1B are patterned through a patterning process to form the gate oxide film 104 and the gate electrodes 106a and 106b in the nMOS region and the pMOS region, respectively. ). Thereafter, an annealing process may be performed to compensate for the etching damage.

Subsequently, in order to form the source / drain of the LDD structure, a low concentration impurity region 107a and a low concentration ion implantation process are applied to the semiconductor substrate 101 at both edges of the gate electrodes 106a and 106b formed in a predetermined pattern in the nMOS region and the pMOS region. 107b), respectively. Here, n-type impurities are implanted into the nMOS region to form a low concentration impurity region 107a, and p-type impurities are implanted into the pMOS region to form a low concentration impurity region 107b.

Referring to FIG. 1D, the first insulating film 108 and the second insulating film 109 for sequentially forming the insulating film spacers on both side surfaces of the gate electrodes 106a and 106b are sequentially formed on the entire top. Subsequently, the first and second insulating layers 108 and 109 are left only on both sides of the gate electrodes 106a and 106b by the entire surface etching process, thereby forming the insulating layer spacer 110 including the first and second insulating layers 108 and 109. Form.

In the above description, the first insulating layer 108 is formed of low pressure silicon oxide (LP-TEOS), and the second insulating layer 109 is formed of silicon nitride (Si ₃ N ₄ ). In this case, the first insulating film 108 serves as a buffer oxide film that prevents stress from occurring when the gate electrodes 106a and 106b made of the polysilicon layer and the second insulating film 109 made of silicon nitride directly contact each other. .

Thereafter, the high concentration impurity regions 111a to 111d are formed by the high concentration ion implantation process into the semiconductor substrate 101 at the edge of the insulating film spacer 110 formed on both sides of the gate electrodes 106a and 106b to form the source / drain. It is formed deeper than 107a and 107b. Here, n-type impurities are implanted into the nMOS region to form high concentration impurity regions 111a and 111b, and p-type impurities are implanted into the pMOS region to form high concentration impurity regions 111c and 111d, respectively. As a result, a source / drain of an LDD structure composed of the low concentration impurity regions 107a and 107b and the high concentration impurity regions 111a to 111d is formed in the nMOS regions 112a and 112b and the pMOS regions 112c and 112d, respectively.

Referring to FIG. 1E, silicide layers 113 are formed on the top surfaces of the gate electrodes 106a and 106b and the sources / drains 112a through 112d. In this way, a general transistor is manufactured.

When fabricating a transistor by the above method, the gate oxide film is made thin in order to increase driving capability and reduce power consumption. The thermal oxide film applied as a conventional gate insulating film may be formed to have a thickness lowered to about 15 mA, but the leakage current through the thermal oxide film is rapidly increased due to the low physical thickness of the gate insulating film. For this reason, there is a limit in applying the thermal oxide film to the gate insulating film.

In addition, in the subsequent low concentration ion implantation process and the high concentration ion implantation process, boron injected into the floating gate electrode of the pMOS region penetrates into the channel region through the gate oxide layer in the subsequent heat treatment process to change the doping concentration of the channel region and the threshold voltage. To decrease the reliability of the device. Because of this, there is a difficulty in raising the temperature of the subsequent heat treatment process above a certain temperature. However, failure to increase the temperature above a certain temperature may reduce the junction depth of the source / drain and increase the leakage current. In addition, since the ions implanted into the gate electrode are not sufficiently activated, an insulating region in which the impurity concentration decreases is generated in the gate electrode, which may cause an increase in the electrical thickness of the gate oxide layer and thus increase a threshold voltage. have.

On the other hand, in the case of the nMOS transistor, electrons / holes moving from the source to the drain may be introduced into the gate oxide film (hot carrier) by obtaining a higher energy than the energy barrier of the silicon substrate and the gate oxide film interface from the electric field, thereby causing a threshold voltage. This may cause a problem of reducing and decreasing the reliability of the device.

Therefore, in order to solve the above problems, the present invention forms a gate insulating film in a laminated structure of a nitride-based insulating film and a high dielectric insulating film containing hafnium or zirconium, thereby further reducing the electrical thickness of the gate oxide film, In this case, the reliability of the device can be prevented from being degraded by hot carriers flowing into the gate oxide film, and in the case of a pMOS transistor, a transistor manufacturing method of a semiconductor device can be prevented from diffusing into the channel region. Its purpose is to.

A transistor of a semiconductor device according to an embodiment of the present invention is formed between a gate electrode formed in a predetermined pattern on a semiconductor substrate, a source / drain formed on a semiconductor substrate at both edges of the gate electrode, and between the gate electrode and the semiconductor substrate. And a gate insulating film formed of a laminated structure of a series insulating film and a hafnium or zirconium-containing high dielectric film.

In the above, the nitride series insulating film is a nitride oxide film. On the other hand, the hafnium or zirconium-containing high-k dielectric insulating film has a laminated structure of a hafnium oxide film and a hafnium silicon oxide film, or a laminated structure of a zirconium oxide film and a zirconium silicon oxide film.

According to another aspect of the present invention, there is provided a method of manufacturing a transistor of a semiconductor device, including forming a nitride-based first insulating film on a semiconductor substrate, and forming a second insulating film having a high dielectric constant including hafnium or zirconium on the first insulating film. Forming a gate electrode material layer on the second insulating film, patterning the gate electrode material layer, the second and first insulating films by an etching process, and forming a gate insulating film and a gate electrode formed of the first and second insulating films. Forming, and forming a source / drain.

In the above description, the first insulating film may be formed as an nitride oxide film by plasma-nitriding the ozone water oxide film after forming the ozone water oxide film. At this time, the plasma nitridation treatment is preferably applied at a temperature of 5mTorr to 100Torr and a bias of 100W to 1000W for 10 seconds to 1 minute in a nitrogen atmosphere.

The second insulating film can be formed in a stacked structure of a third insulating film containing hafnium or zirconium and a fourth insulating film containing silicon / hafnium or silicon / zirconium. Here, the third insulating film can be formed of a hafnium oxide film or a zirconium oxide film, and is preferably formed to a thickness of 10 to 140 kPa using an atomic layer deposition method or a plasma deposition method. The fourth insulating film can be formed of a hafnium silicon oxide film or a zirconium silicon oxide film, and is preferably formed to a thickness of 2 kPa or less using an atomic layer deposition method or a plasma deposition method.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

2A to 2G are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, after forming an isolation layer 202 in an isolation region of a semiconductor substrate 201 in which an nMOS region in which an nMOS transistor is to be formed and a pMOS region in which a pMOS transistor is to be formed are defined, an nMOS region is formed by an ion implantation process. The p well 203a is formed in the semiconductor substrate 201 of the semiconductor substrate 201, and the n well 203b is formed in the semiconductor substrate 201 of the pMOS region, respectively. On the other hand, the p well 203a and the n well 203b are each subjected to an ion implantation process for adjusting the threshold voltage of the transistor to be formed in a subsequent process.

Referring to FIG. 2B, an oxide film 204 is formed after removing the natural oxide film or the remaining oxide film formed on the semiconductor substrate 201 with ammonia water and a hydrofluoric acid-based cleaning solution. Here, the washing process proceeds to a first washing process using a mixed solution in which NH ₄ OH, H ₂ O ₂ and H ₂ O are mixed at a ratio of about 1: 1: 5, and a second washing process using a hydrofluoric acid solution. On the other hand, the oxide film 204 is formed by growing an ozone water oxide film by washing with ozone water, and having a thickness of 3 kPa or less.

Referring to FIG. 2C, an oxide film (204 of FIG. 2B) is formed of a nitride oxide film 205. The nitride oxide film 205 can be formed by nitriding an oxide film (204 in Fig. 2B). In this case, the nitriding treatment may be performed by a plasma nitriding method, and the plasma nitriding method may be performed at a normal temperature for 10 seconds to 1 minute by applying a pressure of 5 mTorr to 100 Torr and a bias of 100 W to 1000 W.

Next, a high dielectric insulating film 206 is formed over the nitride oxide film 205. The high dielectric insulating film 206 may be formed of an insulating film containing hafnium or zirconium, and more specifically, may be formed of, for example, a hafnium oxide film (HfO ₂ ) or a zirconium oxide film (ZrO ₂ ). At this time, the high-k dielectric layer 206 is formed to a thickness of 10 to 140Å, and is formed by atomic layer deposition (ALD) or plasma deposition.

Subsequently, a silicon-containing high dielectric insulating film 207 is formed over the high dielectric insulating film 206. The silicon-containing high dielectric insulating film 207 may be formed of an insulating film containing silicon / hafnium or silicon zirconium, and more specifically, for example, a hafnium silicon oxide film (HfSiO ₂ ) or a zirconium silicon oxide film (ZrSiO ₂ ). Can be. In this case, the silicon-containing high-k dielectric layer 207 is formed to a thickness of 2 Å or less, and is formed by atomic layer deposition (ALD) or plasma deposition.

As a result, a gate insulating film 208 having a stacked structure of the nitride oxide film 205, the high dielectric insulating film 206, and the silicon-containing high dielectric insulating film 207 is formed.

In general, the high dielectric insulating film is poor in thermal stability and reacts with silicon to generate defects. In the present invention, the semiconductor layer 201 and the high dielectric insulating film 206 have a resistance against impurities or hot carrier penetration as a boundary film. This problem can be solved by forming an excellent plasma nitride oxide film 205. In addition, the silicon-containing high dielectric insulating film 207 is a boundary layer for securing thermal stability between the high dielectric insulating film 206 and the gate electrode material (eg, polysilicon) to be formed in a subsequent process. As a result, the high dielectric insulating film 206 can secure both thermal stability with the lower semiconductor substrate 201 and the upper gate electrode material.

Referring to FIG. 2D, a polysilicon layer 209 for forming a gate is formed. At this time, the polysilicon layer 209 is formed to a thickness of 600 kPa to 2000 kPa.

Referring to FIG. 2E, a polysilicon layer (209 of FIG. 2D) and a gate insulating layer 208 are patterned by an etching process to form gate oxide layers 208 and gate electrodes 210a and 210b in the nMOS region and the pMOS region, respectively. . At this time, the etching process is performed by an anisotropic dry etching method containing HBr gas. Thereafter, the annealing process may be performed in an oxygen atmosphere to compensate for the etching damage.

Subsequently, in order to form the source / drain of the LDD structure, a low concentration impurity region 211a and a low concentration ion implantation process are applied to the semiconductor substrate 201 at both edges of the gate electrodes 210a and 210b formed in a predetermined pattern in the nMOS region and the pMOS region. 211b), respectively. Here, n-type impurities are implanted into the nMOS region to form a low concentration impurity region 211a, and p-type impurities are implanted into the pMOS region to form a low concentration impurity region 211b.

Referring to FIG. 2F, the first insulating layer 212 and the second insulating layer 213 for sequentially forming insulating layer spacers on both side surfaces of the gate electrodes 210a and 210b are sequentially formed on the entire upper portion. Subsequently, the first and second insulating layers 212 and 213 are left only on both sides of the gate electrodes 210a and 210b by the entire surface etching process, thereby forming the insulating layer spacer 214 including the first and second insulating layers 212 and 213. Form.

In the above description, the first insulating layer 212 is formed of low pressure silicon oxide (LP-TEOS), and the second insulating layer 213 is formed of silicon nitride (Si ₃ N ₄ ). In this case, the first insulating film 212 serves as a buffer oxide film that prevents stress from occurring when the gate electrodes 210a and 210b made of the polysilicon layer and the second insulating film 213 made of silicon nitride directly contact each other. .

Thereafter, the high concentration impurity regions 215a to 215d are formed by the high concentration ion implantation process into the semiconductor substrate 201 at the edge of the insulating film spacer 214 formed on both sides of the gate electrodes 210a and 210b to form the source / drain. It is formed deeper than 211a and 211b. Here, n-type impurities are implanted into the nMOS region to form high concentration impurity regions 215a and 215b, and p-type impurities are implanted into the pMOS region to form high concentration impurity regions 215c and 215d, respectively. Thus, the source / drain 216a and 216b of the LDD structure including the low concentration impurity regions 211a and 211b and the high concentration impurity regions 215a to 215d are formed in the nMOS regions 216a and 216b and the pMOS regions 216c and 216d, respectively. Is formed.

Referring to FIG. 2G, silicide layers 217 are formed on upper surfaces of the gate electrodes 210a and 210b and the source / drains 216a to 216d to lower contact resistance.

A method of forming the silicide layer 217 will be described below. First, the natural oxide film on the surfaces of the gate electrodes 210a and 210b and the source / drains 216a to 216d are removed, and then a metal layer (not shown) and a capping layer (not shown) are sequentially formed on the entire upper portion. The silicide layer 217 is formed by reacting the silicon components of the gate electrodes 210a and 210b and the sources / drains 216a to 216d with the metal components of the metal layer by a heat treatment process. Thereafter, after removing the capping layer and the unreacted metal layer, a second heat treatment process is performed to improve the quality of the silicide layer 217.

As a result, a transistor including a gate insulating film 208 having a laminated structure of the nitride oxide film 205 and the high dielectric insulating films 206 and 207 is manufactured.

3 is a characteristic graph comparing leakage current characteristics according to a gate oxide film.

Referring to FIG. 3, it can be seen that the leakage current characteristics of the high-k dielectric films HfO ₂ and ZrO ₂ are superior to the thermal oxide film at the same thickness. Accordingly, in the present invention, even better leakage current characteristics can be obtained by forming the gate oxide film in a stacked structure of a nitride oxide film and a high dielectric insulating film.

As described above, the present invention is to form a gate oxide film in a laminated structure of oxide oxide / hafnium or zirconium-containing oxide film, it is possible to reduce the leakage current through the gate insulating film while further reducing the electrical thickness of the gate oxide film In the case of the nMOS transistor, the reliability of the device can be prevented from being deteriorated by the hot carrier flowing into the gate oxide film, and in the case of the pMOS transistor, the impurities injected into the gate can be prevented from diffusing into the channel region.

In addition, this allows subsequent thermal processes to be carried out at sufficiently high temperatures so that the source / drain can be deeply formed to minimize leakage currents. In addition, it is possible to sufficiently activate the ions implanted into the gate electrode to prevent the generation of an insulating region in which the impurity concentration is reduced inside the gate electrode, thereby increasing the electrical thickness of the gate oxide film to increase the threshold voltage The problem can be solved.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views of devices for describing a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

3 is a characteristic graph comparing leakage current characteristics according to a gate oxide film.

<Explanation of symbols for main parts of the drawings>

101, 201: semiconductor substrate 102, 202: device isolation film

103a, 203a: p well 103b, 203b: n well

204: oxide film 205: nitride oxide film

206: high dielectric insulating film 207: silicon-containing high dielectric insulating film

104, 208: gate insulating film 105, 209: polysilicon layer

106a, 106b, 210a, 210b: gate electrode

107a, 107b, 211a, 211b: low concentration impurity regions

108, 212: buffer oxide film 109, 213: nitride film

110, 214: insulating film spacer 113, 217: silicide layer

111a, 111b, 111c, 111d, 215a, 215b, 215c, 215d: high concentration impurity regions

112a / 112b, 216a / 216b: N-type source / drain

112c / 112d, 216c / 216d: P type source / drain

Claims (11)

A gate electrode formed in a predetermined pattern on the semiconductor substrate; Source / drain formed on the semiconductor substrate at both edges of the gate electrode; And A gate insulating film formed between the gate electrode and the semiconductor substrate, the gate insulating film including a stacked structure of a nitride oxide film, a hafnium or zirconium-containing first high dielectric insulating film, and a silicon hafnium or silicon zirconium-containing second high dielectric insulating film; A transistor of a semiconductor device, characterized in that. delete The method of claim 1, And the gate insulating film is formed by stacking a nitride film, a hafnium oxide film, and a hafnium silicon oxide film, or a stack of a nitride film, a zirconium oxide film, and a zirconium silicon oxide film. Forming an ozone water oxide film on the semiconductor substrate and then plasma-nitriding the ozone water oxide film to form a first insulating film which is a nitride oxide film; Forming a second insulating film on which the insulating film of hafnium or zirconium-containing high dielectric constant and the insulating film of silicon hafnium or silicon zirconium-containing high dielectric constant are stacked on the first insulating film; Forming a gate electrode material layer on the second insulating film; Patterning the gate electrode material layer, the second and first insulating layers by an etching process to form a gate insulating layer and a gate electrode formed of the first and second insulating layers; And And forming a source / drain. delete The method of claim 4, wherein The plasma nitridation treatment is a transistor manufacturing method of a semiconductor device, characterized in that the pressure is applied at a temperature of 5mTorr to 100Torr and a bias of 100W to 1000W for 10 seconds to 1 minute in a nitrogen atmosphere. delete The insulating film of claim 4, wherein the hafnium or zirconium-containing high dielectric constant A hafnium oxide film or a zirconium oxide film, the transistor manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 8, wherein the hafnium or zirconium-containing high dielectric constant insulating film It is formed in the thickness of 10-140 micrometers, and is formed by the atomic layer deposition method or the plasma deposition method. The transistor manufacturing method of the semiconductor element characterized by the above-mentioned. The insulating film of claim 4, wherein the silicon hafnium or silicon zirconium-containing high dielectric constant A hafnium silicon oxide film or a zirconium silicon oxide film, the transistor manufacturing method of the semiconductor element characterized by the above-mentioned. The insulating film of claim 10, wherein the silicon hafnium or silicon zirconium-containing high dielectric constant A method of manufacturing a transistor of a semiconductor device, characterized in that it is formed with a thickness of 2 GHz or less and formed by atomic layer deposition or plasma deposition.