JP2021150635A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a silicon carbide semiconductor device with reduced defects in a silicon dioxide layer.SOLUTION: A silicon carbide semiconductor device includes a silicon carbide layer containing nitrogen and boron, a silicon dioxide layer provided above the silicon carbide layer and containing nitrogen and boron, and an intermediate region containing nitrogen and boron and arranged between the silicon carbide layer and the silicon dioxide layer, and the silicon dioxide layer has a first surface which is a boundary with the intermediate region and a second surface opposite to the first surface, and the nitrogen concentration peak and the boron concentration peak overlap in the intermediate region, and the boron concentration peak extends to the second surface side of the nitrogen concentration peak.SELECTED DRAWING: Figure 3

Description

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

In a silicon carbide semiconductor device in which a silicon dioxide layer is formed on a silicon carbide layer, a silicon carbide semiconductor device in which the electric field effect mobility is improved by reducing defects at the interface between the silicon carbide layer and the silicon dioxide layer is known. There is. (See, for example, Patent Document 1).
International Publication No. 2005-010974

In a silicon carbide semiconductor device, it is preferable to reduce not only defects at the interface between the silicon carbide layer and the silicon dioxide layer (the region between the silicon carbide layer and the silicon dioxide layer) but also defects in the silicon dioxide layer.

In the first aspect of the present invention, a silicon carbide semiconductor device is provided. The silicon carbide semiconductor device may include a silicon carbide layer. The silicon carbide layer may contain nitrogen and boron. The silicon carbide semiconductor device may include a silicon dioxide layer. The silicon dioxide layer may be provided above the silicon carbide layer. The silicon dioxide layer may contain nitrogen and boron. Silicon carbide semiconductor devices may include an intermediate region. The intermediate region may be located between the silicon carbide layer and the silicon dioxide layer. The intermediate region may contain nitrogen and boron. The silicon dioxide layer may have a first surface that is a boundary with the intermediate region. The silicon dioxide layer may have a second surface opposite to the first surface. The nitrogen concentration peak and the boron concentration peak may overlap in the intermediate region. The boron concentration peak may extend to the second surface side of the nitrogen concentration peak.

The apex of the boron concentration peak may be arranged on the second surface side of the apex of the nitrogen concentration peak. The distance between the apex of the boron concentration peak and the apex of the nitrogen concentration peak may be 3 nm or less.

The silicon carbide layer may have a third surface that is a boundary with the intermediate region. The silicon carbide layer may have a fourth surface opposite to the third surface. The spread of the boron concentration peak toward the second surface side in the silicon dioxide layer may be larger than the spread of the boron concentration peak toward the fourth surface side in the silicon carbide layer. The spread of the nitrogen concentration peak toward the second surface side in the silicon dioxide layer may be larger than the spread of the nitrogen concentration peak toward the fourth surface side in the silicon carbide layer. The spread of the boron concentration peak toward the fourth surface side in the silicon carbide layer may be the same as the spread of the nitrogen concentration peak toward the fourth surface side of the silicon carbide layer.

The spread of the boron concentration peak toward the second surface side in the silicon dioxide layer may be 5 nm or more. The spread of the boron concentration peak toward the second surface side in the silicon dioxide layer may be 30 nm or less.

The boron concentration at the apex of the boron concentration peak ^{may be 1 × 10 20} cm ^-3 or more. The boron concentration at the apex of the boron concentration peak ^{may be 5 × 10 22} cm ^-3 or less. The boron concentration at a position 5 nm from the center position in the depth direction of the intermediate region toward the second surface ^{may be 1 × 10 18} cm ^-3 or more. The nitrogen concentration at the apex of the nitrogen concentration peak ^{may be 1 × 10 20} cm ^-3 or more. The nitrogen concentration at the apex of the nitrogen concentration peak ^{may be 5 × 10 22} cm ^-3 or less. The boron concentration at a position 5 nm from the center position in the depth direction of the intermediate region toward the second surface is 5 times or more the nitrogen concentration at a position 5 nm from the center position in the depth direction of the intermediate region toward the second surface. May be. The boron concentration at a position 20 nm from the center position in the depth direction of the intermediate region toward the second surface may be 1/1000 or less of the boron concentration at the apex of the boron concentration peak.

The silicon dioxide layer may have a thin silicon dioxide layer. The silicon dioxide layer may have a thick silicon dioxide layer. The thick silicon dioxide layer may be formed on the thin silicon dioxide layer. The boron concentration peak in the thin silicon dioxide layer may be flatter than the boron concentration peak in the thick silicon dioxide layer. The thick silicon dioxide layer does not have to contain nitrogen.

In the second aspect of the present invention, a method for manufacturing a silicon carbide semiconductor device is provided. The method for manufacturing a silicon carbide semiconductor device may include a boron nitride layer forming step. In this step, a boron nitride layer may be formed on the silicon carbide layer. The method for manufacturing a silicon carbide semiconductor device may include a silicon dioxide layer forming step. In this step, a silicon dioxide layer may be formed on the boron nitride layer. The method for manufacturing a silicon carbide semiconductor device may include a first heat treatment step of performing heat treatment. In this step, in the silicon dioxide layer, the boron of the boron nitride layer may be diffused to a position deeper than the nitrogen of the boron nitride layer. In the first heat treatment step, the heat treatment may be performed in an inert gas at a temperature of 1350 ° C. or higher and 1500 ° C. or lower.

The method for manufacturing a silicon carbide semiconductor device may include a second heat treatment step after the first heat treatment step. In this step, heat treatment may be performed in a gas containing oxygen at a temperature of 800 ° C. or higher and 1300 ° C. or lower.

The method for manufacturing a silicon carbide semiconductor device may include a thin silicon dioxide layer forming step. In this step, a thin silicon dioxide layer may be formed on the silicon carbide layer. The method for manufacturing a silicon carbide semiconductor device may include an addition step. In this step, nitrogen and boron may be added to the thin silicon dioxide layer. The method for manufacturing a silicon carbide semiconductor device may include a thick silicon dioxide layer forming step. In this step, a thick silicon dioxide layer may be formed on the thin silicon dioxide layer. The method for manufacturing a silicon carbide semiconductor device may include a final heat treatment step. In this step, heat treatment may be performed. In the final heat treatment step, in the thick silicon dioxide layer, the boron in the addition step may be diffused closer to the thick silicon dioxide layer than the nitrogen in the addition step.

In the addition step, boron may be added after nitrogen is added. The method for manufacturing a silicon carbide semiconductor device may include an intermediate heat treatment step after the addition step and before the thick silicon dioxide layer forming step. In this step, heat treatment may be performed. In the intermediate heat treatment step, boron may be diffused in the thin silicon dioxide layer.

The outline of the above invention does not list all the necessary features of the present invention. Sub-combinations of these feature groups can also be inventions.

An example of the configuration of the silicon carbide semiconductor device 100 according to one embodiment of the present invention is shown. It is a figure which shows the formation method of the gate structure 61. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 61 of the silicon carbide semiconductor device 100. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 62 of the silicon carbide semiconductor device 100. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 63 of the silicon carbide semiconductor device 100. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 64 of the silicon carbide semiconductor device according to the comparative example. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 65 of the silicon carbide semiconductor device according to the comparative example. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 66 of the silicon carbide semiconductor device according to the comparative example. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 67 of the silicon carbide semiconductor device according to the comparative example. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 68 of the silicon carbide semiconductor device according to the comparative example. It is a figure which shows the formation method of the gate structure 71. This is an example of the concentration profile as a result of SIMS analysis of the gate structure 71 of the silicon carbide semiconductor device 100. An example of the configuration of the silicon carbide semiconductor device 200 according to another embodiment of the present invention is shown.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the inventions that fall within the scope of the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 shows an example of the configuration of the silicon carbide semiconductor device 100 according to one embodiment of the present invention. The silicon carbide semiconductor device 100 of FIG. 1 is a horizontal MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The front surface 91 and the back surface 92 of the silicon carbide semiconductor device 100 may be parallel to the XY plane. FIG. 1 is a cross section obtained by cutting a part of the silicon carbide semiconductor device 100 in the XX plane. In this example, the X-axis direction and the Y-axis direction are perpendicular to each other, and the Z-axis direction is a direction perpendicular to the XY plane.

In this example, the positive direction in the Z-axis direction may be referred to as "up", and the negative direction in the Z-axis direction may be referred to as "down". However, "above" and "below" do not necessarily mean the vertical direction with respect to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely expedient expressions for specifying relative positional relationships on substrates, layers, regions, films, and the like.

The structure shown in FIG. 1 may be a unit structure of a horizontal MOSFET. The unit structure may extend in the Y-axis direction and may be repeatedly provided in the X-axis direction. The plurality of unit structures may be arranged so as to form a substantially rectangular shape in the XY plan view. A region provided with a plurality of unit structures may be referred to as an active region. An edge termination structure having a function of preventing electric field concentration in the active region may be provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure and a JTE (Junction Termination Extension) structure.

The silicon carbide semiconductor device 100 of this example has a silicon carbide substrate 11 and a silicon carbide layer 12. The silicon carbide substrate 11 may be a so-called C-plane silicon carbide substrate. The C-axis direction of the silicon carbide substrate 11 may be parallel to the Z-axis direction. The silicon carbide substrate 11 may be a so-called Si-plane silicon carbide substrate. The Si-axis direction of the silicon carbide substrate 11 may be parallel to the Z-axis direction. The silicon carbide substrate 11 may be a so-called m-plane silicon carbide substrate. The m-axis direction of the silicon carbide substrate 11 may be parallel to the Z-axis direction. The silicon carbide substrate 11 may be a so-called a-side silicon carbide substrate. The a-axis direction of the silicon carbide substrate 11 may be parallel to the Z-axis direction. Further, the silicon carbide substrate 11 may be a low dislocation self-supporting substrate having ^{a through dislocation density of less than 1 × 10 7} cm- ^2. The silicon carbide substrate 11 of this example is an n-type substrate.

The silicon carbide layer 12 may be epitaxially formed on the silicon carbide substrate 11. In this example, the silicon carbide layer 12 is formed on the surface of the silicon carbide substrate 11 opposite to the back surface 92. The silicon carbide layer 12 is a p-type silicon carbide layer. The silicon carbide layer 12 of this example has a thickness of 1 μm or more and 10 μm or less (for example, 4 μm), and as p-type impurities, 5.0 × 10 ¹⁶ cm ^-3 or more and 5.0 × 10 ¹⁷ cm ^-3 or less. Contains elements of aluminum (eg 1.5 x 10 ¹⁷ cm ^-3). In this example, the surface of the silicon carbide layer 12 opposite to the surface in contact with the silicon carbide substrate 11 is referred to as a front surface 91.

In this example, the conductive type of the substrate and each layer is described using either the p-type or the n-type, but in the other example, the conductive type of the substrate and each layer may be the opposite conductive type. .. The n-type or p-type means that electrons or holes are a large number of carriers, respectively. For + or-listed after n or p, + means higher carrier concentration than those not listed, and-means lower carrier concentration than those not listed.

The p-type impurity for the silicon carbide semiconductor may be any element of aluminum (Al) and boron (B). In this example, an aluminum element is used as the p-type impurity. Further, the n-type impurity for the silicon carbide semiconductor may be any element of nitrogen (N) and phosphorus (P). In this example, a phosphorus element is used as the n-type impurity.

The silicon carbide layer 12 has a pair of drain regions 13 and source regions 14 that are separated from each other in the X-axis direction. In this example, the upper parts of the drain region 13 and the source region 14 are exposed to the front surface 91. The drain region 13 and the source region 14 may be provided up to a predetermined depth position shallower than the bottom of the silicon carbide layer 12.

The silicon carbide semiconductor device 100 of this example further includes a gate electrode 19, an intermediate region 17, a silicon dioxide layer 18, a source electrode 16, and a drain electrode 15. The silicon dioxide layer 18 is provided above the silicon carbide layer 12. More specifically, the silicon dioxide layer 18 is above the channel forming region 20 located between the pair of drain regions 13 and the source region 14, and is a part of the drain region 13 and the source region adjacent to the channel forming region 20. It is installed above. In this example, the front surface 91 is etched with dilute hydrofluoric acid to remove the oxide layer from the front surface 91 of the silicon carbide layer 12, the drain region 13 and the source region 14 before forming the silicon dioxide layer 18. After that, the silicon dioxide layer 18 was formed above the front surface 91.

In this example, an intermediate region 17 is formed between the silicon dioxide layer 18 and the silicon carbide layer 12. The thickness of the intermediate region 17 is, for example, less than 3 nm. The intermediate region 17 may be formed by providing a boron nitride layer between the silicon dioxide layer 18 and the silicon carbide layer 12 and heat-treating at a predetermined temperature. By the heat treatment, a part of the nitrogen element and a part of the boron element contained in the boron nitride layer are diffused. Therefore, the nitrogen element and the boron element are present in the intermediate region 17. In the silicon carbide semiconductor device 100 of this example, the gate structure is composed of the gate electrode 19, the silicon dioxide layer 18, the intermediate region 17, and the silicon carbide layer 12.

The gate electrode 19 is in contact with the silicon dioxide layer 18. The gate electrode 19 of this example is located on the silicon dioxide layer 18. The silicon dioxide layer 18 of this example is arranged above the channel forming region 20 between the drain region 13 and the source region 14, and is longer than the length of the channel forming region 20 in the X-axis direction. In this example, the source electrode 16 is in contact with the source region 14 on the front surface 91. The drain electrode 15 is in contact with the drain region 13 on the front surface 91. Each of the gate electrode 19, the source electrode 16 and the drain electrode 15 may be an aluminum electrode. Each of the gate electrode 19, the source electrode 16 and the drain electrode 15 may be formed by resistance heating vapor deposition or photopatterning.

By supplying a predetermined positive potential to the gate electrode 19, a charge inversion region (that is, a channel) is formed in the channel formation region 20 located between the drain region 13 and the source region 14. By applying a predetermined potential difference between the source electrode 16 and the drain electrode 15 in the state where the channel is formed, an electron current flows from the source electrode 16 to the drain electrode 15. Supplying a predetermined positive potential to the gate electrode 19 to form a channel is also referred to as turning on the silicon carbide semiconductor device 100. On the other hand, when the supply of a predetermined positive potential to the gate electrode 19 is stopped, the channel disappears. As a result, the flow of the electron current is stopped and the silicon carbide semiconductor device 100 is turned off.

FIG. 2 is a diagram showing a method of forming the gate structure 61. First, the boron nitride layer forming step S101 for forming the boron nitride layer 30 on the silicon carbide layer 12 is carried out (S101). The thickness of the boron nitride layer 30 of this example is 1 nm or more and 5 nm or less (for example, 3 nm). The boron nitride layer forming step S101 may be carried out by a thermal CVD apparatus. The boron nitride layer forming step S101 may be carried out at a temperature of 900 ° C. or higher and 1100 ° C. or lower (for example, 1000 ° C.). The boron nitride layer 30 formed in this example is a microcrystal.

Next, the silicon dioxide layer forming step S102 for forming the silicon dioxide layer 18 on the boron nitride layer 30 is carried out (S102). The thickness of the silicon dioxide layer 18 of this example is 30 nm or more (for example, 50 nm). The silicon dioxide layer forming step S102 may be carried out by high temperature oxidation (HTO). The silicon dioxide layer forming step S102 may be carried out by any of dry oxidation, wet oxidation, and steam oxidation. The silicon dioxide layer forming step S102 may be carried out by another known method.

After forming the silicon dioxide layer 18, the first heat treatment step S103 is performed (S103). The first heat treatment step S103 may be carried out in _{an N 2} gas atmosphere at atmospheric pressure. The treatment temperature of the first heat treatment step may be 1350 ° C. or higher and 1500 ° C. or lower. The treatment temperature of the first heat treatment step S103 may be 1400 ° C. or higher. The processing time of the first heat treatment step S103 of this example is 5 minutes or more and 20 minutes or less (for example, 10 minutes). The first heat treatment step S103 may be heat-treated in an inert gas at a temperature of 1350 ° C. or higher and 1500 ° C. or lower. In the first heat treatment step S103, the boron element in the boron nitride layer 30 is diffused into the silicon dioxide layer 18. In the first heat treatment step S103, in the silicon dioxide layer 18, the boron of the boron nitride layer 30 may be diffused to a position deeper than the nitrogen of the boron nitride layer 30. The deep position refers to a position where the distance from the boron nitride layer 30 is larger in the Z-axis direction. When the first heat treatment step S103 is carried out, a part of the nitrogen element of the boron nitride layer 30 reacts with the silicon carbide of the silicon carbide layer 12 to form a _{SiN 3 bond.} Therefore, the amount of nitrogen elements diffused into the silicon dioxide layer 18 is reduced, and the impurity concentration of the boron element in the silicon dioxide layer 18 is higher than the impurity concentration of the nitrogen element in the silicon dioxide layer 18.

After the first heat treatment step S103 is carried out, the second heat treatment step S104 is carried out (S104). The second heat treatment step may be carried out in an atmospheric _{pressure O 2 gas atmosphere.} The treatment temperature of the second heat treatment step S104 may be 800 ° C. or higher and 1300 ° C. or lower (for example, 900 ° C.). The treatment time of the second heat treatment step S104 is 10 minutes or more and 60 minutes or less (for example, 30 minutes). After the first heat treatment step S103, a second heat treatment step S104 may be performed in which heat treatment is performed at a temperature of 800 ° C. or higher and 1300 ° C. or lower in a gas containing oxygen. The temperature of the second heat treatment step S104 may be lower than the temperature of the first heat treatment step S103. In the second heat treatment step S104, the nitrogen element in the silicon dioxide layer 18 is released as _{N 2.} When the first heat treatment step S103 and the second heat treatment step S104 are carried out, the intermediate region 17 is formed.

FIG. 3 is an example of the concentration profile as a result of SIMS analysis of the gate structure 61 of the silicon carbide semiconductor device 100. (A) and (b) of FIG. 3 show the concentration profile in the vicinity of the intermediate region 17. The vicinity of the intermediate region 17 is a part of the silicon dioxide layer 18, a part of the intermediate region 17 and a part of the silicon carbide layer 12 (channel forming region 20). Further, the center position of the intermediate region 17 in the Z-axis direction (depth direction) is Zc. FIG. 3 (a) shows the concentration profiles of boron and nitrogen. FIG. 3B shows the oxygen, carbon and silicon concentration profiles. The vertical axis of FIGS. 3A and 3B is the impurity concentration. The horizontal axes of FIGS. 3A and 3B are depths (depths in the Z-axis direction in FIG. 3). In FIGS. 3 (a) and 3 (b), the depths are also shown.

FIG. 3C shows a layered structure in the vicinity of the gate structure 61. In FIG. 3C, in addition to the silicon dioxide layer 18, the intermediate region 17, and the silicon carbide layer 12, the silicon carbide substrate 11 and the gate electrode 19 are shown. In FIG. 3 (c), the length in the depth direction is partially omitted for the regions not shown in FIGS. 3 (a) and 3 (b).

With reference to FIG. 3B, the oxygen concentration is a substantially constant impurity concentration d1 in the silicon dioxide layer 18. The oxygen concentration begins to decrease monotonically when it reaches the intermediate region 17, and becomes a constant impurity concentration in the silicon carbide layer 12. The carbon concentration is a substantially constant impurity concentration d2 in the silicon carbide layer 12. The carbon concentration begins to decrease monotonically when it reaches the intermediate region 17, and becomes a constant impurity concentration in the silicon dioxide layer 18.

In the intermediate region 17, in FIG. 3B, the carbon concentration of the silicon carbide layer 12 starts to decrease from the position where the oxygen concentration in the silicon dioxide layer 18 starts to decrease from the silicon dioxide layer 18 toward the silicon carbide layer 12, and the carbon concentration of the silicon carbide layer 12 is silicon carbide. It may be a region from the layer 12 to the position where it starts to decrease toward the silicon dioxide layer 18. The position where the oxygen concentration in the silicon dioxide layer 18 starts to decrease may be a position where the oxygen concentration becomes 95% of the maximum value of the oxygen concentration in the silicon dioxide layer 18, and is a position where the oxygen concentration becomes 90% or less. May be good. In FIG. 3C, the XY plane at the position is the first plane 93. The maximum value of the oxygen concentration in the silicon dioxide layer 18 may be the impurity concentration d1.

Similarly, the position where the carbon concentration of the silicon carbide layer 12 starts to decrease may be a position where the carbon concentration becomes 95% or less of the maximum value of the carbon concentration in the silicon carbide layer 12, and becomes 90% or less. It may be a position. In FIG. 3C, the XY plane at the position is the third plane 95. The maximum value of the carbon concentration in the silicon carbide layer 12 may be the impurity concentration d2. Further, the silicon concentration begins to decrease monotonically when it reaches the intermediate region 17, and becomes a constant impurity concentration in the silicon dioxide layer 18.

Next, referring to (c) of FIG. 3, the first surface 93 of the silicon dioxide layer 18 is the boundary between the silicon dioxide layer 18 and the intermediate region 17. Further, the silicon dioxide layer 18 may have a second surface 94. The second surface 94 is a surface opposite to the first surface 93. The second surface 94 may be a boundary between the silicon dioxide layer 18 and the gate electrode 19. The boundary between the silicon dioxide layer 18 and the gate electrode 19 may be a position where the concentration of the metal element (for example, aluminum element) of the gate electrode 19 is equal to or less than a certain threshold value (for example, 0 or a detection limit value).

The third surface 95 of the silicon carbide layer 12 is a boundary between the silicon carbide layer 12 and the intermediate region 17. Further, the silicon carbide layer 12 may have a fourth surface 96. The fourth surface 96 is a surface opposite to the third surface 95. The fourth surface 96 may be a boundary between the silicon carbide layer 12 and the silicon carbide substrate 11. The boundary between the silicon carbide layer 12 and the silicon carbide substrate 11 may be a position where impurities (for example, aluminum element) in the silicon carbide layer 12 have a concentration equal to or less than a certain threshold value (for example, 0 or a detection limit value).

Here, referring to FIG. 3A, there are a boron concentration peak 21 and a nitrogen concentration peak 22. The boron concentration peak 21 means a peak of the profile of the impurity concentration of boron. Therefore, at the boron concentration peak 21, the boron concentration indicates an impurity concentration equal to or higher than the detection lower limit. The lower limit of detection of the impurity concentration of boron is, for example, 5 × 10 ¹⁵ cm ^-3 . Further, the boron concentration peak 21 has a vertex 23. The apex 23 is a point where the impurity concentration of the boron concentration peak 21 becomes the maximum value. The boron concentration at the apex 23 of the boron concentration peak 21 may be 1 × 10 ²⁰ cm ^-3 or more and 5 × 10 ²² cm ^-3 or less. The boron concentration at the apex 23 may be 1 × 10 ²¹ cm ^-3 or more and ^{may be 5 × 10 21} cm ^-3 or more. In this example, the impurity concentration of boron at the apex 23 is 5 × 10 ²¹ cm ^-3 .

Similarly, the nitrogen concentration peak 22 means a peak of the profile of the impurity concentration of nitrogen. Therefore, at the nitrogen concentration peak 22, the boron concentration shows an impurity concentration equal to or higher than the detection lower limit. The lower limit of detection of the impurity concentration of nitrogen is, for example, 5 × 10 ¹⁵ cm ^-3 . Further, the nitrogen concentration peak 22 has a vertex 24. The apex 24 is a point where the impurity concentration of the nitrogen concentration peak 22 becomes the maximum value. The nitrogen concentration at the apex 24 of the nitrogen concentration peak 22 may be 1 × 10 ²⁰ cm ^-3 or more and 5 × 10 ²² cm ^-3 or less. The nitrogen concentration at the apex 24 may be 1 × 10 ²¹ cm ^-3 or more, and may be 5 × 10 ²¹ cm ^{-3 or more.} In this example, the nitrogen impurity concentration at the apex 24 is 1 × 10 ²² cm ^-3 . The nitrogen concentration at the apex 24 may be higher or lower than the impurity concentration of boron at the apex 23.

Since the intermediate region 17 is formed by heat-treating the boron nitride layer 30, the nitrogen concentration peak 22 and the boron concentration peak 21 overlap in the intermediate region 17. The nitrogen concentration peak 22 and the boron concentration peak 21 overlap in the intermediate region 17 means that the apex 24 of the nitrogen concentration peak 22 falls within the half-value full width range of the boron concentration peak 21 in the intermediate region 17. It may be there. Similarly, when the nitrogen concentration peak 22 and the boron concentration peak 21 overlap in the intermediate region 17, the peak 23 of the boron concentration peak 21 in the intermediate region 17 is in the range of the half-value full width of the nitrogen concentration peak 22. It may be to enter. The silicon carbide layer 12 may contain nitrogen and boron. The silicon dioxide layer 18 is provided above the silicon carbide layer 12 and may contain nitrogen and boron.

The boron concentration peak 21 may extend closer to the second surface 94 side than the nitrogen concentration peak 22. The boron concentration peak 21 spreads toward the second surface 94 side of the nitrogen concentration peak 22, and the boron concentration peak 21 is distributed in a wider range than the nitrogen concentration peak 22 in the silicon dioxide layer 18. That is. Further, the position where the boron concentration in the silicon dioxide layer 18 is 1/1000 of the boron concentration at the apex 23 is the second surface than the position where the nitrogen concentration in the silicon dioxide layer 18 is 1/1000 of the nitrogen concentration at the apex 24. It may be arranged on the 94 side.

In this example, since the boron concentration peak 21 spreads toward the second surface 94 side of the nitrogen concentration peak 22, the boron element is diffused in the silicon dioxide layer 18 at a higher concentration than the nitrogen element. Since the boron element is diffused in the silicon dioxide layer 18, the defects are terminated by the boron element, and the defects in the silicon dioxide layer 18 can be reduced. Further, since a large amount of nitrogen element is present in the intermediate region 17, defects are terminated by the nitrogen element, and defects in the intermediate region 17 and the silicon carbide layer 12 in contact with the intermediate region 17 can be reduced. Therefore, the electric field effect mobility of the silicon carbide semiconductor device 100 can be increased.

Further, since the boron concentration peak 21 extends closer to the second surface 94 side than the nitrogen concentration peak 22, the apex 23 of the boron concentration peak 21 is also closer to the second surface 94 side than the apex 24 of the nitrogen concentration peak 22. Have been placed. The apex 23 of the boron concentration peak 21 may be arranged on the second surface 94 side of the apex 24 of the nitrogen concentration peak 22. The apex 23 of the boron concentration peak 21 may be arranged in the vicinity of the apex 24 of the nitrogen concentration peak 22. The distance between the apex 23 of the boron concentration peak 21 and the apex 24 of the nitrogen concentration peak 22 may be 3 nm or less.

In the silicon carbide layer 12, the elements are difficult to diffuse. Therefore, the spread of elements in the silicon carbide layer 12 may be smaller than the spread of elements in the silicon dioxide layer 18. The spread of the boron concentration peak 21 toward the second surface 94 side of the silicon dioxide layer 18 may be larger than the spread of the boron concentration peak 21 toward the fourth surface 96 side of the silicon carbide layer 12. The spread of the nitrogen concentration peak 22 toward the second surface 94 side of the silicon dioxide layer 18 may be larger than the spread of the nitrogen concentration peak 22 toward the fourth surface 96 side of the silicon carbide layer 12. The spread is a range in which each peak indicates an impurity concentration equal to or higher than the lower limit of detection. The spread may be a range indicating an impurity concentration of 1/1000 or more of the impurity concentration at the apex of the peak.

Since the elements are difficult to diffuse in the silicon carbide layer 12, all the elements have the same profile in the silicon carbide layer 12. The spread of the boron concentration peak 21 toward the fourth surface 96 side of the silicon carbide layer 12 may be the same as the spread of the nitrogen concentration peak 22 toward the fourth surface 96 side of the silicon carbide layer 12. The same spread may have an error of 50% or less, an error of 30% or less, and an error of 10% or less. When the lower limit of detection is different between boron and nitrogen, a common threshold value may be determined, and the range in which each peak indicates an impurity concentration equal to or higher than the common threshold value may be defined as the spread of each peak.

The spread of the boron concentration peak 21 to the second surface 94 side in the silicon dioxide layer 18 may be 5 nm or more. The spread of the boron concentration peak 21 to the second surface 94 side in the silicon dioxide layer 18 may be 30 nm or less. By adjusting the treatment temperature and treatment time of the first heat treatment step S103 and the second heat treatment step S104, it is possible to adjust the spread of the boron concentration peak 21 on the second surface 94 side of the silicon dioxide layer 18. Therefore, the electric field effect mobility of the silicon carbide semiconductor device 100 can be controlled.

The boron concentration at a position of 5 nm from Zc toward the second surface 94 ^{may be 1 × 10 18} cm ^-3 or more. The boron concentration at the position 5 nm from Zc toward the second surface 94 may be five times or more the nitrogen concentration at the position 5 nm from Zc toward the second surface 94. By adjusting the treatment temperature and treatment time of the first heat treatment step S103 and the second heat treatment step S104, it is possible to adjust the impurity concentration at the position of 5 nm from Zc toward the second surface 94.

The boron concentration at the position of 20 nm from Zc toward the second surface 94 may be 1/1000 or less of the boron concentration at the apex 23 of the boron concentration peak 21. The boron concentration at a position of 20 nm from Zc toward the second surface 94 ^{may be 5 × 10 18} cm ^-3 or less. In this example, the boron concentration at a position of 20 nm from Zc toward the second surface 94 is 5 × 10 ¹⁷ cm ^-3 . By adjusting the treatment temperature and treatment time of the first heat treatment step S103 and the second heat treatment step S104, it is possible to adjust the impurity concentration at the position of 20 nm from Zc toward the second surface 94.

FIG. 4 is an example of the concentration profile as a result of SIMS analysis of the gate structure 62 of the silicon carbide semiconductor device 100. The gate structure 62 of the silicon carbide semiconductor device 100 of FIG. 4 is heated at 1250 ° C. for 30 minutes in a 10% NO gas atmosphere in the second heat treatment step S104. It is different from the structure 61. The other manufacturing steps of the gate structure 62 of the silicon carbide semiconductor device 100 of FIG. 4 may be the same as the manufacturing steps of the gate structure 61 of the silicon carbide semiconductor device 100 of FIG. The profile of FIG. 4A is substantially the same as the profile of FIG. 3A.

FIG. 5 is an example of the concentration profile as a result of SIMS analysis of the gate structure 63 of the silicon carbide semiconductor device 100. The gate structure 63 of the silicon carbide semiconductor device 100 of FIG. 5 is different from the gate structure 61 of the silicon carbide semiconductor device 100 of FIG. 3 in that the thickness of the boron nitride layer 30 in the boron nitride layer forming step S101 is 1 nm. The other manufacturing steps of the gate structure 63 of the silicon carbide semiconductor device 100 of FIG. 5 may be the same as the manufacturing process of the gate structure 61 of the silicon carbide semiconductor device 100 of FIG.

As a result of reducing the thickness of the boron nitride layer 30, in FIG. 5A, the value of the impurity concentration at the apex 23 of the boron concentration peak 21 and the apex 24 of the nitrogen concentration peak 22 is compared with that of FIG. 3A. Then it is down. The value of the impurity concentration has decreased, but the shape of the profile is almost the same.

FIG. 6 is an example of the concentration profile as a result of SIMS analysis of the gate structure 64 of the silicon carbide semiconductor device according to the comparative example. The gate structure 64 of the silicon carbide semiconductor device of FIG. 6 is different from the gate structure 61 of the silicon carbide semiconductor device 100 of FIG. 3 in that the boron nitride layer forming step S101 is not carried out. The other manufacturing steps of the gate structure 64 of the silicon carbide semiconductor device of FIG. 6 may be the same as the manufacturing steps of the gate structure 61 of the silicon carbide semiconductor device 100 of FIG. Since the boron nitride layer forming step S101 is not carried out, the boron concentration peak and the nitrogen concentration peak do not exist.

FIG. 7 is an example of the concentration profile as a result of SIMS analysis of the gate structure 65 of the silicon carbide semiconductor device according to the comparative example. The gate structure 65 of the silicon carbide semiconductor device of FIG. 6 is the silicon carbide of FIG. 3 in that the first heat treatment step S103 is carried out at a treatment temperature of 1000 ° C. and a treatment time of 30 minutes, and the second heat treatment step S104 is not carried out. It is different from the gate structure 61 of the semiconductor device 100. The other manufacturing steps of the gate structure 65 of the silicon carbide semiconductor device of FIG. 7 may be the same as the manufacturing steps of the gate structure 61 of the silicon carbide semiconductor device 100 of FIG.

Under the heat treatment conditions of the gate structure 65, the boron nitride layer 30 of the gate structure 65 is not decomposed, and the nitrogen element and the boron element contained in the boron nitride layer 30 are not diffused. Therefore, the profiles of the boron concentration peak 21 and the nitrogen concentration peak 22 are substantially the same, and are substantially line-symmetrical with respect to the line passing through Zc.

FIG. 8 is an example of the concentration profile as a result of SIMS analysis of the gate structure 66 of the silicon carbide semiconductor device according to the comparative example. The manufacturing process of the gate structure 66 of the silicon carbide semiconductor device of FIG. 8 is described in detail because there are many differences from the manufacturing process of the gate structure 61 of the silicon carbide semiconductor device 100 of FIG.

First, the boron nitride layer forming step S101 for forming the boron nitride layer 30 on the silicon carbide layer 12 is carried out. The thickness of the boron nitride layer 30 of this example is 3 nm. The boron nitride layer forming step S101 may be carried out by a thermal CVD apparatus. The boron nitride layer forming step S101 is carried out at a temperature of 1000 ° C. The boron nitride layer 30 formed in this example is a microcrystal.

First, a first silicon dioxide layer forming step of forming a part of the silicon dioxide layer 18 on the silicon carbide layer 12 is carried out. In the first silicon dioxide layer forming step, the thickness of the silicon dioxide layer is 20 nm. The first silicon dioxide layer formation process may be carried out in N 2 _O atmosphere. By first silicon dioxide layer forming step is performed in a N _{2 O} atmosphere, it is possible to reduce the defects in the intermediate region 17 near. After the first silicon dioxide layer forming step, the second silicon dioxide layer forming step may be carried out. In the second silicon dioxide layer forming step, the thickness of the silicon dioxide layer is 50 nm. The second silicon dioxide layer forming step may be carried out by high temperature oxidation (HTO). The silicon dioxide layer forming step may be carried out by other known methods. When the second silicon dioxide layer forming step is carried out, the silicon dioxide layer 18 is formed on the silicon carbide layer 12.

Next, the boron nitride solid source was placed in contact with the silicon dioxide layer 18 and heat-treated. The boron nitride solid source is, for example, a boron nitride wafer. The boron nitride solid source may be arranged parallel to the silicon carbide layer 12. A solid boron nitride source may be placed at a position 2 mm from the second surface 94 in the positive direction in the Z-axis direction, and heat treatment may be performed. The heat treatment is carried out in an _{O 2 atmosphere under atmospheric pressure.} The processing temperature of the heat treatment is 1000 ° C. The heat treatment treatment time may be 30 minutes. In FIG. 8A, the boron concentration in the silicon dioxide layer 18 becomes a substantially constant value.

FIG. 9 is an example of the concentration profile as a result of SIMS analysis of the gate structure 67 of the silicon carbide semiconductor device according to the comparative example. The gate structure 67 of the silicon carbide semiconductor device of FIG. 9 is different from the gate structure 61 of the silicon carbide semiconductor device 100 of FIG. 3 in that the second heat treatment step S104 is not performed. The other manufacturing steps of the gate structure 67 of the silicon carbide semiconductor device of FIG. 9 may be the same as the manufacturing process of the gate structure 61 of the silicon carbide semiconductor device 100 of FIG. Since the second heat treatment step S104 is not carried out in the gate structure 67, the spread of the boron concentration peak 21 to the second surface 94 side in the silicon dioxide layer 18 is the second surface 94 side in the silicon dioxide layer 18 of the nitrogen concentration peak 22. It is almost the same as the spread to.

FIG. 10 is an example of a concentration profile as a result of SIMS analysis of the gate structure 68 of the silicon carbide semiconductor device according to the comparative example. The gate structure 68 of the silicon carbide semiconductor device of FIG. 10 is different from the gate structure 61 of the silicon carbide semiconductor device 100 of FIG. 3 in that the thickness of the boron nitride layer 30 in the boron nitride layer forming step S101 is 8 nm. The other manufacturing steps of the gate structure 68 of the silicon carbide semiconductor device of FIG. 10 may be the same as the manufacturing process of the gate structure 61 of the silicon carbide semiconductor device 100 of FIG.

As a result of increasing the thickness of the boron nitride layer 30, in FIG. 10A, the impurity concentration at the apex 23 of the boron concentration peak 21 is larger than that in FIG. 3A. The value of the impurity concentration is large, but the shape of the profile is almost the same.

FIG. 11 is a diagram showing a method of forming the gate structure 71. First, the thin silicon dioxide layer forming step S201 for forming the thin silicon dioxide layer 40 on the silicon carbide layer 12 is carried out (S201). The thickness of the thin silicon dioxide layer 40 of this example is 2 nm or more and 8 nm or less (more preferably 4 nm or more and 6 nm or less). The thin silicon dioxide layer forming step S201 may be carried out by a chemical vapor deposition method (CVD method) such as a thermal CVD method or a plasma CVD method. The thin silicon dioxide layer forming step S201 may be carried out by any of dry oxidation, wet oxidation, and steam oxidation. The thin silicon dioxide layer forming step S201 may be carried out by other known methods.

Next, the addition step S202 of adding nitrogen and boron to the thin silicon dioxide layer 40 is carried out (S202). In the addition step S202, nitrogen is added by first nitriding the interface between the thin silicon dioxide layer 40 and the silicon carbide layer 12. Nitride interface, heat treatment in an atmosphere containing NO or _{N 2} O gas (exemplary temperature is 1150 ° C. or higher, 1350 ° C. or less) may be performed by performing. Further, the nitriding of the interface may be carried out by performing heat treatment (implementation temperature is 1400 ° C. or higher and 1500 ° C. or lower) in an atmosphere containing _{N 2 gas.} Nitriding of the interface may be performed by _{N 2 plasma treatment.}

In the addition step S202, boron is added by arranging a solid source such as boron nitride or a ceramic plate containing boron oxide in contact with the thin silicon dioxide layer 40 and performing heat treatment. The boron nitride solid source may be arranged parallel to the silicon carbide layer 12. The boron nitride solid source may be arranged away from the surface of the thin silicon dioxide layer 40 that is not in contact with the silicon carbide layer 12 in the positive direction in the Z-axis direction, and heat treatment may be performed. For example, a solid boron nitride source is placed at a position 2 mm from the surface of the thin silicon dioxide layer 40 that is not in contact with the silicon carbide layer 12 in the positive direction in the Z-axis direction, and heat treatment is performed. The heat treatment is carried out in a mixed atmosphere of _{Ar or N 2} and O _2. The treatment temperature of the heat treatment is 950 ° C. If the temperature of the heat treatment at the time of adding boron is too high, the state of the interface between the thin silicon dioxide layer 40 and the silicon carbide layer 12 deteriorates. Therefore, it is preferable to carry out the heat treatment at 1000 ° C. or lower. The heat treatment treatment time may be 10 minutes.

As explained, the heat treatment when nitrogen is added is higher than the heat treatment when boron is added. Therefore, the addition of boron first affects the profile of the boron concentration. Therefore, in the addition step S202, nitrogen is added to the thin silicon dioxide layer 40, and then boron is added.

An intermediate heat treatment step S203 in which the heat treatment is performed after the addition step S202 may be carried out (S203). In the intermediate heat treatment step S203, boron is diffused in the thin silicon dioxide layer 40. By carrying out the intermediate heat treatment step S203, the boron concentration in the thin silicon dioxide layer 40 can be made substantially constant. The intermediate heat treatment step S203 does not have to be carried out.

Next, the thick silicon dioxide layer forming step S204 for forming the thick silicon dioxide layer 50 on the thin silicon dioxide layer 40 is carried out (S204). The thickness of the thick silicon dioxide layer 50 of this example is, for example, 40 nm. The thick silicon dioxide layer forming step S204 may be carried out by a chemical vapor deposition method (CVD method) such as a thermal CVD method or a plasma CVD method. The thick silicon dioxide layer forming step S204 may be carried out by other known methods. Since the thick silicon dioxide layer 50 is formed thicker than the thin silicon dioxide layer 40 and having a uniform film thickness, it is preferably formed by a thermal CVD method.

After the thick silicon dioxide layer forming step S204, the final heat treatment step S205 for performing the heat treatment is carried out (S205). In the final heat treatment step 205, in the thick silicon dioxide layer 50, the boron in the addition step S202 is diffused closer to the thick silicon dioxide layer 50 than the nitrogen in the addition step S202. The final heat treatment step S205 may be carried out in an atmosphere of an inert gas such as _{N 2 or Ar.} The processing temperature of the final heat treatment step S205 is, for example, 950 ° C. The treatment time of the final heat treatment step S205 is 10 minutes or more and 60 minutes or less (for example, 30 minutes). By carrying out the final heat treatment step S205, the interface state generated at the interface between the thin silicon dioxide layer 40 and the thick silicon dioxide layer 50 can be eliminated, and the insulation performance of the thick silicon dioxide layer 50 can be improved.

FIG. 12 is an example of the concentration profile as a result of SIMS analysis of the gate structure 71 of the silicon carbide semiconductor device 100. 12 (a) and 12 (b) show the concentration profile in the vicinity of the thin silicon dioxide layer 40. The vicinity of the thin silicon dioxide layer 40 is a part of the thick silicon dioxide layer 50, a part of the thin silicon dioxide layer 40, and a part of the silicon carbide layer 12. Further, in FIG. 12, the intermediate region 17 is also shown. FIG. 12 (a) shows the concentration profiles of boron and nitrogen. FIG. 12 (b) shows the concentration profiles of oxygen, carbon and silicon. The vertical axis of FIGS. 12A and 12B is the impurity concentration. The horizontal axes of FIGS. 12A and 12B are depths (depths in the Z-axis direction in FIG. 12). In FIGS. 12A and 12B, the depths are also shown.

FIG. 12C shows a layered structure in the vicinity of the gate structure 71. In FIG. 12C, in addition to the thick silicon dioxide layer 50, the thin silicon dioxide layer 40, and the silicon carbide layer 12, the silicon carbide substrate 11 and the gate electrode 19 are shown. In FIG. 12 (c), the length in the depth direction is partially omitted for the regions not shown in FIGS. 12 (a) and 12 (b).

In FIG. 12, the boron concentration peak 21 extends closer to the second surface 94 side than the nitrogen concentration peak 22. Further, since the boron concentration peak 21 extends closer to the second surface 94 side than the nitrogen concentration peak 22, the apex 23 of the boron concentration peak 21 is also closer to the second surface 94 side than the apex 24 of the nitrogen concentration peak 22. Have been placed. Therefore, even in the configuration of the gate structure 71, the boron element can be diffused in the silicon dioxide layer 18 at a higher concentration than the nitrogen element. Therefore, the electric field effect mobility of the silicon carbide semiconductor device 100 can be increased.

Since boron is added to the thin silicon dioxide layer 40 by heat-treating a solid source such as boron nitride, the boron concentration peak in the thin silicon dioxide layer 40 is a substantially constant value. Therefore, in FIG. 12, the boron concentration peak in the thin silicon dioxide layer 40 may be flatter than the boron concentration peak in the thick silicon dioxide layer 50. Since the boron concentration peak in the thin silicon dioxide layer 40 is flat, the positions of the boron concentration peak 21 and the nitrogen concentration peak 22 can be shifted.

Further, the thick silicon dioxide layer 50 is formed after the addition step S202. Therefore, the thick silicon dioxide layer 50 does not have to contain nitrogen. Even with such a configuration, the positions of the boron concentration peak 21 and the nitrogen concentration peak 22 can be shifted.

In each gate structure, the field effect mobility and Vth shift are shown in Table 1 below. For the Vth shift, 20V and -20V were applied to the source region and the drain region, respectively, and the change in Vth (gate threshold voltage) after 1000 hours had elapsed was measured.

The gate structure 61 and the gate structure 62 have a boron concentration of 1 × 10 ¹⁸ cm ^-3 or more at a position of 5 nm from Zc toward the second surface 94. Further, in the gate structure 61 and the gate structure 62, the boron concentration at the position of 5 nm from Zc toward the second surface 94 is five times or more the nitrogen concentration at the position of 5 nm from Zc toward the second surface 94. Therefore, the boron element in the silicon dioxide layer 18 that is not bonded to the nitrogen element can reduce the defects in the vicinity of the intermediate region 17, and the electric field effect mobility is higher than that of the gate structure 65. Further, when the gate structure 61 and the gate structure 63 are compared, the higher the maximum boron concentration, the higher the defect reduction effect and the higher the field effect mobility. The maximum boron concentration is ^{preferably 1 × 10 20} cm ^-3 or more.

Further, as in the gate structure 61, the gate structure 62, and the gate structure 63, the boron concentration at the position of 20 nm from Zc toward the second surface 94 is 1/1000 or less of the boron concentration at the apex 23 of the boron concentration peak 21. It is preferable to have. The Vth shift can be suppressed by setting the boron concentration at the position of 20 nm from Zc toward the second surface 94 to 1/1000 or less of the boron concentration at the apex 23 of the boron concentration peak 21. Compared with the case where boron is diffused from the surface of the silicon dioxide layer 18 as in the gate structure 66, the reliability of the silicon dioxide layer 18 can be improved.

If the width of the gate structure 68 is high and the boron concentration is wide, the reliability (Vth shift) deteriorates. Therefore, it is preferable to control the boron concentration of the gate structure. Summarizing the above, by controlling the boron concentration and the nitrogen concentration as in the present embodiment (gate structures 61, 62, 63, 71), the electric field effect mobility can be increased and the reliability can be improved.

FIG. 13 shows an example of the configuration of the silicon carbide semiconductor device 200 according to another embodiment of the present invention. The silicon carbide semiconductor device 200 of FIG. 13 is a vertical MOSFET.

The silicon carbide substrate 121 is, for example, a silicon carbide crystal substrate doped with a nitrogen element. The silicon carbide layer 122 is a low-concentration n-type drift layer in which, for example, a nitrogen element is doped with an impurity concentration lower than that of the silicon carbide substrate 121. A high concentration region 105 is formed on the surface side of the silicon carbide layer 122 opposite to the silicon carbide substrate 121 side. The high-concentration region 105 is a high-concentration n-type drift layer which is lower than the silicon carbide substrate 121 and has a higher impurity concentration than the silicon carbide layer 122, for example, and is doped with a nitrogen element.

As shown in FIG. 13, a drain electrode 114 is provided on the back surface of the silicon carbide substrate 121. A drain electrode pad 116 is provided below the drain electrode 114.

A trench structure is formed on the front surface side of the silicon carbide semiconductor device 200. Specifically, the trench 117 penetrates the base layer 106 from the surface opposite to the silicon carbide substrate 121 side of the base layer 106 (the front surface side of the silicon carbide semiconductor device 200) and penetrates the high concentration region 105. To reach. An intermediate region 109 is formed on the bottom and side walls of the trench 117 along the inner wall of the trench 117, and a silicon dioxide layer 110 is formed inside the intermediate region 109 in the trench 117. Further, a gate electrode 111 is formed inside the silicon dioxide layer 110 in the trench 117. The silicon dioxide layer 110 insulates the gate electrode 111 from the silicon carbide layer 122 and the base layer 106. A part of the gate electrode 111 may project from above the trench 117 (on the source electrode pad 115 side) toward the source electrode pad 115. The intermediate region 109 may be formed by the same method as the gate structure 61. Further, an interlayer insulating film 112 may be formed on the gate electrode 111. The interlayer insulating film 112 insulates the gate electrode 111 and the source electrode pad 115.

A source region 107 and a contact region 108 are selectively provided on the front surface side of the silicon carbide semiconductor device 200. The source region 107 and the contact region 108 may be in contact with the source electrode 113. Further, the source region 107 may be in contact with the trench 117.

A first base region 123 and a second base region 124 are selectively provided on the surface layer of the silicon carbide layer 122 on the side opposite to the silicon carbide substrate 121 side. The first base region 123 reaches a position deeper on the drain side than the bottom of the trench 117. The lower end of the first base region 123 is located on the drain side of the bottom of the trench 117. The lower end of the second base region 124 is located on the drain side of the bottom of the trench 117. The second base region 124 is formed at a position facing the bottom of the trench 117 in the depth direction (Z-axis direction). The width of the second base region 124 in the X-axis direction may be wider than the width of the trench 117 in the X-axis direction. The bottom of the trench 117 may reach the second base region 124 or is located within the high concentration region 105 sandwiched between the base layer 106 and the second base region 124 without contacting the second base region 124. May be good. The first base region 123 and the second base region 124 are doped with, for example, an aluminum element.

A predetermined potential difference is formed between the source electrode 113 (source electrode pad 115) and the drain electrode 114 (drain electrode pad 116), and a predetermined positive potential is supplied to the gate electrode 111 to charge the base layer 106. An inverted region (ie, channel) is formed. As a result, an electron current flows from the source electrode 113 to the drain electrode 114.

In this example, the silicon carbide semiconductor device 200 has an intermediate region 109, similar to the gate structure 61 of FIG. Therefore, the concentration profile at the position where the base layer 106 and the intermediate region 109 are in contact with each other is the same as the concentration profile shown in FIG. Therefore, in the silicon carbide semiconductor device 200, it is possible to reduce defects near the position where the base layer 106 and the intermediate region 109 are in contact with each other, and it is possible to increase the electric field effect mobility.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

The order of execution of operations, procedures, steps, steps, etc. in the devices, systems, programs, and methods shown in the claims, specification, and drawings is particularly "before" and "prior to". It should be noted that it can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the scope of claims, the specification, and the operation flow in the drawings are explained using "first", "next", etc. for convenience, it means that it is essential to carry out in this order. It's not a thing.

11 ... Silicon carbide substrate, 12 ... Silicon carbide layer, 13 ... Drain region, 14 ... Source region, 15 ... Drain electrode, 16 ... Source electrode, 17 ... Intermediate region, 18 ... Silicon dioxide layer , 19 ... Gate electrode, 20 ... Channel formation region, 21 ... Boron concentration peak, 22 ... Nitrogen concentration peak, 23 ... Peak, 24 ... Peak, 30 ... Boron nitride layer, 40 ... Thin dioxide Silicon layer, 50 ... thick silicon dioxide layer, 61 ... gate structure, 62 ... gate structure, 63 ... gate structure, 64 ... gate structure, 65 ... gate structure, 66 ... gate structure, 67 ... Gate structure, 68 ... Gate structure, 71 ... Gate structure, 91 ... Front surface, 92 ... Back surface, 93 ... 1st surface, 94 ... 2nd surface, 95 ... 3rd surface, 96 Fourth surface, 100 ... Silicon carbide semiconductor device, 105 ... High concentration region, 106 ... Base layer, 107 ... Source region, 108 ... Contact region, 109 ... Intermediate region, 110 ... Silicon dioxide Layer, 111 ... Gate electrode, 112 ... Interlayer insulation film, 113 ... Source electrode, 114 ... Drain electrode, 115 ... Source electrode pad, 116 ... Drain electrode pad, 117 ... Trench, 121 ... Carbon Silicon substrate, 122 ... Silicon carbide layer, 123 ... 1st base region, 124 ... 2nd base region, 200 ... Silicon carbide semiconductor device

Claims (21)

With a silicon carbide layer containing nitrogen and boron,
A silicon dioxide layer provided above the silicon carbide layer and containing nitrogen and boron, and
Arranged between the silicon carbide layer and the silicon dioxide layer and provided with an intermediate region containing nitrogen and boron.
The silicon dioxide layer has a first surface that is a boundary with the intermediate region and a second surface that is opposite to the first surface.
The nitrogen concentration peak and the boron concentration peak overlap in the intermediate region.
A silicon carbide semiconductor device in which the boron concentration peak extends toward the second surface side of the nitrogen concentration peak. The silicon carbide semiconductor device according to claim 1, wherein the apex of the boron concentration peak is arranged on the second surface side of the apex of the nitrogen concentration peak. The silicon carbide semiconductor device according to claim 2, wherein the distance between the apex of the boron concentration peak and the apex of the nitrogen concentration peak is 3 nm or less. The silicon carbide layer has a third surface that is a boundary with the intermediate region and a fourth surface that is opposite to the third surface.
Any one of claims 1 to 3 that the spread of the boron concentration peak toward the second surface side in the silicon dioxide layer is larger than the spread of the boron concentration peak toward the fourth surface side of the silicon carbide layer. The silicon carbide semiconductor device according to. The silicon carbide semiconductor device according to claim 4, wherein the spread of the nitrogen concentration peak toward the second surface side in the silicon dioxide layer is larger than the spread of the nitrogen concentration peak toward the fourth surface side in the silicon carbide layer. .. The spread of the boron concentration peak toward the fourth surface side in the silicon carbide layer is the same as the spread of the nitrogen concentration peak toward the fourth surface side of the silicon carbide layer according to claim 4 or 5. Silicon carbide semiconductor device. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the spread of the boron concentration peak toward the second surface side in the silicon dioxide layer is 5 nm or more. The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the spread of the boron concentration peak toward the second surface side in the silicon dioxide layer is 30 nm or less. The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein the boron concentration at the peak of the boron concentration peak is 1 × 10 ²⁰ cm ^-3 or more and 5 × 10 ²² cm ^{-3 or less.} The carbide according to any one of claims 1 to 9, wherein the boron concentration at a position 5 nm from the center position in the depth direction of the intermediate region toward the second surface is 1 × 10 ¹⁸ cm ^{-3 or more.} Silicon semiconductor device. The silicon carbide semiconductor device according to any one of claims 1 to 10, wherein the nitrogen concentration at the peak of the nitrogen concentration peak is 1 × 10 ²⁰ cm ^-3 or more and 5 × 10 ²² cm ^{-3 or less.} The boron concentration at a position 5 nm from the center position in the depth direction of the intermediate region toward the second surface is the nitrogen concentration at a position 5 nm from the center position in the depth direction of the intermediate region toward the second surface. The silicon carbide semiconductor device according to any one of claims 1 to 11, which is 5 times or more the amount of the above. Any of claims 1 to 12, wherein the boron concentration at a position 20 nm from the central position in the depth direction of the intermediate region toward the second surface is 1/1000 or less of the boron concentration at the apex of the boron concentration peak. The silicon carbide semiconductor device according to item 1. The silicon dioxide layer is
With a thin silicon dioxide layer,
It has a thick silicon dioxide layer formed on the thin silicon dioxide layer, and has
The silicon carbide semiconductor device according to claim 1 or 2, wherein the boron concentration peak in the thin silicon dioxide layer is flatter than the boron concentration peak in the thick silicon dioxide layer. The silicon carbide semiconductor device according to claim 14, wherein the thick silicon dioxide layer does not contain nitrogen. The boron nitride layer forming step of forming the boron nitride layer on the silicon carbide layer,
A silicon dioxide layer forming step of forming a silicon dioxide layer on a boron nitride layer,
The first heat treatment step to perform heat treatment and
Have,
In the first heat treatment step, a method for manufacturing a silicon carbide semiconductor device that diffuses boron in the boron nitride layer to a position deeper than nitrogen in the boron nitride layer in the silicon dioxide layer. The method for manufacturing a silicon carbide semiconductor device according to claim 16, wherein the first heat treatment step is heat treatment at a temperature of 1350 ° C. or higher and 1500 ° C. or lower in an inert gas. The method for manufacturing a silicon carbide semiconductor device according to claim 16 or 17, further comprising a second heat treatment step of performing heat treatment at a temperature of 800 ° C. or higher and 1300 ° C. or lower in a gas containing oxygen after the first heat treatment step. A thin silicon dioxide layer forming step of forming a thin silicon dioxide layer on the silicon carbide layer,
The addition step of adding nitrogen and boron to the thin silicon dioxide layer, and
A thick silicon dioxide layer forming step of forming a thick silicon dioxide layer on the thin silicon dioxide layer,
It has a final heat treatment process to perform heat treatment,
A method for manufacturing a silicon carbide semiconductor device in which in the final heat treatment step, boron in the addition step is diffused closer to the thick silicon dioxide layer than nitrogen in the addition step in the thick silicon dioxide layer. The method for manufacturing a silicon carbide semiconductor device according to claim 19, wherein in the addition step, nitrogen is added and then boron is added. It has an intermediate heat treatment step of performing a heat treatment after the addition step and before the thick silicon dioxide layer forming step.
The method for manufacturing a silicon carbide semiconductor device according to claim 19 or 20, wherein in the intermediate heat treatment step, boron is diffused in the thin silicon dioxide layer.

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