WO2012111120A1 - Dispositif d'affichage d'image et son procédé de réglage de la fréquence d'horloge - Google Patents

Dispositif d'affichage d'image et son procédé de réglage de la fréquence d'horloge Download PDF

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Publication number
WO2012111120A1
WO2012111120A1 PCT/JP2011/053337 JP2011053337W WO2012111120A1 WO 2012111120 A1 WO2012111120 A1 WO 2012111120A1 JP 2011053337 W JP2011053337 W JP 2011053337W WO 2012111120 A1 WO2012111120 A1 WO 2012111120A1
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WO
WIPO (PCT)
Prior art keywords
display
horizontal
video signal
value
end position
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PCT/JP2011/053337
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English (en)
Japanese (ja)
Inventor
充彦 齋藤
Original Assignee
Ｎｅｃディスプレイソリューションズ株式会社
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Priority to PCT/JP2011/053337 priority Critical patent/WO2012111120A1/fr
Priority to JP2012557723A priority patent/JPWO2012111120A1/ja
Publication of WO2012111120A1 publication Critical patent/WO2012111120A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G09G5/008—Clock recovery

Definitions

  • the present invention relates to an image display device connected to a video signal source that outputs RGB video signals and a clock frequency adjusting method thereof.
  • a liquid crystal panel in which pixels are arranged in a grid pattern is known.
  • This type of image display device is connected to a video signal source such as a personal computer (hereinafter abbreviated as PC) or a workstation, and can display an image based on a video signal supplied from the video signal source. is there.
  • a video signal source such as a personal computer (hereinafter abbreviated as PC) or a workstation.
  • the image display device is supplied with a video signal whose signal level changes at a constant frequency (hereinafter referred to as a dot clock) higher than a horizontal synchronizing signal indicating a horizontal display cycle of a display image.
  • the image display device reproduces a dot clock having the same frequency as the dot clock used in the video signal source, and displays an image based on the video signal from the video signal source using the reproduced dot clock.
  • a dot clock reproduced by an image display device is called a reproduction dot clock.
  • the image display device includes a clock generation circuit based on PLL (Phase Locked Loop), and an integer number of horizontal synchronization signals of the video signal supplied from the video signal source by changing the frequency division ratio of the frequency divider included in the circuit. The frequency of the reproduction dot clock is adjusted so as to be doubled.
  • PLL Phase Locked Loop
  • the frequency of the reproduction dot clock can be accurately set by setting the frequency division ratio accordingly. It is possible to match the dot clock on the side.
  • the input video signal is an analog signal
  • the timing information is only the horizontal synchronization signal and the vertical synchronization signal.
  • the information on the dot clock frequency (or frequency division ratio) on the video signal source side cannot be acquired in advance by the image display device, so there is no guarantee that the frequency division ratio of the clock generation circuit is set correctly. If the frequency division ratio is not set correctly, the frequency of the reproduction dot clock does not match the frequency of the dot clock on the video signal source side, so that the image cannot be displayed correctly.
  • Patent Document 1 describes the following clock frequency adjustment method.
  • the frequency of the horizontal synchronizing signal is measured and the number of lines between one frame is counted.
  • the horizontal resolution of the analog video signal and the frequency of the dot clock are estimated by referring to the table from the frequency of the horizontal synchronization signal and the number of lines between one frame, and the horizontal display width E of the analog video signal (ie, the estimated horizontal Resolution) and frequency division ratio n are provisionally set.
  • the horizontal display width W of the video signal actually captured is obtained by the reproduction dot clock generated with the frequency division ratio n.
  • a reproduction dot clock is generated with a frequency division ratio corresponding to the determined type of the input signal, a horizontal display width is detected by the reproduction dot clock, and a horizontal display corresponding to the determined type of the input signal is performed.
  • the frequency of the reproduction dot clock and the frequency of the dot clock of the video signal are matched by re-adjusting the frequency division ratio if necessary, so there is no need to manually adjust the clock frequency.
  • the present invention has been made to solve the above-described problems of the prior art, and when an image signal is received, such as a screen saver, which has an image only in a part of the image signal and moves over time.
  • Another object of the present invention is to provide an image display device and a clock frequency adjusting method thereof that can obtain a reproduced dot clock having a frequency equal to the dot clock of a video signal and display an image correctly.
  • an image display device of the present invention provides: A clock generator for multiplying the horizontal synchronization signal and generating a reproduction dot clock for displaying the input video signal; A synchronization detection unit that detects the frequency of the horizontal synchronization signal and the vertical synchronization signal and the total number of vertical lines that are the total number of lines of one frame of the video signal, and outputs the number of synchronization signals as synchronization signal information; A video to be output as video signal information by measuring the display start position and display end position of a horizontal video signal to be displayed included in the video signal using the reproduced dot clock generated by the clock generator.
  • a detection unit A video image obtained by estimating the resolution of the input signal based on the synchronization signal information, and temporarily setting the frequency division ratio of the clock generation unit to a predetermined value corresponding to the estimated resolution, and measuring the video signal
  • a control unit that obtains an actual measurement value of the horizontal display width from the signal information, compares the estimated resolution, and resets the division ratio
  • a storage unit for storing the minimum value of the display start position and the maximum value of the display end position; The control unit updates and stores the minimum value of the display start position and the maximum value of the display end position every predetermined time, and stores the minimum value of the display start position and the maximum value of the display end position in the storage unit.
  • the measured value of the horizontal display width is updated according to the value, the updated measured value of the horizontal display width is compared with the estimated resolution, and the division ratio is reset.
  • the frequency adjustment method of the present invention includes: A clock generator for multiplying the horizontal synchronization signal and generating a reproduction dot clock for displaying the input video signal; A synchronization detection unit that detects the frequency of the horizontal synchronization signal and the vertical synchronization signal and the total number of vertical lines that are the total number of lines of one frame of the video signal, and outputs the number of synchronization signals as synchronization signal information; A video to be output as video signal information by measuring the display start position and display end position of a horizontal video signal to be displayed included in the video signal using the reproduced dot clock generated by the clock generator.
  • a detection unit A storage unit for storing the minimum value of the display start position and the maximum value of the display end position;
  • a clock frequency adjusting method for adjusting the frequency of the reproduced dot clock corresponding to the video signal by an image display device comprising: Estimating the resolution of the input signal based on the synchronization signal information; Temporarily set a predetermined value corresponding to the estimated resolution of the frequency division ratio of the clock generation unit, Obtain the actual value of the horizontal display width from the video signal information measured in the video detection unit, Compare the measured value of the horizontal display width with the estimated resolution and reset the division ratio, Update the minimum value of the display start position and the maximum value of the display end position every predetermined time and save in the storage unit, Update the measured value of the horizontal display width according to the minimum value of the display start position and the maximum value of the display end position in the storage unit, The actually measured value of the updated horizontal display width is compared with the estimated resolution, and the division ratio is reset.
  • FIG. 1 is a block diagram showing an example of the configuration of the image display apparatus of the present invention. It is a block diagram which shows the example of 1 structure of the control part shown in FIG. It is a block diagram which shows one structural example of the image
  • video detection part shown in FIG. 3 is a flowchart illustrating a processing procedure of the image processing apparatus illustrated in FIG. 1.
  • 3 is a flowchart illustrating a processing procedure of the image processing apparatus illustrated in FIG. 1. It is a figure which shows the timing of a signal. It is a figure which shows the example of a screen saver. It is a figure which shows the example of a screen saver. It is a block diagram which shows the example of 1 structure of 2nd Example.
  • FIG. 9 is a block diagram illustrating a configuration example of a video detection unit illustrated in FIG. 8. It is a figure which shows the example of a screen saver.
  • FIG. 1 is a block diagram showing a configuration example of the image display apparatus of the present invention
  • FIG. 2 is a block diagram showing a configuration example of the control unit shown in FIG.
  • the image display device shown in FIG. 1 when the video signal input from a PC or the like is a composite signal or a sync on green signal, an analog video signal and a synchronization signal (horizontal synchronization signal and It is assumed that they are input separately from each other.
  • the image display device generates an reproduced dot clock by multiplying an A / D converter 1 that converts an analog video signal into a digital video signal using a reproduced dot clock, and a horizontal synchronizing signal.
  • a clock generation unit 2 capable of adjusting the phase of a reproduction dot clock for an analog video signal, and synchronization detection for detecting synchronization signal information such as a horizontal synchronization frequency, a vertical synchronization frequency, and the total number of vertical lines from the horizontal synchronization signal and the vertical synchronization signal 3, a video detection unit 4 that detects a display signal to be actually displayed from the digital video signal and outputs values such as a horizontal video start position and video end position as video signal information, and a video based on the digital video signal
  • the video processing unit 6 for executing processing for displaying the image on the display unit 8, and information detected by the synchronization detection unit 3 and the video detection unit 4; And a control unit 5 for performing an operation processing of a main. Note that the total number of vertical lines is the
  • the processing of the control unit 5 estimates the type (format) of the input signal based on the total number of vertical lines of the input analog video signal, and the clock generation unit corresponding to the estimated type
  • the frequency division ratio and the phase adjustment value of 2 are provisionally set (temporary setting) to predetermined values. Then, the display start position and the display end position in the horizontal direction are monitored using the reproduced dot clock generated by the clock generation unit 2 based on the frequency division ratio after the temporary setting, and the horizontal display width is detected.
  • the horizontal display width can be obtained by subtracting the minimum value of the display start position from the maximum value of the display end position.
  • the phase adjustment of the reproduction dot clock with respect to the analog video signal is performed using the reproduction dot clock.
  • a method of accumulating and adding the absolute value of the difference between adjacent pixels for one frame to obtain the optimum value of the phase is known, and a detailed description thereof will be omitted.
  • FIG. 3 is a block diagram illustrating a configuration example of the video detection unit 4.
  • the video detection unit 4 includes a horizontal display start position detection unit 20 that detects a display start position of a video in the horizontal direction, and a horizontal display end position detection unit 21 that detects a display end position of the video.
  • the horizontal display start position detection unit 20 includes a counter that counts a video signal with a reproduction dot clock, and a comparator that compares the video signal with a threshold value.
  • the digitized RGB signals may be compared with individually set threshold values, and the output may be logically summed or output, or RGB logical sums may be taken as video signals.
  • a signal may be employed.
  • the count value of the reproduction dot clock when any one of RGB exceeds the threshold value is output as a signal indicating the horizontal display start position.
  • the horizontal display end position detector 21 can be configured in the same manner. In the case of the horizontal display end position detection unit 21, the count value of the reproduction dot clock when all the RGB signals fall below the threshold value is output as a signal indicating the horizontal display end position.
  • the counters of the horizontal display start position detection unit 20 and the horizontal display end position detection unit 21 are each reset by the input of a horizontal synchronization signal. Each counter starts counting, for example, from the falling edge of the horizontal synchronizing signal.
  • the video detection unit 4 sends the count value of the horizontal display start position detection unit 20 and the count value of the horizontal display end position detection unit 21 to the control unit 5 as video signal information indicating the horizontal display start position and the horizontal display end position, respectively. Output. When black is included in the video signal in one horizontal scanning period, it is output every time the display end position and the display start position are detected.
  • the synchronization detection unit 3 detects the frequency of each synchronization signal by counting each period of the horizontal synchronization signal and the vertical synchronization signal with the measurement clock.
  • the measurement clock is a clock having a fixed frequency regardless of the frequency of the input signal and a frequency sufficiently higher than the frequency of the horizontal synchronization signal. In general, since the frequency of the horizontal synchronization signal is several tens of KHz, if a clock of several MHz or more is used as the measurement clock, sufficient accuracy can be obtained for frequency detection of the synchronization signal.
  • the measurement clock for example, a CPU driving clock or the like is used.
  • the synchronization detection unit 3 further includes a counter that detects the number of horizontal scanning lines in one frame period. That is, the count value of the horizontal synchronization signal in one cycle of the vertical synchronization signal is obtained and output to the control unit 5 as a signal indicating the total number of vertical lines.
  • the synchronization signal information output by the synchronization detection unit 3 includes at least (1) horizontal synchronization frequency (2) vertical synchronization frequency (3) total number of vertical lines.
  • the control unit 5 monitors the video signal information from the video detection unit 4 and starts horizontal display start position (hereinafter referred to as Hs) and end position (hereinafter referred to as He). )), A storage unit 13 for storing the minimum value of the video display start position (hereinafter referred to as Hs-Min) and the maximum value of the display end position (hereinafter referred to as He-Max), The type of the input signal is determined according to the synchronization signal information from the synchronization detection unit 3 and the signal from the video monitoring processing unit 11, and the clock automatic control for controlling the clock generation unit 2 and the video processing unit 6 based on the determination result.
  • Hs-Min minimum value of the video display start position
  • He-Max maximum value of the display end position
  • the control unit 5 can be realized by an integrated circuit device including a memory, a CPU, or the like, or an integrated circuit device including a DSP or a logic circuit that executes processing according to a program or the like.
  • the video monitoring processing unit 11 detects Hs and He based on the video signal information output from the video detection unit 4, updates Hs to the smallest value, and updates He to the largest value, and the storage unit 13 is stored.
  • Hs-Min and He-Max are output to the automatic clock adjustment processing unit 12.
  • the clock automatic adjustment processing unit 12 automatically adjusts the reproduction dot clock.
  • FIG. 4A is a flowchart showing a processing procedure of the control unit 5 of the image processing apparatus shown in FIG. 1, and FIG. 4B is a flowchart showing the video monitoring process S4 in more detail.
  • ⁇ Automatic adjustment of regenerative dot clock starts (1) when power is turned on, (2) when input terminal is switched, (3) when input signal changes, and (4) by an explicit instruction from the operator.
  • the time when the input signal changes in (3) indicates when any one of the horizontal synchronization frequency, the vertical synchronization frequency, and the total number of vertical lines, which are the synchronization signal information, changes.
  • the explicit instruction by the operator in (4) means that the automatic clock adjustment mode is entered by pressing a key as an input means.
  • step S1 initialization processing
  • the counters of the synchronization detection unit 3 and the video detection unit 4 are reset, and Hs-Min in the storage unit 13 is set to the maximum value (FFFF in the case of 16 bits), and He-Max is set to 0.
  • the type (resolution) of the input video signal is discriminated based on the sync signal information from the sync detector 3. For example, when the total number of vertical lines is 806 from the synchronization signal information, it can be determined that the resolution of the input signal is 1024 ⁇ 768. This is because the total number of vertical lines is determined in advance for each resolution signal, and in many cases, the resolution of the input signal can be uniquely determined from the total number of vertical lines.
  • the storage unit 14 stores resolution information corresponding to the total number of vertical lines as a LUT (Look Up Table).
  • the assumed horizontal display width E is set to 1024 which is the horizontal resolution (step S2).
  • the start position and end position of the effective video area in the frame are also defined and stored in the LUT of the storage unit 14.
  • step S4 first, the minimum value (Hs-Min) of the horizontal display start position and the maximum value (Hs-Max) of the display end position are detected (step S11).
  • Hs-Min is set to FFFF in the initialization process (step S1). Similarly, He-Max is set to 0.
  • the video monitoring processor 11 compares Hs-Min with the horizontal display start position Hs every time video signal information is received. When Hs is smaller than Hs-Min, the value of Hs that has received the value of Hs-Min. Update to Similarly, every time video signal information is received, the video monitoring processing unit 11 compares He-Max with the horizontal display end position He. If He is greater than He-Max, the He that received the value of He-Max. Update to the value of.
  • FIG. 5 shows the distribution of video signals at certain times t1 to t4.
  • the hatched portion in the figure indicates a region where the video signal exists.
  • Hs and He are respectively detected where two video signals are present.
  • t2 since there are three portions where the video signal exists, three sets of Hs and He are detected.
  • Hs-Min becomes the minimum value of Hs at t3 when the scanning at t4 is completed.
  • Me-Max is the maximum value of He at t2.
  • Hs-Min and He-Max are repeated until the vertical synchronization signal is input (step S12), and when the vertical synchronization signal is input, Hs-Min and Me-Max are stored (step S13). .
  • the stored Hs-Min and He-Max represent the minimum value of the video display start position and the maximum value of the end position in the frame.
  • the video monitoring processing unit 11 stores Hs-Min and He-Max when a vertical synchronization signal is input, and outputs these to the automatic clock adjustment processing unit 12.
  • the clock automatic adjustment processing unit 12 obtains the horizontal display width W of the detected video from the received Hs-Min and He-Max. That is, if Hs-Min is subtracted from He-Max, the horizontal display width W of the video in that frame can be obtained (step S14).
  • the clock automatic adjustment processing unit 12 compares the assumed horizontal display width E set in step S2 with the horizontal display width W detected in step S14, and the absolute value of the difference between the two is within a predetermined range (for example, 4 dots). If it is within the range, it is determined that the signal discrimination is correct, the set frequency division ratio is maintained, and the frequency adjustment of the reproduction dot clock is finished. If the absolute value of the difference is larger than the predetermined range, the process returns to step S11 (step S15).
  • a predetermined range for example, 4 dots
  • Fig. 6 shows an example of a screen saver.
  • the background is black and the star-shaped image moves with time. Even if the horizontal display width W of one frame is obtained at the time of receiving such a signal, the value is significantly different from the assumed horizontal display width E. Therefore, the frequency of the reproduction dot clock cannot be adjusted correctly with the conventional technology. .
  • the frequency of the reproduced dot clock can be adjusted correctly after a certain amount of time has passed.
  • FIGS. 7 (a) to 7 (f) show how Hs-Min and He-Max are updated when the star-shaped figure of the screen saver in FIG. 6 moves.
  • FIGS. 7 (a) to 7 (f) show the positions of star-shaped figures in a certain frame, respectively, and FIG. 7 (a) shows the start of the automatic clock adjustment processing.
  • Hs-Min becomes the start end of the effective video area, and has a predetermined number of clocks from the falling edge of the horizontal synchronization signal.
  • the predetermined number of clocks is stored in advance in the storage unit 14 depending on the type of signal.
  • the value of He-Max is as shown in the figure.
  • He-Max is the end of the effective video area
  • the display width W matches the effective display area (that is, the assumed display width E)
  • the minimum value of the video display start position and the maximum value of the display end position are updated for each frame.
  • the frequency of the reproduction dot clock can be adjusted correctly.
  • the minimum value of the display start position in the horizontal direction and the maximum value of the display end position are updated and held over a plurality of frames. It is possible to automatically adjust the frequency of the dot clock.
  • the screen saver is updated and held by the minimum value of the vertical display start position and the maximum value of the display end position in addition to the minimum value of the horizontal display start position and the maximum value of the display end position. Even during reception, the display area of the image can be obtained accurately.
  • the vertical display width itself is not necessary for adjusting the frequency of the reproduction dot clock, but when the control unit 5 controls the video processing unit 6, the vertical display width is accurately obtained to display the input signal more accurately. It becomes possible. Specifically, correct display is possible for signals having different aspect ratios.
  • FIG. 8 is a block diagram showing a configuration example of the second embodiment.
  • the same components as those in the first embodiment are denoted by the same reference numerals.
  • the difference from FIG. 1 is that a vertical synchronizing signal is also input to the video detection unit 4 in addition to the horizontal synchronizing signal. That is, in the second embodiment, the configuration of the video detection unit 4 is different.
  • FIG. 9 is a block diagram illustrating a configuration example of the video detection unit 4 in the second embodiment.
  • a vertical display start position detector 22 and a vertical display end position detector 23 are provided.
  • the vertical display start position detection unit 22 and the vertical display end position detection unit 23 include a counter, and use a horizontal synchronization signal as a count clock.
  • the vertical start position Vs and the vertical end position Ve start counting from, for example, the falling edge of the vertical synchronization signal, and the count value of the horizontal synchronization signal when any of RGB signals exceeds the threshold value is Vs. Further, the count value of the horizontal synchronizing signal when all the RGB signals fall below the threshold value is output as Ve.
  • four signals Hs, He, Vs, and Ve are output as video signal information.
  • the video surveillance processing unit 11 updates and stores Vs-Min and Ve-Max for each frame in addition to Hs-Min and He-Max.
  • FIG. 10 is a diagram showing how Hs-Min, He-Max, Vs-Min, and Ve-Max are updated when a screen saver is received.
  • control unit 5 can accurately detect the aspect ratio of the input signal. Can do.

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Controls And Circuits For Display Device (AREA)
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Abstract

Un dispositif d'affichage d'image selon l'invention comprend : une unité de génération d'horloge qui génère une horloge de point de lecture ; une unité de détection de synchronisation qui détecte la fréquence et le compte total de lignes verticales d'un signal de synchronisation horizontale ainsi que d'un signal de synchronisation verticale, et qui les émet sous la forme d'informations de signal de synchronisation ; une unité de détection de vidéo qui utilise ladite horloge de point de lecture pour mesurer un emplacement de début d'affichage et un emplacement de fin d'affichage d'un signal vidéo dans la direction horizontale pour l'affichage dans un signal vidéo, et qui les émet sous la forme d'informations de signal vidéo ; une unité de commande qui estime la résolution d'un signal d'entrée sur la base desdites informations de signal de synchronisation, qui donne provisoirement à un rapport de division de ladite unité de génération d'horloge une valeur imposée correspondant à la résolution, qui dérive la valeur mesurée réelle correspondant à la largeur d'affichage horizontale à partir desdites informations de signal vidéo, qui la compare à la résolution, et qui réinitialise le rapport de division ; et une unité de stockage qui stocke la valeur minimale dudit emplacement de début d'affichage ainsi que la valeur maximale dudit emplacement de fin d'affichage. Ladite unité de commande actualise et stocke la valeur minimale de l'emplacement de début d'affichage ainsi que la valeur maximale de l'emplacement de fin d'affichage en respectant des intervalles imposés, elle actualise la valeur mesurée réelle de la largeur d'affichage horizontale sur la base de la valeur minimale de l'emplacement de début d'affichage et de la valeur maximale de l'emplacement de fin d'affichage présentes dans l'unité de stockage, elle compare la valeur mesurée réelle actualisée de la largeur d'affichage horizontale à la résolution, et elle réinitialise le rapport de division.
PCT/JP2011/053337 2011-02-17 2011-02-17 Dispositif d'affichage d'image et son procédé de réglage de la fréquence d'horloge WO2012111120A1 (fr)

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PCT/JP2011/053337 WO2012111120A1 (fr) 2011-02-17 2011-02-17 Dispositif d'affichage d'image et son procédé de réglage de la fréquence d'horloge
JP2012557723A JPWO2012111120A1 (ja) 2011-02-17 2011-02-17 画像表示装置及びそのクロック周波数調整方法

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014123042A (ja) * 2012-12-21 2014-07-03 Canon Inc 表示装置及びその制御方法
JP2015135388A (ja) * 2014-01-16 2015-07-27 キヤノン株式会社 映像信号判定装置
EP2911381A4 (fr) * 2012-10-18 2016-01-13 Leyard Optoelectronic Co Ltd Procédé et dispositif de traitement d'image vidéo
CN112954432A (zh) * 2021-01-28 2021-06-11 合肥宏晶微电子科技股份有限公司 视频数据处理方法、装置、系统及可读存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1063234A (ja) * 1996-04-26 1998-03-06 Matsushita Electric Ind Co Ltd デジタル画像表示装置
JPH11311985A (ja) * 1998-04-28 1999-11-09 Matsushita Electric Ind Co Ltd 映像有効領域検出装置
JP2001013944A (ja) * 1999-06-28 2001-01-19 Matsushita Electric Ind Co Ltd サンプリングクロック発生装置、及びサンプリングクロックの発生制御プログラムが格納された記憶媒体

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1063234A (ja) * 1996-04-26 1998-03-06 Matsushita Electric Ind Co Ltd デジタル画像表示装置
JPH11311985A (ja) * 1998-04-28 1999-11-09 Matsushita Electric Ind Co Ltd 映像有効領域検出装置
JP2001013944A (ja) * 1999-06-28 2001-01-19 Matsushita Electric Ind Co Ltd サンプリングクロック発生装置、及びサンプリングクロックの発生制御プログラムが格納された記憶媒体

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2911381A4 (fr) * 2012-10-18 2016-01-13 Leyard Optoelectronic Co Ltd Procédé et dispositif de traitement d'image vidéo
JP2014123042A (ja) * 2012-12-21 2014-07-03 Canon Inc 表示装置及びその制御方法
JP2015135388A (ja) * 2014-01-16 2015-07-27 キヤノン株式会社 映像信号判定装置
CN112954432A (zh) * 2021-01-28 2021-06-11 合肥宏晶微电子科技股份有限公司 视频数据处理方法、装置、系统及可读存储介质

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