WO2012108334A1 - アクティブマトリクス基板、x線センサ装置、表示装置 - Google Patents
アクティブマトリクス基板、x線センサ装置、表示装置 Download PDFInfo
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- WO2012108334A1 WO2012108334A1 PCT/JP2012/052419 JP2012052419W WO2012108334A1 WO 2012108334 A1 WO2012108334 A1 WO 2012108334A1 JP 2012052419 W JP2012052419 W JP 2012052419W WO 2012108334 A1 WO2012108334 A1 WO 2012108334A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 239000011159 matrix material Substances 0.000 title claims abstract description 63
- 230000002093 peripheral effect Effects 0.000 claims description 18
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- 230000007423 decrease Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000011144 upstream manufacturing Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229940007424 antimony trisulfide Drugs 0.000 description 1
- NVWBARWTDVQPJD-UHFFFAOYSA-N antimony(3+);trisulfide Chemical class [S-2].[S-2].[S-2].[Sb+3].[Sb+3] NVWBARWTDVQPJD-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Definitions
- the present invention relates to an active matrix substrate having two signal lines extending in the same direction and arranged in this direction.
- signal lines (reading lines or data lines) corresponding to the same pixel column may be divided into two to achieve high speed driving and load reduction (Patent Literature). 1).
- the gap is reduced.
- the gap is reduced, there is a problem that the two signal lines are easily short-circuited in the manufacturing process.
- An object of the present invention is to suppress the occurrence of a short circuit between signal lines extending in the same direction in an active matrix substrate and arranged in this direction.
- first and second signal lines extending in the column direction are arranged in the column direction, and the first signal line is connected to the first electrode through a first transistor, and the second signal line
- the line is an active matrix substrate connected to the second electrode through the second transistor, and the first end located on the second signal line side of the both ends of the first signal line is the second signal line. It is characterized by including a tapered portion that becomes thinner as it approaches. With the above configuration, occurrence of a short circuit between the first and second signal lines can be suppressed.
- the present invention it is possible to suppress the occurrence of a short circuit between signal lines extending in the same direction on the active matrix substrate and arranged in this direction.
- FIG. 4 is a cross-sectional view taken along the line X-X ′ of FIG. 3.
- FIG. 4 is a sectional view taken along line Y-Y ′ of FIG. 3.
- It is a top view which shows the specific shape of a 1st and 2nd edge part.
- It is a top view which shows the structural example (The periphery of both the 1st and 2nd edge part is a broken line) of a 1st and 2nd edge part.
- FIG. 1 It is a top view which shows the structural example (The periphery of both the 1st and 2nd edge part is a curve) of the 1st and 2nd edge part. It is a top view which shows the modification of FIG. It is a top view which shows another modification of FIG. It is a top view which shows the structural example (only one peripheral edge of a 1st and 2nd edge part is a broken line) of a 1st and 2nd edge part. It is a top view which shows the structural example (only one peripheral edge of a 1st and 2nd edge part is a curve) of a 1st and 2nd edge part. It is a schematic diagram which shows the structure of the liquid crystal display device concerning this invention.
- FIG. 16 is a cross-sectional view taken along the line X-X ′ of FIG. 15.
- FIG. 16 is a cross-sectional view taken along the line Y-Y ′ of FIG. 15.
- It is a top view which shows the modification of FIG. It is a top view which shows another modification of FIG. It is a top view which shows another modification of FIG.
- Embodiments of the present invention will be described with reference to FIGS. 1 to 20 as follows.
- the term “column direction (the direction perpendicular to the column direction is the row direction)” is used for convenience of description, and an X-ray sensor device or a liquid crystal display device is used.
- the “column direction” may be the vertical direction or the horizontal direction.
- FIG. 1 is a schematic diagram showing the configuration of the X-ray sensor device of Example 1
- FIG. 2 is a plan view showing the configuration of a portion (part of the active matrix substrate) surrounded by a broken line in FIG. 3 is an enlarged view of a part of FIG. 2
- FIG. 4 is a sectional view taken along the line XX ′ of FIG. 3
- FIG. 5 is a sectional view taken along the line YY ′ of FIG.
- the X-ray sensor device 1s includes an active matrix substrate 3s, a gate driver GD, a first readout driver RD, a second readout driver rd, and a sensor control circuit SCC.
- the active matrix substrate 3s is provided with a first region 10a on the upstream side in the scanning direction and a second region 10b on the downstream side in the scanning direction.
- a plurality of readout lines including readout lines 14a
- a plurality of scanning lines including the scanning line 16a
- extending in the direction are arranged in the column direction (vertical direction in the figure), and extend in the column direction (scanning direction, vertical direction in the figure) in the second region 10b.
- a plurality of readout lines (including the readout line 14b) are arranged in the row direction (horizontal direction in the figure), and a plurality of scanning lines (including the scanning line 16b) extending in the row direction are arranged in the column direction (vertical direction in the figure). Are lined up.
- readout lines 14a and 14b provided corresponding to the same pixel column are arranged in the column direction (up and down in the figure), and the readout line 14a is a sensing pixel via a transistor 12a.
- the readout line 14b is connected to the electrode 17a (first electrode) and the pixel line 17b (second electrode) for sensing via the transistor 12b.
- the gate electrode 16ag of the transistor 12a is connected to the scanning line 16a (the most downstream scanning line of the first region 10a), and the source electrode 6a of the transistor 12a is connected to the readout line 14a.
- the drain electrode 7a of the transistor 12a is connected to a drain lead electrode 27a that overlaps the storage capacitor line 18a, and the drain lead electrode 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the gate electrode 16bg of the transistor 12b is connected to the scanning line 16b (the uppermost scanning line in the second region 10b), the source electrode 6b of the transistor 12b is connected to the readout line 14b, and the drain electrode 7b of the transistor 12b is
- the drain lead electrode 27b overlaps the storage capacitor line 18b, and the drain lead electrode 27b is connected to the pixel electrode 17b through the contact hole 11b.
- a gate metal including the storage capacitor wiring 18b and the gate electrode 16bg of the transistor 12b is formed on the glass substrate 31, and the gate insulating film covers the gate metal. 21 are formed, and semiconductor layers 24b, 24A, and 24B, read lines 14a and 14b, a drain lead electrode 27b, and a source metal including a source electrode and a drain electrode of the transistor 12b are stacked on the gate insulating film 21.
- an inorganic interlayer insulating film 25 and an organic interlayer insulating film 26 thicker than the inorganic interlayer insulating film 25 are stacked on the source metal, and a pixel electrode layer including the pixel electrode 17b is formed on the organic interlayer insulating film 26.
- a charge conversion layer 35 (a laminated structure of an antimony trisulfide layer 33 and a selenium layer 34) is formed on the pixel electrode layer.
- the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 are removed, and the pixel electrode 17b and the drain lead electrode 27b are in contact (contact).
- the charge conversion layer 35 supplies charges corresponding to the X-ray irradiation amount to the pixel electrode 17b.
- the gate driver GD drives the scanning lines (including the scanning lines 16a) in the first region 10a and the scanning lines (including the scanning lines 16b) in the second region 10b based on a command from the sensor control circuit SCC.
- the first read driver RD drives the read lines (including the read line 14a) of the first region 10a based on the command of the sensor control circuit SCC, and the second read driver rd receives the command of the sensor control circuit SCC. Based on this, the readout line (including the readout line 14b) in the second region 10b is driven.
- the charge accumulated in the pixel electrode 17a (charge corresponding to the amount of X-ray irradiation to the pixel electrode 17a) passes through the transistor 12a and the readout line 14a.
- the charge accumulated in the pixel electrode 17b (charge corresponding to the amount of X-ray irradiation to the pixel electrode 17b) is the transistor 12b and the read line.
- the data is read to the second read driver rd via 14b.
- the end 30a located on the side of the readout line 14b among the both ends of the readout line 14a has a symmetrical shape with respect to the row direction, and a part of the peripheral edge is convex in a direction approaching the readout line 14b.
- a tapered portion 40a (a portion that becomes narrower as it approaches the readout line 14b) formed by forming the shape of the three sides excluding the bottom of the isosceles trapezoid.
- the end 30b positioned on the side of the readout line 14a among the both ends of the readout line 14b has a symmetrical shape with respect to the row direction, and a part of the periphery thereof is a bent line that protrudes toward the readout line 14a.
- the polygonal line includes a tapered portion 40b (a portion that becomes narrower as it approaches the readout line 14a) formed by forming a shape of three sides excluding the bottom of the isosceles trapezoid. That is, the end portion 30b has a shape that is symmetrical with the end portion 30a about the line extending in the row direction through the center of the gap between the end portion 30a and the end portion 30b.
- the end portion 30a of the readout line 14a has a shape including the tapered portion 40a
- the end portion 30b of the readout line 14b has a shape including the tapered portion 40b, so that each readout line is formed.
- light from the opening of the photomask easily enters the gap region between the readout line 14a and the readout line 14b, and resist residue due to insufficient exposure amount or the like hardly occurs in the gap region.
- resist residue due to insufficient exposure amount or the like hardly occurs in the gap region.
- each of the tapered portions 40a and 40b has a periphery of three sides excluding the lower base of the isosceles trapezoidal shape, so that the angle is 4 with respect to the gap region between the readout line 14a and the readout line 14b. The light spills from the direction, and the generation of the resist residue is effectively suppressed.
- Example 1 the length of the portion along the readout line 14a in the edge of the pixel electrode 17b is made shorter than the length of the portion along the readout line 14b in the edge of the pixel electrode 17b. In addition, the influence of the parasitic capacitance between the readout lines 14a is reduced.
- FIG. 6 is a plan view showing the shapes of the end portions 30a and 30b.
- L1 to L5 are the peripheral edges of the end portion 30a.
- the minimum distance between the lines 14a and 14b is preferably greater than or equal to the distance between the source electrode 6b and the drain electrode 7b of the transistor 12b.
- the gap area between the readout line 14a and the readout line 14b receives a reflected light from the gate electrode 16bg, and the exposure amount is smaller than the gap area between the source electrode 6b and the drain electrode 7b. This is because it is easy to.
- the width of the tip of each of the tapered portions 40a and 40b (d2 in FIG. 6) is 11 ⁇ m or less when the width (d3 in FIG. 6) other than the ends of the read line 14a and the read line 14b is 13 ⁇ m.
- a short-circuit suppressing effect can be obtained by reducing one side (d4 in FIG. 6) by 1 ⁇ m or more.
- the distance (d5 in FIG. 6) between the original portion of the tapered portion 40a and the original portion of the tapered portion 40b is the width (d3 in FIG. 6) other than the end portions of the read line 14a and the read line 14b. ) Or more.
- the ends 30a and 30b in FIG. 3 may have the shapes shown in FIGS. That is, the end portion 30a includes a tapered portion 40a formed by forming a part of the peripheral edge into a polygonal line that protrudes in a direction approaching the readout line 14b, and the polygonal line forms a shape of two sides of a triangle. Further, the end portion 30b includes a tapered portion 40b that is formed by forming a part of the peripheral edge thereof into a bent line that protrudes toward the readout line 14a, and the bent line forms a shape of two sides of a triangle.
- This configuration is particularly suitable when the size of the pixel electrode is large (when the influence of the parasitic capacitance is unlikely to be different between the pixel electrode 17b and the other pixel electrodes). Compared to the shape of FIG. More light from the photomask opening from the sneak around, and the short-circuit suppressing effect is high.
- the end portion 30a includes a tapered portion 40a formed by forming a part of the peripheral edge into a polygonal line that protrudes in a direction away from the readout line 14b, and the polygonal line forms a shape of two sides of a triangle.
- the end portion 30b includes a tapered portion 40b that is formed by forming a part of the peripheral edge thereof as a bent line that protrudes in a direction away from the readout line 14a, and the bent line forms a shape of two sides of a triangle.
- edge part 30a * 30b is the shape of FIG.7 (e). That is, the end 30a is formed by forming a part of the peripheral edge into a polygonal line that protrudes away from the readout line 14b, and the polygonal line has a shape of three sides excluding the bottom of the isosceles trapezoid.
- the taper part 40a is included.
- the end portion 30b is formed by forming a part of its peripheral edge into a polygonal line that protrudes away from the readout line 14a, and this polygonal line has a shape of three sides excluding the bottom of the isosceles trapezoid.
- the taper part 40b is included.
- the end portion 30a includes a tapered portion 40a that is formed such that a part of the periphery of the end portion 30a is convex in a direction approaching the readout line 14b, and the curved line forms an arc shape.
- the end portion 30b includes a tapered portion 40b that is formed such that a part of the peripheral edge thereof is a curve that protrudes toward the readout line 14a, and this curve forms an arc shape.
- the end portions 30a and 30b may have the shapes shown in FIGS.
- the end portion 30a includes a tapered portion 40a formed by forming a part of the periphery of the end portion 30a into a convex curve in a direction approaching the readout line 14b and forming a quadratic curve.
- the end portion 30b includes a tapered portion 40b that is formed by a part of the periphery of the end portion 30b being a curve that is convex in a direction approaching the readout line 14a, and this curve forms a quadratic curve.
- the end portion 30a includes a tapered portion 40a that is formed such that a part of the periphery of the end portion 30a is convex in a direction away from the readout line 14b, and the curved line forms an arc shape.
- the end portion 30b includes a tapered portion 40b that is formed such that a part of the periphery thereof is a curve that protrudes in a direction away from the readout line 14a, and this curve forms an arc shape.
- the end portions 30a and 30b may have the shapes shown in FIGS. That is, the end portion 30a includes a tapered portion 40a formed by forming a part of the peripheral edge into a curve that protrudes in a direction away from the readout line 14b, and this curve forms a quadratic curve.
- the end portion 30b includes a tapered portion 40b that is formed by a part of the periphery of the end portion 30b being a curve that protrudes in a direction away from the readout line 14a, and this curve forms a quadratic curve.
- the gap between the readout line 14a and the readout line 14b is formed close to the scanning line 16a side, but the present invention is not limited to this. As shown in FIG. 9, this gap can be formed close to the scanning line 16b side (formed in the vicinity of the transistor 12b).
- the end portions 30a and 30b are provided with tapered portions, but the present invention is not limited to this.
- a tapered portion 40a (a portion that becomes narrower as it approaches the readout line 14b) can be provided only in the end portion 30a.
- the tapered portion 40a has a part of the periphery of the end 30a as a fold line that protrudes toward the readout line 14b, and this fold line has a shape of three sides excluding the lower base of the isosceles trapezoid. It is formed. This configuration is particularly suitable when the size of the pixel electrode is small (when the influence of parasitic capacitance is likely to be different between the pixel electrode 17b and other pixel electrodes).
- a tapered portion 40a can be provided only at the end 30a, and the configuration can be configured as shown in FIGS. 11A to 11E. Further, in FIGS. 8A to 8F, a tapered portion 40a may be provided only at the end 30a, and the configuration as shown in FIGS. 12A to 12F may be employed.
- FIG. 13 is a schematic diagram showing the configuration of the liquid crystal display device of Example 3, and FIG. 14 is a plan view showing the configuration of a portion (part of the active matrix substrate) surrounded by a broken line in FIG. 15 is an enlarged view of a part of FIG. 14, FIG. 16 is an xx ′ sectional view of FIG. 15, and FIG. 17 is a yy ′ sectional view of FIG.
- the liquid crystal display device 1d includes an active matrix substrate 3d, a gate driver GD, a first source driver SD, a second source driver sd, and a display control circuit DCC.
- the active matrix substrate 3d is provided with a first region 10a on the upstream side in the scanning direction and a second region 10b on the downstream side in the scanning direction.
- a plurality of data lines including the data lines 15a
- a plurality of scanning lines including the scanning line 16a
- the column direction vertical direction in the figure
- a plurality of data lines are arranged in the row direction (horizontal direction in the figure), and a plurality of scanning lines (including scanning lines 16b) extending in the row direction are arranged in the column direction (vertical direction in the figure). Are lined up.
- the data lines 15a and 15b provided corresponding to the same pixel column are arranged in the column direction (up and down in the figure), and the data line 15a is a display pixel via the transistor 12a.
- the data line 15b is connected to the electrode 17a (first electrode), and the data line 15b is connected to the display pixel electrode 17b (second electrode) via the transistor 12b.
- the gate electrode 16ag of the transistor 12a is connected to the scanning line 16a (the most downstream scanning line of the first region 10a), and the source electrode 6a of the transistor 12a is connected to the data
- the drain electrode 7a of the transistor 12a connected to the line 15a is connected to a drain lead electrode 27a that overlaps the storage capacitor line 18a, and the drain lead electrode 27a is connected to the pixel electrode 17a through the contact hole 11a.
- the gate electrode 16bg of the transistor 12b is connected to the scanning line 16b (the most upstream scanning line in the second region 10b), the source electrode 6b of the transistor 12b is connected to the data line 15b, and the drain electrode 7b of the transistor 12b is The drain lead electrode 27b overlaps the storage capacitor line 18b, and the drain lead electrode 27b is connected to the pixel electrode 17b through the contact hole 11b.
- the gate metal including the storage capacitor wiring 18b and the gate electrode 16bg of the transistor 12b is formed on the glass substrate 31, and the gate insulating film covers the gate metal. 21 are formed, and semiconductor layers 24b, 24A, and 24B, data lines 15a and 15b, a drain lead electrode 27b, and a source metal including a source electrode and a drain electrode of the transistor 12b are stacked on the gate insulating film 21.
- an inorganic interlayer insulating film 25 and an organic interlayer insulating film 26 thicker than the inorganic interlayer insulating film 25 are stacked on the source metal, and a transparent electrode layer (for example, ITO) including the pixel electrode 17b is formed on the organic interlayer insulating film 26. ) And an alignment film (not shown) is formed on the transparent electrode layer.
- the contact hole 11b the inorganic interlayer insulating film 25 and the organic interlayer insulating film 26 are removed, and the pixel electrode 17b and the drain lead electrode 27b are in contact (contact).
- the gate driver GD drives the scanning lines (including the scanning lines 16a) in the first region 10a and the scanning lines (including the scanning lines 16b) in the second region 10b based on a command from the display control circuit DCC.
- the first source driver SD drives the data lines (including the data line 15a) of the first region 10a based on the command from the display control circuit DCC, and the second source driver sd receives the command from the display control circuit DCC. Based on this, the data lines (including the data line 15b) in the second region 10b are driven.
- a data signal is written from the first source driver SD to the pixel electrode 17a via the transistor 12a and the data line 15a, and the scanning line 16b is selected.
- the data signal is written from the second source driver sd to the pixel electrode 17b via the transistor 12b and the data line 15b. Since the first and second regions 10a and 10b are independently driven, double speed driving is possible.
- the end 30a located on the data line 15b side among the both ends of the data line 15a has a symmetrical shape with respect to the row direction, and a part of the peripheral edge is convex in a direction approaching the data line 15b. And includes a tapered portion 40a (a portion that becomes narrower as it approaches the data line 15b) formed by forming the shape of the three sides excluding the lower base of the isosceles trapezoid.
- the end 30b located on the data line 15a side of both ends of the data line 15b has a symmetrical shape with respect to the row direction, and a part of the periphery of the end 30b is a bent line that protrudes toward the data line 15a.
- the polygonal line includes a tapered portion 40b (a portion that becomes narrower as it approaches the data line 15a) formed by forming a shape of three sides excluding the bottom of the isosceles trapezoid. That is, the end portion 30b has a shape that is symmetrical with the end portion 30a about the line extending in the row direction through the center of the gap between the end portion 30a and the end portion 30b.
- the end 30a of the data line 15a has a shape including the tapered portion 40a
- the end 30b of the data line 15b has a shape including the tapered portion 40b, so that each data line is formed.
- each of the tapered portions 40a and 40b has a periphery of three sides excluding the lower base of the isosceles trapezoid, so that it is oblique to the gap region between the data line 15a and the data line 15b. The light spills from the direction, and the generation of the resist residue is effectively suppressed.
- the length of the portion along the data line 15a in the edge of the pixel electrode 17b is made shorter than the length of the portion along the data line 15b in the edge of the pixel electrode 17b. The influence of the parasitic capacitance between the data lines 15a is reduced.
- Example 4 The end portions 30a and 30b in FIG. 14 can also be configured as shown in FIGS.
- the gap between the data line 15a and the data line 15b is formed close to the scanning line 16a side, but the present invention is not limited to this. As shown in FIG. 18, this gap can be formed close to the scanning line 16b side (formed in the vicinity of the transistor 12b).
- the transistor 12b is covered (light-shielded) with a black matrix formed on the counter substrate (color filter substrate)
- the gap between the data line 15a and the data line 15b is overlapped with the black matrix covering the transistor 12b. (The gap is covered with a black matrix and shielded from light).
- the end portions 30a and 30b are each provided with a tapered portion, but the present invention is not limited to this.
- a tapered portion 40a (a portion that becomes narrower as it approaches the data line 15b) can be provided only in the end portion 30a.
- the tapered portion 40a is formed as a polygonal line in which a part of the periphery of the end 30a is convex toward the data line 15b, and this polygonal line has a shape of three sides excluding the lower base of the isosceles trapezoid. It is formed.
- the end portions 30a and 30b can be configured as shown in FIGS.
- the edge of the pixel electrode 17b is overlapped with the data lines 15a and 15b and the scanning line 16b in order to increase the aperture ratio, but the present invention is not limited to this. As shown in FIG. 20, the edge of the pixel electrode 17b can be formed along the data lines 15a and 15b and the scanning line 16b.
- the first and second signal lines extending in the column direction are arranged in the column direction, and the first signal line is connected to the first electrode through the first transistor.
- the second signal line is an active matrix substrate connected to the second electrode through a second transistor, and the first end located on the second signal line side of both ends of the first signal line is The taper part which becomes thin as it approaches the 2nd signal line is characterized.
- a part of the edge of the second electrode may be formed along the gap between the first and second signal lines, or may be formed so as to overlap the gap.
- a part of the edge of the second electrode may be formed along the first signal line, or may be formed so as to overlap the first signal line.
- the present active matrix substrate may be configured such that the minimum distance between the first and second signal lines is equal to or greater than the distance between the source electrode and the drain electrode of the first transistor.
- the active matrix substrate may have a configuration in which the first end is symmetric with respect to the row direction.
- the tapered portion may be formed by forming a part of the periphery of the first end portion into a polygonal line shape that protrudes toward the second signal line.
- the tapered portion may be formed by forming a part of the peripheral edge of the first end portion into a polygonal line shape that protrudes away from the second signal line.
- the polygonal line shape may be a shape of three sides excluding the bottom of the isosceles trapezoid.
- the polygonal line shape may be a shape of two sides of a triangle.
- the tapered portion may be formed by forming a part of the peripheral edge of the first end portion into a curved shape that protrudes toward the second signal line.
- the tapered portion may be formed by forming a part of the periphery of the first end portion into a curved shape that protrudes away from the second signal line.
- the curved shape may be an arc shape.
- the curve shape may be a quadratic curve shape.
- the second end portion located on the first signal line side of both end portions of the second signal line may include a tapered portion that becomes narrower as it approaches the first signal line.
- the second end portion may have a shape that is symmetrical with the first end portion with a line extending in the row direction passing through the gap between the first and second end portions as an axis. it can.
- the first and second electrodes may be configured for sensing. In the present active matrix substrate, the first and second electrodes may be configured for display.
- the X-ray sensor device includes the active matrix substrate.
- This display device includes the active matrix substrate.
- the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
- the present display device is suitable for a radiation detector (for example, an X-ray sensor device) and a large-sized / high-definition display device (for example, a television receiver, a digital signage, a medical monitor).
- a radiation detector for example, an X-ray sensor device
- a large-sized / high-definition display device for example, a television receiver, a digital signage, a medical monitor.
Abstract
Description
図1は、実施例1のX線センサ装置の構成を示す模式図であり、図2は、図1の破線で囲んだ部分(アクティブマトリクス基板の一部)の構成を示す平面図であり、図3は、図2の一部の拡大図である、また、図4は、図3のX-X’断面図であり、図5は図3のY-Y’断面図である。
図3の端部30a・30bを図7(a)~(c)の形状としてもよい。すなわち、端部30aは、その周縁の一部が、読み出し線14bに近づく向きに凸となる折れ線とされ、この折れ線が三角形の2辺の形状をなすことで形成される先細り部40aを含む。また、端部30bは、その周縁の一部が、読み出し線14aに近づく向きに凸となる折れ線とされ、この折れ線が三角形の2辺の形状をなすことで形成される先細り部40bを含む。この構成は、特に、画素電極のサイズが大きい場合(画素電極17bと他の画素電極とで寄生容量の影響が異なり難い場合)に好適であり、図6の形状と比較して、斜め4方向からのフォトマスク開口部の光がより多くまわり込み、短絡抑制効果が高い。
図13は、実施例3の液晶表示装置の構成を示す模式図であり、図14は、図13の破線で囲んだ部分(アクティブマトリクス基板の一部)の構成を示す平面図であり、図15は、図14の一部の拡大図である、また、図16は、図15のx-x’断面図であり、図17は図15のy-y’断面図である。
図14の端部30a・30bは、図7および図8のように構成することもできる。
本アクティブマトリクス基板では、上記第1および第2電極は表示用である構成とすることもできる。
1d 液晶表示装置
3s 3d アクティブマトリクス基板
16a 走査線(第1走査線)
16b 走査線(第2走査線)
17a 画素電極(第1電極)
17b 画素電極(第2電極)
12a トランジスタ(第1トランジスタ)
12b トランジスタ(第2トランジスタ)
14a 読み出し線(第1信号線)
14b 読み出し線(第2信号線)
15a データ線(第1信号線)
15b データ線(第2信号線)
30a (読み出し線14aあるいはデータ線15aの)端部
30b (読み出し線14bあるいはデータ線15bの)端部
40a (端部30aの)先細り部
40b (端部30bの)先細り部
Claims (19)
- 列方向に延伸する第1および第2信号線が列方向に並べられ、上記第1信号線は第1トランジスタを介して第1電極に接続されるとともに、上記第2信号線は第2トランジスタを介して第2電極に接続されたアクティブマトリクス基板であって、
上記第1信号線の両端部のうち第2信号線側に位置する第1端部は、第2信号線に近づくにつれて細くなる先細り部を含むアクティブマトリクス基板。 - 第2電極のエッジの一部が、第1および2信号線の間隙に沿うように形成されているか、あるいは上記間隙に重なるように形成されている請求項1記載のアクティブマトリクス基板。
- 第2電極のエッジの一部が、第1信号線に沿うように形成されているか、あるいは第1信号線に重なるように形成されている請求項1記載のアクティブマトリクス基板。
- 第1および第2信号線の最小距離が、第1トランジスタのソース電極およびドレイン電極の距離以上とされている請求項1記載のアクティブマトリクス基板。
- 上記第1端部が行方向に関して対称な形状となっている請求項1記載のアクティブマトリクス基板。
- 上記先細り部は、第1端部の周縁の一部を、第2信号線に近づく向きに凸となる折れ線形状とすることで形成される請求項1記載のアクティブマトリクス基板。
- 上記先細り部は、第1端部の周縁の一部を、第2信号線から離れる向きに凸となる折れ線形状とすることで形成される請求項1記載のアクティブマトリクス基板。
- 上記折れ線形状が等脚台形の下底を除く3辺の形状である請求項6または7記載のアクティブマトリクス基板。
- 上記折れ線形状が三角形の2辺の形状である請求項6または7記載のアクティブマトリクス基板。
- 上記先細り部は、第1端部の周縁の一部を、第2信号線に近づく向きに凸となる曲線形状とすることで形成される請求項1記載のアクティブマトリクス基板。
- 上記先細り部は、第1端部の周縁の一部を、第2信号線から離れる向きに凸となる曲線形状とすることで形成される請求項1記載のアクティブマトリクス基板。
- 上記曲線形状が円弧形状である請求項10または11記載のアクティブマトリクス基板。
- 上記曲線形状が二次曲線形状である請求項10または11記載のアクティブマトリクス基板。
- 上記第2信号線の両端部のうち第1信号線側に位置する第2端部は、第1信号線に近づくにつれて細くなる先細り部を含む請求項1~13のいずれか1項に記載のアクティブマトリクス基板。
- 上記第2端部は、第1および第2端部の間隙を通り行方向に延伸する線を軸として第1端部と線対称となる形状を有する請求項7記載のアクティブマトリクス基板。
- 上記第1および第2電極はセンシング用である請求項1記載のアクティブマトリクス基板。
- 上記第1および第2電極は表示用である請求項1記載のアクティブマトリクス基板。
- 請求項16記載のアクティブマトリクス基板を含むX線センサ装置。
- 請求項17記載のアクティブマトリクス基板を含む表示装置。
Priority Applications (3)
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US13/982,569 US8941185B2 (en) | 2011-02-09 | 2012-02-02 | Active matrix substrate, x-ray sensor device, display device |
CN201280007217.4A CN103348474B (zh) | 2011-02-09 | 2012-02-02 | 有源矩阵基板、x射线传感装置、显示装置 |
JP2012556850A JP5542973B2 (ja) | 2011-02-09 | 2012-02-02 | アクティブマトリクス基板、x線センサ装置、表示装置 |
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JP2011-026403 | 2011-02-09 | ||
JP2011026403 | 2011-02-09 |
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PCT/JP2012/052419 WO2012108334A1 (ja) | 2011-02-09 | 2012-02-02 | アクティブマトリクス基板、x線センサ装置、表示装置 |
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US (1) | US8941185B2 (ja) |
JP (1) | JP5542973B2 (ja) |
CN (1) | CN103348474B (ja) |
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US9461072B2 (en) * | 2013-12-25 | 2016-10-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display array substrates and a method for manufacturing the same |
JP6523803B2 (ja) * | 2015-06-10 | 2019-06-05 | キヤノン電子管デバイス株式会社 | アレイ基板、および放射線検出器 |
CN112234088B (zh) * | 2017-04-21 | 2023-04-18 | 群创光电股份有限公司 | 显示装置 |
CN110619825B (zh) * | 2019-10-31 | 2022-01-04 | 錼创显示科技股份有限公司 | 电极结构、微型发光元件以及显示面板 |
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KR101430639B1 (ko) * | 2008-03-17 | 2014-08-18 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판 및 이를 포함하는 표시 장치 |
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CN103348474A (zh) | 2013-10-09 |
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US8941185B2 (en) | 2015-01-27 |
JP5542973B2 (ja) | 2014-07-09 |
CN103348474B (zh) | 2016-05-04 |
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