WO2012106889A1 - 接收机及其接收方法 - Google Patents

接收机及其接收方法 Download PDF

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Publication number
WO2012106889A1
WO2012106889A1 PCT/CN2011/077140 CN2011077140W WO2012106889A1 WO 2012106889 A1 WO2012106889 A1 WO 2012106889A1 CN 2011077140 W CN2011077140 W CN 2011077140W WO 2012106889 A1 WO2012106889 A1 WO 2012106889A1
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WO
WIPO (PCT)
Prior art keywords
signal
frequency
local oscillator
intermediate frequency
oscillating
Prior art date
Application number
PCT/CN2011/077140
Other languages
English (en)
French (fr)
Inventor
何卓彪
吴剑锋
马正翔
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN2011800013063A priority Critical patent/CN102308484B/zh
Priority to PCT/CN2011/077140 priority patent/WO2012106889A1/zh
Publication of WO2012106889A1 publication Critical patent/WO2012106889A1/zh
Priority to US14/086,726 priority patent/US9401732B2/en
Priority to US15/189,751 priority patent/US9634706B2/en
Priority to US15/458,757 priority patent/US9843350B2/en
Priority to US15/807,544 priority patent/US10326485B2/en
Priority to US16/442,572 priority patent/US10911087B2/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/26—Circuits for superheterodyne receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/26—Circuits for superheterodyne receivers
    • H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/30—Circuits for homodyne or synchrodyne receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W84/00—Network topologies
    • H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
    • H04W84/04—Large scale networks; Deep hierarchical networks
    • H04W84/042—Public Land Mobile systems, e.g. cellular systems

Definitions

  • Embodiments of the present invention relate to the field of communications, and more particularly, to a receiver and a method of receiving the same. Background technique
  • the base station or the radio frequency integrated circuit (RFIC) receivers are basically single-band reception at the same time, and the future evolution requirement is ultra-wideband multi-band simultaneous reception. There is currently no good solution for multi-band simultaneous reception.
  • the most straightforward basic architecture is achieved by single or parallel connection of two or more single-band receivers.
  • the channels of multiple frequency bands are all based on the DIF (Digital Intermediate Frequency) architecture, the cost, area, and power consumption of the receiver are several times that of the single-band frequency band.
  • DIF Digital Intermediate Frequency
  • the cost, area, and power consumption of the receiver are several times that of the single-band frequency band.
  • the 3G (3 rd Generation, third generation) / 4G (4 th Generation, fourth generation) base stations the large number of elements, the power consumption is large, and each channel VCO (Voltage Controlled Oscillator, Voltage-Controlled Oscillator )
  • VCO Voltage Controlled Oscillator, Voltage-Controlled Oscillator
  • the integration degree of each channel can be improved, but the cost, area, and power consumption of the receiver are several times that of the single frequency band.
  • ZIF zero intermediate frequency
  • the image rejection and second2 (input second-order intercept point) problems will limit the practical application, and the VCO of each channel.
  • the frequencies are independent of each other and the frequency is close, so it is not suitable for single chip integration.
  • a solution in the prior art can use a zero-IF architecture in some channels and a super-heterodyne architecture in other channels to combine the advantages of zero-IF and super-heterodyne architectures, such as linearity such as 3G/4G.
  • linearity such as 3G/4G.
  • the signal goes to the zero-IF channel, and the 2G ( 2nd Generation, second generation) and other signals with high linearity require the super-heterodyne channel.
  • the inventors have found that the VCO frequencies of the respective channels are independent of each other and the frequency is relatively close, and it is still not suitable for single chip integration, which increases the complexity of the solution configuration. Summary of the invention
  • Embodiments of the present invention provide a receiver and a receiving method thereof, which can implement monolithic integration of multiple receiving channels.
  • a receiver including: a zero intermediate frequency channel, performing IQ down conversion on a radio frequency signal of a first frequency band by using a frequency division or frequency multiplication signal of a first oscillation signal; using a first super-heterodyne channel The frequency-divided or multi-frequency signal of the oscillating signal down-converts the radio frequency signal of the second frequency band, wherein the first frequency band and the second frequency band are different.
  • a receiver receiving method includes a zero intermediate frequency channel and a super heterodyne channel, the method comprising: receiving a first oscillation signal; and using a frequency division of the first oscillation signal by a zero intermediate frequency channel Or the frequency multiplied signal performs IQ down conversion on the radio frequency signal of the first frequency band; the superheterodyne channel down-converts the radio frequency signal of the second frequency band by using the frequency division or frequency multiplication signal of the first oscillation signal, where the first The frequency band is different from the second frequency band.
  • the zero intermediate frequency channel and the super heterodyne channel of the embodiment of the present invention use the same oscillating signal or the frequency dividing or frequency doubling signal of the oscillating signal, thereby overcoming the problem that the oscillating signals caused by the two channels are integrated, thereby achieving multiple Monolithic integration of receive channels.
  • FIG. 1 is a schematic block diagram of a receiver in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic block diagram of a receiver in accordance with one embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a receiver according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a receiver in accordance with another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a receiver according to another embodiment of the present invention.
  • FIG. 6 is a flow chart of a receiving method in accordance with an embodiment of the present invention. detailed description
  • GSM code division multiple access
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GSM General Packet Radio Service
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • UE User Equipment
  • the radio access network for example, RAN
  • Radio Access Network communicates with one or more core networks, which may be mobile terminals, such as mobile phones (or “cellular” phones) and computers with mobile terminals, for example, portable, pocket, handheld Mobile computers built into the computer, or in-vehicle, that exchange language and/or data with the wireless access network.
  • mobile terminals such as mobile phones (or "cellular" phones) and computers with mobile terminals, for example, portable, pocket, handheld Mobile computers built into the computer, or in-vehicle, that exchange language and/or data with the wireless access network.
  • the base station may be a base station (BTS, Base Transceiver Station) in GSM or CDMA, or may be a base station (NodeB) in WCDMA, or may be an evolved base station (eNB or e-NodeB, evolutional Node B) in LTE.
  • BTS Base Transceiver Station
  • NodeB base station
  • eNB evolved base station
  • e-NodeB evolutional Node B
  • FIG. 1 is a schematic block diagram of a receiver in accordance with an embodiment of the present invention.
  • the receiver 10 of Figure 1 can be located in a base station or user equipment, including a zero intermediate frequency channel 11 and a superheterodyne channel 12.
  • Zero IF channel 11 uses the first oscillating signal VI to divide the frequency or multiplier signal to the first frequency band
  • the BAND1 RF signal is IQ (In-phase/Quadrature) downconverted.
  • the superheterodyne channel 12 downconverts the radio frequency signal of the second frequency band BAND2 using the divided or multiplied signal of the first oscillating signal VI.
  • the first frequency band BAND1 is different from the second frequency band BAND2.
  • the zero intermediate frequency channel and the super heterodyne channel of the embodiment of the present invention use the same oscillating signal or the frequency dividing or frequency doubling signal of the oscillating signal, thereby overcoming the problem that the oscillating signals caused by the two channels are integrated, thereby achieving multiple Monolithic integration of receive channels.
  • the divided or multiplied signal of the first oscillating signal VI includes the first oscillating signal VI itself (i.e., can be regarded as 1 octave).
  • the first oscillating signal VI itself (i.e., can be regarded as 1 octave).
  • the first oscillating signal VI itself (i.e., can be regarded as 1 octave).
  • only one zero intermediate frequency channel 11 and one superheterodyne channel 12 are depicted for cleaning.
  • embodiments of the invention are not limited thereto.
  • more zero intermediate frequency channels 11 or more superheterodyne channels 12 can be used as needed, as long as the two channels use the frequency division or multiplication signals of the same oscillation signal.
  • BAND 1 may be a frequency band belonging to 3G/4G
  • BAND2 may be other frequency bands belonging to 2G/3G/4G, but the embodiment of the present invention is not limited thereto.
  • the signal with high reception requirement can go through the heterodyne channel 12, which can reduce the burden on the duplexer and facilitate the miniaturization of the duplexer.
  • the 2G receiving superheterodyne channel of the embodiment of the invention does not have problems such as in-band image suppression.
  • the 3G/4G zero-IF channel can be integrated into the chip together with LPF (Low Pass Filter) / ADC (Analog-Digit Converter).
  • the first oscillating signal VI may be derived from an oscillator integrated in the receiver, or may be an oscillating signal received from an oscillator external to the receiver, which is not limited in this embodiment of the present invention.
  • the first oscillator 11 for generating the first oscillating signal VI is included in the receiver, but the embodiment of the present invention is not limited thereto.
  • the receiver of the embodiment of the present invention can receive the first oscillating signal VI from the outside.
  • auxiliary components such as amplifiers (including fixed gain amplifiers, variable gain amplifiers) may be added before, between, or after the respective components as needed.
  • filters including RF filters, anti-aliasing filters, etc.
  • Some or all of these auxiliary components may be integrated with the necessary components shown below according to actual needs, or may be located outside the integrated chip.
  • FIG. 2 is a schematic block diagram of a receiver in accordance with one embodiment of the present invention.
  • the receiver of Figure 2 includes a zero intermediate frequency channel 11, a superheterodyne channel 12, and a first oscillator 13.
  • the first oscillator 13 generates a first oscillating signal VI and supplies the first oscillating signal VI to the zero IF channel 11 and the superheterodyne channel 12.
  • the first oscillating signal VI is directly sent to the two channels.
  • the embodiment of the present invention is not limited thereto, and the VI may be separately divided or multiplied and then sent to the two channels separately.
  • One implementation of the first oscillator 13 is a voltage controlled oscillator VCO. Alternatively, the frequency range of the first oscillator 13 can be adjusted.
  • the zero intermediate frequency channel 11 includes a first local oscillator unit 111 and a first mixer 112.
  • the first local oscillation unit 111 receives the first oscillation signal VI and generates a first IQ local oscillation signal IQ1 according to the first oscillation signal VI.
  • the first mixer 112 receives the first IQ local oscillator signal IQ1, and performs IQ down-conversion on the radio frequency signal BAND1 of the first frequency band by using the first IQ local oscillator signal IQ1 to generate a first baseband signal B1, and the first baseband signal B1 is used. For analog to digital conversion.
  • the superheterodyne channel 12 includes a second local oscillator unit 121 and a second mixer 122.
  • the second local oscillator unit 121 receives the first oscillating signal VI, and divides or multiplies the first oscillating signal VI to generate a first super-heterodyne local oscillator signal L1.
  • the second mixer 122 receives the first super-heterodyne local oscillator signal L1 and down-converts the radio frequency signal BAND2 of the second frequency band using the first super-heterodyne local oscillator signal L1 to generate a first intermediate frequency signal M1.
  • the base station simultaneously receives two frequency bands.
  • Signals for UMTS BAND I (corresponding to BAND1) and DCS1800 (corresponding to BAND2).
  • the DCS 1800 band generally has GSM requirements
  • the UMTS BAND I generally has no GSM requirements.
  • the antenna simultaneously receives signals of two frequency bands. After the signals of the two frequency bands are separated by the front duplexer (or filter), the DCS 1800 frequency band signal goes to the superheterodyne channel 12, and the UMTS BAND I band signal goes to the zero intermediate frequency channel 11.
  • the two channels share the same VCO 13, and are sent to the first mixer 112 of the zero intermediate frequency channel 11 and the second mixer 122 of the super heterodyne channel 12 through different frequency dividing ratio and frequency multiplication ratio circuits, respectively.
  • the frequency is divided by two to generate the IQ local oscillator (IQ1) to provide the local oscillator signal to the UMTS BAND I.
  • the VCO frequency is divided by 4 to provide 975MHz.
  • the local oscillator signal (L1) provides the first superheterodyne local oscillator to the superheterodyne channel.
  • the UMTS BAND I is directly changed to zero frequency, and then sent to the ADC for sampling after the on-chip or external controllable gain amplifier and anti-aliasing low-pass filter.
  • the first intermediate frequency signal M1 may be directly used for analog-to-digital conversion, for example, the first intermediate frequency signal M1 is subjected to anti-aliasing filtering. It is sampled directly by the ADC. In this way, there is no need to change the process again, which saves the BOM (Bill of Material) and realizes the single-chip dual-band requirement.
  • the first intermediate frequency signal M1 does not meet the input frequency range requirement of the ADC, for example, the performance of the ADC device is insufficient, the first intermediate frequency signal M1 can be further down-converted.
  • An embodiment in which the first intermediate frequency signal M1 is further down-converted is described below.
  • FIG. 3 is a schematic structural diagram of a receiver according to another embodiment of the present invention.
  • the same elements as in Fig. 2 are given the same reference numerals.
  • the superheterodyne channel 12 of FIG. 3 further includes a second oscillator 123 and a third mixer 124.
  • the second oscillator 123 generates a second super-heterodyne local oscillation signal L2.
  • the second oscillator 123 in Fig. 3 directly sends the second super-heterodyne local oscillator signal L2 to the third mixer 124, but the embodiment of the present invention is not limited thereto.
  • the vibration signal L2 is supplied to the third mixer 124.
  • two oscillators 13 and 123 are used in the embodiment of FIG. 3, and embodiments of the present invention are not limited thereto.
  • the two oscillators can be combined into one oscillator with a variable frequency output.
  • the third mixer 124 receives the second super-heterodyne local oscillator signal L2, and down-converts the first intermediate frequency signal M1 using the second super-heterodyne local oscillator signal L2 to generate a second intermediate frequency signal M2, and a second intermediate frequency signal M2. Used for analog to digital conversion.
  • the output frequency becomes 735MHz ⁇ 810MHz (the first intermediate frequency signal Ml).
  • the first intermediate frequency signal M1 can be further mixed by the third mixer 124, and converted into a suitable second intermediate frequency signal M2 (for example, 100 ⁇ 200MHz) for sampling by the ADC.
  • the frequency division ratio multiplication ratio of the second local oscillation unit 121 in Fig. 3 is configurable.
  • Zero-IF channel 11 can include a bandwidth configurable low-pass filter to support different receive bandwidth requirements.
  • the superheterodyne channel 12 can include a variable gain amplifier to adjust the gain of the IF VGA, zero IF VGA, and reduce the dynamic demand on the ADC.
  • L2 can also support a wider adjustment range to ensure that the frequency of the second intermediate frequency signal M2 is appropriate.
  • the first intermediate frequency signal M1 when the output frequency of the first intermediate frequency signal M1 is high or the in-band image rejection is strictly required, the first intermediate frequency signal M1 can be subjected to secondary frequency conversion to satisfy high performance occasions.
  • FIG. 4 is a schematic structural diagram of a receiver in accordance with another embodiment of the present invention.
  • the same elements as in Fig. 2 are given the same reference numerals.
  • the zero intermediate frequency channel 11 is used to downconvert the first intermediate frequency signal M1 outputted by the superheterodyne channel 12 (as indicated by the dashed arrow in Fig. 4), thereby saving the number of components.
  • the first oscillator 13 also generates a second oscillating signal V2.
  • the first local oscillator unit 111 also receives the second oscillating signal V2 and generates a second IQ local oscillator signal IQ2 based on the second oscillating signal V2.
  • the frequencies of the first oscillation signal VI and the second oscillation signal V2 may be the same or different.
  • the first oscillator 13 can be a variable frequency output oscillator.
  • the first mixer 112 receives the second IQ local oscillator signal IQ2 and the first intermediate frequency signal M1, and performs IQ down-conversion on the first intermediate frequency signal M1 using the second IQ local oscillator signal IQ2 to generate a second baseband signal B2, the second baseband Signal B2 is used to perform analog to digital conversion.
  • the embodiment of FIG. 4 can reduce the type and number of devices, and the same device can support two frequency band reception, mainly after the super-heterodyne channel 12 is subjected to the first frequency conversion (the first intermediate frequency signal M1 ) can be sent to the same chip.
  • the first intermediate frequency signal M1 the first intermediate frequency signal M1
  • the VGA gain adjustment can be performed on the first intermediate frequency signal M1, so that the GSM multi-carrier image suppression requirement is relaxed. If the zero intermediate frequency channel IQ is used to demodulate the first intermediate frequency signal M1 to the zero frequency (the second baseband signal B2), the operating frequency is low, Image rejection performance and ⁇ 2 performance are better.
  • the first frequency conversion is a super-heterodyne channel frequency conversion
  • the second frequency conversion is a zero-IF frequency channel frequency conversion
  • a frequency-to-zero-frequency architecture zero-IF channel conversion
  • 3G/4G multi-carrier signals it is difficult to satisfy the problem that the image suppression of the 2G base station multi-carrier directly changes to zero frequency is difficult to satisfy, and ⁇ 2 is difficult to satisfy.
  • FIG. 5 is a schematic structural diagram of a receiver according to another embodiment of the present invention.
  • the same elements as in Fig. 2 are given the same reference numerals.
  • the second mixer 122 using the superheterodyne channel 12 again downconverts the first intermediate frequency signal M1 outputted by the superheterodyne channel 12 (as indicated by the dashed arrow in FIG. 5). Save on the number of components.
  • the first oscillator 13 also generates a third oscillating signal V3.
  • the second local oscillator unit 122 also receives the third oscillating signal V3 and divides or multiplies the third oscillating signal V3 to generate a third super-heterodyne local oscillator signal L3.
  • the second mixer 122 further receives the third super-heterodyne local oscillator signal L3 and the first intermediate frequency signal M1, and down-converts the first intermediate frequency signal M1 using the third super-heterodyne local oscillator signal L3 to generate a third intermediate frequency signal M3.
  • the third intermediate frequency signal M3 is used for analog to digital conversion.
  • the embodiment of Figure 5 is capable of reducing the type and number of devices.
  • the 2G base station signal (BAND2) can be further converted to an arbitrary intermediate frequency through the super-heterodyne channel 12 of the same chip, and then sent to the ADC for sampling and quantization.
  • the frequency setting of L3 is different from the L1 frequency setting.
  • the frequency range of the first oscillator 13 in the designed chip can be adjusted, and the frequencies of the output oscillating signals VI and V3 are different, so that the frequencies of L1 and L3 are different.
  • the frequencies of the oscillating signals VI and V3 output by the first oscillator 13 may be the same, and the frequency range of the first oscillator 13 cannot be adjusted.
  • the frequency dividing ratio of the second local oscillator unit 121 can be adjusted so that the output L1 and The frequency of L3 is different.
  • the crossover ratio of the superheterodyne channel 12 and the second stage local oscillator are flexibly configurable, enhancing the flexibility of the IF selection flexibility of the superheterodyne channel and the flexibility of the ADC sampling rate selection.
  • the zero intermediate frequency channel 11 and the super heterodyne channel 12 share an oscillating signal.
  • the local oscillator signal L1 of the super-heterodyne channel can be obtained by dividing or doubling the oscillating signal VI, and the frequency division ratio or multiplier can be configured.
  • the signal of the super-heterodyne channel 12 can be converted to the baseband through the zero-IF channel 11 of the same chip, or can be sampled by another independent chip to the low-IF frequency, or after the same superheterodyne.
  • Channel 12 is downconverted to a low IF post-sampling, or it can be directly sampled by the ADC.
  • the 2G/3G/4G receiving and other signals requiring higher signals go beyond the heterodyne channel, and the super-heterodyne reduces the burden on the duplexer, which is advantageous for miniaturization of the duplexer, and the 2G receiving super-heterodyne is not There are problems with in-band mirror suppression.
  • the 3G/4G zero-IF channel can integrate LPF/ADC into the chip.
  • the super-heterodyne channel division ratio and the second-level local oscillator can be flexibly configured to enhance the MF selection flexibility of the superheterodyne channel.
  • Embodiments of the present invention overcome the problem of VCO interactions encountered by the integration of two channels in a single cartridge, enabling integration of two or more receiving channels operating simultaneously.
  • a single chip coding can be used to meet the combination of different frequency bands of different 2G/3G/4G systems, and the BOM component type is minimized.
  • the intermediate frequency selection of the superheterodyne channel is more flexible, and the optimal combination can be selected in terms of duplexer size and ADC requirements; the zero-IF channel greatly enlarges the BOM, and the integration degree is high, and the integration can be included in the ADC. Mixed signal components within.
  • FIG. 6 is a flow chart of a receiving method in accordance with an embodiment of the present invention.
  • the receiving method of Fig. 6 can be performed by the receiver 10 of Fig. 1.
  • the receiving method of Fig. 6 will be described with reference to Fig. 1 .
  • Step 61 Acquire a first oscillating signal VI.
  • a first oscillating signal VI For example, an oscillator that can be internal to the receiver 10
  • the first oscillator 13 in Fig. 2-5) generates a first oscillating signal VI or receives a first oscillating signal VI from an oscillator external to the receiver 10.
  • Step 62 Perform in-phase quadrature IQ down-conversion on the radio frequency signal of the first frequency band by using the frequency division or frequency multiplication signal of the first oscillation signal VI, and use the frequency division or frequency multiplication signal of the first oscillation signal VI to the radio frequency of the second frequency band.
  • the signal is subjected to super-heterodyne down-conversion, wherein the first frequency band and the second frequency band are different.
  • the zero intermediate frequency channel and the super heterodyne channel of the embodiment of the present invention use the same oscillating signal or the frequency dividing or frequency doubling signal of the oscillating signal, thereby overcoming the problem that the oscillating signals caused by the two channels are integrated, thereby achieving multiple Monolithic integration of receive channels.
  • the divided or multiplied signal of the first oscillating signal VI includes the first oscillating signal VI itself (i.e., can be regarded as 1 octave).
  • BAND 1 may be a frequency band belonging to 3G/4G
  • BAND2 may be other frequency bands belonging to 2G/3G/4G
  • the embodiment of the present invention is not limited thereto.
  • the signal having a higher reception requirement can go through the heterodyne channel 12, which can reduce the burden on the duplexer and the like, and facilitates miniaturization of the duplexer.
  • the 2G receiving superheterodyne channel of the embodiment of the present invention does not exist in the band. Problems such as image suppression.
  • the 3G/4G zero-IF channel can be integrated into the chip together with LPF (Low Pass Filter) / ADC (Analog-Digit Converter).
  • LPF Low Pass Filter
  • ADC Analog-Digit Converter
  • the signals converted by the superheterodyne channel 12 can be subjected to the second frequency conversion to the baseband through the zero intermediate frequency channel 11 of the same chip. It can also be sampled by another independent chip down-converted to a low-IF frequency, or down-converted to the low-IF frequency after the same superheterodyne channel 12, or directly sampled by the ADC.
  • the first local oscillator signal IQ1 may be generated by the first local oscillation unit 111 based on the first oscillation signal VI. Then, the first mixer unit 112 uses the first IQ local oscillator signal IQ1 to IQ down-convert the radio frequency signal BAND1 of the first frequency band to generate a first baseband signal Bl.
  • the first baseband signal B1 is used for analog to digital conversion.
  • the first oscillating signal VI may be generated by the first oscillator 11 or externally received by the first oscillating signal VI.
  • the first oscillation signal VI may be divided or multiplied by the second local oscillation unit 121 to generate a first super-heterodyne local oscillation signal L1.
  • the second mixer 122 uses the first super-heterodyne local oscillator signal L1 to down-convert the radio frequency signal BAND2 of the second frequency band to generate a first intermediate frequency signal M1.
  • the first intermediate frequency signal M1 may be directly used for analog-to-digital conversion, for example, the first intermediate frequency signal M1 is subjected to anti-aliasing filtering. It is sampled directly by the ADC.
  • the first intermediate frequency signal M1 satisfies the input frequency range requirement of the ADC, the first intermediate frequency signal M1 can be directly used for analog to digital conversion. In this way, the embodiment of the present invention does not need another frequency conversion process, which can save BOM and realize single-chip dual-band demand.
  • a second superheterodyne local oscillator signal L2 can be generated by the second oscillator 123. Then, the first intermediate frequency signal M1 is down-converted by the third mixer 124 using the second super-heterodyne local oscillator signal L2 to generate a second intermediate frequency signal M2. The second intermediate frequency signal M2 is used for analog to digital conversion.
  • the first intermediate frequency signal M1 of the embodiment of the present invention can perform secondary frequency conversion to meet high performance occasions.
  • the second oscillator signal V2 may be further generated by the first oscillator 13, and at this time, the second local oscillator unit 111 generates a second according to the second oscillation signal V2.
  • IQ local oscillator signal IQ2 IQ local oscillator signal IQ2.
  • the frequencies of the first oscillation signal VI and the second oscillation signal V2 may be the same or different.
  • the first intermediate frequency signal M1 is IQ down-converted by the first mixer 112 using the second IQ local oscillator signal IQ2 to generate a second baseband signal B2.
  • the second baseband signal B2 is used to perform analog to digital conversion.
  • the embodiment of the present invention can reduce the type and number of devices, and the same device can support the reception of two frequency bands.
  • a third oscillating signal V3 may also be generated by the first oscillator 13.
  • the third oscillation signal V3 is divided or multiplied by the second local oscillation unit 122 to generate a third super-heterodyne local oscillation signal L3.
  • the first intermediate frequency signal M1 is down-converted by the second mixer 122 using the third super-heterodyne local oscillator signal L3 to generate a third intermediate frequency signal M3.
  • the third intermediate frequency signal M3 is used for analog to digital conversion.
  • embodiments of the present invention can also reduce the number and variety of devices.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the unit described as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, may be located in one place. Or it can be distributed to multiple network elements. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software function unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention may contribute to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program codes. .

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Description

接收机及其接收方法 技术领域
本发明实施例涉及通信领域，并且更具体地，涉及接收机及其接收方法。 背景技术
目前基站或 波传输或终端 RFIC ( Radio Frequency Integrated Circuit, 射频集成电路）接收机基本上都是同一时刻只是单频段接收， 未来的演进需 求是超宽带多频段同时接收。 多频段同时接收的解决方案目前没有好的解决 方案， 最直接的基本架构是通过两个或多个单频段接收机筒单并联实现。
如果多个频段的通道均采用超外差数字中频（ DIF, Digital Intermediate Frequency )架构， 则接收机的成本、 面积、 功耗是单频段的频段数倍。 对于 3G ( 3rd Generation, 第三代） /4G ( 4th Generation, 第四代）基站而言， 元件 数量较多、功耗较大，并且各个通道的 VCO (压控振荡器， Voltage-Controlled Oscillator )频率相互独立且频率较近， 不宜单片集成。
如果多个频段的通道均采用零中频（ ZIF, Zero Intermediate Frequency ) 架构， 则每个通道的集成度能有所提高， 但是接收机的成本、 面积、 功耗是 单频段的频段数倍。用在基站 GSM( Global System of Mobile communication, 全球移动通信系统） 多载波接收时， 镜像抑制和 ΠΡ2 ( input second-order intercept point, 输入二阶截点）问题将制约实际应用， 并且各个通道的 VCO 频率相互独立且频率较近， 不宜单片集成。
现有技术中有一种解决方案可以在部分通道中采用零中频架构并在其 他通道中采用超外差架构， 以结合零中频和超外差架构各自的优势， 例如使 得 3G/4G等线性度等要求不高的场合信号走零中频通道, 2G( 2nd Generation, 第二代）等线性度要求高的信号走超外差通道。 但是， 发明人在实现本发明 的过程中发现， 各个通道的 VCO频率相互独立且频率较近， 仍然不宜单片 集成， 增加了解决方案配置的复杂度。 发明内容
本发明实施例提供一种接收机及其接收方法， 能够实现多个接收通道的 单片集成。 一方面， 提供了一种接收机， 包括： 零中频通道， 使用第一振荡信号的 分频或倍频信号对第一频段的射频信号进行 IQ下变频； 超外差通道， 使用 所述第一振荡信号的分频或倍频信号对第二频段的射频信号进行下变频， 其 中所述第一频段和第二频段不同。
另一方面， 提供了一种接收机的接收方法， 接收机包括零中频通道和超 外差通道， 所述方法包括： 接收第一振荡信号； 零中频通道使用所述第一振 荡信号的分频或倍频信号对第一频段的射频信号进行 IQ下变频； 超外差通 道使用所述第一振荡信号的分频或倍频信号对第二频段的射频信号进行下 变频， 其中所述第一频段和第二频段不同。
本发明实施例的零中频通道和超外差通道使用同一振荡信号或者该振 荡信号的分频或倍频信号，克服了筒单集成两种通道引起的振荡信号相互影 响的问题， 从而能够实现多个接收通道的单片集成。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图 仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造 性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1是根据本发明实施例的接收机的示意框图。
图 2是根据本发明一个实施例的接收机的示意结构图。
图 3是根据本发明另一实施例的接收机的示意结构图。
图 4是根据本发明另一实施例的接收机的示意结构图。
图 5是根据本发明另一实施例的接收机的示意结构图。
图 6是根据本发明实施例的接收方法的流程图。 具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是 全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创 造性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本发明的技术方案， 可以应用于各种通信系统， 例如： GSM, 码分多址 ( CDMA, Code Division Multiple Access ) 系统， 宽带码分多址（ WCDMA, Wideband Code Division Multiple Access Wireless ) , 通用分组无线业务
( GPRS , General Packet Radio Service ) , 长期演进 （LTE , Long Term Evolution )等。
用户设备（ UE , User Equipment ), 可以经无线接入网 （例如， RAN ,
Radio Access Network )与一个或多个核心网进行通信， 用户设备可以是移动 终端， 如移动电话（或称为"蜂窝"电话）和具有移动终端的计算机， 例如， 可以是便携式、 袖珍式、 手持式、 计算机内置的或者车载的移动装置， 它们 与无线接入网交换语言和 /或数据。
基站，可以是 GSM或 CDMA中的基站（ BTS, Base Transceiver Station ), 也可以是 WCDMA中的基站（ NodeB ) ,还可以是 LTE中的演进型基站（ eNB 或 e-NodeB , evolutional Node B ), 本发明并不限定。
图 1是根据本发明实施例的接收机的示意框图。 图 1的接收机 10可以 位于基站或用户设备中， 包括零中频通道 11和超外差通道 12。
零中频通道 11 使用第一振荡信号 VI 的分频或倍频信号对第一频段
BAND1的射频信号进行 IQ ( In-phase/Quadrature, 同相正交） 下变频。
超外差通道 12使用该第一振荡信号 VI 的分频或倍频信号对第二频段 BAND2的射频信号进行下变频。
其中第一频段 BAND1和第二频段 BAND2不同。
本发明实施例的零中频通道和超外差通道使用同一振荡信号或者该振 荡信号的分频或倍频信号，克服了筒单集成两种通道引起的振荡信号相互影 响的问题， 从而能够实现多个接收通道的单片集成。
本发明实施例中， 第一振荡信号 VI的分频或倍频信号包括第一振荡信 号 VI本身（即， 可以看作是 1倍频）。 图 1的实施例中， 为了筒洁， 只描绘 了一个零中频通道 11和一个超外差通道 12。 但是本发明实施例不限于此。 本发明实施例可以根据需要采用更多个零中频通道 11 或者更多个超外差通 道 12,只要这两种通道使用同一振荡信号的分频或倍频信号即可。这些修改 均落入本发明的范围内。
例如， BAND 1可以是属于 3G/4G的频段， BAND2可以是属于 2G/3G/4G 的其他频段， 但本发明实施例不限于此。 一般而言， 对接收要求较高的信号 可以走超外差通道 12, 这样可以减轻双工器等负担， 利于双工器小型化， 本 发明实施例的 2G接收超外差通道不存在带内镜像抑制等问题。 3G/4G走零 中频通道， 可以将 LPF ( Low Pass Filter, 低通滤波器） /ADC ( Analog-Digit Converter, 模数转换器）等一并集成到片内。
第一振荡信号 VI可以来自接收机中集成的振荡器， 也可以是从接收机 外部的振荡器接收的振荡信号， 本发明实施例对此不做限制。
下面结合具体例子， 更加详细地描述本发明实施例。 下面的例子中， 接 收机中包括用于生成第一振荡信号 VI的第一振荡器 11 , 但本发明实施例不 限于此。 本发明实施例的接收机可以从外部接收第一振荡信号 VI。
另外， 下面各个例子的电路图中仅仅显示了必要元件， 但本发明实施例 不限于此， 可以按照需要在各个元件之前、 之间或之后增加辅助元件， 例如 放大器（包括固定增益放大器、 可变增益放大器等）、 滤波器（包括 RF滤波 器、 抗混叠滤波器等）。 这些辅助元件中的部分或全部元件可以根据实际需 要和下面所示的必要元件集成在一起， 也可以位于集成芯片之外。
图 2是根据本发明一个实施例的接收机的示意结构图。 图 2的接收机包 括零中频通道 11、 超外差通道 12和第一振荡器 13。
第一振荡器 13生成第一振荡信号 VI , 并将第一振荡信号 VI送给零中 频通道 11和超外差通道 12。 虽然图 2的实施例中， 第一振荡信号 VI直接 送给两种通道， 但是本发明实施例不限于此， 也可以将 VI经分频或倍频后 再分别送给两种通道。 第一振荡器 13的一个实现方式是压控振荡器 VCO。 可选地， 第一振荡器 13的频率范围可调节。
零中频通道 11包括第一本振单元 111和第一混频器 112。第一本振单元 111接收第一振荡信号 VI , 并根据第一振荡信号 VI生成第一 IQ本振信号 IQ1。 第一混频器 112接收第一 IQ本振信号 IQ1 , 并使用第一 IQ本振信号 IQ1对第一频段的射频信号 BAND1进行 IQ下变频，生成第一基带信号 B1 , 第一基带信号 B1用于进行模数转换。
超外差通道 12包括第二本振单元 121和第二混频器 122。第二本振单元 121接收第一振荡信号 VI , 将第一振荡信号 VI分频或倍频， 以生成第一超 外差本振信号 Ll。 第二混频器 122接收第一超外差本振信号 L1 , 并使用第 一超外差本振信号 L1对第二频段的射频信号 BAND2进行下变频， 生成第 一中频信号 Ml。
举例来说， 假设图 2的接收机位于基站中， 并且基站同时接收两个频段 UMTS BAND I (对应于 BAND1 )和 DCS1800 (对应于 BAND2 ) 的信号。 DCS 1800频段一般有 GSM需求， UMTS BAND I一般无 GSM需求。天线同 时接收两个频段的信号， 两个频段的信号经过前段双工器（或滤波器）分开 频段后， DCS 1800频段信号走超外差通道 12, UMTS BAND I频段信号走零 中频通道 11。 两个通道共享同一 VCO 13, 经过不同的分频比、 倍频比等电 路分别送给零中频通道 11的第一混频器 112和超外差通道 12的第二混频器 122。 筒单举例： 将 VCO 13的振荡频率 VI选为 1950MHzx2=3900MHz, 该 频率经过二分频后产生 IQ本振（ IQ1 )给 UMTS BAND I提供本振信号， 该 VCO频率经过 4分频后提供 975MHz本振信号 （ L1 )给超外差通道提供第 一超外差本振。 UMTS BAND I经过模拟 IQ下变频后直接变到了零频，后接 片内或皮外可控增益放大器、 抗混叠低通滤波器后等送给 ADC 采样。 DCS 1800 频段信号经过 975MHz 信号变频后输 出 频率变为 (1710MHz~1785MHz)-975MHz=735MHz~810MHz (第一中频信号 Ml )。
可选地， 在一个实施例中， 如果第一中频信号 Ml满足 ADC的输入频 率范围要求， 可以直接将第一中频信号 Ml用于进行模数转换， 例如第一中 频信号 Ml经过抗混叠滤波器后直接由 ADC采样。 这样， 无需再一次变频 过程， 可以节省 BOM ( Bill of Material, 元器件清单）， 实现单芯片双频段需 求。
如果第一中频信号 Ml不能满足 ADC的输入频率范围要求， 例如 ADC 器件的性能不够， 可以对第一中频信号 Ml进一步进行下变频处理。 下面描 述对第一中频信号 Ml进一步下变频的实施例。
图 3是根据本发明另一实施例的接收机的示意结构图。图 3的接收机中， 与图 2相同的元件采用相同的附图标记。
除了第二本振单元 121和第二混频器 122之外， 图 3的超外差通道 12 还包括第二振荡器 123和第三混频器 124。
第二振荡器 123生成第二超外差本振信号 L2。 图 3 中第二振荡器 123 将第二超外差本振信号 L2直接送给第三混频器 124, 但本发明实施例不限 于此。在第二振荡器 123和第三混频器 124之间也可以存在分频 /倍频的元件， 将第二振荡器 123 生成的振荡信号经分频 /倍频后作为第二超外差本振信号 L2送给第三混频器 124。
另外， 图 3的实施例中使用两个振荡器 13和 123,本发明实施例不限于 此， 可以将两个振荡器合并为一个可变频率输出的振荡器。
第三混频器 124接收第二超外差本振信号 L2, 并使用第二超外差本振 信号 L2对第一中频信号 Ml进行下变频， 生成第二中频信号 M2, 第二中频 信号 M2用于进行模数转换。
还是使用上面所述的例子， DCS1800频段信号 （对应于 BAND2 ) 经过
975MHz信号变频后输出频率变为 735MHz~810MHz (第一中频信号 Ml )。 第一中频信号 Ml可以再经过第三混频器 124的一次混频， 变频为合适的第 二中频信号 M2 (比如 100~200MHz )后供 ADC采样。
图 3中第二本振单元 121的分频比倍频比可配置。 零中频通道 11中可 包含带宽可配置的低通滤波器， 以支持不同接收带宽需求。 超外差通道 12 中可包含可变增益放大器， 以调节中频 VGA、 零中频 VGA的增益， 降低对 ADC的动态需求。 图 3中 L2也可支持较宽的调节范围， 保证第二中频信号 M2的频率合适。
在超外差通道 12中第一中频信号 Ml的输出频率较高或带内镜像抑制 有严格要求时， 第一中频信号 Ml可以进行二次变频， 满足高性能场合。
图 4是根据本发明另一实施例的接收机的示意结构图。图 4的接收机中， 与图 2相同的元件采用相同的附图标记。 图 4的实施例中， 采用零中频通道 11对超外差通道 12输出的第一中频信号 Ml进行下变频（如图 4中的虚线 箭头所示）， 能够节省元件数目。
第一振荡器 13还生成第二振荡信号 V2。 第一本振单元 111还接收第二 振荡信号 V2, 并根据第二振荡信号 V2生成第二 IQ本振信号 IQ2。 这里， 第一振荡信号 VI和第二振荡信号 V2的频率可以相同， 也可以不同。 在两 者不同的情况下， 第一振荡器 13可以是一个可变频率输出的振荡器。
第一混频器 112接收第二 IQ本振信号 IQ2和第一中频信号 Ml ,使用第 二 IQ本振信号 IQ2对第一中频信号 Ml进行 IQ下变频，生成第二基带信号 B2, 第二基带信号 B2用于进行模数转换。
图 4的实施例能够减少器件种类和数目， 采用同一种器件可以支持两个 频段接收，主要体现在超外差通道 12经过第一次变频后（第一中频信号 Ml ) 可以送入相同芯片的零中频通道 11。此时可以对第一中频信号 Ml进行 VGA 增益调节， 从而使得 GSM多载波镜像抑制要求有所放宽。 如果使用零中频 通道 IQ解调第一中频信号 Ml到零频（第二基带信号 B2 ), 工作频率较低， 镜像抑制性能、 ΠΡ2性能较好。 因此， 能够实现针对 2G基站多载波信号采 用两次变频到零频的架构（第一次变频为超外差通道变频， 第二次变频为零 中频通道变频）。 针对 3G/4G多载波信号实施一次变频到零频的架构 （零中 频通道变频）。从而克服 2G基站多载波直接变到零频面临的镜像抑制难以满 足、 ΠΡ2难以满足的问题。
图 5是根据本发明另一实施例的接收机的示意结构图。图 5的接收机中， 与图 2相同的元件采用相同的附图标记。 图 5的实施例中， 采用超外差通道 12的第二混频器 122再次对超外差通道 12输出的第一中频信号 Ml进行下 变频（如图 5中的虚线箭头所示）， 能够节省元件数目。
第一振荡器 13还生成第三振荡信号 V3。 第二本振单元 122还接收第三 振荡信号 V3, 并将第三振荡信号 V3分频或倍频， 以生成第三超外差本振信 号 L3。
第二混频器 122还接收第三超外差本振信号 L3和第一中频信号 Ml ,使 用第三超外差本振信号 L3对第一中频信号 Ml进行下变频， 生成第三中频 信号 M3, 第三中频信号 M3用于进行模数转换。
图 5的实施例能够减少器件种类和数目。 例如， 2G基站信号（BAND2 ) 经过第一次变频到第一中频信号 （Ml )后可以再经过相同芯片的超外差通 道 12再一次变频到任意中频， 再送给 ADC采样量化。 其中 L3的频率设置 不同于 L1频率设置。例如，所设计芯片中第一振荡器 13的频率范围可调节， 输出的振荡信号 VI和 V3的频率不同， 从而使得 L1和 L3的频率不同。 或 者， 第一振荡器 13输出的振荡信号 VI和 V3的频率可以相同， 第一振荡器 13的频率范围不能调节，此时第二本振单元 121的分频比可调节，使得输出 的 L1和 L3的频率不同。
超外差通道 12的分频比和第二级本振可灵活配置， 增强了超外差通道 的中频选择灵活性和 ADC采样率选择的灵活性。
本发明实施例中， 零中频通道 11和超外差通道 12共享振荡信号。 超外 差通道的本振信号 L1可以是经过该振荡信号 VI—定分频或倍频后得到， 这个分频比或倍频数可配置。
超外差通道 12变频后的信号可以经过相同的芯片的零中频通道 11完成 第二次变频到基带， 也可经过另外一颗独立的芯片下变频到低中频后采样， 或者经过同一超外差通道 12下变频到低中频后采样， 也可直接 ADC采样。 当接收机在基站中时， 2G/3G/4G接收等要求较高的信号走超外差通道， 超外差减轻了双工器等负担， 利于双工器小型化， 2G接收超外差不存在带 内镜像抑制等问题。 3G/4G走零中频通道， 可以将 LPF/ADC等一并集成到 片内； 超外差通道分频比和第二级本振可灵活配置， 增强了超外差通道的中 频选择灵活性和 ADC采样率选择的灵活性。
本发明实施例克服了筒单集成两个通道所遇到的 VCO 相互影响的问 题， 使得能够集成同时工作的两个或多个接收通道。 通过本发明实施例， 可 以采用单个芯片编码来满足 2G/3G/4G不同制式的各不同频段的组合， 实现 了 BOM元件种类的最少化。
本发明实施例中超外差通道的中频选择更加灵活， 进而可以在双工器尺 寸、 ADC要求等方面选取最优的组合； 零中频通道极大筒化了 BOM, 集成 度高， 可以集成包括 ADC在内的混合信号部件。
图 6是根据本发明实施例的接收方法的流程图。 图 6的接收方法可以由 图 1的接收机 10执行。 参照图 1描述图 6的接收方法。
步骤 61 , 获取第一振荡信号 VI。 例如， 可以由接收机 10内部的振荡器
(如图 2-5中的第一振荡器 13 )生成第一振荡信号 VI , 或者从接收机 10外 部的振荡器接收第一振荡信号 VI。
步骤 62,使用第一振荡信号 VI的分频或倍频信号对第一频段的射频信 号进行同相正交 IQ下变频，使用第一振荡信号 VI的分频或倍频信号对第二 频段的射频信号进行超外差下变频， 其中第一频段和第二频段不同。
本发明实施例的零中频通道和超外差通道使用同一振荡信号或者该振 荡信号的分频或倍频信号，克服了筒单集成两种通道引起的振荡信号相互影 响的问题， 从而能够实现多个接收通道的单片集成。
本发明实施例中， 第一振荡信号 VI的分频或倍频信号包括第一振荡信 号 VI本身 （即， 可以看作是 1倍频）。
例如， BAND 1可以是属于 3G/4G的频段， BAND2可以是属于 2G/3G/4G 的其他频段， 但本发明实施例不限于此。 一般而言， 对接收要求较高的信号 可以走超外差通道 12, 这样可以减轻双工器等负担， 利于双工器小型化， 本 发明实施例的 2G接收超外差通道不存在带内镜像抑制等问题。 3G/4G走零 中频通道， 可以将 LPF ( Low Pass Filter, 低通滤波器） /ADC ( Analog-Digit Converter, 模数转换器）等一并集成到片内。 可通过图 2-图 5所示的接收机来实现图 6的接收方法的各个过程，超外 差通道 12变频后的信号可以经过相同的芯片的零中频通道 11完成第二次变 频到基带， 也可经过另外一颗独立的芯片下变频到低中频后采样， 或者经过 同一超外差通道 12下变频到低中频后采样， 也可直接 ADC采样。
例如， 参照图 2, 在图 6的步骤 62中， 可由第一本振单元 111根据第一 振荡信号 VI生成第一 IQ本振信号 IQ1。 然后， 由第一混频器 112使用第一 IQ本振信号 IQ1对第一频段的射频信号 BAND1进行 IQ下变频， 生成第一 基带信号 Bl。 该第一基带信号 B1用于进行模数转换。
可选地，在一个实施例中，第一振荡信号 VI可以由第一振荡器 11生成， 或者从外部接收第一振荡信号 VI。
另外， 在图 6的步骤 62中， 可由第二本振单元 121将第一振荡信号 VI 分频或倍频， 以生成第一超外差本振信号 Ll。 然后， 由第二混频器 122使 用第一超外差本振信号 L1对第二频段的射频信号 BAND2进行下变频， 生 成第一中频信号 Ml。
可选地， 在一个实施例中， 如果第一中频信号 Ml满足 ADC的输入频 率范围要求， 可以直接将第一中频信号 Ml用于进行模数转换， 例如第一中 频信号 Ml经过抗混叠滤波器后直接由 ADC采样。
如果第一中频信号 Ml满足 ADC的输入频率范围要求， 可以直接将第 一中频信号 Ml用于进行模数转换。 这样， 本发明实施例无需再一次变频过 程， 可以节省 BOM , 实现单芯片双频段需求。
参照图 3,在图 6的步骤 62中，可由第二振荡器 123生成第二超外差本 振信号 L2。 然后， 由第三混频器 124使用第二超外差本振信号 L2对第一中 频信号 Ml进行下变频， 生成第二中频信号 M2。 该第二中频信号 M2用于 进行模数转换。
在超外差通道 12中第一中频信号 Ml的输出频率较高或带内镜像抑制 有严格要求时， 本发明实施例的第一中频信号 Ml可以进行二次变频， 满足 高性能场合。
可选地， 在另一实施例中， 参照图 4, 可以由第一振荡器 13还可以生成 第二振荡信号 V2, 此时， 由第一本振单元 111根据第二振荡信号 V2生成第 二 IQ本振信号 IQ2。 这里， 第一振荡信号 VI和第二振荡信号 V2的频率可 以相同， 也可以不同。 然后，由第一混频器 112使用第二 IQ本振信号 IQ2对第一中频信号 Ml 进行 IQ下变频， 生成第二基带信号 B2。 该第二基带信号 B2用于进行模数 转换。
这样， 本发明实施例能够减少器件种类和数目， 采用同一种器件可以支 持两个频段接收。
可选地， 在另一实施例中， 参照图 5, 还可以由第一振荡器 13生成第三 振荡信号 V3。 由第二本振单元 122将第三振荡信号 V3分频或倍频， 以生成 第三超外差本振信号 L3。
然后， 由第二混频器 122使用第三超外差本振信号 L3对第一中频信号 Ml进行下变频， 生成第三中频信号 M3。 该第三中频信号 M3用于进行模数 转换。
这样， 本发明实施例也能够减少器件种类和数目。
本领域普通技术人员可以意识到， 结合本文中所公开的实施例描述的各 示例的单元及算法步骤， 能够以电子硬件、 计算机软件或者二者的结合来实 现， 为了清楚地说明硬件和软件的可互换性， 在上述说明中已经按照功能一 般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执 行， 取决于技术方案的特定应用和设计约束条件。 专业技术人员可以对每个 特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超 出本发明的范围。
所属领域的技术人员可以清楚地了解到， 为描述的方便和筒洁， 上述描 述的接收方法的具体工作过程， 可以参考前述装置实施例中的对应过程， 在 此不再赘述。
在本申请所提供的几个实施例中， 应该理解到， 所揭露的系统、 装置和 方法， 可以通过其它的方式实现。 例如， 以上所描述的装置实施例仅仅是示 意性的， 例如， 所述单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可 以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个 系统， 或一些特征可以忽略， 或不执行。 另一点， 所显示或讨论的相互之间 的耦合或直接耦合或通信连接可以是通过一些接口， 装置或单元的间接耦合 或通信连接， 可以是电性， 机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作 为单元显示的部件可以是或者也可以不是物理单元， 即可以位于一个地方， 或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或 者全部单元来实现本实施例方案的目的。
另外， 在本发明各个实施例中的各功能单元可以集成在一个处理单元 中， 也可以是各个单元单独物理存在， 也可以两个或两个以上单元集成在一 个单元中。 上述集成的单元既可以采用硬件的形式实现， 也可以采用软件功 能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销 售或使用时， 可以存储在一个计算机可读取存储介质中。 基于这样的理解， 本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方 案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在 一个存储介质中， 包括若干指令用以使得一台计算机设备（可以是个人计算 机， 服务器， 或者网络设备等）执行本发明各个实施例所述方法的全部或部 分步骤。 而前述的存储介质包括： U盘、 移动硬盘、 只读存储器（ROM, Read-Only Memory )、 随机存取存储器 ( RAM, Random Access Memory )、 磁碟或者光盘等各种可以存储程序代码的介质。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应所述以权利要求的保护范围为准。

Claims

权利要求
1、 一种接收机， 其特征在于， 包括：
零中频通道， 用于使用第一振荡信号的分频或倍频信号对第一频段的射 频信号进行同相正交 IQ下变频；
超外差通道， 用于使用所述第一振荡信号的分频或倍频信号对第二频段 的射频信号进行下变频， 其中所述第一频段和第二频段不同。
2、 如权利要求 1所述的接收机， 其特征在于， 还包括：
第一振荡器， 用于生成所述第一振荡信号。
3、 如权利要求 1或 2所述的接收机， 其特征在于， 所述零中频通道包 括：
第一本振单元， 用于接收所述第一振荡信号， 并根据所述第一振荡信号 生成第一 IQ本振信号；
第一混频器， 用于接收所述第一 IQ本振信号， 并使用所述第一 IQ本振 信号对所述第一频段的射频信号进行 IQ下变频， 生成第一基带信号， 所述 第一基带信号用于进行模数转换。
4、 根据权利要求 3所述的接收机， 其特征在于， 所述超外差通道包括： 第二本振单元， 用于接收所述第一振荡信号， 将所述第一振荡信号分频 或倍频， 以生成第一超外差本振信号；
第二混频器， 用于接收所述第一超外差本振信号， 并使用所述第一超外 差本振信号对所述第二频段的射频信号进行下变频， 生成第一中频信号。
5、 根据权利要求 4所述的接收机， 其特征在于， 所述第一中频信号用 于进行模数转换。
6、 根据权利要求 4所述的接收机， 其特征在于， 所述超外差通道还包 括：
第二振荡器， 用于生成第二超外差本振信号；
第三混频器， 用于接收所述第二超外差本振信号， 并使用所述第二超外 差本振信号对所述第一中频信号进行下变频， 生成第二中频信号， 所述第二 中频信号用于进行模数转换。
7、 根据权利要求 4所述的接收机， 其特征在于，
所述第一振荡器还用于生成第二振荡信号； 所述第一本振单元还用于接收所述第二振荡信号， 并根据所述第二振荡 信号生成第二 IQ本振信号；
所述第一混频器还用于接收所述第二 IQ 本振信号和所述第一中频信 号， 使用所述第二 IQ本振信号对所述第一中频信号进行 IQ下变频， 生成第 二基带信号， 所述第二基带信号用于进行模数转换。
8、 根据权利要求 7所述的接收机， 其特征在于，
所述第一振荡信号与第二振荡信号的频率相同或不同。
9、 根据权利要求 4所述的接收机， 其特征在于，
所述第一振荡器还用于生成第三振荡信号；
所述第二本振单元还用于接收所述第三振荡信号， 并将所述第三振荡信 号分频或倍频， 以生成第三超外差本振信号；
所述第二混频器还用于接收所述第三超外差本振信号和所述第一中频 信号， 使用所述第三超外差本振信号对所述第一中频信号进行下变频， 生成 所述第三中频信号， 所述第三中频信号用于进行模数转换。
10、 一种接收机的接收方法， 其特征在于， 包括：
获取第一振荡信号；
使用所述第一振荡信号的分频或倍频信号对第一频段的射频信号进行 同相正交 IQ下变频；
使用所述第一振荡信号的分频或倍频信号对第二频段的射频信号进行 超外差下变频， 其中所述第一频段和第二频段不同。
11、 如权利要求 10所述的方法， 其特征在于， 所述使用所述第一振荡 信号的分频或倍频信号对第一频段的射频信号进行同相正交 IQ 下变频包 括：
根据所述第一振荡信号生成第一 IQ本振信号；
使用所述第一 IQ本振信号对所述第一频段的射频信号进行 IQ下变频， 生成第一基带信号， 所述第一基带信号用于进行模数转换。
12、 如权利要求 11 所述的方法， 其特征在于， 所述使用所述第一振荡 信号的分频或倍频信号对第二频段的射频信号进行超外差下变频包括：
将所述第一振荡信号分频或倍频， 以生成第一超外差本振信号； 使用所述第一超外差本振信号对所述第二频段的射频信号进行下变频， 生成第一中频信号。
13、 根据权利要求 12所述的方法， 其特征在于， 还包括： 将所述第一 中频信号用于进行模数转换。
14、 根据权利要求 12所述的方法， 其特征在于， 所述使用所述第一振 荡信号的分频或倍频信号对第二频段的射频信号进行超外差下变频， 还包 括：
生成第二超外差本振信号；
使用所述第二超外差本振信号对所述第一中频信号进行下变频， 生成第 二中频信号， 所述第二中频信号用于进行模数转换。
15、 根据权利要求 12所述的方法， 其特征在于， 还包括：
生成第二振荡信号；
根据所述第二振荡信号生成第二 IQ本振信号；
使用所述第二 IQ本振信号对所述第一中频信号进行 IQ下变频，生成第 二基带信号， 所述第二基带信号用于进行模数转换。
16、 根据权利要求 12所述的方法， 还包括：
生成第三振荡信号；
将所述第三振荡信号分频或倍频， 以生成第三超外差本振信号； 使用所述第三超外差本振信号对所述第一中频信号进行下变频， 生成所 述第三中频信号， 所述第三中频信号用于进行模数转换。
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US9401732B2 (en) 2016-07-26
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US20160301438A1 (en) 2016-10-13
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US10326485B2 (en) 2019-06-18
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US20200162119A1 (en) 2020-05-21
US10911087B2 (en) 2021-02-02

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