WO2012103712A1 - Cpu互联装置 - Google Patents

Cpu互联装置 Download PDF

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Publication number
WO2012103712A1
WO2012103712A1 PCT/CN2011/076430 CN2011076430W WO2012103712A1 WO 2012103712 A1 WO2012103712 A1 WO 2012103712A1 CN 2011076430 W CN2011076430 W CN 2011076430W WO 2012103712 A1 WO2012103712 A1 WO 2012103712A1
Authority
WO
WIPO (PCT)
Prior art keywords
qpi
interface module
data
serdes
cpu
Prior art date
Application number
PCT/CN2011/076430
Other languages
English (en)
French (fr)
Inventor
常胜
杨荣玉
侯新宇
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN2011800009797A priority Critical patent/CN102301364B/zh
Priority to PCT/CN2011/076430 priority patent/WO2012103712A1/zh
Publication of WO2012103712A1 publication Critical patent/WO2012103712A1/zh
Priority to US13/707,188 priority patent/US8909979B2/en
Priority to US13/707,209 priority patent/US8990460B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3852—Converter between protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
PCT/CN2011/076430 2011-06-27 2011-06-27 Cpu互联装置 WO2012103712A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2011800009797A CN102301364B (zh) 2011-06-27 2011-06-27 Cpu互联装置
PCT/CN2011/076430 WO2012103712A1 (zh) 2011-06-27 2011-06-27 Cpu互联装置
US13/707,188 US8909979B2 (en) 2011-06-27 2012-12-06 Method and system for implementing interconnection fault tolerance between CPU
US13/707,209 US8990460B2 (en) 2011-06-27 2012-12-06 CPU interconnect device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/076430 WO2012103712A1 (zh) 2011-06-27 2011-06-27 Cpu互联装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2011/076471 Continuation-In-Part WO2012167461A1 (zh) 2011-06-27 2011-06-28 Cpu间互联容错的实现方法及系统
US13/707,209 Continuation US8990460B2 (en) 2011-06-27 2012-12-06 CPU interconnect device

Publications (1)

Publication Number Publication Date
WO2012103712A1 true WO2012103712A1 (zh) 2012-08-09

Family

ID=45360527

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/076430 WO2012103712A1 (zh) 2011-06-27 2011-06-27 Cpu互联装置

Country Status (3)

Country Link
US (1) US8990460B2 (zh)
CN (1) CN102301364B (zh)
WO (1) WO2012103712A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2778939A3 (en) * 2013-03-15 2015-08-26 Intel Corporation Optical memory extension architecture
TWI507868B (zh) * 2014-12-15 2015-11-11 Inventec Corp 快速通道互聯匯流排的壓力測試方法和壓力測試裝置

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US8909979B2 (en) * 2011-06-27 2014-12-09 Huawei Technologies Co., Ltd. Method and system for implementing interconnection fault tolerance between CPU
WO2012103712A1 (zh) 2011-06-27 2012-08-09 华为技术有限公司 Cpu互联装置
CN105229621B (zh) 2013-05-16 2018-08-28 慧与发展有限责任合伙企业 多模式代理器
CN103916276B (zh) * 2014-04-11 2018-03-06 华为技术有限公司 具有多通道绑定接口的设备和系统及其快速初始化方法
CN104408014A (zh) * 2014-12-23 2015-03-11 浪潮电子信息产业股份有限公司 一种计算系统之间处理单元互连的系统及方法
CN105892347B (zh) * 2015-01-26 2018-10-30 北京电子工程总体研究所 一种基于仲裁技术的双单片机检测装置及方法
CN108701117B (zh) * 2017-05-04 2022-03-29 华为技术有限公司 互连系统、互连控制方法和装置
CN107239376B (zh) * 2017-06-23 2020-12-01 苏州浪潮智能科技有限公司 一种服务器互联芯片的自动化调试方法及装置
CN107480332B (zh) * 2017-07-07 2021-03-09 苏州浪潮智能科技有限公司 一种fpga芯片、高速接口互联系统及实现互联的方法
CN107423178A (zh) * 2017-07-17 2017-12-01 天津市英贝特航天科技有限公司 一种 Serdes接口测试方法及系统
US11296921B2 (en) * 2017-12-03 2022-04-05 Intel Corporation Out-of-band management of FPGA bitstreams
CN107977519A (zh) * 2017-12-07 2018-05-01 郑州云海信息技术有限公司 一种高速互联接口的自动化检错机制
JP7020991B2 (ja) * 2018-05-01 2022-02-16 株式会社東芝 信号制御回路
CN110008157A (zh) * 2019-04-02 2019-07-12 北京工业大学 一种串行解串器的硬件架构
RU206189U1 (ru) * 2021-04-23 2021-08-30 Федеральное государственное унитарное предприятие "Государственный научно-исследовательский институт авиационных систем" (ФГУП "ГосНИИАС") Плата сопряжения компьютера с внешними устройствами для организации информационного обмена по оптическому каналу связи

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US20090083518A1 (en) * 2007-09-25 2009-03-26 Glew Andrew F Attaching and virtualizing reconfigurable logic units to a processor
CN101753388A (zh) * 2008-11-28 2010-06-23 中国科学院微电子研究所 适用于多核处理器片上和片间扩展的路由及接口装置
CN101930422A (zh) * 2010-08-26 2010-12-29 浪潮电子信息产业股份有限公司 一种基于多层ahb总线的多核cpu互连结构

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US8909979B2 (en) * 2011-06-27 2014-12-09 Huawei Technologies Co., Ltd. Method and system for implementing interconnection fault tolerance between CPU
US8719843B2 (en) 2011-07-27 2014-05-06 Intel Corporation Virtualizable and forward-compatible hardware-software interface
RU2633126C2 (ru) * 2013-02-28 2017-10-11 Интел Корпорейшн Усиление механизма перечисления и/или конфигурации одного протокола межсоединений для другого протокола межсоединений

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090083518A1 (en) * 2007-09-25 2009-03-26 Glew Andrew F Attaching and virtualizing reconfigurable logic units to a processor
CN101753388A (zh) * 2008-11-28 2010-06-23 中国科学院微电子研究所 适用于多核处理器片上和片间扩展的路由及接口装置
CN101930422A (zh) * 2010-08-26 2010-12-29 浪潮电子信息产业股份有限公司 一种基于多层ahb总线的多核cpu互连结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2778939A3 (en) * 2013-03-15 2015-08-26 Intel Corporation Optical memory extension architecture
TWI507868B (zh) * 2014-12-15 2015-11-11 Inventec Corp 快速通道互聯匯流排的壓力測試方法和壓力測試裝置

Also Published As

Publication number Publication date
CN102301364A (zh) 2011-12-28
US20130103875A1 (en) 2013-04-25
CN102301364B (zh) 2013-01-02
US8990460B2 (en) 2015-03-24

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