WO2012098903A1 - Dispositif de visualisation d'image et procédé de commande pour dispositif de visualisation d'image - Google Patents

Dispositif de visualisation d'image et procédé de commande pour dispositif de visualisation d'image Download PDF

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Publication number
WO2012098903A1
WO2012098903A1 PCT/JP2012/000336 JP2012000336W WO2012098903A1 WO 2012098903 A1 WO2012098903 A1 WO 2012098903A1 JP 2012000336 W JP2012000336 W JP 2012000336W WO 2012098903 A1 WO2012098903 A1 WO 2012098903A1
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Prior art keywords
code
subfield
gradation
error
image signal
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PCT/JP2012/000336
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English (en)
Japanese (ja)
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広史 本田
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パナソニック株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2059—Display of intermediate tones using error diffusion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge

Definitions

  • the present invention relates to an image display device that displays an image in an image display region by combining binary control of light emission and non-light emission in a light emitting element that constitutes a pixel, and a driving method of the image display device.
  • a plasma display panel (hereinafter abbreviated as “panel”) is a typical image display device that displays an image in an image display area by combining binary control of light emission and non-light emission in a light emitting element constituting a pixel. is there.
  • a large number of discharge cells which are light-emitting elements constituting pixels, are formed between a front substrate and a rear substrate that are arranged to face each other.
  • a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other.
  • a dielectric layer and a protective layer are formed so as to cover the display electrode pairs.
  • the back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.
  • the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed.
  • a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.
  • ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.
  • a subfield method is generally used as a method for displaying an image in an image display region by combining binary control of light emission and non-light emission in a light emitting element.
  • each discharge cell In the subfield method, one field is divided into a plurality of subfields having different emission luminances.
  • each discharge cell light emission / non-light emission of each subfield is controlled by a combination according to a desired gradation value.
  • each discharge cell emits light with the emission luminance of one field set to a desired gradation value, and an image composed of various combinations of gradation values is displayed in the image display area of the panel.
  • each subfield has an address period and a sustain period.
  • the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed.
  • an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).
  • the number of sustain pulses based on the gradation weights determined for each subfield is alternately applied to the display electrode pairs composed of the scan electrodes and the sustain electrodes.
  • a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”). Also written as “lit”.)
  • each discharge cell is made to emit light with the luminance according to the gradation weight.
  • each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.
  • the plasma display device has an image signal processing circuit.
  • the image signal processing circuit converts an image signal (hereinafter simply referred to as “image signal”) input to the plasma display device into a subfield code indicating lighting / non-lighting for each subfield in each discharge cell.
  • the image signal processing circuit has a conversion table composed of a plurality of subfield codes.
  • one subfield code is associated with one gradation value. That is, when one gradation value is input, the conversion table outputs one subfield code associated with the gradation value.
  • the conversion table is stored in a semiconductor storage element such as a ROM and provided in the image signal processing circuit. Then, using the conversion table, the image signal processing circuit converts each gradation value of the image signal into a subfield code (data indicating light emission / non-light emission for each subfield) corresponding to each gradation value. Output to the circuit.
  • the number of gradation values that can be displayed on the panel is determined by the number of subfield codes constituting the conversion table. If the number of subfield codes constituting the conversion table is large, the number of gradation values that can be displayed on the panel increases, and if the number of subfield codes constituting the conversion table is small, the number of gradation values that can be displayed on the panel. Decrease.
  • the number of gradation values that can be displayed on the panel is related to the power consumption of the plasma display device, and the number of gradation values that can be displayed on the panel is relatively reduced when the power consumption is reduced. Therefore, the subfield codes constituting the conversion table are generally determined in consideration of the power consumption of the plasma display device, the smoothness of the image that can be displayed on the panel, and the like.
  • the gradation values that cannot be displayed on the panel increase. For example, if the conversion table includes the subfield code of gradation value “7” and gradation value “9” and does not include the subfield code of gradation value “8”, the gradation value “8” is displayed on the panel. "Cannot be displayed. However, gradation values that cannot be displayed on the panel can be displayed on the panel in a pseudo manner by using a generally known method such as a dither method or an error diffusion method.
  • this moving image pseudo contour changes according to the number of subfield codes constituting the conversion table, and when the number of subfield codes constituting the conversion table increases, the moving image pseudo contour is likely to occur. .
  • the plasma display device it is desirable to display the image with a smooth gradation change by increasing the gradation values that can be displayed on the panel as much as possible, while reducing the moving image pseudo contour as much as possible.
  • the plasma display device includes a plurality of conversion tables having different numbers and types of subfield codes constituting the conversion table, and the plurality of conversion tables. Has been disclosed (for example, see Patent Document 1).
  • a plasma display device includes a plurality of conversion tables. Then, a minimum value and an average value of the image signal are obtained, and a threshold value is calculated from the minimum value and the average value. Then, one conversion table is selected from a plurality of conversion tables based on this threshold value. Then, the image signal is converted into a subfield code based on the selected conversion table.
  • the number of conversion tables to be provided in the plasma display device is very large as compared with the conventional plasma display device. For this reason, it is difficult to configure an image signal processing circuit having such a large number of conversion tables and selecting an optimum one from a large number of conversion tables according to various conditions. It is coming.
  • the plasma display device includes a plurality of electrode driving circuits for driving each electrode, and the driving voltage waveforms necessary for displaying an image on the panel are respectively displayed using the plurality of electrode driving circuits. Apply to electrode.
  • the plurality of electrode drive circuits include a data electrode drive circuit for driving the data electrodes.
  • the data electrode driving circuit applies a write pulse for a write operation to each of the plurality of data electrodes according to the image signal. Therefore, the data electrode driving circuit is generally configured using a dedicated integrated circuit (IC) for generating an address pulse.
  • IC integrated circuit
  • the data electrode viewed from the data electrode driving circuit is a capacitive load having a stray capacitance between adjacent data electrodes, a stray capacitance between the scan electrodes, and a stray capacitance between the sustain electrodes. Therefore, in order to apply a drive voltage waveform to the data electrode, the data electrode drive circuit must charge and discharge this capacitor, and power consumption for that purpose is required.
  • a plurality of subfields having gradation weights constitute one field, and each of the plurality of subfields is expressed using a subfield code indicating a combination of light emission and non-light emission in each of the plurality of subfields.
  • This is an image display device that controls the light emission and non-light emission, displays a gradation value based on an image signal on each of a plurality of pixels constituting the image display area, and displays an image in the image display area.
  • This image display device includes an image signal processing circuit that outputs a display code that is a subfield code for displaying a gradation value based on an image signal on a pixel.
  • the image signal processing circuit includes a subfield code conversion circuit, a subfield code arrangement circuit, and an error control circuit.
  • the subfield code conversion circuit performs error diffusion processing on the image signal and converts the image signal into a subfield code.
  • the subfield code array circuit calculates a predicted value of power consumption when performing a sequential write operation in the write period as sequential write power based on the subfield code for one field output from the subfield code conversion circuit and writes Calculate the predicted power consumption when performing the interlaced write operation in the period as the interlaced write power, select the write operation with the smaller predicted power consumption, and select the subfields in the order corresponding to the selected write operation. Rearrange the code.
  • the error control circuit When the interlaced write power is smaller than the sequential write power, the error control circuit adds the horizontal error that is the error diffused from the horizontal pixel to the vertical error that is the error diffused from the vertical pixel. The calculated code conversion error is output to the sub-field code conversion circuit.
  • the code error When the interlaced write power is larger than the sequential write power, the code error is calculated by adding the limited vertical error to the horizontal error. The error is output to the subfield code conversion circuit.
  • the conversion from the image signal to the subfield code can be performed by calculation using the calculation circuit. Therefore, even in an image display device that needs to cope with high functionality and multi-function, it is not necessary to provide a huge number of conversion tables for converting image signals into subfield codes. That is, it is not necessary to configure the image signal processing circuit so as to select an optimal one from a vast number of conversion tables according to various conditions. Furthermore, power consumption can be suppressed while preventing deterioration in image display quality in the image display device.
  • the vertical error is arranged in the error generated in the pixel arranged at the upper left of the target pixel, the error generated in the pixel arranged above the target pixel, and the upper right of the target pixel.
  • the horizontal error is an error generated in a pixel arranged on the left of the target pixel.
  • the image display device of the present invention includes a base code generation unit, a rule generation unit, an upper and lower code generation unit, and a display code selection unit.
  • the base code generation unit has a gradation value that is larger than the gradation value of the image signal at the target pixel and has the closest gradation value to the gradation value of the image signal at the target pixel, from among a plurality of basic subfield codes.
  • the field code is selected as the upper gradation base code.
  • the rule generation unit generates a rule for generating a new subfield code by changing the light-emitting subfield in the upper gradation base code to a non-light-emitting subfield based on the image signal at the target pixel.
  • the upper / lower code generation unit applies the above-described rule to the upper gradation base code, and the gradation of the image signal at the target pixel is larger than the gradation value of the image signal at the target pixel.
  • the subfield code having the gradation value closest to the value is selected as the upper gradation code, and the gradation value closest to the gradation value of the image signal at the target pixel is equal to or lower than the gradation value of the image signal at the target pixel.
  • the subfield code having the lower gradation code is selected as the lower gradation code.
  • the display code selection unit calculates a code conversion gradation value by adding a predetermined value to the gradation value of the image signal in the pixel of interest, and the code conversion gradation of the upper gradation code and the lower gradation code The one having a gradation value closer to the value is selected as a display code.
  • the predetermined values described above are a dither value calculated by dither processing and an error for code conversion.
  • the plurality of basic subfield codes described above are all subfields having the largest gradation weight among the subfields that emit light, and all having a gradation weight smaller than that subfield.
  • This is a sub-field code in which the sub-field emits light.
  • the present invention also comprises a plurality of subfields using a subfield code indicating a combination of light emission and non-light emission in each of the plurality of subfields, with a plurality of subfields having gradation weights defined.
  • Method for driving an image display apparatus for controlling each light emission and non-light emission of each of the image display, displaying a gradation value based on an image signal on each of a plurality of pixels constituting the image display area, and displaying an image on the image display area It is. According to this driving method, an error diffusion process is performed on an image signal and the image signal is converted into a subfield code. Based on the subfield code for one field, the power consumption is predicted when sequential write operations are performed in the write period.
  • the conversion from the image signal to the subfield code can be performed by calculation using the calculation circuit. Therefore, even in an image display device that needs to cope with high functionality and multi-function, it is not necessary to provide a huge number of conversion tables for converting image signals into subfield codes. That is, it is not necessary to configure the image signal processing circuit so as to select an optimal one from a vast number of conversion tables according to various conditions. Furthermore, power consumption can be suppressed while preventing deterioration in image display quality in the image display device.
  • the driving method of the image display device is more than the gradation value of the image signal at the pixel of interest, and is the highest in the gradation value of the image signal at the pixel of interest, among a plurality of basic subfield codes.
  • a subfield code having a gradation value that is larger and closest to the gradation value of the image signal at the target pixel is defined as the upper gradation code.
  • FIG. 1 is an exploded perspective view showing a structure of a panel used in an image display apparatus according to an embodiment of the present invention.
  • FIG. 2 is an electrode array diagram of a panel used in the image display apparatus according to the embodiment of the present invention.
  • FIG. 3 is a diagram schematically showing drive voltage waveforms applied to the respective electrodes of the panel used in the image display device according to the embodiment of the present invention.
  • FIG. 4 is a diagram showing an example of a code set when one field is composed of eight subfields.
  • FIG. 5 is a diagram schematically showing an example of a circuit block constituting the image display device according to the embodiment of the present invention.
  • FIG. 1 is an exploded perspective view showing a structure of a panel used in an image display apparatus according to an embodiment of the present invention.
  • FIG. 2 is an electrode array diagram of a panel used in the image display apparatus according to the embodiment of the present invention.
  • FIG. 3 is a diagram schematically showing drive voltage waveforms applied to the respective electrodes of the panel used
  • FIG. 6 is a diagram schematically showing an example of a circuit block constituting the image signal processing circuit of the image display apparatus according to the embodiment of the present invention.
  • FIG. 7 is a diagram schematically showing an example of a circuit block constituting the subfield code conversion circuit and the error control circuit of the image display device according to the embodiment of the present invention.
  • FIG. 8A is a diagram illustrating an example of a base code set used in the image display device according to the embodiment of the present invention.
  • FIG. 8B is a diagram showing another example of the base code set used in the image display device according to the embodiment of the present invention.
  • FIG. 8C is a diagram illustrating another example of the base code set used in the image display device according to the embodiment of the present invention.
  • FIG. 8A is a diagram illustrating an example of a base code set used in the image display device according to the embodiment of the present invention.
  • FIG. 8B is a diagram showing another example of the base code set used in the image display device according to the embodiment of the present invention.
  • FIG. 9A is a diagram illustrating an example of an intermediate code set generated by the intermediate code generation unit of the image display device according to the embodiment of the present invention.
  • FIG. 9B is a diagram showing another example of the intermediate code set generated by the intermediate code generation unit of the image display device according to the embodiment of the present invention.
  • FIG. 9C is a diagram showing another example of the intermediate code set generated by the intermediate code generation unit of the image display device according to the embodiment of the present invention.
  • FIG. 10A is a diagram showing an example of a dither pattern used in the image display device in one embodiment of the present invention.
  • FIG. 10B is a diagram showing another example of the dither pattern used in the image display device according to the embodiment of the present invention.
  • FIG. 10A is a diagram showing an example of a dither pattern used in the image display device in one embodiment of the present invention.
  • FIG. 10B is a diagram showing another example of the dither pattern used in the image display device according to the embodiment of the present invention.
  • FIG. 11 is a schematic diagram for explaining the operation of the error diffusing unit and the error limiting unit of the image display device according to the embodiment of the present invention.
  • FIG. 12 is a flowchart showing the operation of the image signal processing circuit of the image display device according to the embodiment of the present invention.
  • FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the image display apparatus according to the embodiment of the present invention.
  • a plurality of display electrode pairs 14 each including a scanning electrode 12 and a sustaining electrode 13 are formed on a glass front substrate 11.
  • a dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15.
  • This protective layer 16 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is made of a material mainly composed of magnesium oxide (MgO).
  • the protective layer 16 may be composed of a single layer or may be composed of a plurality of layers. Moreover, the structure which particle
  • a plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is further formed thereon.
  • a phosphor layer 25R that emits red (R)
  • a phosphor layer 25G that emits green (G)
  • a phosphor layer 25B that emits blue (B).
  • the phosphor layer 25R, the phosphor layer 25G, and the phosphor layer 25B are collectively referred to as a phosphor layer 25.
  • the front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect each other with a minute space therebetween, and a discharge space is provided in the gap between the front substrate 11 and the rear substrate 21.
  • the outer peripheral part is sealed with sealing materials, such as glass frit.
  • sealing materials such as glass frit.
  • a mixed gas of neon and xenon is sealed in the discharge space as a discharge gas.
  • the discharge space is partitioned into a plurality of sections by the barrier ribs 24, and discharge cells, which are light-emitting elements constituting the pixels, are formed at the intersections between the display electrode pairs 14 and the data electrodes 22.
  • one pixel is composed of three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends.
  • the three discharge cells are a discharge cell having a phosphor layer 25R and emitting red (R) (red discharge cell), and a discharge cell having a phosphor layer 25G and emitting green (G) (green). And a discharge cell having a phosphor layer 25B and emitting blue (B) light (blue discharge cell).
  • the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.
  • FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device according to one embodiment of the present invention.
  • the panel 10 includes n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) extended in the horizontal direction (row direction and line direction) and n sustain electrodes SU1 to SUn (FIG. 1).
  • the sustain electrodes 13) are arranged, and m data electrodes D1 to Dm (data electrodes 22 in FIG. 1) extending in the vertical direction (column direction) are arranged.
  • m discharge cells are formed on one pair of display electrodes 14 and m / 3 pixels are formed.
  • the plasma display device in the present embodiment drives the panel 10 by the subfield method.
  • the subfield method one field of an image signal is divided into a plurality of subfields on the time axis, and a gradation weight is set for each subfield. Therefore, each field has a plurality of subfields having different gradation weights.
  • Each subfield has an initialization period, an address period, and a sustain period. Based on the image signal, light emission / non-light emission of each discharge cell is controlled for each subfield. That is, a plurality of gradations based on the image signal are displayed on the panel 10 by combining the light-emitting subfield and the non-light-emitting subfield based on the image signal.
  • an initializing operation is performed in which initializing discharge is generated in the discharge cells and wall charges necessary for the address discharge in the subsequent address period are formed on each electrode.
  • Initialization operation includes “forced initialization operation” that forcibly generates an initializing discharge in all discharge cells regardless of the operation of the immediately preceding subfield and an addressing discharge that occurs in the addressing period of the immediately preceding subfield.
  • the forced initializing operation the rising ramp waveform voltage and the falling ramp waveform voltage are applied to the scan electrode 12 to generate an initializing discharge in the discharge cell.
  • the forced initializing operation is performed in all discharge cells in the initializing period of one subfield, and all the discharge cells are selected in the initializing period of the other subfield. Perform initialization.
  • force initialization period the initialization period in which the forced initialization operation is performed
  • subfield having the forced initialization period is referred to as “forced initialization subfield”.
  • An initialization period for performing the selective initialization operation is referred to as a “selective initialization period”
  • a subfield having the selective initialization period is referred to as a “selective initialization subfield”.
  • subfield SF1 is a forced initialization subfield
  • the other subfields are selected initialization subfields.
  • the present invention is not limited to the above-described subfields as subfields for forced initialization subfields and subfields for selective initialization subfields.
  • the structure which switches a subfield structure based on an image signal etc. may be sufficient.
  • a scan pulse is applied to the scan electrode 12 and an address pulse is selectively applied to the data electrode 22 to selectively generate an address discharge in the discharge cells to emit light. Then, an address operation is performed to form wall charges in the discharge cells for generating a sustain discharge in the subsequent sustain period.
  • sustain pulses of the number obtained by multiplying the gradation weight set in each subfield by a predetermined proportional constant are alternately applied to the scan electrode 12 and the sustain electrode 13 to generate an address discharge in the immediately preceding address period.
  • a sustain discharge is generated in the discharged discharge cell, and a sustain operation for emitting light from the discharge cell is performed.
  • This proportionality constant is a luminance multiple.
  • the gradation weight represents the ratio of the magnitude of the luminance displayed in each subfield, and the number of sustain pulses corresponding to the gradation weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the gradation weight “8” emits light with a luminance about eight times that of the subfield with the gradation weight “1”, and about four times as high as the subfield with the gradation weight “2”. Emits light. Therefore, for example, if the subfield with the gradation weight “8” and the subfield with the gradation weight “2” are emitted, the discharge cell can emit light with a luminance corresponding to the gradation value “10”.
  • each discharge cell emits light with various gradation values by selectively emitting light in each subfield by controlling light emission / non-light emission of each discharge cell for each subfield in a combination according to the image signal. That is, a gradation value corresponding to an image signal can be displayed on each discharge cell, and an image based on the image signal can be displayed on the panel 10.
  • one pixel includes three consecutive discharge cells arranged in the direction in which the display electrode pair 14 extends, that is, a red discharge cell, a green discharge cell, and a blue discharge.
  • a red discharge cell is also referred to as a “red pixel”, a green discharge cell as a “green pixel”, and a blue discharge cell as a “blue pixel”.
  • FIG. 3 is a diagram schematically showing drive voltage waveforms applied to the respective electrodes of panel 10 used in the plasma display device according to one embodiment of the present invention.
  • FIG. 3 shows data electrode D1 to data electrode Dm, scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), sustain electrode SU1 to The drive voltage waveform applied to each of the sustain electrodes SUn is shown.
  • Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.
  • FIG. 3 shows a subfield SF1 that is a forced initialization subfield, and a subfield SF2 and a subfield SF3 that are selective initialization subfields.
  • the subfield SF1, the subfield SF2, and the subfield SF3 have different waveform shapes of the drive voltage applied to the scan electrode 12 in the initialization period.
  • each subfield except subfield SF1 is a selective initialization subfield, and substantially the same drive voltage waveform in each period except the number of sustain pulses. Is generated.
  • the voltage 0 (V) is applied to the data electrode D1 to the data electrode Dm and the sustain electrode SU1 to the sustain electrode SUn.
  • a voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn after voltage 0 (V) is applied, and a ramp waveform voltage that gradually rises from voltage Vi1 to voltage Vi2 (hereinafter referred to as an “upward ramp waveform voltage”). ) Is applied.
  • voltage Vi1 is set to a voltage lower than the discharge start voltage for sustain electrode SU1 to sustain electrode SUn
  • voltage Vi2 is set to a voltage exceeding the discharge start voltage for sustain electrode SU1 to sustain electrode SUn.
  • the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.
  • the positive voltage Ve is applied to the sustain electrodes SU1 to SUn, and the voltage 0 (V) is applied to the data electrodes D1 to Dm.
  • a scan waveform SC1 to scan electrode SCn are applied with a ramp waveform voltage that gently falls from voltage Vi3 to negative voltage Vi4 (hereinafter referred to as “down ramp waveform voltage”).
  • Voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn
  • voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
  • the above voltage waveform is a forced initializing waveform that generates an initializing discharge in the discharge cell regardless of the operation of the immediately preceding subfield.
  • the operation for applying the forced initialization waveform to the scan electrode 12 is the forced initialization operation.
  • the forced initialization operation in the initialization period Ti1 of the forced initialization subfield ends.
  • initializing discharge is forcibly generated in all the discharge cells in the image display area of the panel 10.
  • either the “sequential writing operation” or the “interlace writing operation” is performed during the writing period.
  • the sequential address operation scan pulses are applied to scan electrode 12 in the order of scan electrode SC1, scan electrode SC2, scan electrode SC3, scan electrode SC4,..., Scan electrode SCn-1, and scan electrode SCn.
  • the sequential address operation is an address operation in which scan pulses are sequentially applied to the scan electrodes 12 in the order in which the scan electrodes 12 are arranged on the panel 10.
  • the interlaced write operation includes scan electrode SC1, scan electrode SC3, scan electrode SC5,..., Scan electrode SCn-3, scan electrode SCn-1, scan electrode SC2, scan electrode SC4, scan electrode SC6,.
  • a scan pulse is applied to scan electrode 12 in the order of electrode SCn-4, scan electrode SCn-2, and scan electrode SCn. That is, in the interlaced write operation, first, scan pulses are sequentially applied to the odd-numbered (or even-numbered) scan electrodes 12 in the order in which the scan electrodes 12 are arranged on the panel 10, and then the even-numbered (or odd-numbered). This is an address operation in which scan pulses are sequentially applied to the scan electrode 12.
  • the interlaced write operation is different from the sequential write operation only in the order in which the scan pulses are applied to the scan electrodes 12, and the other operations are the same as the sequential write operation, and thus description thereof is omitted.
  • voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn
  • voltage 0 (V) is applied to data electrode D1 through data electrode Dm
  • scan electrode SC1 through scan electrode SCn are applied. Applies a voltage Vc.
  • a negative scan pulse having a negative voltage Va is applied to the first (first row) scan electrode SC1 in terms of arrangement.
  • a positive address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row of the data electrodes D1 to Dm.
  • sustain electrode SU1 since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, sustain electrode SU1 in a region intersecting data electrode Dk is induced by a discharge generated between data electrode Dk and scan electrode SC1. Discharge also occurs between scan electrode SC1 and scan electrode SC1. Thus, address discharge is generated in the discharge cells (discharge cells to emit light) to which the scan pulse voltage Va and the address pulse voltage Vd are simultaneously applied.
  • a positive wall voltage is accumulated on the scan electrode SC1
  • a negative wall voltage is accumulated on the sustain electrode SU1
  • a negative wall voltage is also accumulated on the data electrode Dk.
  • the address operation in the discharge cells in the first row is completed.
  • the discharge cell having the data electrode Dh to which the address pulse is not applied the data electrode Dh is the data electrode D1 to the data electrode Dm excluding the data electrode Dk
  • the intersection of the data electrode Dh and the scan electrode SC1 Since the voltage of the portion does not exceed the discharge start voltage, the address discharge does not occur, and the wall voltage after the end of the initialization period Ti1 is maintained.
  • a scan pulse of the voltage Va is applied to the second (second row) scan electrode SC2 from the top, and the voltage Vd is applied to the data electrode Dk corresponding to the discharge cell to emit light in the second row. Apply the write pulse.
  • address discharge occurs in the discharge cells in the second row to which the scan pulse and address pulse are simultaneously applied.
  • the address operation in the discharge cells in the second row is performed.
  • the order in which the scan pulse is applied to the scan electrode 12 is not limited to the order described above. What is necessary is just to set arbitrarily the order which applies a scanning pulse to the scanning electrode 12 according to the specification etc. in an image display apparatus.
  • voltage Ve applied to sustain electrode SU1 through sustain electrode SUn in the second half of initialization period Ti1 and voltage Ve applied to sustain electrode SU1 through sustain electrode SUn in address period Tw1 may have different voltage values. .
  • Each data electrode 22 is driven by a data electrode driving circuit.
  • Each of the data electrodes 22 viewed from the data electrode driving circuit has a stray capacitance generated between the adjacent data electrodes 22, a stray capacitance generated between the scan electrodes 12, and a stray capacitance generated between the sustain electrodes 13. It has a capacitive load.
  • the data electrode driving circuit has the capacitance when the voltage applied to each data electrode 22 is switched from the voltage 0 (V) to the voltage Vd and from the voltage Vd to the voltage 0 (V) in the address period. Must be charged and discharged, and power consumption for that purpose is required.
  • the power consumption of the data electrode driving circuit is also relatively large. Conversely, in the address period in which the number of times of charging / discharging is relatively small, the power consumption of the data electrode driving circuit is relatively small. Therefore, the power consumption of the data electrode driving circuit can be suppressed by suppressing the number of times of charging / discharging.
  • the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn. Then, sustain pulse of positive voltage Vs is applied to scan electrode SC1 through scan electrode SCn.
  • the voltage difference between the scan electrode SCi and the sustain electrode SUi exceeds the discharge start voltage, and is maintained between the scan electrode SCi and the sustain electrode SUi. Discharge occurs.
  • the phosphor layer 25 of the discharge cell in which the sustain discharge has occurred emits light by the ultraviolet rays generated by the sustain discharge.
  • a negative wall voltage is accumulated on scan electrode SCi
  • a positive wall voltage is accumulated on sustain electrode SUi.
  • a positive wall voltage is also accumulated on the data electrode Dk.
  • the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred in the address period Tw1.
  • the sustain pulses of the number obtained by multiplying the gradation weight by a predetermined luminance multiple are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.
  • the discharge cells that have generated the address discharge in the address period generate the sustain discharges the number of times corresponding to the gradation weight, and emit light with the luminance corresponding to the gradation weight.
  • scan electrode SC1 to scan are performed while voltage 0 (V) is applied to sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm.
  • An upward ramp waveform voltage that gradually rises from voltage 0 (V) to voltage Vr is applied to electrode SCn.
  • the sustain of the discharge cell that has generated the sustain discharge is maintained while the rising ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn exceeds the discharge start voltage.
  • a weak discharge (erase discharge) is continuously generated between the electrode SUi and the scan electrode SCi.
  • the charged particles generated by this weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi.
  • the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi are weakened while the positive wall voltage on data electrode Dk remains.
  • unnecessary wall charges in the discharge cell are erased.
  • the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the positive voltage Ve is applied to the sustain electrodes SU1 to SUn.
  • Scan electrode SC1 to scan electrode SCn decrease from a voltage lower than the discharge start voltage (for example, voltage 0 (V)) toward negative voltage Vi4 at the same gradient as the downward ramp waveform voltage generated in initialization period Ti1. Apply a downward ramp waveform voltage.
  • the voltage Vi4 is set to a voltage exceeding the discharge start voltage.
  • the negative wall voltage on scan electrode SCi and the positive wall voltage on sustain electrode SUi are weakened.
  • an excessive portion of the positive wall voltage on the data electrode Dk is discharged.
  • the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation in the address period Tw2.
  • the voltage waveform described above is a selective initialization waveform in which an initializing discharge is selectively generated in a discharge cell that has performed an address operation in the address period (here, address period Tw1) of the immediately preceding subfield.
  • the operation of applying the selective initialization waveform to the scan electrode 12 is the selective initialization operation.
  • the same drive voltage waveform as that in the address period Tw1 of the subfield SF1 is applied to each electrode.
  • the number of sustain pulses corresponding to the gradation weights are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn.
  • each subfield after subfield SF3 the same drive voltage waveform as in subfield SF2 is applied to each electrode except for the number of sustain pulses generated in the sustain period.
  • Voltage Vc ⁇ 60 (V)
  • voltage Va ⁇ 200 (V)
  • voltage Vs 200 (V)
  • voltage Vr 200 (V)
  • voltage Ve 130 (V)
  • voltage Vd 70 (V)
  • the gradient of the rising ramp waveform voltage generated in the initialization period Ti1 is about 1.3 V / ⁇ sec
  • the gradient of the rising ramp waveform voltage generated in each sustain period is about 10 V / ⁇ sec.
  • the gradient of the generated downward ramp waveform voltage is about ⁇ 1.5 V / ⁇ sec.
  • the specific numerical values such as the voltage value and the gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value and the gradient.
  • Each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.
  • subfield SF1 is a forced initialization subfield for performing a forced initialization operation
  • other subfields are a selective initialization subfield for performing a selective initialization operation
  • the present invention is not limited to this configuration.
  • the subfield SF1 may be a selective initialization subfield and other subfields may be forced initialization subfields, or a plurality of subfields may be forced initialization subfields.
  • one field is composed of a plurality of subfields in which gradation weights are determined in advance. Then, by combining a subfield that is lit (lighting subfield) and a subfield that is not lit (non-lighting subfield), each discharge cell emits light with a light emission luminance corresponding to the magnitude of the gradation value based on the image signal. .
  • subfield code a combination of a lighting subfield and a non-lighting subfield
  • code set a set of a plurality of subfield codes
  • a subfield code is selected from a plurality of subfield codes constituting a code set according to a gradation value. Then, light emission / non-light emission of each subfield is controlled based on the subfield code, and the discharge cell is caused to emit light with a luminance corresponding to the magnitude of the gradation value, and an image is displayed on the panel 10.
  • the gradation value when displaying black (the gradation value when no sustain discharge occurs) is assumed to be “0”.
  • a gradation value corresponding to the gradation weight “N” is expressed as a gradation value “N”.
  • the gradation value displayed by the discharge cells that emit light only in the subfield SF1 having the gradation weight “1” is the gradation value “1”.
  • FIG. 4 is a diagram showing an example of a code set when one field is composed of eight subfields.
  • the numerical value shown immediately below the notation indicating each subfield represents the gradation weight of each subfield.
  • FIG. 4 includes eight subfields SF1 to SF8 in one field, and each subfield is “1”, “2”, “3”, “5”, “8”, respectively. ”,“ 13 ”,“ 21 ”, and“ 34 ”indicate code sets having gradation weights.
  • the light emitting subfield is indicated by “1”
  • the non-light emitting subfield is indicated by a blank
  • the leftmost column indicates the gradation value to be displayed in each subfield code.
  • the subfield code corresponding to the gradation value “2” is “01000000”.
  • subfield code data 0 or 1 is arranged in the order of subfield SF1, subfield SF2, subfield SF3, subfield SF4, subfield SF5, subfield SF6, subfield SF7, and subfield SF8 from the left.
  • binary numerical values shown as subfield codes are arranged in the order of subfield SF1, subfield SF2, subfield SF3,.
  • the subfield code corresponding to the gradation value “14” is “11101000”. Accordingly, in the discharge cell displaying the gradation value “14”, the subfield SF1, the subfield SF2, the subfield SF3, and the subfield SF5 emit light.
  • FIG. 5 is a diagram schematically showing an example of a circuit block constituting the image display device 30 according to the embodiment of the present invention.
  • the image display device 30 includes a panel 10 and a drive circuit that drives the panel 10.
  • the drive circuit includes an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.
  • the image signals input to the image signal processing circuit 31 are a red image signal, a green image signal, and a blue image signal. Based on the red image signal, the green image signal, and the blue image signal, the image signal processing circuit 31 sets each gradation value of red, green, and blue (a gradation value expressed by one field) to each discharge cell. To do.
  • the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, or RY signal and BY signal, or u signal and v signal, etc.).
  • a red image signal, a green image signal, and a blue image signal are calculated based on the luminance signal and the saturation signal, and then, each gradation value of red, green, and blue is set in each discharge cell.
  • the red, green, and blue gradation values set for each discharge cell are subfield codes indicating lighting / non-lighting for each subfield (light emission / non-light emission corresponds to digital signals “1” and “0”).
  • the subfield code is output as a display code. That is, the image signal processing circuit 31 converts the red image signal, the green image signal, and the blue image signal into a red display code, a green display code, and a blue display code and outputs the converted signals.
  • the image signal processing circuit 31 in the present embodiment predicts the power consumption of the data electrode driving circuit 32 when performing sequential write operations and when performing interlaced write operations in the write period. Then, the write operation with the lower power consumption of the data electrode drive circuit 32 is selected. Then, the display code whose arrangement is changed in the order corresponding to the write operation of the selected one is output.
  • the image signal processing circuit 31 does not convert an image signal into a subfield code using a conversion table, but converts the image signal into a subfield code by a logical operation. Details of this will be described later.
  • the timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal.
  • the generated timing signal is supplied to each circuit block (data electrode drive circuit 32, scan electrode drive circuit 33, sustain electrode drive circuit 34, image signal processing circuit 31, etc.).
  • Scan electrode drive circuit 33 includes a ramp waveform generation unit, a sustain pulse generation unit, and a scan pulse generation unit (not shown in FIG. 5), and generates a drive voltage waveform based on a timing signal supplied from timing generation circuit 35. Then, the voltage is applied to each of scan electrode SC1 to scan electrode SCn.
  • the ramp waveform generator generates a forced initialization waveform and a selective initialization waveform to be applied to scan electrode SC1 through scan electrode SCn during the initialization period based on the timing signal.
  • the sustain pulse generator generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn during the sustain period based on the timing signal.
  • the scan pulse generator includes a plurality of scan electrode drive ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn during the address period based on the timing signal.
  • Sustain electrode drive circuit 34 includes a sustain pulse generation unit and a circuit (not shown in FIG. 5) for generating voltage Ve, and generates and maintains a drive voltage waveform based on the timing signal supplied from timing generation circuit 35.
  • the voltage is applied to each of electrode SU1 through sustain electrode SUn.
  • a sustain pulse is generated based on the timing signal and applied to sustain electrode SU1 through sustain electrode SUn.
  • voltage Ve is generated based on the timing signal and applied to sustain electrode SU1 through sustain electrode SUn.
  • the data electrode drive circuit 32 includes the same number of switch circuits 36 as the data electrodes 22. In this embodiment, since the number of data electrodes 22 is “m”, the data electrode drive circuit 32 includes m switch circuits 36 (switch circuit 36 (1) to switch circuit 36 (m)). Each of the m switch circuits 36 (1) to 36 (m) corresponds to each of the m data electrodes D1 to Dm.
  • the data electrode drive circuit 32 generates an address pulse corresponding to each of the data electrodes D1 to Dm based on the display code of each color output from the image signal processing circuit 31 and the timing signal supplied from the timing generation circuit 35. .
  • the data electrode drive circuit 32 then writes a write pulse (write pulse voltage Vd or 0 (V) from the switch circuit 36 (1) to the switch circuit 36 (m) to the data electrode D1 to the data electrode Dm during the write period. )) Is applied.
  • the dedicated IC In order for the dedicated IC to operate normally, it is necessary to keep the power consumption, temperature, etc. within the predetermined range as the standard for the dedicated IC. For example, if the power consumption exceeds a predetermined upper limit of power consumption (allowable power loss), the dedicated IC may cause an abnormal operation. Therefore, in the image display device 30, the data electrode drive circuit 32 needs to operate so that the power consumption of the dedicated IC does not exceed a predetermined upper limit.
  • the display code is generated so as to reduce the power consumption of the data electrode driving circuit 32 while preventing the image display quality in the image display device 30 from deteriorating. Details of generation of the display code will be described later.
  • the object of the image signal processing circuit 31 in the present embodiment is to reduce the power consumption of the data electrode driving circuit 32 while preventing the image display quality in the image display device 30 from being deteriorated.
  • the image signal processing circuit 31 reduces the number of subfield codes used for displaying an image. Then, the image signal processing circuit 31 generates rules to be described later in order to reduce the number of subfield codes used for image display.
  • FIG. 6 is a diagram schematically showing an example of a circuit block constituting the image signal processing circuit 31 of the image display device 30 according to the embodiment of the present invention.
  • the image signal processing circuit 31 has a subfield code conversion circuit 37, a subfield code arrangement circuit 38, and an error control circuit 39.
  • the subfield code conversion circuit 37 performs error diffusion processing on the image signal (hereinafter simply referred to as “image signal”) input to the image signal processing circuit 31 and converts the image signal into a subfield code (display code). Convert.
  • the subfield code conversion circuit 37 does not convert the image signal into the subfield code using the conversion table, but converts the image signal into the subfield code by a logical operation. Details of this will be described later.
  • the subfield code array circuit 38 calculates “sequential write power” and “interlaced write power” for the subfield code for one field output from the subfield code conversion circuit 37.
  • “Sequential write power” predicts the power consumption of the data electrode drive circuit 32 if a sequential write operation is performed based on the subfield code for one field output from the subfield code conversion circuit 37 in the write period. It is a predicted value (estimated value of power consumption).
  • Interlaced writing power predicted how the power consumption of the data electrode driving circuit 32 would be if the interlaced writing operation was performed based on the subfield code for one field output from the subfield code conversion circuit 37 in the writing period. It is a predicted value (estimated value of power consumption).
  • the subfield code array circuit 38 selects the write operation with the smaller predicted power consumption value of the data electrode drive circuit 32. Further, the subfield code array circuit 38 outputs from the subfield code conversion circuit 37 so that the write operation is performed in the correct order when the scan pulses are generated in the write period in the order based on the selected write operation. Change the array of subfield codes to be displayed.
  • the subfield code arrangement circuit 38 includes a sequential write arrangement unit 91, an interlaced write arrangement unit 92, a power prediction unit 93, a power prediction unit 94, and an arrangement selection unit 95.
  • the sequential write array unit 91 rearranges the array of subfield codes output from the subfield code conversion circuit 37 in the order corresponding to the sequential write operation.
  • the subfield code arrangement circuit 38 has a storage device (for example, a semiconductor storage device such as a RAM, not shown in FIG. 6) that stores a subfield code for one field and can read it arbitrarily.
  • a storage device for example, a semiconductor storage device such as a RAM, not shown in FIG. 6
  • the sequential write array unit 91 reads the subfield codes stored in the storage device so as to correspond to the order of scan electrode SC1, scan electrode SC2, scan electrode SC3,..., Scan electrode SCn, Output.
  • the interlaced write array unit 92 rearranges the array of subfield codes output from the subfield code conversion circuit 37 in the order corresponding to the interlaced write operation. That is, the interlaced address array unit 92 converts the subfield codes stored in the storage device into scan electrode SC1, scan electrode SC3, scan electrode SC5,..., Scan electrode SCn-3, scan electrode SCn-1, The electrodes SC2, the scan electrode SC4, the scan electrode SC6,..., The scan electrode SCn-4, the scan electrode SCn-2, and the scan electrode SCn are read and output in order.
  • each of the write array unit 91 and the interlaced write array unit 92 is configured to sequentially read in the order corresponding to each write operation. This is because the output of the sequential write array unit 91 and the output of the interlaced write array unit 92 are matched with each other.
  • the power predicting unit 93 calculates the power consumption of the data electrode driving circuit 32 based on the subfield codes sequentially output from the write array unit 91. This calculation result is a predicted value of the power consumption of the data electrode driving circuit 32 when the sequential address operation is performed based on the subfield code for one field output from the subfield code conversion circuit 37 in the address period.
  • the power prediction unit 93 outputs the calculation result as “sequential write power Pprg”.
  • the power predicting unit 94 calculates the power consumption of the data electrode driving circuit 32 based on the subfield code output from the interlaced writing array unit 92. This calculation result is a predicted value of the power consumption of the data electrode driving circuit 32 when performing the interlaced write operation based on the subfield code for one field output from the subfield code conversion circuit 37 in the write period. The power predicting unit 94 outputs the calculation result as “interlaced writing power Pint”.
  • the power consumption of the data electrode drive circuit 32 increases as the number of changes in voltage applied to each of the data electrodes 22 (from voltage 0 (V) to voltage Vd or from voltage Vd to voltage 0 (V)) increases. . Further, when the voltage applied to the adjacent data electrode 22 changes in the opposite phase, it further increases.
  • the “reverse phase” refers to, for example, when the voltage applied to the data electrode Dk changes from the voltage 0 (V) to the voltage Vd, the voltage applied to the data electrode Dk + 1 changes from the voltage Vd to the voltage 0 (V). Things that change.
  • the pixel of interest is a pixel that is an object of calculation at that time.
  • the “bit” described above is data constituting a subfield code, and the numerical value of 1 or 0 represented by each bit represents lighting or non-lighting in each subfield.
  • each of the power prediction unit 93 and the power prediction unit 94 calculates a predicted value of power consumption in the data electrode drive circuit 32.
  • the power predicting unit 93 calculates a predicted value of the power consumption of the data electrode driving circuit 32 when performing the sequential address operation in the address period. Therefore, the power prediction unit 93 performs an exclusive OR operation for each bit of the subfield code assigned to each pixel for each pixel of interest and each pixel adjacent to the top, bottom, left, and right of the pixel of interest, The sum of the calculation results is calculated.
  • the power predicting unit 94 calculates a predicted value of the power consumption of the data electrode driving circuit 32 when performing the interlaced address operation in the address period.
  • the power predicting unit 94 includes the pixel of interest arranged between the pixel of interest and one pixel between the pixel of interest, and the pixel arranged below with the pixel of interest interposed therebetween. For each of the pixels adjacent to the left and right of the target pixel, an exclusive OR operation is performed for each bit of the subfield code assigned to each pixel, and the sum of the operation results is calculated.
  • the power prediction unit 93 and the power prediction unit 94 perform an exclusive OR operation of “11110000” and “11001100” and an exclusive OR operation of “11110000” and “11000011”.
  • the calculation results are “00111100” and “00110011”, respectively. Therefore, the sum of these calculation results is “8”.
  • the power predicting unit 93 and the power predicting unit 94 perform the same calculation on the target pixel and each pixel arranged above and below the target pixel, and calculate the sum of them.
  • the power prediction unit 93 and the power prediction unit 94 calculate the predicted value of power consumption in the target pixel. Then, the power prediction unit 93 and the power prediction unit 94 perform the above-described calculation for all the pixels provided in the image display area, and calculate the sum of them.
  • each of the power prediction unit 93 and the power prediction unit 94 predicts the power consumption in the data electrode drive circuit 32 for each field.
  • pixels continuously arranged on one data electrode 22 are referred to as “vertically continuous pixels”.
  • pixels continuously arranged on one display electrode pair 14 are referred to as “horizontal pixels”. Therefore, the pixels adjacent above and below the pixel of interest are pixels adjacent to the pixel of interest on one data electrode 22.
  • the pixels adjacent to the left and right of the target pixel are pixels adjacent to the target pixel on one display electrode pair 14.
  • the vertical direction is a direction in which the data electrode 22 extends
  • the horizontal direction is a direction in which the display electrode pair 14 extends.
  • the array selection unit 95 sequentially compares the write power Pprg and the interlaced write power Pint, and selects the one with the smaller numerical value.
  • the sequential write power Pprg is selected
  • the subfield code output from the sequential write array unit 91 is output to the data electrode drive circuit 32.
  • the interlaced write power Pint is selected
  • the subfield code output from the interlaced write array unit 92 is output to the data electrode drive circuit 32. That is, the array selection unit 95 compares the sequential write operation and the interlaced write operation with respect to the subfield code for one field output from the subfield code conversion circuit 37, and the power consumption of the data electrode drive circuit 32 is smaller. Select one of the write operations.
  • the error control circuit 39 causes the error diffused from the pixel arranged in the vertical direction with respect to the target pixel to the target pixel to be lateral to the target pixel.
  • the error diffused from the pixel arranged in the direction to the target pixel is added. Then, the addition result is output to the subfield code conversion circuit 37.
  • an error diffused from a pixel arranged in the vertical direction with respect to the target pixel to the target pixel is referred to as a “vertical error”.
  • an error diffused from a pixel arranged in the horizontal direction to the target pixel to the target pixel is referred to as a “lateral error”.
  • a result obtained by adding the vertical error and the horizontal error is referred to as “code conversion error”.
  • the error control circuit 39 limits the magnitude of the vertical error when the interlaced write power Pint is sequentially larger than the write power Pprg, and adds the limited vertical error to the horizontal error.
  • the code conversion error thus obtained is output to the subfield code conversion circuit 37.
  • the error control circuit 39 calculates an error to be displayed on the target pixel by adding the horizontal error to the vertical error which is not limited, and converts the calculation result (error to be displayed on the target pixel) into subfield code conversion. Output to the circuit 37.
  • FIG. 7 is a diagram schematically showing an example of circuit blocks constituting the subfield code conversion circuit 37 and the error control circuit 39 of the image display device 30 according to the embodiment of the present invention.
  • the subfield code conversion circuit 37 includes an attribute detection unit 41, a base code generation unit 50, a rule generation unit 61, an upper and lower code generation unit 70, and a display code selection unit 80.
  • the error control circuit 39 includes an error diffusion unit 84 and an error limiting unit 85.
  • the attribute detection unit 41 specifies the relationship between the image signal and the position of the pixel displaying the image signal.
  • the time differentiation of the image signal corresponding to each pixel determines whether each pixel is in the moving image area or the still image area. Detect if there is any.
  • a change in brightness is detected by spatial differentiation of the image signal (detecting a change in the image signal between adjacent pixels), and it is detected whether or not each pixel corresponds to the contour portion of the image. Then, those detection results are output as attributes of the image signal corresponding to each pixel.
  • a subfield code that is basic in subsequent signal processing is referred to as a “basic code”, and a code set including the base code is referred to as a “basic code set”.
  • the base code is a subfield code generated by lighting one by one or two in order from the subfield having the smallest gradation weight. Therefore, the base code is a subfield code in which a subfield having the largest gradation weight among the subfields to emit light and all subfields having a gradation weight smaller than that subfield emit light.
  • the base code generation unit 50 converts the tone value (hereinafter referred to as “input tone”) of the image signal input to the image signal processing circuit 31 from the base code set including a plurality of base codes. Based on the above, select “upper tone base code”.
  • the upper tone base code is a base code having a tone value larger than the input tone and having a tone value closest to the input tone. Accordingly, in the upper gradation base code, the subfield having the largest gradation weight among the lighting subfields and all subfields having the gradation weight smaller than that subfield are the lighting subfields.
  • the base code generation unit 50 selects a base code having a gradation value larger than the input gradation and closest to the input gradation, and outputs it as an upper gradation base code.
  • FIG. 8A is a diagram illustrating an example of a base code set used in the image display device 30 according to an embodiment of the present invention.
  • FIG. 8B is a diagram showing another example of the base code set used in the image display device 30 according to the embodiment of the present invention.
  • FIG. 8C is a diagram illustrating another example of the base code set used in the image display device 30 according to the embodiment of the present invention.
  • the light-emitting subfield is “1”
  • the non-light-emitting subfield is blank
  • each subfield code (base) is displayed in the second column from the left.
  • Code) represents the gradation value to be displayed.
  • the numerical value written immediately below the notation indicating each subfield in each base code set represents the gradation weight of each subfield.
  • FIG. 8A shows an example of a base code set often used in the NTSC standard.
  • one field is composed of eight subfields, and each subfield is “1”, “2”, “3”, “5”, “ It has gradation weights of “8”, “13”, “21”, and “34”.
  • the first subfield (subfield SF1) of one field is set to the subfield having the smallest gradation weight, and thereafter, the subfields are arranged so that the gradation weight is sequentially increased. . And it is set as a lighting subfield one by one in an order from the subfield with the smallest gradation weight. Therefore, the number of base codes included in this base code set is (the number of subfields constituting one field + 1). For example, in the example of the base code set shown in FIG. 8A, the number of base codes is nine.
  • FIG. 8B shows an example of a base code set often used in the PAL standard.
  • one field includes 12 subfields, and each subfield is “1”, “2”, “4”, “9”, “9” in order from the subfield SF1. It has gradation weights of “18”, “36”, “65”, “5”, “7”, “15”, “33”, “60”.
  • the base code set shown in FIG. 8B has two subfield groups.
  • the first subfield group is composed of subfields SF1 to SF7, and the second subfield group is composed of subfields SF8 to SF12.
  • Each subfield group has the first subfield of each subfield group (subfield SF1 and subfield SF8 in the example shown in FIG. 8B) as the subfield having the smallest gradation weight in each subfield group. Thereafter, the subfields are arranged so that the gradation weights are sequentially increased. In each subfield group, one or two lighting subfields are set in order from the subfield having the smallest gradation weight. Therefore, the number of base codes included in this base code set is equal to or less than (the number of subfields constituting one field + 1). For example, in the example of the base code set shown in FIG. 8B, the number of base codes is 10.
  • FIG. 8C shows an example of a base code set used in a 3D display device (stereoscopic display device).
  • the base code set shown in FIG. 8C includes one sub-field consisting of five sub-fields, and each sub-field is “1”, “16”, “8”, “4”, “ 2 "gradation weight.
  • the first subfield (subfield SF1) of one field is the subfield having the smallest gradation weight
  • the second subfield (subfield SF2) is the subfield having the largest gradation weight.
  • the subfields are arranged so that the gradation weights are sequentially reduced. And it is set as a lighting subfield one by one in an order from the subfield with the smallest gradation weight. Therefore, the number of base codes included in this base code set is (the number of subfields constituting one field + 1). For example, in the example of the base code set shown in FIG. 8C, the number of base codes is 6.
  • the image display device 30 in the present embodiment generates a new code set based on the base code set as described above, and converts the input gradation into a subfield code using the code set.
  • the base code generation unit 50 includes a base code storage unit 52 and a base code selection unit 54.
  • the base code storage unit 52 stores a base code set and gradation values of a plurality of base codes constituting the base code set. Each base code and each gradation value of the base code are stored in the base code storage unit 52 in association with each other.
  • the base code selection unit 54 compares each tone value of the base code constituting the base code set with the input tone. Then, a base code having a gradation value larger than the input gradation and closest to the input gradation is selected. Then, the selected base code is output as an upper gradation base code.
  • a new subcode not included in the base code set is obtained.
  • the rule generation unit 61 generates a rule for generating this new subfield code.
  • the rule generation unit 61 generates a base code based on the image signal and the attribute (attribute associated with the image signal) detected by the attribute detection unit 41 in order to increase the number of subfield codes used for image display.
  • a rule for changing the lighting subfield in the upper gradation base code selected in the unit 50 to the non-lighting subfield is generated.
  • the rule generated by the rule generation unit 61 defines a rule for changing the lighting subfield in the upper gradation base code to the non-lighting subfield.
  • the rule generated by the rule generation unit 61 restricts subfields to be changed from lighting to non-lighting in the upper gradation base code. This is because the gradation value of the new subfield code created by changing the lighting subfield to the non-lighting subfield in the upper gradation base code is smaller than the upper gradation base code. This is in order not to fall below.
  • the upper gradation base code allows unlimited subfields to change from lighting to non-lighting, all lighting subfields become non-lighting subfields, and subfield codes with a gradation value of “0” are generated. This is because there is a possibility that it may occur.
  • the rule generation unit 61 generates a rule so that the subfield code generated based on the rule has the next gradation value.
  • the “lower gradation base code” is a base code having a gradation value that is equal to or lower than the input gradation and closest to the input gradation.
  • the rule generated by the rule generation unit 61 is composed of one or more of the following three rules. 1) A rule for setting the first subfield to be changed from the lighting subfield to the non-lighting subfield. 2) A rule for setting the second subfield to be changed from the lighting subfield to the non-lighting subfield. 3) A rule for setting a sub-field that prohibits non-lighting.
  • the upper / lower code generation unit 70 applies the rule generated by the rule generation unit 61 to the upper gradation base code output from the base code generation unit 50 to generate an upper gradation code and a lower gradation code.
  • the upper gradation code is a sub-field code that can be newly generated based on the rule generated by the rule generation unit 61 and has a gradation value larger than the input gradation and closest to the input gradation. It is a field code.
  • the lower gradation code has a gradation value that is equal to or lower than the input gradation and closest to the input gradation among subfield codes that can be newly generated based on the rule generated by the rule generation unit 61. It is a subfield code.
  • the upper / lower code generation unit 70 includes an intermediate code generation unit 72 and an upper / lower code selection unit 74.
  • the intermediate code generation unit 72 changes the lighting subfield in the upper gradation base code to the non-lighting subfield and generates a new subfield code.
  • the newly generated subfield code is referred to as “intermediate code”.
  • a set obtained by adding the original upper tone base code to these intermediate codes is referred to as an “intermediate code set”.
  • the intermediate code is a subfield code used when displaying an image on panel 10. Therefore, each discharge cell of panel 10 emits light with a luminance of a gradation value based on the intermediate code.
  • FIG. 9A is a diagram illustrating an example of an intermediate code set generated by the intermediate code generation unit 72 of the image display device 30 according to the embodiment of the present invention.
  • FIG. 9B is a diagram illustrating another example of the intermediate code set generated by the intermediate code generation unit 72 of the image display device 30 according to the embodiment of the present invention.
  • FIG. 9C is a diagram illustrating another example of the intermediate code set generated by the intermediate code generation unit 72 of the image display device 30 according to the embodiment of the present invention.
  • the light-emitting subfield is “1”
  • the non-light-emitting subfield is blank
  • the second column from the left is the subfield code (intermediate code).
  • Code represents the gradation value to be displayed.
  • the numerical value written immediately below the notation indicating each subfield in each intermediate code set represents the gradation weight of each subfield.
  • one field includes eight subfields, and each subfield is “1”, “2”, and “3” in order from the subfield SF1. , “5”, “8”, “13”, “21”, “34”.
  • FIG. 9A as an example of the intermediate code set, the above-described “1) rule for setting the first subfield to be changed from the lighting subfield to the non-lighting subfield” is shown in FIG.
  • An intermediate code set generated by applying to the base code “11111100” of the value “32” is shown.
  • rule 1 This “1) rule for setting the first subfield to be changed from a lighting subfield to a non-lighting subfield” is a rule that “one of the lighting subfields is changed to a non-lighting subfield”. (Hereinafter referred to as “rule 1”).
  • the subfield code “11111000” obtained by changing the subfield SF6 to the non-lighting subfield is equal to the base code (No. 6) of the gradation value “19” illustrated in FIG. 8A. Accordingly, five subfield codes excluding the subfield code “11111000” are newly generated intermediate codes.
  • FIG. 9B as an example of the intermediate code set, in addition to the above-described rule 1, “2) a rule for setting the second subfield to be changed from the lighting subfield to the non-lighting subfield” is shown in FIG.
  • Rule 2 for setting the second subfield to be changed from the lighting subfield to the non-lighting subfield is “the subfield code having the smallest gradation value among the newly generated intermediate codes”.
  • the sub-field SF2 is a non-lighting sub-field ”(hereinafter referred to as“ rule 2 ”).
  • FIG. 9C as an example of the intermediate code set, in addition to the above-described rule 1, “3) a rule for setting a subfield that prohibits non-lighting” is shown in the gradation value “A” a rule for setting a subfield that prohibits non-lighting” is shown in the gradation value “A” a rule for setting a subfield that prohibits non-lighting” is shown in the gradation value “A” a rule for setting a subfield that prohibits non-lighting” is shown in the gradation value “ An intermediate code set generated by applying to the base code “11111100” of “32” is shown.
  • rule for setting a subfield that prohibits non-lighting is a rule that “subfield SF1 and subfield SF2 are prohibited from being non-lighting subfield” (hereinafter “rule”). 3 ”).
  • sub-field code in which sub-field SF1 or sub-field SF2 is a non-lighting sub-field has a sub-field code “10111100” with a gradation value “30” and a gradation value “ 31 ”is a sub-field code“ 01111100 ”.
  • the subfield codes having the gradation value “30” and the gradation value “31” are excluded from the intermediate code set.
  • the intermediate code generation unit 72 applies the rule generated by the rule generation unit 61 to the upper gradation base code output from the base code generation unit 50 to generate an intermediate code, and the intermediate code set Is generated.
  • rule 1 and rule 3 are used when generating intermediate code.
  • rule 2 may be added when generating intermediate code.
  • the image display device 30 displays an image with relatively low power consumption, or when an image with relatively little occurrence of moving image pseudo contour is displayed, the number of intermediate codes generated can be increased. It is. Then, by increasing the number of intermediate codes generated, an image can be displayed with a smoother gradation change.
  • the upper / lower code selection unit 74 compares each gradation value of the subfield code constituting the intermediate code set generated by the intermediate code generation unit 72 with the input gradation. Then, the upper / lower code selection unit 74 selects a subfield code having a gradation value larger than the input gradation and closest to the input gradation, and outputs it as an upper gradation code. In addition, the upper / lower code selection unit 74 selects a subfield code having a gradation value equal to or lower than the input gradation and closest to the input gradation, and outputs it as a lower gradation code.
  • the display code selection unit 80 calculates a code conversion gradation value by adding a predetermined value to the input gradation. Then, the display code selection unit 80 selects one of the upper gradation code and the lower gradation code that has a gradation value closer to the code conversion gradation value, and outputs it as a display code.
  • the above-described predetermined value added to the input gradation is a code conversion error output from the error control circuit 39 and a dither value calculated by dither processing. Therefore, the display code selection unit 80 adds the code conversion error and the dither value to the input gradation.
  • the result of adding a predetermined value to the input gradation is referred to as a “code conversion gradation value”.
  • the display code selection unit 80 calculates the code conversion gradation value by adding the code conversion error and the dither value to the input gradation.
  • the predetermined value described above includes at least the code conversion error output from the error control circuit 39, but does not include the dither value when the dither processing is not performed.
  • the display code selection unit 80 selects, as a display code, one of the upper gradation code and the lower gradation code that has a gradation value closer to the code conversion gradation value.
  • the display code selection unit 80 adds the error to be displayed on the target pixel and the dither value to the input gradation to calculate the gradation value to be displayed on the target pixel, and the gradation to be displayed on the target pixel.
  • the difference between the value and the gradation value of the display code is calculated, and the difference is output to the error control circuit 39 as an error.
  • the display code selection unit 80 includes a dither selection unit 82 and a display code determination unit 86.
  • the dither selection unit 82 stores a plurality of dither patterns. Then, one dither pattern is selected from a plurality of stored dither patterns based on the image signal and the attribute detected by the attribute detection unit 41.
  • the dither selection unit 82 selects a dither element corresponding to the position of the pixel from the selected dither pattern based on the position of the pixel displaying the image signal. Further, the dither selection unit 82 calculates the dither value by multiplying the selected dither element by the difference between the gradation value of the upper gradation code and the gradation value of the lower gradation code.
  • FIG. 10A is a diagram illustrating an example of a dither pattern used in the image display device 30 according to an embodiment of the present invention.
  • FIG. 10B is a diagram showing another example of the dither pattern used in the image display device 30 according to the embodiment of the present invention.
  • one column represents one pixel.
  • FIG. 10A shows the simplest binary dither.
  • “+0.25” and “ ⁇ 0.25” are arranged in a checkered pattern as dither elements.
  • FIG. 10B is a diagram showing an example of quaternary dither. In FIG. 10B, dither elements “+0.375”, “+0.125”, “ ⁇ 0.375” and “ ⁇ 0.125” are arranged.
  • the dither selection unit 82 stores, for example, the two types of dither patterns shown in FIGS. 10A and 10B, and selects either one of the dither patterns based on the image signal and the attribute detected by the attribute detection unit 41. .
  • the dither pattern shown in FIG. 10A is selected, the dither element is either “+0.25” or “ ⁇ 0.25”.
  • the dither element shown in FIG. 10B is selected, the dither element is “+0”. .375 ”,“ +0.125 ”,“ ⁇ 0.375 ”, and“ ⁇ 0.125 ”.
  • the dither selection unit 82 selects any one of these dither elements based on the position of the pixel displaying the image signal.
  • the error control circuit 39 calculates the code conversion error by adding the horizontal error to the vertical error when the interlaced write power Pint is sequentially smaller than the write power Pprg. Then, the code conversion error is output to the subfield code conversion circuit 37.
  • the error control circuit 39 limits the magnitude of the vertical error, and adds the limited vertical error to the horizontal error for code conversion. Calculate the error. Then, the code conversion error is output to the subfield code conversion circuit 37. Furthermore, the error control circuit 39 calculates an error to be displayed on the target pixel by adding the horizontal error to the unrestricted vertical error. Then, the calculation result (error to be displayed on the target pixel) is output to the subfield code conversion circuit 37.
  • the error control circuit 39 includes an error diffusion unit 84 and an error limiting unit 85.
  • the error diffusion unit 84 diffuses the error output from the display code selection unit 80 to the peripheral pixels of the target pixel.
  • the error limiting unit 85 calculates a code conversion error and an error to be displayed on the target pixel based on the error output from the error diffusion unit 84.
  • the error output from the error diffusion unit 84 is an error that has already been calculated in the error diffusion unit 84 and should be diffused from the pixel adjacent to the target pixel to the target pixel.
  • the error generated in the target pixel is arranged in the pixel arranged to the right of the target pixel, the pixel arranged in the lower left of the target pixel, the pixel arranged under the target pixel, and the lower right of the target pixel. Diffuse to each pixel of the pixel.
  • the pixel arranged at the upper left of the target pixel, the pixel arranged above the target pixel, and the pixel arranged at the upper right of the target pixel A sum of errors diffused from each pixel to the target pixel is defined as a vertical error. Further, an error diffused from the pixel arranged on the left of the target pixel to the target pixel is defined as a lateral error. Then, different processing is performed for the vertical error and the horizontal error.
  • FIG. 11 is a schematic diagram for explaining operations of the error diffusing unit 84 and the error limiting unit 85 of the image display device 30 in the embodiment of the present invention.
  • one column represents one pixel.
  • the middle column in FIG. 11 represents a pixel (target pixel) that is a target of error diffusion processing.
  • the error diffusion unit 84 is a value obtained by multiplying the error generated in the pixel arranged at the upper left of the target pixel by the diffusion coefficient k1, and a value obtained by multiplying the error generated in the pixel arranged above the target pixel by the diffusion coefficient k2. And a value obtained by multiplying the error generated in the pixel arranged at the upper right of the target pixel by the diffusion coefficient k3 are added to each other, and the addition result is output to the error limiting unit 85 as a vertical error to be added to the target pixel. Further, the error diffusion unit 84 outputs a value obtained by multiplying the error generated in the pixel arranged on the left of the target pixel by the diffusion coefficient k4 to the error limiting unit 85 as a lateral error to be added to the target pixel.
  • the error diffusion unit 84 diffuses (adds) a value obtained by multiplying the error generated in the target pixel by the diffusion coefficient k4 to the pixel arranged on the right side of the target pixel. Further, the error diffusion unit 84 diffuses (adds) a value obtained by multiplying the error generated in the target pixel by the diffusion coefficient k3 to the pixel arranged at the lower left of the target pixel. Further, the error diffusion unit 84 diffuses (adds) a value obtained by multiplying the error generated in the target pixel by the diffusion coefficient k2 to the pixel arranged below the target pixel. Further, the error diffusion unit 84 diffuses (adds) a value obtained by multiplying the error generated in the target pixel by the diffusion coefficient k1 to the pixel arranged at the lower right of the target pixel.
  • which diffusion coefficient is selected is determined using a random number generated by a random number generator (not shown).
  • the error limiting unit 85 calculates a code conversion vertical error by limiting the vertical error output from the error diffusion unit 84 based on a limit value set in advance to limit the size of the vertical error. Then, the error limiting unit 85 calculates the code conversion error by adding the code conversion vertical error and horizontal error to each other, and outputs the calculated code conversion error to the display code determination unit 86. To do.
  • the vertical error output from the error diffusion unit 84 is input to the error limiting unit 85. Further, the error limiting unit 85 receives the sequential write power Pprg and the interlaced write power Pint one field before output from the subfield code arrangement circuit 38, and further receives the power control signal Cnt. Then, the error limiting unit 85 limits the magnitude of the vertical error based on the input signals and calculates the code conversion vertical error.
  • the vertical error for code conversion is calculated by the following equation.
  • Vertical error for code conversion sgn (vertical error) ⁇ Max (0, abs (vertical error) ⁇ K ⁇ Min (Cnt, IP))
  • Cnt is a power control signal Cnt input to the error control circuit 39 from the outside of the image signal processing circuit 31.
  • K is a constant.
  • abs (x) is a function for obtaining the absolute value of x
  • Min (x, y) is a function for obtaining the smaller one of x and y (including the case where they are equal)
  • Max (x, y y) is a function for obtaining the larger one (including the case where x and y are equal).
  • sgn (x) is a function for obtaining the sign (+ or ⁇ ) of x.
  • IP is the power ratio between the sequential write power Pprg and the interlaced write power Pint, and is calculated by the following equation.
  • IP Pint / (Pint + Pprg)
  • the power ratio IP is a numerical value in a range from “0” to “1”. If the power ratio IP is a numerical value relatively close to “0”, it indicates that the write power Pprg is sequentially larger than the interlaced write power Pint. Further, if the power ratio IP is a numerical value relatively close to “1”, it indicates that the interlaced write power Pint is larger than the sequential write power Pprg.
  • the vertical error for code conversion is almost equal to the vertical error, and the image signal processing circuit 31 performs normal error diffusion processing.
  • the vertical error for code conversion becomes smaller than the vertical error. Therefore, when the display code selection unit 80 selects a display code, the influence of the lateral error becomes relatively large.
  • the power consumption of the data electrode driving circuit 32 can be suppressed by performing such an operation in the image signal processing circuit 31. The reason will be described below.
  • Dither processing and error diffusion processing are methods of displaying on the panel 10 pseudo gradation values not included in the display code. However, when dither processing or error diffusion processing is performed, fine patterns appearing on the panel 10 are generated by performing these processing, although they are not included in the image signal.
  • the user averages and observes the gradation values displayed on adjacent pixels.
  • this phenomenon is used, and the gradation values not included in the intermediate code set are displayed on the panel 10 in a pseudo manner using a plurality of gradation values included in the intermediate code set. That is, by displaying a plurality of gradation values included in the intermediate code set on a plurality of adjacent pixels, the user averages and observes the gradation values displayed on those pixels, and the intermediate code set It is perceived that gradation values not included in the screen are displayed on the panel 10. Therefore, even if the number of gradation values that can be displayed by individual pixels is limited, an image can be displayed on the panel 10 using a larger number of gradation values than the limited number.
  • a pixel that displays a gradation value higher than the gradation value based on the image signal and a gradation value lower than the gradation value based on the image signal are displayed.
  • the pixels to be arranged are arranged in a certain pattern. This pattern depends on the diffusion coefficients k1 to k4 used in the error diffusion process. This pattern may be perceived by the user as a fine pattern (pattern) appearing on the panel 10 by the error diffusion process.
  • the diffusion coefficient k2 for diffusing the error in the vertical direction and the diffusion coefficient k4 for diffusing the error in the diagonal direction are set by relatively setting a diffusion coefficient k2 for diffusing the error in the vertical direction and the diffusion coefficient k4 for diffusing the error in the horizontal direction.
  • the coefficient k3 is set to a relatively small value, a checkered pattern is likely to occur on the panel 10.
  • the voltage applied to the data electrode 22 is changed from the voltage 0 (V) to the voltage Vd, or from the voltage Vd to the voltage 0 (V).
  • the number of times of switching is relatively increased, and the power consumption of the data electrode drive circuit 32 is relatively likely to increase.
  • the diffusion coefficient k1 and diffusion coefficient k3 for diffusing errors in the oblique direction and the diffusion coefficient k4 for diffusing errors in the horizontal direction are set to relatively large values, and the errors are diffused in the vertical direction. If the diffusion coefficient k2 is set to a relatively small numerical value, a vertical line pattern is likely to occur on the panel 10.
  • Such a vertical line pattern can relatively suppress the power consumption of the data electrode drive circuit 32, but the pattern is easily perceived by the user, and the image display quality is likely to be deteriorated.
  • the diffusion coefficient k2 for diffusing the error in the vertical direction and the diffusion coefficient k1 and the diffusion coefficient k3 for diffusing the error in the oblique direction are relatively It is set to the same value.
  • the inventor of the present application obtained the following results as a result of examining the diffusion coefficient.
  • the vertical error (code conversion vertical error) used when selecting the display code based on the input gradation and the error diffusion vertical error are set as different systems.
  • the display code selection unit 80 selects a display code based on the input gradation, the influence of the vertical error is limited and the influence of the horizontal error is dominant. In this way, when displaying a natural image on the panel 10, the power consumption of the data electrode driving circuit 32 is suppressed, and a pattern that is relatively difficult for the user to perceive (appears on the panel 10 by error diffusion processing). A fine pattern) occurs.
  • the voltage applied to the data electrode 22 is set to a voltage of 0 (V) compared to when displaying an image of a geometric pattern such as a checkered pattern on the panel 10. It is considered that the number of times of switching from voltage Vd to voltage Vd or voltage Vd to voltage 0 (V) is relatively small, and the power consumption of the data electrode driving circuit 32 is relatively easily suppressed.
  • the code conversion gradation value is calculated using the code conversion error, and the gradation value to be displayed on the target pixel using the unrestricted vertical error. Is calculated. Then, the difference between the code conversion gradation value and the gradation value to be displayed on the target pixel is diffused as an error to the peripheral pixels of the target pixel. Therefore, unlike a one-dimensional error diffusion process that diffuses an error only in the horizontal direction, a decrease in average luminance (average luminance of one screen) in a display image is prevented. Then, a vertically long pattern whose length is determined stochastically occurs in the display image.
  • the array selection unit 95 selects the interlace write operation, the code conversion vertical error Is set to a value substantially equal to the vertical error, and normal error diffusion processing is performed.
  • the array selecting unit 95 sequentially selects the write operation. Therefore, at that time, the code conversion vertical error is made smaller than the vertical error, the power consumption of the data electrode drive circuit 32 is suppressed, and an error diffusion process that generates a pattern that is relatively difficult for the user to perceive is performed.
  • the power control signal Cnt is a control signal provided to limit the upper limit value of the power ratio IP. If the power control signal Cnt is set to a small value, the vertical error for code conversion can always be made equal to the vertical error regardless of the magnitude of the power ratio IP.
  • the error limiting unit 85 calculates the code conversion error calculated by adding the horizontal error to the vertical error whose size is limited, and the attention calculated by adding the horizontal error to the vertical error which is not limited.
  • the error to be displayed on the pixel is output to the display code determination unit 86.
  • the display code determination unit 86 of the subfield code conversion circuit 37 actually displays an image based on the input gradation, the dither value output from the dither selection unit 82, and the code conversion error output from the error limiting unit 85.
  • the display code used for is determined as either the upper gradation code or the lower gradation code.
  • the display code determination unit 86 calculates a code conversion gradation value by adding a dither value and a code conversion error to the input gradation.
  • the display code is selected as the display code.
  • the display code determination unit 86 adds the dither value and the error to be displayed on the target pixel to the input gradation, and calculates the gradation value to be displayed on the target pixel.
  • the display code determination unit 86 calculates the difference between the gradation value to be displayed on the target pixel and the gradation value of the display code, and outputs the difference to the error diffusion unit 84 as a newly generated error.
  • the image signal processing circuit 31 operates based on the following conditions. 1)
  • the base code set shown in FIG. 8A is used as the base code set. 2)
  • the rules used in the description of FIG. 9A are used. That is, rule 1 “change any one of the lighting subfields to a non-lighting subfield” is used. 3) Based on the attribute accompanying the image signal, “Rule for setting sub-field forbidden to turn off” (rule 3) is added to rule 1.
  • FIG. 12 is a flowchart showing the operation of the image signal processing circuit 31 of the image display device 30 according to the embodiment of the present invention.
  • the image signal processing circuit 31 executes the following series of steps.
  • Step S41 An image signal corresponding to one pixel (target pixel) is input to the image signal processing circuit 31.
  • the attribute detection unit 41 detects an attribute associated with the image signal.
  • the image signal corresponding to the target pixel has a gradation value (input gradation) of “25”, and the attribute detection unit 41 detects that the attribute associated with the image signal is a moving image and a contour portion.
  • the description will be given on the assumption that it was obtained.
  • Step S50 The base code generation unit 50 selects an upper tone base code corresponding to the image signal.
  • step S50 the sub-field code having a gradation value that is larger than the gradation value of the image signal at the target pixel and closest to the gradation value of the image signal at the target pixel is selected from the plurality of basic sub-field codes.
  • the field code is selected as the upper gradation base code.
  • the base code generation unit 50 compares each tone value of the base code constituting the base code set stored in the base code storage unit 52 with the input tone. Then, a base code having a gradation value larger than the input gradation and closest to the input gradation is selected and output as an upper gradation base code.
  • the base code generation unit 50 selects the base code “11111100” having the gradation value “32” and outputs it as the upper gradation base code.
  • Step S61 The rule generation unit 61 generates a rule for generating an intermediate code set.
  • step S61 a rule for generating a new subfield code by changing the light emitting subfield in the upper gradation base code to a non-light emitting subfield is generated based on the image signal at the target pixel.
  • the rule generation unit 61 performs a basic rule (rule 1) “change any one of the lighting subfields to the non-lighting subfield” if the attribute attached to the image signal is a still image. ) Is generated.
  • the rule generation unit 61 restricts the subfield codes that can be used for displaying the image in order to suppress the moving image pseudo contour.
  • the subfield codes include those that have a high effect of suppressing moving image pseudo contours and those that do not.
  • the base codes shown in FIGS. 8A to 8C are subfield codes that have a high effect of suppressing the moving image pseudo contour.
  • the appearance of the moving image pseudo contour depends on the subfield code that can be used to display the image, and the image is displayed using the subfield code that is highly effective in suppressing the moving image pseudo contour.
  • the moving image pseudo contour can be suppressed.
  • the subfield code that can be used for displaying an image is limited as compared with the case where the suppression of the moving image pseudo contour is unnecessary. This is the reason why the rule generation unit 61 restricts the subfield codes that can be used for image display in order to suppress the moving image pseudo contour.
  • the rule generating unit 61 sets “a subfield that prohibits non-lighting” in the basic rule 1 in order to suppress the moving image pseudo contour. Add “When the rule”.
  • This additional rule is, for example, rule 3 described with reference to FIG. 9C, that “subfield SF1 and subfield SF2 are prohibited from being non-lighting subfields”.
  • the rule generation unit 61 limits the subfield codes that can be used for displaying an image.
  • the rule generated by the rule generation unit 61 is that the attribute attached to the image signal is a still image.
  • the rule generation unit 61 includes a rule that is generated when the image signal at the target pixel is a still image.
  • Step S72 The intermediate code generation unit 72 generates an intermediate code set.
  • the intermediate code generation unit 72 generates an intermediate code from the upper gradation base code based on the rules generated by the rule generation unit 61, and generates an intermediate code set.
  • step S50 For example, if the upper tone base code selected in step S50 is the base code “11111100” having the tone value “32” and the rules generated by the rule generation unit 61 are rule 1 and rule 3, intermediate code generation is performed.
  • the unit 72 applies the rules 1 and 3 generated by the rule generation unit 61 to the base code “11111100” to generate a new intermediate code.
  • the subfields SF1 to SF6 which are the lighting subfields of the base code “11111100”
  • the subfields (subfield SF3 to subfield are excluded based on rule 3 except for subfield SF1 and subfield SF2).
  • SF6 is to be replaced with a non-lighting subfield.
  • the subfields SF3 to SF6 are set to non-lighting subfields.
  • the intermediate code generation unit 72 generates four intermediate codes “11111000”, “11110100”, “11101100”, and “11011100”.
  • the intermediate code set thus obtained is, for example, the intermediate code set shown in FIG. 9C.
  • the upper / lower code selection unit 74 selects an upper gradation code and a lower gradation code.
  • step S74 the tone value of the image signal at the target pixel is larger than the tone value of the image signal at the target pixel from the intermediate code set generated by applying the above-described rule to the upper tone base code.
  • the subfield code having the closest gradation value is selected as the upper gradation code, and the subfield code having the gradation value closest to the gradation value of the image signal at the target pixel is equal to or smaller than the gradation value of the image signal at the target pixel.
  • Select the field code as the lower gradation code.
  • the upper / lower code selection unit 74 compares each gradation value of the subfield code constituting the intermediate code set with the input gradation. Then, a subfield code having a gradation value larger than the input gradation and closest to the input gradation is selected and output as an upper gradation code. Also, a subfield code having a gradation value that is equal to or lower than the input gradation and closest to the input gradation is selected, and is output as a lower gradation code.
  • the subfield code corresponding to the upper gradation code is gradation. It is a subfield code of value “27”.
  • the subfield code corresponding to the lower gradation code is a subfield code having a gradation value of “24”. Therefore, the upper / lower code selection unit 74 selects the subfield code “11101100” having the gradation value “27” as the upper gradation code, and the subfield code “11110100” having the gradation value “24” as the lower gradation code. ”Is selected.
  • Step S82 The dither selection unit 82 selects a dither element based on the attribute of the image signal.
  • the dither selection unit 82 uses the attribute detected by the image signal and attribute detection unit 41. Based on the above, one of the dither patterns is selected.
  • the dither pattern shown in FIG. 10A is selected. If the attribute attached to the image signal is not a contour portion, the dither pattern shown in FIG. 10B is selected. If the selection unit 82 is set, when the attribute attached to the image signal is a contour portion, the dither selection unit 82 selects the dither pattern shown in FIG. 10A. Then, the dither selection unit 82 selects one of the dither elements set in the dither pattern based on the position of the target pixel. For example, the dither selection unit 82 selects “0.25” as the dither element based on the dither pattern shown in FIG. 10A.
  • Step S83 The dither selector 82 calculates a dither value.
  • the dither selection unit 82 calculates the dither value by multiplying the selected dither element by the difference between the tone value of the upper tone code and the tone value of the lower tone code.
  • the upper gradation code selected in step S74 is the gradation value “27”, the gradation value of the lower gradation code selected in step S74 is “24”, and the dither selected in step S82. If the element is “0.25”, the dither selector 82 multiplies the difference “3” between the gradation value of the upper gradation code and the gradation value of the lower gradation code by the dither element “0.25”. Then, the dither value “0.75” is calculated.
  • Step S85 The error limiting unit 85 calculates the vertical error for code conversion and the error to be displayed on the target pixel.
  • the error limiting unit 85 receives the vertical error and the horizontal error output from the error diffusion unit 84, sequentially receives the write power Pprg and the interlaced write power Pint, and further receives the power control signal Cnt. Then, the error limiting unit 85 calculates the vertical error for code conversion and the error to be displayed on the target pixel based on these input signals.
  • the vertical error for code conversion is the following numerical value.
  • the error “ ⁇ 0.5” to be displayed on the target pixel which is calculated by adding the horizontal error “2.5” to the vertical error “ ⁇ 3.0”, is output to the display code determination unit 86.
  • the array selection unit 95 sequentially selects the write operation. Therefore, even in the current field, there is a high possibility that the array selection unit 95 selects the sequential write operation.
  • the error limiting unit 85 sets the vertical error for code conversion to a numerical value smaller than the vertical error. Thus, the power consumption of the data electrode driving circuit 32 is suppressed.
  • Step S86 The display code determination unit 86 calculates a tone value for code conversion and a tone value to be displayed on the target pixel.
  • step S86 a predetermined value is added to the gradation value of the image signal in the target pixel to calculate the code conversion gradation value and the gradation value to be displayed on the target pixel.
  • the display code determination unit 86 adds the dither value calculated in step S83 to the input gradation, and further adds the code conversion error calculated in step S85 to obtain the code conversion floor. Calculate the key value.
  • the display code determination unit 86 adds the dither value calculated in step S83 to the input gradation, and further adds the error to be displayed to the target pixel calculated in step S85, and displays it on the target pixel.
  • the gradation value to be calculated is calculated.
  • the above-mentioned predetermined value is a numerical value obtained by adding the vertical error for code conversion output from the error limiting unit 85 or the error to be displayed on the target pixel to the dither value output from the dither selection unit 82.
  • the code conversion gradation value is “27.25”.
  • Step S87 The display code determining unit 86 determines a display code to be used when displaying the gradation value on the target pixel.
  • step S87 the upper gradation code and the lower gradation code having the gradation value closer to the code conversion gradation value is selected as the display code.
  • the display code determining unit 86 compares the code conversion gradation value with the gradation value of the upper gradation code and the gradation value of the lower gradation code. If the tone value for code conversion is closer to the tone value of the upper tone code than the tone value of the lower tone code, the upper code is displayed as the display code used when displaying the tone value on the target pixel. Select the gradation code and output it. If the tone value for code conversion is closer to the tone value of the lower tone code than the tone value of the upper tone code, the display code used when displaying the tone value on the target pixel Select the lower gradation code and output it.
  • the display code determination unit 86 outputs the lower gradation code “11101100” having the gradation value “27” as the display code.
  • Step S88 The display code determination unit 86 calculates a newly generated error and outputs it to the error diffusion unit 84.
  • the display code determination unit 86 subtracts the gradation value of the display code from the gradation value to be displayed on the target pixel, and outputs the subtraction result to the error diffusion unit 84 as a newly generated error.
  • the display code determination unit 86 outputs “ ⁇ 1.75” to the error diffusion unit 84 as a newly generated error.
  • step S88 When step S88 is completed, the process returns to step S41. In this way, a series of steps from step S41 to step S88 are repeatedly executed.
  • the sequential writing array unit 91 rearranges the array of subfield codes for the image signal of one field output from the subfield code conversion circuit 37 in the order corresponding to the sequential writing operation.
  • the interlaced writing array unit 92 rearranges the array of subfield codes for the image signal of one field output from the subfield code conversion circuit 37 in the order corresponding to the interlaced writing operation.
  • the power predicting unit 93 calculates the sequential write power Pprg of the data electrode driving circuit 32 based on the subfield code output from the sequential write array unit 91.
  • the power predicting unit 94 calculates the interlaced write power Pint of the data electrode drive circuit 32 based on the subfield code output from the interlaced write array unit 92.
  • the array selection unit 95 sequentially compares the write power Pprg and the interlaced write power Pint, and selects the one with the smaller numerical value.
  • the sequential write power Pprg is selected, the subfield code output from the sequential write array unit 91 is output to the data electrode drive circuit 32.
  • the interlaced write power Pint is selected, the subfield code output from the interlaced write array unit 92 is output to the data electrode drive circuit 32.
  • conversion from an image signal to a display code can be performed by calculation using an arithmetic circuit. Therefore, even in such an image display device, it is not necessary to provide a huge number of conversion tables, and a minimum necessary table (for example, the base code set shown in FIGS. 8A, 8B, and 8C) and an image signal It is only necessary to provide an arithmetic circuit for converting from to display code.
  • the write operation is performed by either the sequential write operation or the interlaced write operation. Further, the error value used for the error diffusion process is controlled in accordance with the selected write operation. Thereby, the power consumption in the data electrode drive circuit 32 is suppressed while using both the error diffusion process and the dither process.
  • the conversion from the image signal to the subfield code can be performed by the logical operation, and the data electrode drive circuit is prevented while preventing the image display quality from being deteriorated.
  • the power consumption in 32 can be suppressed.
  • the configuration in which the base code generation unit 50 has the base code storage unit 52 and the base code set is stored in advance in the base code storage unit 52 has been described.
  • the present invention is not limited to this configuration.
  • a configuration may be adopted in which a rule for generating a base code is determined in advance and the base code is generated based on the rule.
  • the upper / lower code generation unit 70 selects the upper gradation code and the lower gradation code by the upper / lower code selection unit 74 after the intermediate code set is generated by the intermediate code generation unit 72.
  • the present invention is not limited to this configuration.
  • an intermediate code is generated in order of increasing gradation value, and at the same time, the intermediate code and the input gradation are sequentially compared to select the upper gradation code and the lower gradation code.
  • dither processing and error diffusion processing are performed after setting a subfield for prohibiting the write operation. Therefore, even in the image display device 30 that selects a display code from an intermediate code set having a limited number of subfield codes and uses it to display an image, it is possible to prevent a decrease in image display quality.
  • the display code selection unit 80 includes the dither selection unit 82
  • the present invention is not necessarily limited to this configuration.
  • the dither selection unit 82 may be omitted.
  • the number of subfields constituting one field, the subfields that are forced initialization subfields, the gradation weights of each subfield, and the like are not limited to the above-described numerical values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.
  • the drive voltage waveform shown in FIG. 3 is merely an example in the embodiment of the present invention, and the present invention is not limited to this drive voltage waveform.
  • circuit configurations shown in FIGS. 5, 6, and 7 are merely examples in the embodiment of the present invention, and the present invention is not limited to these circuit configurations.
  • each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.
  • the number of subfields constituting one field is not limited to the above number.
  • the number of gradations that can be displayed on the panel 10 can be further increased.
  • the time required for driving panel 10 can be shortened by reducing the number of subfields.
  • one pixel is constituted by discharge cells of three colors of red, green, and blue.
  • a panel in which one pixel is constituted by discharge cells of four colors or more has been described.
  • the specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 14 of 1024. It is just an example.
  • the present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.
  • the number of subfields constituting one field, the gradation weight of each subfield, and the like are not limited to the values shown in the embodiment of the present invention, and the subfield configuration is based on an image signal or the like. May be configured to switch.
  • the present invention since conversion from an image signal to a subfield code can be performed by calculation, it is not necessary to use a conversion table composed of a large number of subfield codes, and power consumption can be prevented while preventing deterioration in image display quality. Therefore, the present invention is useful as an image display device that displays an image in an image display region by combining binary control of light emission and non-light emission in a light emitting element that constitutes a pixel, and a driving method of the image display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)

Abstract

Selon l'invention, la conversion d'un signal d'image en un code de sous-champ dans un dispositif de visualisation d'image est calculée sans recours à une table de conversion. A cette fin, le dispositif de visualisation d'image comprend un circuit de conversion de code de sous-champ (37), un circuit de réseau de codes de sous-champ (38), et un circuit de contrôle d'erreur (39). Le circuit de conversion de code de sous-champ (37) effectue un traitement de diffusion d'erreur sur un signal d'image et convertit le signal d'image en un code de sous-champ. Le circuit de réseau de codes de sous-champ (38) sélectionne soit une opération d'écriture séquentielle, soit une opération d'écriture discontinue sur la base d'une comparaison entre une puissance d'écriture séquentielle et une puissance d'écriture discontinue, et réorganise le code de sous-champ. Sur la base de cette comparaison entre la puissance d'écriture discontinue et la puissance d'écriture séquentielle, le circuit de contrôle d'erreur (39) ajoute l'erreur horizontale diffusée par des pixels orientés horizontalement à l'erreur verticale diffusée par des pixels orientés verticalement; ajoute à l'erreur horizontale l'erreur verticale dont la taille est limitée ou l'erreur de conversion de code calculée; et envoie l'erreur de conversion de code calculée au circuit de conversion de code de sous-champ.
PCT/JP2012/000336 2011-01-20 2012-01-20 Dispositif de visualisation d'image et procédé de commande pour dispositif de visualisation d'image WO2012098903A1 (fr)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06332416A (ja) * 1993-05-25 1994-12-02 Canon Inc 表示制御装置
JP2002258793A (ja) * 2001-02-27 2002-09-11 Nec Corp プラズマ表示装置及びその駆動方法
JP2005010573A (ja) * 2003-06-20 2005-01-13 Victor Co Of Japan Ltd 画像表示装置の誤差拡散処理方法
JP2006071774A (ja) * 2004-08-31 2006-03-16 Lg Electronics Inc 表示パネルの駆動装置
JP2006079063A (ja) * 2004-09-13 2006-03-23 Lg Electronics Inc プラズマディスプレイパネル制御方法及び装置
JP2009168952A (ja) * 2008-01-11 2009-07-30 Hitachi Ltd プラズマディスプレイ装置
WO2009096186A1 (fr) * 2008-01-31 2009-08-06 Panasonic Corporation Dispositif d'affichage à plasma

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06332416A (ja) * 1993-05-25 1994-12-02 Canon Inc 表示制御装置
JP2002258793A (ja) * 2001-02-27 2002-09-11 Nec Corp プラズマ表示装置及びその駆動方法
JP2005010573A (ja) * 2003-06-20 2005-01-13 Victor Co Of Japan Ltd 画像表示装置の誤差拡散処理方法
JP2006071774A (ja) * 2004-08-31 2006-03-16 Lg Electronics Inc 表示パネルの駆動装置
JP2006079063A (ja) * 2004-09-13 2006-03-23 Lg Electronics Inc プラズマディスプレイパネル制御方法及び装置
JP2009168952A (ja) * 2008-01-11 2009-07-30 Hitachi Ltd プラズマディスプレイ装置
WO2009096186A1 (fr) * 2008-01-31 2009-08-06 Panasonic Corporation Dispositif d'affichage à plasma

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