WO2012097745A1 - 一种功放供电电路及终端 - Google Patents

一种功放供电电路及终端 Download PDF

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Publication number
WO2012097745A1
WO2012097745A1 PCT/CN2012/070600 CN2012070600W WO2012097745A1 WO 2012097745 A1 WO2012097745 A1 WO 2012097745A1 CN 2012070600 W CN2012070600 W CN 2012070600W WO 2012097745 A1 WO2012097745 A1 WO 2012097745A1
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WO
WIPO (PCT)
Prior art keywords
power amplifier
voltage
resistor
power
pin
Prior art date
Application number
PCT/CN2012/070600
Other languages
English (en)
French (fr)
Inventor
钱泽旭
Original Assignee
华为终端有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为终端有限公司 filed Critical 华为终端有限公司
Priority to JP2012554212A priority Critical patent/JP5519031B2/ja
Publication of WO2012097745A1 publication Critical patent/WO2012097745A1/zh

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216Continuous control
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3036Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H03G3/3042Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/451Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/504Indexing scheme relating to amplifiers the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier

Definitions

  • the present invention relates to the field of communications, and in particular, to a power amplifier power supply circuit and a terminal.
  • terminals supporting wireless data services mainly include: wireless data cards, mobile phones, and the like.
  • the uplink process for transmitting signals by the terminal includes the RF signal being amplified by a PA (Power Amplifier, power amplifier, referred to as a power amplifier), and the amplified RF signal is transmitted from the antenna to the space.
  • the PA is an important energy-consuming component in the uplink process of the above terminal. If the efficiency of the PA is low, the power consumption of the whole device will be large.
  • the power supply circuits in the two terminals in the prior art are separately described below.
  • V BAT is the output voltage of the battery, and the voltage is generally stabilized at 3.7V to 4.2V, which is used as the power supply voltage of the PA.
  • U1 is a DC/DC converter chip (also known as DC/DC switching power supply chip);
  • is a wireless data card operating power supply, which is portable
  • the machine is provided through common peripheral interfaces such as USB (Universal Serial Bus) interface, PCMCIA (Personal Computer Memory Card International Association) interface or ExpressCard interface;
  • the PA supply voltage, V FB is a DC / DC switching power supply feedback reference chip, which is a fixed value, obviously, when the fixed and ⁇ , ⁇ OT the PA supply voltage is also a fixed value.
  • the supply voltage of the PA in the prior art is constant.
  • the output power of the required PA changes.
  • the whole machine is made full.
  • the supply voltage of the required PA will decrease accordingly.
  • the PA itself has a certain degree of dispersion. Under the premise that the whole machine meets the radio frequency index, the required power supply voltage of the PA is also different.
  • the power supply voltage of the PA is a constant value, which cannot be used according to the It needs to change the power supply voltage of the PA, which causes the efficiency of the PA to be low, which in turn leads to a large power consumption of the whole machine.
  • Embodiments of the present invention provide a power amplifier power supply circuit and a terminal for improving the efficiency of a power amplifier in a terminal, thereby reducing power consumption of the terminal.
  • a power amplifier power supply circuit includes a DC/DC converter chip, the DC/DC converter chip includes an input pin, an inductor connection pin, and a feedback pin, the input pin is used for connecting a power source, and the inductor
  • the connection pin is connected to the voltage input end of the power amplifier through an LC energy storage circuit, and a control circuit is connected between the voltage input end of the power amplifier and the feedback pin;
  • the control circuit includes a control voltage The control voltage adjusts a voltage of a voltage input terminal of the power amplifier through the control circuit; and the control voltage is variable.
  • a terminal includes a baseband processing unit, a power amplifier power supply circuit, and a power amplifier.
  • the power amplifier power supply circuit includes a DC/DC converter chip, and the DC/DC converter chip includes an input pin, an inductor connection pin, and a feedback pin.
  • the input pin is used for connecting a power source, and the inductive connection pin is connected to a voltage input end of the power amplifier through an LC energy storage circuit, and the voltage input end of the power amplifier and the feedback tube a control circuit is connected between the feet, and the control circuit includes a control voltage;
  • the baseband processing unit is configured to adjust the control voltage, and the control voltage adjusts a voltage of a voltage input terminal of the power amplifier through the control circuit.
  • the power amplifier circuit and the terminal provided by the embodiment of the invention add a control circuit between the voltage input end of the power amplifier and the feedback pin of the DC/DC converter chip, and the control circuit Introducing a variable control voltage that can be adjusted by the control circuit to adjust the voltage at the voltage input of the power amplifier so that the voltage at the voltage input of the power amplifier can be varied according to actual needs, thereby improving the efficiency of the power amplifier and thereby reducing Power loss of the terminal.
  • FIG. 1 is a circuit diagram of a power amplifier power supply circuit in the prior art
  • FIG. 2 is a circuit diagram of another power amplifier power supply circuit in the prior art
  • FIG. 3 is a schematic circuit diagram of a power amplifier power supply circuit according to an embodiment of the present invention.
  • Figure 4 is a flow chart of a method of calibrating a control voltage
  • FIG. 5 is a circuit diagram of a power amplifier power supply circuit according to Embodiment 1 of the present invention.
  • FIG. 6 is a circuit diagram of another power amplifier power supply circuit according to Embodiment 1 of the present invention.
  • Figure ⁇ is a circuit diagram of a power amplifier power supply circuit according to Embodiment 2 of the present invention.
  • FIG. 8 is a circuit diagram of another power amplifier power supply circuit according to Embodiment 2 of the present invention.
  • FIG. 9 is a circuit diagram of a power amplifier power supply circuit according to Embodiment 3 of the present invention.
  • FIG. 10 is a circuit diagram of another power amplifier power supply circuit according to Embodiment 3 of the present invention.
  • FIG. 11 is a schematic structural diagram of a terminal according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural view of the baseband processing unit of FIG. 11;
  • FIG. 13 is another schematic structural view of the baseband processing unit of FIG. 11;
  • Figure 14 is a schematic diagram of a calibration system that implements the method of Figure 4.
  • the embodiment of the present invention provides a power amplifier power supply circuit, as shown in FIG. 3, including a DC/DC converter chip (ie, a DC/DC switching power supply chip), and the DC/DC converter chip includes The input pin IN, the inductive connection pin LX, and the feedback pin FB, the input pin IN is used to connect the power supply V IN , and the inductive connection pin LX is connected to the voltage input end of the power amplifier PA through an LC storage circuit.
  • a control circuit is connected between the voltage input terminal of the power amplifier PA and the feedback pin FB;
  • the control circuit includes a control voltage Vc, and the control voltage Vc adjusts the voltage V OUT of the voltage input terminal of the power amplifier PA through the control circuit; and the control voltage Vc is variable.
  • the power amplifier power supply circuit adds a control circuit between the voltage input end of the power amplifier and the feedback pin of the DC/DC converter chip, and the control circuit introduces a variable control voltage.
  • the control voltage can adjust the voltage of the voltage input terminal of the power amplifier through the control circuit, so that the voltage of the voltage input terminal of the power amplifier can be changed according to actual needs; that is, when the voltage of the voltage input terminal of the power amplifier needs a small value, it can be normal.
  • the control voltage can adjust the voltage value of the power amplifier voltage input terminal to the smaller value through the control circuit, thereby improving the efficiency of the power amplifier.
  • the above power amplifier power supply circuit can be applied to a terminal.
  • control voltage Vc in the power amplifier power supply circuit has a corresponding relationship with the power level and the operating frequency of the power amplifier PA. For details, refer to Table 1.
  • the operating frequency of the power amplifier PA is n (n ⁇ l) frequency points divided by the radio frequency input to the power amplifier, and each power frequency point may be provided with m power levels, the power level It can be divided according to the output power of the PA.
  • Any power level at a certain operating frequency point of the power amplifier PA is referred to as a state of the power amplifier PA.
  • the control voltage Vc corresponding to the power amplifier PA in each state is recorded in Table 1.
  • the value, that is to say, the control voltage Vc can vary depending on the change in the power level of the power amplifier PA and/or the change in the operating frequency.
  • control voltage Vc can adjust the voltage V OUT of the voltage input terminal of the power amplifier PA through the control circuit, the voltage value V OUT of the voltage input terminal of the power amplifier PA can be changed according to the power level of the power amplifier PA and / Or change in the frequency of work.
  • the voltage value V OUT of the power amplifier PA voltage input terminal is as small as possible, so that the efficiency of the power amplifier can be provided.
  • the radio frequency indicator includes: ACLR (Adjacent Channel Leakage Ratio), output power and power of the power amplifier PA.
  • the RF indicators include: ACPR (Adjacent Channel Power Ratio), output power and power of the power amplifier PA The sensitivity of the amplifier PA, etc.
  • the power amplifier circuit in the terminal adjusts the V OUT value by using Vc in step 403, and tests the radio frequency index of the whole machine under the condition that the V OUT is used to supply power to the PA, and determines whether the whole machine meets the radio frequency index.
  • step 405 If the whole machine meets the radio frequency index, go to step 405; otherwise, increase the value of Vc in step 403, and repeat step 404.
  • a working frequency point (e.g., F1) of the power level (P1) is scanned, and step 406 can be continued.
  • step 407 If the scanning is completed, proceed to step 407; otherwise, return to step 403 to calibrate the Vc corresponding to the next frequency point (for example, F2).
  • step 402 Vc corresponding to one operating frequency point of the next power level (P2) is selected for calibration until the calibration of all Vc values in Table 1 is completed.
  • the above calibration process for Vc can be done by a computer equipped with calibration software.
  • the number of calibrations can be appropriately reduced; that is, only the Vc corresponding to the power amplifier PA in a partial state is calibrated, and the Vc value corresponding to other states can be obtained through a certain interpolation algorithm.
  • the optimal Vc value in the state is the optimal Vc value in the state.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • this embodiment provides a specific implementation scheme of a power amplifier power supply circuit.
  • a power amplifier power supply circuit includes a DC/DC converter chip U1.
  • the DC/DC converter chip U1 includes an input pin IN, an inductor connection pin LX, and a feedback pin FB.
  • the input pin IN is used to connect a power source V IN .
  • the inductive connection pin LX is connected to the voltage input end of the power amplifier PA through an LC storage circuit, and a control circuit is connected between the voltage input end of the power amplifier PA and the feedback pin FB;
  • control circuit in Figure 5 is marked with a dashed box.
  • the control circuit includes a control voltage Vc, and the control voltage Vc adjusts the voltage V OUT of the voltage input terminal of the power amplifier PA through the control circuit; and the control voltage Vc is variable.
  • the control voltage Vc can be adjusted according to the correspondence between the control voltage Vc recorded in Table 1 and the power level and operating frequency of the power amplifier PA.
  • the LC energy storage circuit includes an inductor L and a capacitor C2; the inductor L is connected to the inductor connection pin LX of the DC/DC converter chip U1 and the voltage input terminal of the power amplifier PA, and the voltage input terminal of the power amplifier PA Ground through capacitor C2.
  • control circuit includes a differential amplifier circuit, the differential amplifier circuit includes an operational amplifier U2;
  • the non-inverting input terminal of the operational amplifier U2 is connected to the voltage input terminal of the power amplifier PA through the first resistor R11, and the non-inverting input terminal is grounded through the second resistor R12;
  • control voltage Vc is applied to the inverting input terminal of the operational amplifier U2 through the third resistor R13, and the inverting input terminal is connected to the output terminal of the operational amplifier U2 through the fourth resistor R14 to form a feedback loop;
  • the output of the operational amplifier U2 is connected to the feedback pin FB of the DC/DC converter chip U1.
  • V + V_
  • V FB is a fixed value, so it is easy to obtain a linear relationship between V OUT and Vc.
  • the differential amplifying circuit in the power amplifier circuit shown in FIG. 5 is optimized: the output terminal of the operational amplifier U2 is connected to the feedback pin FB of the DC/DC converter chip U1 through a resistor R15. And the feedback pin FB is grounded through a resistor R16.
  • V V_
  • V FB is still a fixed value, so it is easy to obtain a linear relationship between V OUT and Vc. Further, in the design of the differential amplifying circuit, the resistances of the first resistor R11 and the third resistor R13 are generally equal, and the resistances of the second resistor R12 and the fourth resistor R14 are equal;
  • V FB is still a fixed value, and it can be known that V OUT and Vc have a linear relationship, so the voltage V OUT of the power amplifier PA voltage input terminal can be adjusted by adjusting Vc.
  • the control voltage Vc recorded in Table 1 is in a memory chip corresponding to the power level of the power amplifier PA and the operating frequency point, so that Vc can be adjusted according to the state of the power amplifier PA, due to the relationship between V OUT and Vc
  • V OUT can vary depending on changes in the power level of the PA and/or changes in the operating frequency.
  • the V OUT can be adjusted to the state under the premise that the whole machine satisfies the radio frequency index.
  • the minimum value can improve the efficiency of the PA.
  • the power amplifier power supply circuit adds a control circuit between the voltage input end of the power amplifier and the feedback pin of the DC/DC converter chip, and the control circuit is a differential amplification circuit; According to the change of the power level of the power amplifier and/or the change of the operating frequency, and the voltage of the voltage input of the power amplifier is linear with the control voltage, the control voltage can control the power amplifier when the power amplifier is in a certain state. The voltage at the voltage input terminal reaches the minimum value of the radio frequency index in this state, so that the efficiency of the power amplifier can be improved, thereby reducing the power loss of the terminal.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment provides another specific implementation scheme of the power amplifier power supply circuit. As shown in FIG. , the solution provided by this embodiment is only in the design of the control circuit compared to the solution in the first embodiment. The other parts are similar to the first embodiment, and therefore will not be described again.
  • the control circuit in this embodiment is indicated by a dashed box in FIG. 7.
  • the control circuit includes a P-channel type field effect transistor Q1 (P-MOS transistor), and Q1 in FIG. 7 is a P-channel enhancement type MOS transistor.
  • Q1 in FIG. 7 is a P-channel enhancement type MOS transistor.
  • the circuit connection of the P-channel depletion MOS transistor can also be referred to FIG.
  • the source S of Q1 is connected to the voltage input end of the power amplifier, the drain D is connected to the feedback pin FB of the DC/DC converter chip, and the drain D is grounded through a resistor R22; the control voltage Vc acts At the gate G of Q1, the on-resistance of Q1 is R ON .
  • Q1 can be controlled by the Vc to operate in the amplification region, and the functional relationship between Vc and R ON satisfies the monotonicity.
  • the P-channel in the amplification region In the case of a channel-enhanced MOS transistor, the functional relationship between Vc and R ON is monotonically increasing, that is, the smaller the Vc is, the smaller the R ON is.
  • V OUT can be adjusted by adaptively adjusting Vc.
  • the control circuit can be optimized according to Fig. 8.
  • the source S of Q1 is also connected to the voltage input terminal of the power amplifier PA through a resistor R23, and the voltage input terminal is connected to the feedback pin FB of the DC/DC converter chip through a resistor R21.
  • the correspondence between the data recorded in Table 1 can be stored on a board (specifically, a memory chip) of the terminal, so as to find and match according to the power level of the power amplifier PA and the working frequency. This state corresponds to Vc, which in turn adjusts V OUT .
  • the power amplifier power supply circuit provided by the embodiment of the present invention adds a control circuit between the voltage input end of the power amplifier and the feedback pin of the DC/DC converter chip, and the control circuit includes a control circuit.
  • the control voltage can be changed according to the power level of the power amplifier and / or work Changing the frequency point, and causing the P-channel MOS transistor to be turned on, and the on-resistance of the P-channel MOS transistor has a certain function relationship with the voltage of the power amplifier PA voltage input terminal, so that the power amplifier is in a certain In a state, the control voltage can control the voltage of the voltage input terminal of the power amplifier to reach the minimum value of the radio frequency index in the state, thereby improving the efficiency of the power amplifier, thereby reducing the power loss of the terminal.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • This embodiment provides another specific implementation scheme of the power amplifier power supply circuit. As shown in FIG. 9, the solution provided by the specific embodiment is different from the solution in the first embodiment only in the design of the control circuit, and other parts are similar to the first embodiment, and therefore will not be described again.
  • the control circuit in this embodiment is marked with a virtual frame in FIG. 9, the control circuit includes an N-channel type field effect transistor Q2 (N-MOS transistor); and Q2 in FIG. 9 is an N-channel enhancement type MOS transistor.
  • N-MOS transistor N-channel type field effect transistor
  • Q2 in FIG. 9 is an N-channel enhancement type MOS transistor.
  • the circuit connection for the N-channel depletion mode MOS transistor can also be referred to FIG.
  • the source S of Q2 is grounded, the drain D is connected to the feedback pin FB of the DC/DC converter chip, and the control voltage Vc acts on the gate G of Q2; in addition, the voltage input terminal of the power amplifier PA passes through a resistor
  • the R31 is connected to the feedback pin FB of the DC/DC converter chip.
  • Q2 on-resistance be R ON .
  • Q2 can be controlled by the Vc to operate in the amplification region, and the functional relationship between Vc and R ON satisfies the monotonicity.
  • the function relationship between Vc and R ON is monotonously decreasing, that is, the larger Vc, the smaller the 1 ( ⁇ ).
  • V OUT V FB » R + RoN ; and because there is a functional relationship between R ON and Vc, and the function relationship
  • V OUT can be adjusted by adaptively adjusting Vc.
  • the control circuit can be optimized in accordance with FIG.
  • the drain D of Q2 is connected to the feedback pin FB of the DC/DC converter chip through a resistor R33, and the feedback pin FB is grounded through a resistor R32.
  • the correspondence between the data recorded in Table 1 can be stored on a board (specifically, a memory chip) of the terminal, so as to find and match according to the power level of the power amplifier PA and the working frequency. This state corresponds to Vc, which in turn adjusts V OUT .
  • the power amplifier power supply circuit adds a control circuit between the voltage input end of the power amplifier and the feedback pin of the DC/DC converter chip, and the control circuit includes an N-channel MOS transistor;
  • the voltage may vary according to a change in the power level of the power amplifier and/or a change in the operating frequency, and the N-channel MOS transistor is turned on, and the on-resistance of the N-channel MOS transistor and the voltage input terminal of the power amplifier PA
  • the voltage has a certain functional relationship. Therefore, when the power amplifier is in a certain state, the control voltage can control the voltage of the voltage input terminal of the power amplifier to reach the minimum value of the radio frequency index in the state, thereby improving the efficiency of the power amplifier, and further Reduce the power loss of the terminal.
  • the embodiment of the invention further provides a terminal.
  • the terminal includes a baseband processing unit, a power amplifier power supply circuit, and a power amplifier PA, wherein the power amplifier power supply circuit includes a DC/DC converter chip (DC/DC switching power supply chip), and the DC/DC converter chip includes The input pin IN, the inductive connection pin LX, and the feedback pin FB, the input pin IN is used to connect the power source, and the inductive connection pin LX is connected to the voltage input end of the power amplifier PA through an LC tank circuit, and a control circuit is connected between the voltage input terminal of the power amplifier PA and the feedback pin FB, and the control circuit includes a control voltage Vc;
  • the power amplifier power supply circuit includes a DC/DC converter chip (DC/DC switching power supply chip)
  • the DC/DC converter chip includes The input pin IN, the inductive connection pin LX, and the feedback pin FB, the input pin IN is used to connect the power source, and the inductive connection pin LX is connected to the voltage input end of the power amplifier PA through an
  • the baseband processing unit is configured to adjust a control voltage Vc that adjusts a voltage V OUT of a voltage input terminal of the power amplifier PA through a control circuit.
  • the terminal provided by the embodiment of the present invention adjusts the magnitude of the control voltage by the baseband processing unit, and the control voltage can adjust the voltage of the voltage input end of the power amplifier PA through the control circuit, so that the terminal The voltage at the voltage input of the power amplifier can be varied according to actual needs, thereby improving the efficiency of the power amplifier PA, thereby reducing the power loss of the terminal.
  • the baseband processing unit includes a baseband processing chip and a DAC (Digital-to-Analog Converter), and the baseband processing chip adjusts the control voltage Vc by controlling the DAC;
  • the DAC can also be integrated into the baseband processing chip.
  • the baseband processing unit includes a baseband processing chip and a PMIC (Power Management IC), and the baseband processing chip controls the PMIC low-dropout linear regulator LDO (referred to as Low Dropout Regulator) adjustment. Control voltage Vc.
  • PMIC Power Management IC
  • LDO Low Dropout Regulator
  • control voltage Vc has a corresponding relationship with the power level and the operating frequency of the power amplifier PA. For details, refer to Table 1.
  • the system shown in Fig. 14 can be constructed during production to calibrate the control voltage Vc.
  • part A is the RF (Radio Frequency) test instrument and equipment calibration platform used for calibration.
  • the common communication bus between them is GPIB (General-Purpose Interface Bus) or Ethernet.
  • the equipment calibration platform may be a computer with calibration software installed;
  • Part B is the terminal in the embodiment of the present invention.
  • the RF test instrument and the RF test connector in the terminal are connected by an RF test cable for testing whether the RF amplified by the power amplifier PA satisfies the RF index; the equipment calibration platform passes the asynchronous bus UART (Universal Asynchronous) Receiver/Transmitter, Universal Asynchronous Receive/Transmit Device) or USB or other control terminal or read terminal information.
  • UART Universal Asynchronous
  • UART Universal Asynchronous
  • USB Universal Asynchronous Receive/Transmit Device
  • the equipment calibration platform can use the calibration software to run the calibration Vc shown in Figure 4 to determine the Vc corresponding to each operating frequency point at different power levels of the power amplifier PA to complete the calibration of all Vc values in Table 1.
  • the correspondence between the control voltage Vc recorded in Table 1 and the power level and the operating frequency of the power amplifier PA may be stored on a board of the terminal, and may be stored in a memory chip of the terminal so as to be according to the power amplifier PA.
  • the state adjusts Vc.
  • the terminal provided by the embodiment of the present invention adjusts the magnitude of the control voltage by the baseband processing unit, and the control voltage can adjust the voltage of the voltage input end of the power amplifier PA through the control circuit, so that the terminal In the case that the power amplifier PA is in a certain state, the voltage at the voltage input end of the power amplifier PA can be adjusted so that the whole machine satisfies the minimum value of the radio frequency index, thereby improving the efficiency of the power amplifier PA, thereby reducing the power loss of the terminal. .
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • This embodiment provides a specific implementation solution of the terminal.
  • a terminal includes a baseband processing unit, a power amplifier power supply circuit, and a power amplifier PA, wherein the power amplifier power supply circuit includes a DC/DC converter chip (DC/DC switching power supply chip), and the DC/DC converter chip includes an input pin IN Inductor connection pin LX and feedback pin FB, input pin IN is used to connect the power supply, and the inductor connection pin LX is connected to the voltage input terminal of the power amplifier PA through an LC storage circuit, and the power amplifier PA a control circuit is connected between the voltage input terminal and the feedback pin FB, and the control circuit includes a control voltage Vc;
  • the power amplifier power supply circuit includes a DC/DC converter chip (DC/DC switching power supply chip)
  • the DC/DC converter chip includes an input pin IN Inductor connection pin LX and feedback pin FB
  • input pin IN is used to connect the power supply
  • the inductor connection pin LX is connected to the voltage input terminal of the power amplifier PA through an LC storage circuit
  • the power amplifier PA a control circuit is connected between the voltage
  • the baseband processing unit is configured to adjust a control voltage Vc that adjusts a voltage V OUT of a voltage input terminal of the power amplifier PA through a control circuit.
  • the baseband processing unit includes a baseband processing chip and a DAC (Digital-to-Analog Converter), and the baseband processing chip controls the DAC to adjust the control voltage Vc; in practical applications, the DAC also Can be integrated in the baseband processing chip.
  • DAC Digital-to-Analog Converter
  • the baseband processing unit includes a baseband processing chip and a PMIC (Power Management IC), and the baseband processing chip controls the PMIC low-dropout linear regulator LDO (referred to as Low Dropout Regulator) adjustment. Control voltage Vc.
  • PMIC Power Management IC
  • LDO Low Dropout Regulator
  • the power amplifier circuit in the terminal can refer to FIG. 5.
  • the control circuit is marked with a virtual frame.
  • the control circuit includes a differential amplifying circuit, and the differential amplifying circuit includes an operational amplifier U2;
  • the non-inverting input terminal of the operational amplifier U2 is connected to the voltage input terminal of the power amplifier PA through the first resistor R11, and the non-inverting input terminal is grounded through the second resistor R12;
  • control voltage Vc is applied to the inverting input terminal of the operational amplifier U2 through the third resistor R13, and the inverting input terminal is connected to the output terminal of the operational amplifier U2 through the fourth resistor R14 to form a reverse Feed circuit
  • the output of the operational amplifier U2 is connected to the feedback pin FB of the DC/DC converter chip U1.
  • V- represents the voltage of the inverting input terminal of the operational amplifier U2
  • V+ represents the voltage of the non-inverting input terminal of the operational amplifier U2
  • Vo represents the voltage of the output terminal of the operational amplifier U2.
  • V + V_
  • V FB is a fixed value, so it is easy
  • V OUT and Vc are linear.
  • the differential amplifying circuit in the power amplifier circuit shown in FIG. 5 is optimized: the output terminal of the operational amplifier U2 is connected to the feedback pin FB of the DC/DC converter chip U1 through a resistor R15. And the feedback pin FB is grounded through a resistor R16.
  • V FB is still a solid
  • V OUT and Vc are linear.
  • the resistances of the first resistor R11 and the third resistor R13 are generally equal, and the resistances of the second resistor R12 and the fourth resistor R14 are equal;
  • v FB is still a fixed value, and it can be known that ⁇ ⁇ ⁇ ⁇ and Vc are linear, so the power amplifier PA voltage can be adjusted by adjusting Vc.
  • the correspondence between the control voltage Vc recorded in Table 1 and the power level and the operating frequency of the power amplifier ⁇ may be stored on a board of the terminal, and may be specifically stored in the memory chip of the terminal so as to be available according to the power.
  • the state of the amplifier PA adjusts Vc. Since there is a functional relationship between V OUT and Vc, V OUT can be varied according to changes in the power level of the PA and/or changes in the operating frequency. At this time, when the power amplifier PA is in a certain state, according to the value of Vc corresponding to the state recorded in Table 1, the V OUT can be adjusted to the state under the premise that the whole machine satisfies the radio frequency index. The minimum value can improve the efficiency of the PA.
  • the terminal provided by the embodiment of the invention passes through the voltage input end of the power amplifier and the DC/DC A control circuit is added between the feedback pins of the converter chip, and the control circuit is a differential amplifying circuit; since the control voltage can be changed according to a change in the power level of the power amplifier and/or a change in the operating frequency, and the power amplifier The voltage at the voltage input terminal is linear with the control voltage. Therefore, when the power amplifier is in a certain state, the control voltage can control the voltage at the voltage input terminal of the power amplifier to reach the minimum value of the radio frequency index in the state, thereby improving The efficiency of the power amplifier, which in turn reduces the power loss of the terminal.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • This embodiment provides a specific implementation of another terminal.
  • the power amplifier circuit in the solution provided by this embodiment can refer to FIG. 7.
  • the solution in this embodiment is different from the solution in the fourth embodiment only in the design of the control circuit, and the other parts are similar to the fourth embodiment, and therefore will not be described again. .
  • the control circuit in this embodiment includes a P-channel field effect transistor Q1 (P-MOS transistor), and Q1 in FIG. 7 is a P-channel enhancement type MOS transistor, for a P-channel depletion MOS transistor.
  • the circuit connection can also be referred to Figure 7.
  • the source S of Q1 is connected to the voltage input end of the power amplifier, the drain D is connected to the feedback pin FB of the DC/DC converter chip, and the drain D is grounded through a resistor R22; the control voltage Vc acts At gate G of Q1.
  • Q1's on-resistance be R ON .
  • Q1 can be controlled to operate in the amplification region by Vc, and the functional relationship between Vc and R ON satisfies monotonicity.
  • the functional relationship between Vc and R ON is monotonically increasing, that is, the smaller the Vc is, the smaller the 1 ⁇ is.
  • the control circuit can be optimized according to FIG.
  • the source S of Q1 is also connected to the voltage input terminal of the power amplifier PA through a resistor R23, and the voltage input terminal is connected to the feedback pin FB of the DC/DC converter chip through a resistor R21.
  • R ON and Vc since there is a functional relationship between R ON and Vc, and The function relationship is monotonic, so the purpose of adjusting V OUT can be achieved by adjusting Vc.
  • the correspondence between the data recorded in Table 1 may be stored on a board (specifically, a memory chip) of the terminal, so as to find a corresponding to the state according to the power level of the power amplifier PA and the operating frequency point. Vc, and then adjust V OUT .
  • the terminal provided by the embodiment of the present invention adds a control circuit between the voltage input end of the power amplifier and the feedback pin of the DC/DC converter chip, and the control circuit includes a P-channel MOS transistor; According to the change of the power level of the power amplifier and/or the change of the operating frequency, and the P-channel MOS transistor is turned on, and the on-resistance of the P-channel MOS transistor and the voltage input terminal of the power amplifier PA
  • the voltage has a certain functional relationship, so that the control voltage can control the voltage of the voltage input terminal of the power amplifier to reach a certain state, so that the whole machine satisfies the minimum value of the radio frequency index, thereby improving the efficiency of the power amplifier and thereby reducing the power loss of the terminal.
  • This embodiment provides another specific implementation scheme of the terminal.
  • the power amplifier circuit in the solution provided in this embodiment can refer to FIG. 9.
  • the scheme in the fourth embodiment is different only in the design of the control circuit, and the other portions are similar to the fourth embodiment, and therefore will not be described again.
  • the control circuit in this embodiment includes an N-channel type field effect transistor Q2 (N-MOS transistor); Q2 in FIG. 9 takes an N-channel enhancement type MOS transistor as an example, and is an N-channel depletion mode MOS transistor. See also Figure 9 for circuit connections.
  • the source S of Q2 is grounded, the drain D is connected to the feedback pin FB of the DC/DC converter chip, and the control voltage Vc acts on the gate G of Q2; in addition, the voltage input terminal of the power amplifier PA passes through a resistor
  • the R31 is connected to the feedback pin FB of the DC/DC converter chip.
  • Q2's on-resistance be R ON .
  • Q2 can be controlled by the Vc to operate in the amplification region, and the functional relationship between Vc and R ON satisfies the monotonicity.
  • the functional relationship between Vc and R ON is monotonically decreasing, that is, the larger Vc is, the smaller R ON is.
  • V OUT can be adjusted by adaptively adjusting Vc.
  • the control circuit can be optimized in accordance with FIG.
  • the drain D of Q2 is connected to the feedback pin FB of the DC/DC converter chip through a resistor R33, and the feedback pin FB is grounded through a resistor R32.
  • the correspondence between the data recorded in Table 1 may be stored on a board (specifically, a memory chip) of the terminal, so as to find a corresponding to the state according to the power level of the power amplifier PA and the operating frequency point. Vc, and then adjust V OUT .
  • the terminal provided by the embodiment of the present invention adds a control circuit between the voltage input end of the power amplifier and the feedback pin of the DC/DC converter chip, and the control circuit includes an N-channel MOS transistor; According to the change of the power level of the power amplifier and/or the change of the operating frequency, and the N-channel MOS transistor is turned on, and the on-resistance of the N-channel MOS transistor and the voltage input terminal of the power amplifier PA
  • the voltage has a certain functional relationship, so that the control voltage can control the voltage of the voltage input terminal of the power amplifier to reach a certain state, so that the whole machine satisfies the minimum value of the radio frequency index, thereby improving the efficiency of the power amplifier and thereby reducing the power loss of the terminal.
  • the present invention can be implemented by means of software plus necessary general hardware, and of course, by hardware, but in many cases, the former is a better implementation. .
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer. , hard drive or CD And, a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present invention.

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Description

一种功放供电电路及终端 本申请要求于 2011 年 1 月 21 日提交中国专利局, 申请号为 201110024175.2、 发明名称为 "一种功放供电电路及终端" 的中国专利申请, 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信领域, 尤其涉及一种功放供电电路及终端。
背景技术
随着移动通信技术的飞速发展, 越来越多的用户使用无线数据业务进行 通信。 目前, 支持无线数据业务的终端主要包括: 无线数据卡、 手机等。
对于终端发射信号的上行过程包括射频信号经过 PA ( Power Amplifier, 功率放大器, 简称功放)进行放大, 放大后的射频信号由天线发射到空间。 PA是上述终端上行过程中一个重要的耗能元器件, 若 PA的效率较低, 就会 导致整机的功耗较大。 下面分别介绍现有技术中的两种终端中的供电电路。
如图 1所示, 对于手机等使用电池供电的终端中 PA的供电电路, VBAT为 电池的输出电压, 电压一般稳定在 3.7V〜4.2V, 该电压作为 PA的供电电压。
如图 2所示, 对于无线数据卡中常用的 PA供电电路, U1为一直流 /直流 变换器芯片(也称为 DC/DC开关电源芯片); ^为无线数据卡工作电源, 该电 源由便携机通过常用外设接口如 USB ( Universal Serial Bus, 通用串行总线 ) 接口、 PCMCIA ( Personal Computer Memory Card International Association, PC 机内存卡国际联合会)接口或 ExpressCard接口等提供; V0UT = (1 + ) · ^为
PA的供电电压, VFB 为 DC/DC开关电源芯片的反馈参考值,该值为一固定值, 显然, 当 和 ^固定后, PA的供电电压^ OT也为固定值。
现有技术中 PA的供电电压是恒定的。 但在实际工作中, 随着终端网络状 态的变化, 所需 PA的输出功率也会变化; 由 PA的特性可知, 在使得整机满 足射频指标的前提下, 若所需 PA的输出功率减小, 则所需 PA的供电电压会 随之减小, 此时 PA的实际供电电压越接近所需 PA的供电电压, 则 PA的效 率就会越高; 另外, PA本身具有一定的离散性, 在使得整机满足射频指标前 提下, PA所需供电电压也不同, 但在现有技术中 PA的供电电压为恒定值, 不能依照所需 PA的供电电压的改变而改变, 从而造成 PA的效率较低, 进而 导致整机的功耗较大。
发明内容
本发明的实施例提供一种功放供电电路及终端, 用以提高终端中功率放 大器的效率, 进而减少终端的功率消耗。
为达到上述目的, 本发明的实施例采用如下技术方案:
一种功放供电电路, 包括直流 /直流变换器芯片, 所述直流 /直流变换器芯 片包括输入管脚、 电感连接管脚以及反馈管脚, 所述输入管脚用于连接电源, 且所述电感连接管脚通过一 LC储能电路与功率放大器的电压输入端相连接, 另外, 所述功率放大器的电压输入端与所述反馈管脚之间连接有控制电路; 所述控制电路包括一控制电压, 该控制电压通过所述控制电路调整所述 功率放大器的电压输入端的电压; 且该控制电压为可变的。
一种终端, 包括基带处理单元、 功放供电电路以及功率放大器, 所述功 放供电电路包括直流 /直流变换器芯片, 该直流 /直流变换器芯片包括输入管 脚、 电感连接管脚以及反馈管脚, 所述输入管脚用于连接电源, 且所述电感 连接管脚通过一 LC储能电路与所述功率放大器的电压输入端相连接, 另外, 所述功率放大器的电压输入端与所述反馈管脚之间连接有控制电路, 且所述 控制电路包括一控制电压;
所述基带处理单元用于调整所述控制电压, 该控制电压通过所述控制电 路调整所述功率放大器的电压输入端的电压。
本发明实施例提供的功放供电电路及终端, 通过在功率放大器的电压输 入端与直流 /直流变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路 引入了一个可变的控制电压, 该控制电压可以通过控制电路调整功率放大器 的电压输入端的电压, 使得功率放大器的电压输入端的电压可以根据实际需 要而变化, 从而可以提高功率放大器的效率, 进而减少终端的功率损耗。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案, 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍, 显而易见地, 下面 描述中的附图仅仅是本发明的一些实施例, 对于本领域普通技术人员来讲, 在不付出创造性劳动性的前提下, 还可以根据这些附图获得其他的附图。
图 1为现有技术中的一种功放供电电路的电路图;
图 2为现有技术中的另一功放供电电路的电路图;
图 3为本发明实施例提供的一种功放供电电路的电路示意图;
图 4为校准控制电压的方法流程图;
图 5为本发明实施例一提供的一种功放供电电路的电路图;
图 6为本发明实施例一提供的另一功放供电电路的电路图;
图 Ί为本发明实施例二提供的一种功放供电电路的电路图;
图 8为本发明实施例二提供的另一功放供电电路的电路图;
图 9为本发明实施例三提供的一种功放供电电路的电路图;
图 10为本发明实施例三提供的另一功放供电电路的电路图;
图 11为本发明实施例提供的一种终端结构示意图;
图 12为图 11中的基带处理单元的一种结构示意图;
图 13为图 11中的基带处理单元的另一结构示意图;
图 14为实现图 4所示方法的校准系统示意图。
具体实施方式
下面将结合本发明实施例中的附图, 对本发明实施例中的技术方案进行 清楚、 完整地描述, 显然, 所描述的实施例仅仅是本发明一部分实施例, 而 不是全部的实施例。 基于本发明中的实施例, 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例, 都属于本发明保护的范围。
为提高功率放大器的效率, 本发明实施例提供了一种功放供电电路, 如 图 3 所示, 包括直流 /直流变换器芯片 (即 DC/DC开关电源芯片), 该直流 / 直流变换器芯片包括输入管脚 IN、 电感连接管脚 LX以及反馈管脚 FB, 输入 管脚 IN用于连接电源 VIN,电感连接管脚 LX通过一 LC储能电路与功率放大 器 PA的电压输入端相连接, 该功率放大器 PA的电压输入端与反馈管脚 FB 之间连接有控制电路;
该控制电路包括一控制电压 Vc, 且控制电压 Vc通过该控制电路调整该 功率放大器 PA的电压输入端的电压 VOUT; 且该控制电压 Vc为可变的。
本发明实施例提供的功放供电电路, 通过在功率放大器的电压输入端与 直流 /直流变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路引入了 一个可变的控制电压, 该控制电压可以通过控制电路调整功率放大器的电压 输入端的电压, 使得功率放大器的电压输入端的电压可以根据实际需要而变 化; 也就说, 当功率放大器电压输入端的电压需要一较小的值就可正常工作 时, 控制电压可通过控制电路调整功率放大器电压输入端的电压值至该较小 的值, 从而可以提高功率放大器的效率。
上述功放供电电路可以应用于一终端。
进一步地, 上述功放供电电路中控制电压 Vc与功率放大器 PA的功率等 级、 工作频点存在对应关系, 具体可参考表 1。
表 1
控制电压 工作频点 Fl F2 Fn
PI Vn Vl2 • . . Vln
P2 V21 V22 • . . V2n - · · - · · - · · - · · - · ·
Pm Vml Vm2 - · · Vmn
其中,功率放大器 PA的工作频点为针对输入到该功率放大器的射频频率 所分的 n ( n≥l )个频点, 且每个工作频点下可设有 m个功率等级, 该功率等 级可以依照 PA的输出功率的大小来划分。 功率放大器 PA的某一工作频点下 的任一功率等级称为该功率放大器 PA的一个状态。 当包含有上述功放供电电 路的终端正常工作时, 该功率放大器的功率等级和 /或工作频点会实时变化, 表 1中记录了该功率放大器 PA在每一状态下所对应的控制电压 Vc的值, 也 就是说,控制电压 Vc可以根据功率放大器 PA的功率等级的改变和 /或工作频 点的改变而变化。 另外, 又因为控制电压 Vc可以通过控制电路调整功率放大 器 PA的电压输入端的电压 VOUT,故使得该功率放大器 PA的电压输入端的电 压值 VOUT可以随着功率放大器 PA的功率等级的改变和 /或工作频点的改变而 变化。 在本实施例中, 在使得该终端 (整机) 满足射频指标的前提下, 功率 放大器 PA电压输入端的电压值 VOUT越小越好, 从而可以提供功率放大器的 效率。
需要说明的是, 在 WCDMA ( Wideband Code Division Multiple Access, 宽带码分多址)标准中, 该射频指标包括: ACLR ( Adjacent Channel Leakage Ratio, 相邻频道泄漏比)、 功率放大器 PA的输出功率以及功率放大器 PA的 灵敏度等;在 CDMA2000( Code Division Multiple Access 2000,码分多址 2000 ) 标准中, 该射频指标包括: ACPR ( Adjacent Channel Power Ratio , 邻道功率 比)、 功率放大器 PA的输出功率以及功率放大器 PA的灵敏度等。
下面, 针对如何确定表 1 中 PA在每一状态下的控制电压 Vc, 在生产中 可以采用图 4所示的方法对 Vc的值进行校准, 并将经过校准得到的 Vc记录 在表 1中。
401、 选定 PA的功率等级, 例如表 1中的 P1 ;
402、 选定该功率等级 ( P1 ) 下的一个工作频点, 例如表 1中的 F1 ; 403、 选取在该状态 (如表 1 中 Pl、 F1 的状态) 下使得 PA能够工作的 VOUT最小值所对应的 Vc;
404、 判断整机是否满足射频指标;
具体为, 终端中的功放供电电路利用步骤 403中的 Vc调整 VOUT值, 在 利用该 VOUT给 PA供电的条件下, 测试此时整机的射频指标, 并判断整机是 否满足射频指标。
若整机满足射频指标进行步骤 405; 否则提高步骤 403中 Vc的值, 重复 步骤 404。
405、 保存满足要求的 Vc值, 即表 1中的 Vu;
此时, 该功率等级(P1 ) 的一个工作频点 (例如: F1 )扫描完毕, 可继 续进行步骤 406。
406、 判断该功率等级(P1 ) 中的所有工作频点是否扫描完毕;
若扫描完毕, 则进行步骤 407; 否则, 返回至步骤 403 , 对下一频点 (例 如: F2 )对应的 Vc进行校准。
407、 判断该功率等级(P1 )是否为最后一个功率等级, 即判断是否所有 功率等级扫描完毕;
若扫描完毕, 则完成 PA不同功率等级的各个工作频点所对应的 Vc的校 准, 并将校准后得到的 Vc保存在表 1中;
否则, 则返回至步骤 402, 选定下一功率等级(P2 )的一个工作频点对应 的 Vc进行校准, 直至完成表 1中所有 Vc值的校准。
上述针对 Vc的校准过程可以由一台装有校准软件的计算机来完成。
为了减小校准时间, 可以适当减少校准次数; 也就是说, 只对功率放大 器 PA处于部分状态下所对应的 Vc进行校准, 对与其他状态下所对应的 Vc 值可以经过一定的插值算法获得其他状态下最优的 Vc值。
需要说明的是, 上述校准 Vc的方法只是作为一种具体实施方案, 实现对 功率放大器 PA处于不同状态时所对应的 Vc进行校准的目的, 但本实施例的 校准方法并不局限于此, 只要可以达到相同的目的即可。
实施例一:
如图 5所示, 本实施例提供一种功放供电电路的具体实现方案。
一种功放供电电路, 包括直流 /直流变换器芯片 U1 , 该直流 /直流变换器 芯片 U1包括输入管脚 IN、 电感连接管脚 LX以及反馈管脚 FB, 输入管脚 IN 用于连接电源 VIN, 电感连接管脚 LX通过一 LC储能电路与功率放大器 PA 的电压输入端相连接, 该功率放大器 PA的电压输入端与反馈管脚 FB之间连 接有控制电路;
其中, 图 5中的控制电路用虚框标出。 该控制电路包括一控制电压 Vc, 且控制电压 Vc通过该控制电路调整该功率放大器 PA 的电压输入端的电压 VOUT; 而且控制电压 Vc为可变的。 具体地, 控制电压 Vc可以按照表 1中所 记录的控制电压 Vc与功率放大器 PA的功率等级、 工作频点的对应关系进行 调整。
另外, LC储能电路包括一电感 L以及一电容 C2; 电感 L连接直流 /直流 变换器芯片 U1的电感连接管脚 LX与该功率放大器 PA的电压输入端, 且该 功率放大器 PA的电压输入端通过电容 C2接地。
在本具体实施例中, 该控制电路包括一差分放大电路, 该差分放大电路 包括一运算放大器 U2;
运算放大器 U2的同相输入端通过第一电阻 R11与功率放大器 PA的电压 输入端相连接, 且该同相输入端通过第二电阻 R12接地;
控制电压 Vc通过第三电阻 R13作用于运算放大器 U2的反相输入端, 且 该反相输入端通过第四电阻 R14与运算放大器 U2的输出端相连接,形成一反 馈回路;
运算放大器 U2的输出端与直流 /直流变换器芯片 U1的反馈管脚 FB相连 接。
根据上述功放供电电路的设计, 可以得到以下关系表达式; 其中, V-表 示运算放大器 U2的反相输入端的电压, V+表示运算放大器 U2的同相输入端 的电压, Vo表示运算放大器 U2的输出端的电压;
V - RU V -
+ 1 + 2
Vc-V V - Vo
R\3
V+ = V_;
由上述各式, 最终得到 VOUT和 Vc之间的关系表达式:
v _ R (R\\ + RU) v^ | RU(R\\ + RU) v . ①
①式中, VFB为一固定值, 故易得 VOUT和 Vc呈线性关系。
进一步地, 参考图 6, 对图 5所示的功放供电电路中的差分放大电路进行 优化: 运算放大器 U2的输出端通过一电阻 R15与直流 /直流变换器芯片 U1 的反馈管脚 FB相连接, 且该反馈管脚 FB通过一电阻 R16接地。
此时, 可以得到以下各关系表达式:
+ RW + R12 ουτ.
Vc-V V - Vo
RU
V =V_;
VFB=. 6
5 + i?16 由上述各式, 得到 VOUT和 Vc之间的关系表达式:
v _ i?14(i?ll + 2)^ | R\3(R\ 1 + R\2)(R\5 + R\6) γ .
② ουτ ~ i?12( 3 + 4) C ~ 2« 6( 3 + i?14) ~ FB ' ②式中, VFB仍为一固定值, 故易得 VOUT和 Vc呈线性关系。 进一步地, 在差分放大电路的设计中, 通常取第一电阻 R11 与第三电阻 R13的阻值相等, 且第二电阻 R12与第四电阻 R14的阻值相等;
故此时, 针对图 6中的功放供电电路, 得到最终的 VOUT和 Vc之间的关 系表达式:
0UT RU * R\6 FB
③式中, VFB仍为一固定值, 可以得知 VOUT和 Vc呈线性关系, 故可以通 过调整 Vc来调整功率放大器 PA电压输入端的电压 VOUT的大小。 另外, 表 1 中所记录的控制电压 Vc与功率放大器 PA的功率等级、 工作频点的对应关系 的存储芯片中,以便可以根据功率放大器 PA的状态对 Vc进行调整,由于 VOUT 和 Vc之间存在函数关系, 故使得 VOUT可以根据 PA的功率等级的改变和 /或 工作频点的改变而变化。 此时, 在功率放大器 PA处于某一状态下, 按照表 1 中所记录的与该状态对应的 Vc取值,就可以在使得整机满足射频指标的前提 下, 将 VOUT调整到该状态下的最小值, 故能够提高 PA的效率。
本发明实施例提供的功放供电电路, 通过在功率放大器的电压输入端与 直流 /直流变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路为一差 分放大电路; 由于控制电压可以根据功率放大器的功率等级的改变和 /或工作 频点的改变而变化, 且功率放大器电压输入端的电压大小与控制电压呈线性 关系, 故在功率放大器处于某一状态时, 控制电压可以控制功率放大器电压 输入端的电压达到在该状态下使得整机满足射频指标的最小值, 从而可以提 高功率放大器的效率, 进而减少终端的功率损耗。
实施例二:
本实施例提供另一种功放供电电路的具体实现方案。 如图 Ί所示, 本具 体实施例提供的方案相较于实施例一中的方案只是在控制电路的设计上不 同, 其他部分与实施例一类似, 故不再贅述。
本实施例中的控制电路在图 7中用虚框标出, 该控制电路包括一 P沟道 型场效应管 Ql ( P-MOS管), 图 7中的 Q1以 P沟道增强型 MOS管为例, 对 于 P沟道耗尽型 MOS管的电路连接同样可参考图 7。 Q1的源极 S与该功率 放大器的电压输入端相连接,漏极 D与该直流 /直流变换器芯片的反馈管脚 FB 相连接,且该漏极 D通过一电阻 R22接地;控制电压 Vc作用于 Q1的栅极 G„ 设 Ql的导通电阻为 RON。 此时, 可以通过 Vc控制 Q1工作于放大区, 则 Vc和 RON的函数关系满足单调性。 具体针对处于放大区的 P沟道增强型 MOS管来讲, Vc和 RON的函数关系为单调递增, 即 Vc越小, RON也越小。
易得, 功率放大器电压输入端的电压 VOUT和导通电阻 RON函数关系为: vom = vP ; 又由于!^^和 vc之间存在函数关系, 且该函数关系具
Figure imgf000012_0001
有单调性, 故可通过自适应调整 Vc来达到调整 VOUT的目的。
进一步地, 为了降低对 Vc精度的要求, 从而便于对 Vc的调整, 故可以 按照图 8优化控制电路。 Q1的源极 S还通过一电阻 R23与功率放大器 PA的 电压输入端相连接, 且该电压输入端通过一电阻 R21与直流 /直流变换器芯片 的反馈管脚 FB相连接。
此时, 易得功率放大器电压输入端的电压 VOUT和导通电阻 RON函数关系 为: v0UT ; 同样, 由于 1 和 Vc之间存在函数关系,
Figure imgf000012_0002
且该函数关系具有单调性, 故可通过调整 Vc来达到调整 VOUT的目的。
另外, 类似实施例一可在终端的单板(具体可以是存储芯片 )上存储表 1 中所记录的数据之间的对应关系, 以便于根据功率放大器 PA的功率等级以及 工作频点查找到与该状态对应的 Vc, 进而调整 VOUT
本发明实施例提供的功放供电电路, 通过在功率放大器的电压输入端与 直流 /直流变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路包括一
P沟道 MOS管;由于控制电压可以根据功率放大器的功率等级的改变和 /或工 作频点的改变而变化 , 并使得该 P沟道 MOS管导通, 且该 P沟道 MOS管的 导通电阻与功率放大器 PA电压输入端的电压具有一定的函数关系,故而在功 率放大器处于某一状态时, 使得控制电压可以控制功率放大器电压输入端的 电压达到该状态下整机满足射频指标的最小值, 从而可以提高功率放大器的 效率, 进而减少终端的功率损耗。
实施例三:
本实施例提供又一种功放供电电路的具体实现方案。 如图 9所示, 本具 体实施例提供的方案相较于实施例一中的方案只是在控制电路的设计上不 同, 其他部分与实施例一类似, 故不再贅述。
本实施例中的控制电路在图 9中用虚框标出, 该控制电路包括一 N沟道 型场效应管 Q2 ( N-MOS管); 图 9中的 Q2以 N沟道增强型 MOS管为例, 对于 N沟道耗尽型 MOS管的电路连接同样可参考图 9。 Q2的源极 S接地, 漏极 D与该直流 /直流变换器芯片的反馈管脚 FB相连接,且控制电压 Vc作用 于 Q2的栅极 G; 另外, 功率放大器 PA的电压输入端通过一电阻 R31与直流 /直流变换器芯片的反馈管脚 FB相连接。
设 Q2的导通电阻为 RON。 此时, 可以通过 Vc控制 Q2工作于放大区, 则 Vc和 RON的函数关系满足单调性。 具体针对处于放大区的 N沟道增强型 MOS管来讲, Vc和 RON的函数关系为单调递减, 即 Vc越大, 1 (^也越小。
易得, 功率放大器 PA电压输入端的电压 VOUT和导通电阻 RON函数关系 为: VOUT = VFB » R + RoN; 又由于 RON和 Vc之间存在函数关系, 且该函数关系
R。N
具有单调性, 故可通过自适应调整 Vc来达到调整 VOUT的目的。
进一步地, 为了降低对 Vc精度的要求, 从而便于对 Vc的调整, 故可以 按照图 10优化控制电路。 Q2的漏极 D通过一电阻 R33与该直流 /直流变换器 芯片的反馈管脚 FB相连接, 且该反馈管脚 FB通过一电阻 R32接地。
此时, 易得功率放大器电压输入端的电压 VOUT和导通电阻 RON函数关系 为: v< OUT FB 1 + ; 同样, 由于 RON和 Vc之间存在函数关系,
Figure imgf000014_0001
且该函数关系具有单调性,故可通过自适应调整 Vc来达到调整 VOUT的目的。
另外, 类似实施例一可在终端的单板(具体可以是存储芯片 )上存储表 1 中所记录的数据之间的对应关系, 以便于根据功率放大器 PA的功率等级以及 工作频点查找到与该状态对应的 Vc, 进而调整 VOUT
本发明实施例提供的功放供电电路, 通过在功率放大器的电压输入端与 直流 /直流变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路包括一 N沟道 MOS管; 由于控制电压可以根据功率放大器的功率等级的改变和 /或 工作频点的改变而变化, 并使得该 N沟道 MOS管导通,且该 N沟道 MOS管 的导通电阻与功率放大器 PA电压输入端的电压具有一定的函数关系,故而在 功率放大器处于某一状态时, 使得控制电压可以控制功率放大器电压输入端 的电压达到该状态下整机满足射频指标的最小值, 从而可以提高功率放大器 的效率, 进而减少终端的功率损耗。 本发明实施例还提供了一种终端。 如图 11所示, 该终端包括基带处理单 元、 功放供电电路以及功率放大器 PA, 其中, 功放供电电路包括直流 /直流变 换器芯片(DC/DC开关电源芯片),该直流 /直流变换器芯片包括输入管脚 IN、 电感连接管脚 LX以及反馈管脚 FB,输入管脚 IN用于连接电源,且电感连接 管脚 LX通过一 LC储能电路与功率放大器 PA的电压输入端相连接, 并且, 功率放大器 PA的电压输入端与反馈管脚 FB之间连接有控制电路, 且该控制 电路包括一控制电压 Vc;
该基带处理单元用于调整控制电压 Vc, 该控制电压 Vc通过控制电路调 整功率放大器 PA的电压输入端的电压 VOUT
本发明实施例提供的终端, 通过基带处理单元调整控制电压的大小, 且 该控制电压可以通过控制电路调整功率放大器 PA的电压输入端的电压,使得 功率放大器的电压输入端的电压可以根据实际需要而变化, 从而可以提高功 率放大器 PA的效率, 进而减少终端的功率损耗。
进一步地, 如图 12 所示, 该基带处理单元包括基带处理芯片和 DAC ( Digital-to-Analog Converter, 数模转换器), 且基带处理芯片通过控制 DAC 调整控制电压 Vc; 在实际应用中, DAC也可以集成于基带处理芯片中。
或者, 如图 13所示, 该基带处理单元包括基带处理芯片和 PMIC ( Power Management IC, 电源管理芯片), 且基带处理芯片控制 PMIC的低压差线性 稳压器 LDO (全称为 Low Dropout Regulator )调整控制电压 Vc。
进一步地, 控制电压 Vc与功率放大器 PA的功率等级、 工作频点存在对 应关系, 具体可参考表 1。
另外,在生产过程中可以构建图 14所示的系统对控制电压 Vc进行校准。 其中, A部分为校准时所用的 RF ( Radio Frequency, 射频) 测试仪器和装备 校准平台, 两者之间为通用的通信总线,例如 GPIB ( General-Purpose Interface Bus, 通用接口总线)或以太网等, 该装备校准平台可以为一台安装有校准软 件的计算机; B部分为本发明实施例中的终端。 并且, RF测试仪器和终端中 的 RF测试连接器通过 RF测试电缆相连接, 该 RF测试仪器用于测试经过功 率放大器 PA放大后的射频是否满足射频指标; 装备校准平台通过异步总线 UART ( Universal Asynchronous Receiver/Transmitter ,通用异步接收 /发送装置 ) 或 USB等控制终端或读取终端信息。
装备校准平台可以利用校准软件运行图 4所示的校准 Vc的方法,确定在 功率放大器 PA的不同功率等级下的各个工作频点所对应的 Vc, 以完成表 1 中所有 Vc值的校准。 表 1中所记录的控制电压 Vc与功率放大器 PA的功率 等级、 工作频点的对应关系可以存储在该终端的单板上, 具体可以存储在终 端的存储芯片中, 以便可以根据功率放大器 PA的状态对 Vc进行调整。
本发明实施例提供的终端, 通过基带处理单元调整控制电压的大小, 且 该控制电压可以通过控制电路调整功率放大器 PA的电压输入端的电压,使得 在该功率放大器 PA处于某一状态的情况下, 该功率放大器 PA的电压输入端 的电压可以调整到使得整机满足射频指标的最小值, 从而可以提高功率放大 器 PA的效率, 进而减少终端的功率损耗。
实施例四:
本实施例提供一种终端的具体实现方案。
一种终端, 包括基带处理单元、 功放供电电路以及功率放大器 PA, 其中, 功放供电电路包括直流 /直流变换器芯片 (DC/DC开关电源芯片), 该直流 /直 流变换器芯片包括输入管脚 IN、 电感连接管脚 LX以及反馈管脚 FB, 输入管 脚 IN用于连接电源, 且电感连接管脚 LX通过一 LC储能电路与功率放大器 PA的电压输入端相连接, 并且, 功率放大器 PA的电压输入端与反馈管脚 FB 之间连接有控制电路, 且该控制电路包括一控制电压 Vc;
该基带处理单元用于调整控制电压 Vc, 该控制电压 Vc通过控制电路调 整功率放大器 PA的电压输入端的电压 VOUT
其中, 如图 12 所示, 该基带处理单元包括基带处理芯片和 DAC ( Digital-to-Analog Converter, 数模转换器), 且基带处理芯片控制 DAC调整 控制电压 Vc; 在实际应用中, DAC也可以集成于基带处理芯片中。
或者, 如图 13所示, 该基带处理单元包括基带处理芯片和 PMIC ( Power Management IC, 电源管理芯片), 且基带处理芯片控制 PMIC的低压差线性 稳压器 LDO (全称为 Low Dropout Regulator )调整控制电压 Vc。
在本具体实施例中, 该终端中的功放供电电路可参考图 5。 其中, 控制电 路用虚框标出。 该控制电路包括一差分放大电路, 该差分放大电路包括一运 算放大器 U2;
运算放大器 U2的同相输入端通过第一电阻 R11与功率放大器 PA的电压 输入端相连接, 且该同相输入端通过第二电阻 R12接地;
控制电压 Vc通过第三电阻 R13作用于运算放大器 U2的反相输入端, 且 该反相输入端通过第四电阻 R14与运算放大器 U2的输出端相连接,形成一反 馈回路;
运算放大器 U2的输出端与直流 /直流变换器芯片 U1的反馈管脚 FB相连 接。
根据上述功放供电电路的设计, 可以得到以下关系表达式; 其中, V-表 示运算放大器 U2的反相输入端的电压, V+表示运算放大器 U2的同相输入端 的电压, Vo表示运算放大器 U2的输出端的电压;
R V ·
+ 1 + 2 ουτ.
Vc-V V - Vo
R\3
V+ = V_;
由上述各式, 最终得到 VOUT和 Vc之间的关系表达式:
vOUT- 4(Rn+Rn)vc + 3 Rn+Rn)vPB; 此式中, VFB为一固定值, 故易
0UT R12(R13 + R ) R12(R13 + R ) FB
得 VOUT和 Vc呈线性关系。
进一步地, 参考图 6, 对图 5所示的功放供电电路中的差分放大电路进行 优化: 运算放大器 U2的输出端通过一电阻 R15与直流 /直流变换器芯片 U1 的反馈管脚 FB相连接, 且该反馈管脚 FB通过一电阻 R16接地。
此时, 可以得到以下各关系表达式: V - RU v , ·
Rll + Rll
Vc-V V -Vo
R\l> R\4 V =V: vFS m6
R15 + R16 由上述各式, 得到 VOUT和 Vc之间的关系表达式:
v0UT = 11 + RU) vc +尋11 + )( + 6) VFB; 此式中, VFB仍为一固
0UT i?12( 3 + 4) 2· 6( 3 + Μ4) FB
定值, 故易得 VOUT和 Vc呈线性关系。
进一步地, 在差分放大电路的设计中, 通常取第一电阻 R11 与第三电阻 R13的阻值相等, 且第二电阻 R12与第四电阻 R14的阻值相等;
故此时, 针对图 6中的功放供电电路, 得到最终的 VOUT和 Vc之间的关 系表达式:
VOUT-VC+ R ^5+ D^6)VFB; 此式中, vFB仍为一固定值, 可以得知 νουτ 和 Vc呈线性关系, 故可以通过调整 Vc来调整功率放大器 PA电压输入端的 电压 νουτ的大小。
另外, 表 1中所记录的控制电压 Vc与功率放大器 ΡΑ的功率等级、 工作 频点的对应关系可以存储在该终端的单板上, 具体可以存储在该终端的存储 芯片中, 以便可以根据功率放大器 PA的状态对 Vc进行调整, 由于 VOUT和 Vc之间存在函数关系,故使得 VOUT可以根据 PA的功率等级的改变和 /或工作 频点的改变而变化。 此时, 在功率放大器 PA处于某一状态下, 按照表 1中所 记录的与该状态对应的 Vc取值, 就可以在使得整机满足射频指标的前提下, 将 VOUT调整到该状态下的最小值, 故能够提高 PA的效率。
本发明实施例提供的终端, 通过在功率放大器的电压输入端与直流 /直流 变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路为一差分放大电 路; 由于控制电压可以根据功率放大器的功率等级的改变和 /或工作频点的改 变而变化, 且功率放大器电压输入端的电压大小与控制电压呈线性关系, 故 在功率放大器处于某一状态时, 控制电压可以控制功率放大器电压输入端的 电压达到在该状态下使得整机满足射频指标的最小值, 从而可以提高功率放 大器的效率, 进而减少终端的功率损耗。
实施例五:
本实施例提供另一种终端的具体实现方案。 本具体实施例提供的方案中 的功放供电电路可参考图 7,其中本方案相较于实施例四中的方案只是在控制 电路的设计上不同, 其他部分与实施例四类似, 故不再贅述。
本实施例中的控制电路包括一 P沟道型场效应管 Ql ( P-MOS管), 图 7 中的 Q1 以 P沟道增强型 MOS管为例, 对于 P沟道耗尽型 MOS管的电路连 接同样可参考图 7。 Q1的源极 S与该功率放大器的电压输入端相连接, 漏极 D与该直流 /直流变换器芯片的反馈管脚 FB相连接, 且该漏极 D通过一电阻 R22接地; 控制电压 Vc作用于 Q1的栅极 G。
设 Ql的导通电阻为 RON。 此时, 可以通过 Vc控制 Q1工作于放大区, 则 Vc和 RON的函数关系满足单调性。 具体针对处于放大区的 P沟道增强型 MOS管来讲, Vc和 RON的函数关系为单调递增, 即 Vc越小, 1 ^也越小。
易得, 功率放大器电压输入端的电压 VOUT和导通电阻 RON函数关系为: νουτ = νΡΒ ·^^ ~; 又由于 RON和 Vc之间存在函数关系, 且该函数关系具 有单调性, 故可通过自适应调整 Vc来达到调整 VOUT的目的。
进一步地, 为了降低对 Vc精度的要求, 从而便于对 Vc的调整, 故可以 按照图 8优化控制电路。 Q1的源极 S还通过一电阻 R23与功率放大器 PA的 电压输入端相连接, 且该电压输入端通过一电阻 R21与直流 /直流变换器芯片 的反馈管脚 FB相连接。 此时, 易得功率放大器电压输入端的电压 VOUT和导通电阻 RON函数关系 为: V0UT = VFB ~~ ~~ -- ; 同样, 由于 RON和 Vc之间存在函数关系, 且该函数关系具有单调性, 故可通过调整 Vc来达到调整 VOUT的目的。
另外, 可在终端的单板(具体可以是存储芯片)上存储表 1 中所记录的 数据之间的对应关系,以便于根据功率放大器 PA的功率等级以及工作频点查 找到与该状态对应的 Vc, 进而调整 VOUT
本发明实施例提供的终端, 通过在功率放大器的电压输入端与直流 /直流 变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路包括一 P 沟道 MOS管; 由于控制电压可以才艮据功率放大器的功率等级的改变和 /或工作频点 的改变而变化 , 并使得该 P沟道 MOS管导通, 且该 P沟道 MOS管的导通电 阻与功率放大器 PA电压输入端的电压具有一定的函数关系,故而使得控制电 压可以控制功率放大器电压输入端的电压达到某一状态下使得整机满足射频 指标的最小值, 从而可以提高功率放大器的效率, 进而减少终端的功率损耗。
实施例六:
本实施例提供又一种终端的具体实现方案。 本具体实施例提供的方案中 的功放供电电路可参考图 9,相较于实施例四中的方案只是在控制电路的设计 上不同, 其他部分与实施例四类似, 故不再贅述。
本实施例中的控制电路包括一 N沟道型场效应管 Q2 ( N-MOS管); 图 9 中的 Q2以 N沟道增强型 MOS管为例, 对于 N沟道耗尽型 MOS管的电路连 接同样可参考图 9。 Q2的源极 S接地, 漏极 D与该直流 /直流变换器芯片的反 馈管脚 FB相连接, 且控制电压 Vc作用于 Q2的栅极 G; 另外, 功率放大器 PA的电压输入端通过一电阻 R31与直流 /直流变换器芯片的反馈管脚 FB相连 接。
设 Q2的导通电阻为 RON。 此时, 可以通过 Vc控制 Q2工作于放大区, 则 Vc和 RON的函数关系满足单调性。 具体针对处于放大区的 N沟道增强型 MOS管来讲, Vc和 RON的函数关系为单调递减, 即 Vc越大, RON也越小。 易得, 功率放大器 PA电压输入端的电压 VOUT和导通电阻 RON函数关系 为: V0UT = VFB * R'l + R°N; 又由于 RON和 Vc之间存在函数关系, 且该函数关系
R。
具有单调性, 故可通过自适应调整 Vc来达到调整 VOUT的目的。
进一步地, 为了降低对 Vc精度的要求, 从而便于对 Vc的调整, 故可以 按照图 10优化控制电路。 Q2的漏极 D通过一电阻 R33与该直流 /直流变换器 芯片的反馈管脚 FB相连接, 且该反馈管脚 FB通过一电阻 R32接地。
此时, 易得功率放大器电压输入端的电压 VOUT和导通电阻 RON函数关系 为: v< 1 + - 1 ; 同样, 由于 RON和 Vc之间存在函数关系,
Figure imgf000021_0001
且该函数关系具有单调性,故可通过自适应调整 Vc来达到调整 VOUT的目的。
另外, 可在终端的单板(具体可以是存储芯片)上存储表 1 中所记录的 数据之间的对应关系,以便于根据功率放大器 PA的功率等级以及工作频点查 找到与该状态对应的 Vc, 进而调整 VOUT
本发明实施例提供的终端, 通过在功率放大器的电压输入端与直流 /直流 变换器芯片的反馈管脚之间增设一控制电路, 且该控制电路包括一 N 沟道 MOS管; 由于控制电压可以才艮据功率放大器的功率等级的改变和 /或工作频点 的改变而变化 , 并使得该 N沟道 MOS管导通, 且该 N沟道 MOS管的导通电 阻与功率放大器 PA电压输入端的电压具有一定的函数关系,故而使得控制电 压可以控制功率放大器电压输入端的电压达到某一状态下使得整机满足射频 指标的最小值, 从而可以提高功率放大器的效率, 进而减少终端的功率损耗。
通过以上的实施方式的描述, 所属领域的技术人员可以清楚地了解到本 发明可借助软件加必需的通用硬件的方式来实现, 当然也可以通过硬件, 但 很多情况下前者是更佳的实施方式。 基于这样的理解, 本发明的技术方案本 质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来, 该 计算机软件产品存储在可读取的存储介质中, 如计算机的软盘, 硬盘或光盘 等, 包括若干指令用以使得一台计算机设备(可以是个人计算机, 服务器, 或者网络设备等)执行本发明各个实施例所述的方法。
以上所述, 仅为本发明的具体实施方式, 但本发明的保护范围并不局限 于此, 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内, 可轻易 想到的变化或替换, 都应涵盖在本发明的保护范围之内。 因此, 本发明的保 护范围应以所述权利要求的保护范围为准。

Claims

权利 要求 书
1、 一种功放供电电路, 包括直流 /直流变换器芯片, 所述直流 /直流变换器 芯片包括输入管脚、 电感连接管脚以及反馈管脚, 所述输入管脚用于连接电源, 所述电感连接管脚通过一 LC储能电路与功率放大器的电压输入端相连接,其特 征在于, 所述功率放大器的电压输入端与所述反馈管脚之间连接有控制电路; 所述控制电路包括一控制电压, 该控制电压通过所述控制电路调整所述功 率放大器的电压输入端的电压,其中,该控制电压为可变的。
2、 根据权利要求 1所述的功放供电电路, 其特征在于, 所述控制电压与功 率放大器的功率等级、 工作频点存在对应关系;
所述控制电压为可变的,具体为:
所述控制电压根据所述功率放大器的功率等级的改变和 /或工作频点的改变 而变化。
3、 根据权利要求 1所述的功放供电电路, 其特征在于, 所述控制电路包括 一差分放大电路, 该差分放大电路包括一运算放大器;
所述运算放大器的同相输入端通过第一电阻与所述功率放大器的电压输入 端相连接, 且该同相输入端通过第二电阻接地;
所述控制电压通过第三电阻作用于所述运算放大器的反相输入端, 且该反 相输入端通过第四电阻与所述运算放大器的输出端相连接, 形成一反馈回路; 所述运算放大器的输出端与所述直流 /直流变换器芯片的反馈管脚相连接。
4、 根据权利要求 3所述的功放供电电路, 其特征在于, 所述运算放大器的 输出端通过一电阻与所述直流 /直流变换器芯片的反馈管脚相连接, 且该反馈管 脚通过一电阻接地。
5、 根据权利要求 3或 4所述的功放供电电路, 其特征在于, 所述第一电阻 与所述第三电阻的阻值相等, 且所述第二电阻与所述第四电阻的阻值相等。
6、 根据权利要求 1所述的功放供电电路, 其特征在于, 所述控制电路包括 一 P沟道型场效应管; 所述 P沟道型场效应管的源极与所述功率放大器的电压输入端相连接; 所述 P沟道型场效应管的漏极与所述直流 /直流变换器芯片的反馈管脚相连 接, 且该 P沟道型场效应管的漏极通过一电阻接地;
所述控制电压作用于所述 P沟道型场效应管的栅极。
7、 根据权利要求 6所述的功放供电电路, 其特征在于, 所述 P沟道型场效 应管的源极通过一电阻与所述功率放大器的电压输入端相连接; 且该电压输入 端通过一电阻与所述直流 /直流变换器芯片的反馈管脚相连接。
8、 根据权利要求 1所述的功放供电电路, 其特征在于, 所述控制电路包括 一 N沟道型场效应管;
所述 N沟道型场效应管的源极接地;
所述 N沟道型场效应管的漏极与所述直流 /直流变换器芯片的反馈管脚相连 接;
所述控制电压作用于所述 N沟道型场效应管的栅极;
且所述功率放大器的电压输入端通过一电阻与所述直流 /直流变换器芯片的 反馈管脚相连接。
9、 根据权利要求 8所述的功放供电电路, 其特征在于, 所述 N沟道型场效 应管的漏极通过一电阻与所述直流 /直流变换器芯片的反馈管脚相连接; 且该反 馈管脚通过一电阻接地。
10、 根据权利要求 1所述的功放供电电路, 其特征在于, 所述 LC储能电路 包括一电感以及一电容;
所述电感连接所述直流 /直流变换器芯片的电感连接管脚与所述功率放大器 的电压输入端, 且该功率放大器的电压输入端通过所述电容接地。
11、 一种终端, 包括基带处理单元、 功放供电电路以及功率放大器, 所述 功放供电电路包括直流 /直流变换器芯片, 该直流 /直流变换器芯片包括输入管 脚、 电感连接管脚以及反馈管脚, 所述输入管脚用于连接电源, 且所述电感连 接管脚通过一 LC储能电路与所述功率放大器的电压输入端相连接, 其特征在 于, 所述功率放大器的电压输入端与所述反馈管脚之间连接有控制电路, 且所 述控制电路包括一控制电压;
所述基带处理单元用于调整所述控制电压, 该控制电压通过所述控制电路 调整所述功率放大器的电压输入端的电压。
12、 根据权利要求 11所述的终端, 其特征在于, 所述基带处理单元包括基 带处理芯片和数模转换器, 所述基带处理单元用于调整所述控制电压具体为, 所述基带处理芯片通过所述数模转换器调整所述控制电压; 或者,
所述基带处理单元包括基带处理芯片和电源管理芯片 , 所述基带处理单元 用于调整所述控制电压具体为, 所述基带处理芯片通过所述电源管理芯片中的 低压差线性稳压器调整所述控制电压。
13、 根据权利要求 11所述的终端, 其特征在于, 所述控制电压与功率放大 器的功率等级、 工作频点存在对应关系;
所述调整所述控制电压具体为:
根据所述功率放大器的功率等级的改变和 /或工作频点的改变调整所述控制 电压。
14、 根据权利要求 11所述的终端, 其特征在于, 所述控制电路包括一差分 放大电路, 该差分放大电路包括一运算放大器;
所述运算放大器的同相输入端通过第一电阻与所述功率放大器的电压输入 端相连接, 且该同相输入端通过第二电阻接地;
所述控制电压通过第三电阻作用于所述运算放大器的反相输入端, 且该反 相输入端通过第四电阻与所述运算放大器的输出端相连接, 形成一反馈回路; 所述运算放大器的输出端与所述直流 /直流变换器芯片的反馈管脚相连接。
15、 根据权利要求 14所述的终端, 其特征在于, 所述运算放大器的输出端 通过一电阻与所述直流 /直流变换器芯片的反馈管脚相连接, 且该反馈管脚通过 一电阻接地。
16、 根据权利要求 11所述的终端, 其特征在于, 所述控制电路包括一 P沟 道型场效应管;
所述 P沟道型场效应管的源极与所述功率放大器的电压输入端相连接; 所述 P沟道型场效应管的漏极与所述直流 /直流变换器芯片的反馈管脚相连 接, 且该 P沟道型场效应管的漏极通过一电阻接地;
所述控制电压作用于所述 P沟道型场效应管的栅极。
17、 根据权利要求 16所述的终端, 其特征在于, 所述 P沟道型场效应管的 源极通过一电阻与所述功率放大器的电压输入端相连接; 且该电压输入端通过 一电阻与所述直流 /直流变换器芯片的反馈管脚相连接。
18、 根据权利要求 11所述的终端, 其特征在于, 所述控制电路包括一 N沟 道型场效应管;
所述 N沟道型场效应管的源极接地;
所述 N沟道型场效应管的漏极与所述直流 /直流变换器芯片的反馈管脚相连 接;
所述控制电压作用于所述 N沟道型场效应管的栅极;
且所述功率放大器的电压输入端通过一电阻与所述直流 /直流变换器芯片的 反馈管脚相连接。
19、 根据权利要求 18所述的终端, 其特征在于, 所述 N沟道型场效应管的 漏极通过一电阻与所述直流 /直流变换器芯片的反馈管脚相连接;且该反馈管脚通 过一电阻接地。
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