WO2012093424A1 - Synthétiseur de fréquence à pas fractionnaire à boucle asservie et modulation delta-sigma, et dispositif de communication sans fil en étant équipé - Google Patents

Synthétiseur de fréquence à pas fractionnaire à boucle asservie et modulation delta-sigma, et dispositif de communication sans fil en étant équipé Download PDF

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Publication number
WO2012093424A1
WO2012093424A1 PCT/JP2011/003182 JP2011003182W WO2012093424A1 WO 2012093424 A1 WO2012093424 A1 WO 2012093424A1 JP 2011003182 W JP2011003182 W JP 2011003182W WO 2012093424 A1 WO2012093424 A1 WO 2012093424A1
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WIPO (PCT)
Prior art keywords
delta
fractional
frequency
data
frequency division
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PCT/JP2011/003182
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English (en)
Japanese (ja)
Inventor
陽一郎 堀内
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パナソニック株式会社
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Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2012093424A1 publication Critical patent/WO2012093424A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention concerne un synthétiseur de fréquence à pas fractionnaire à boucle asservie et modulation delta-sigma qui sert à effectuer un fractionnement par la modulation d'un diviseur (25), le synthétiseur comprenant : un moyen de traitement arithmétique (27) servant, d'une part, à obtenir une quantité de décalage (S) à ajouter à une donnée de partie fractionnaire (K), et, d'autre part, à générer la quantité de décalage (S) et une donnée de partie fractionnaire (K2) ; un premier modulateur delta-sigma (28) servant à intégrer et quantifier la donnée de partie fractionnaire décalée (K2) ; un deuxième modulateur delta-sigma (29) servant à intégrer et quantifier la quantité du décalage (S) ; un premier additionneur (30) servant à additionner les séries produites par le premier modulateur delta-sigma (28) et la sortie à inversion de signe du deuxième modulateur delta-sigma (29) ; et un deuxième additionneur (31) servant à ajouter une donnée de partie entière (M) et la sortie du premier additionneur (30). Le diviseur (25) est modulé par la sortie du deuxième additionneur (31).
PCT/JP2011/003182 2011-01-07 2011-06-06 Synthétiseur de fréquence à pas fractionnaire à boucle asservie et modulation delta-sigma, et dispositif de communication sans fil en étant équipé WO2012093424A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011001908A JP2012147080A (ja) 2011-01-07 2011-01-07 デルタシグマ変調型分数分周ｐｌｌ周波数シンセサイザおよびそれを備えた無線通信装置
JP2011-001908 2011-01-07

Publications (1)

Publication Number Publication Date
WO2012093424A1 true WO2012093424A1 (fr) 2012-07-12

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PCT/JP2011/003182 WO2012093424A1 (fr) 2011-01-07 2011-06-06 Synthétiseur de fréquence à pas fractionnaire à boucle asservie et modulation delta-sigma, et dispositif de communication sans fil en étant équipé

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JP (1) JP2012147080A (fr)
WO (1) WO2012093424A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110190847A (zh) * 2019-04-26 2019-08-30 西安邮电大学 一种应用于频率合成器的小数n分频电路及方法
WO2020012557A1 (fr) * 2018-07-10 2020-01-16 三菱電機株式会社 Circuit à boucle à verrouillage de phase
US20230126891A1 (en) * 2021-10-27 2023-04-27 Nxp B.V. Circuitry and methods for fractional division of high-frequency clock signals

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6439915B2 (ja) 2014-09-12 2018-12-19 セイコーエプソン株式会社 フラクショナルｎ−ｐｌｌ回路、発振器、電子機器及び移動体

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003046389A (ja) * 2001-08-03 2003-02-14 Nippon Precision Circuits Inc フラクショナルｎ周波数シンセサイザ及びその動作方法
JP2004147106A (ja) * 2002-10-24 2004-05-20 Matsushita Electric Works Ltd フラクショナルｎｐｌｌシンセサイザ、フラクショナルｎｐｌｌシンセサイザの発振周波数帯域制限方法、及びそれを用いた無線通信方法
US7187313B1 (en) * 2005-10-31 2007-03-06 Mediatek Inc. Fractional-N frequency synthesizer with sigma-delta modulator for variable reference frequencies

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003046389A (ja) * 2001-08-03 2003-02-14 Nippon Precision Circuits Inc フラクショナルｎ周波数シンセサイザ及びその動作方法
JP2004147106A (ja) * 2002-10-24 2004-05-20 Matsushita Electric Works Ltd フラクショナルｎｐｌｌシンセサイザ、フラクショナルｎｐｌｌシンセサイザの発振周波数帯域制限方法、及びそれを用いた無線通信方法
US7187313B1 (en) * 2005-10-31 2007-03-06 Mediatek Inc. Fractional-N frequency synthesizer with sigma-delta modulator for variable reference frequencies

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KOKUBO, M. ET AL.: "Spread-spectrum clock generator for serial ATA using fractional PLL controlled by DELTASIGMA modulator with level shifter", 2005 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS, 10 February 2005 (2005-02-10), pages 160 - 161,590 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020012557A1 (fr) * 2018-07-10 2020-01-16 三菱電機株式会社 Circuit à boucle à verrouillage de phase
JPWO2020012557A1 (ja) * 2018-07-10 2020-12-17 三菱電機株式会社 位相同期回路
CN110190847A (zh) * 2019-04-26 2019-08-30 西安邮电大学 一种应用于频率合成器的小数n分频电路及方法
US20230126891A1 (en) * 2021-10-27 2023-04-27 Nxp B.V. Circuitry and methods for fractional division of high-frequency clock signals
US11784651B2 (en) * 2021-10-27 2023-10-10 Nxp B.V. Circuitry and methods for fractional division of high-frequency clock signals

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