Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/3452—Solder masks

Definitions

• the inventions generally relate to crosstalk reduction for microstrip routing.
• Microstrip routing is commonly used for trace routing on boards such as Printed Circuit Boards (PCBs).
• PCBs Printed Circuit Boards
• microstrip routing suffers a much greater amount of crosstalk as compared with stripline routing. This is due to the fact that there is more inductive coupling (which results in a positive crosstalk value) than capacitive coupling (which results in a negative crosstalk value) when using microstrip routing.
• Microstrip traces usually have a large far-end crosstalk (FEXT), which degrades the quality of the signal transmitted using the microstrip traces.
• FEXT far-end crosstalk
• FIG 1 illustrates a system according to some embodiments of the inventions.
• Some embodiments of the inventions relate to crosstalk reduction on microstrip routing.
• a plurality of differential pair traces include microstrip routing and a layer is formed over the plurality of differential pair traces.
• the layer formed over the plurality of differential pair traces is a thick solder mask, a dielectric layer, and/or a solder mask with a high dielectric constant.
• FIG 1 illustrates a system 100 according to some embodiments.
• system 100 is included on a board and/or a PCB.
• system includes a dielectric (and/or dielectric layer and/or dielectric substrate) 102, a first differential signaling pair 104, a second differential signaling pair 106, and a solder mask 108.
• s in FIG 1 illustrates an intra-pair spacing
• w in FIG 1 illustrates a trace width
• d in FIG 1 illustrates an inter-pair spacing
• hus in FIG 1 illustrates a dielectric height
• Sm solder mask height
• tus in FIG 1 illustrates a trace and copper plating height.
• the first differential signaling pair 104 and/or the second differential signaling pair 106 are high speed differential signaling pairs. In some embodiments, the first differential signaling pair 104 and/or the second differential signaling pair 106 each include a trace and copper plating. In some embodiments, the first differential signaling pair 104 and/or the second differential signaling pair 106 are implemented using microstrip trace routing. As discussed above, microstrip traces usually have a far-end crosstalk (FEXT) that degrades signal quality. Microstrip routing is commonly used in PCB routing, although it suffers much greater crosstalk than that of stripline routing.
• FEXT far-end crosstalk
• the solder mask 108 height (Sm) is at least 0.8mils higher than the trace and copper plating height of the first differential signal (that is, the thickness of the solder mask 108 is 0.8mils or greater).
• a solder mask such as solder mask 108 is intentionally thickened (for example, to 0.8mils or more).
• a dielectric layer is included on top of the traces (for example, on top of the traces of differential signals 104 and/or 106).
• a high dielectric constant is used in a solder mask (for example, in solder mask 108).
• a closer spacing is provided between the routing traces (for example between the traces of differential signals 104 and/or 106).
• far-end crosstalk is reduced, thereby improving the signaling performance.
• solder mask 108 is placed on the board to keep parts from shorting out.
• the solder mask 108 is intentionally made thicker.
• the thickness Sm of the solder mask is 0.8 mil or more greater than the height of the trace (that is solder mask 108 extends a distance Sm of 0.8 mil or more higher than the height tus of the trace and copper plating of the differential signaling pairs such as differential signaling pairs 104 and/or 106 of FIG 1). This is much thicker than the solder mask used in a typical PCB stackup, where the solder mask extends only about 0.3 mils higher than the height of the trace plus the copper plating (tus).
• microstrip where layer count is a concern, for example, signals are often routed on the surface layers as microstrip. This leads to space constraints because microstrip traces have previously needed to be spaced farther apart than stripline traces in order to reduce crosstalk effects. Thus, according to some embodiments, crosstalk is reduced and a reduction of interpair spacing for microstrip traces is implemented. Additionally, the signaling performance is improved due to the reduced crosstalk.
• the crosstalk of a system such as system 100 of FIG 1 with a solder mask 108 thickness Sm of 0.8 mils higher than the height tus of the trace plus the copper plating is reduced by as much as 40% compared with a solder mask thickness (Sm) of 0.3 mils higher than the height (tus) of the trace plus the copper plating.
• the crosstalk of the 0.8 mil solder mask implementation is inverted relative to the 0.3 mil implementation for a 5mil trace width (w), a 5mil intra-pair spacing (s), and a 4mil inter-pair spacing (d).
• inter-pair spacing (d) As the inter-pair spacing (d) is changed from 4mils to 14mils, for example, inter-pair spacing (d) dominates the capacitive coupling effect, which results in a lower crosstalk for implementations using an inter-pair spacing (d) in the range of 4mils to 7mils.
• the combination of solder mask thickness and a small inter-pair spacing between differential pair signals helps to significantly reduce crosstalk and increase routing density on a board.
• the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar.
• an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein.
• the various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
• Coupled may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
• An algorithm is here, and generally, considered to be a self-consistent sequence of acts or operations leading to a desired result. These include physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
• Some embodiments may be implemented in one or a combination of hardware, firmware, and software. Some embodiments may also be implemented as instructions stored on a machine- readable medium, which may be read and executed by a computing platform to perform the operations described herein.
• a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer).
• a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, the interfaces that transmit and/or receive signals, etc.), and others.
• An embodiment is an implementation or example of the inventions.
• Reference in the specification to "an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions.
• the various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Structure Of Printed Boards (AREA)

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Citations (3)

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• 2010
  • 2010-12-22 US US12/976,551 patent/US20120160542A1/en not_active Abandoned
• 2011
  • 2011-12-13 WO PCT/US2011/064504 patent/WO2012087647A1/en active Application Filing
  • 2011-12-13 CN CN201180062111.XA patent/CN103270645B/zh active Active
  • 2011-12-20 TW TW100147466A patent/TWI609523B/zh active

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