WO2012077178A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- WO2012077178A1 WO2012077178A1 PCT/JP2010/071885 JP2010071885W WO2012077178A1 WO 2012077178 A1 WO2012077178 A1 WO 2012077178A1 JP 2010071885 W JP2010071885 W JP 2010071885W WO 2012077178 A1 WO2012077178 A1 WO 2012077178A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- diffusion layer
- transistors
- layer
- nmos
- length
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Definitions
- This invention relates to a semiconductor device.
- MOS transistors Semiconductor integrated circuits, especially integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region.
- the basic circuit of the digital circuit is an inverter circuit.
- the MOS transistors constituting the inverter circuit are miniaturized, it is difficult to suppress the leakage current, and the reliability is lowered due to the hot carrier effect. There is a problem that the occupied area of the circuit cannot be made small because of a demand for securing a sufficient amount of current.
- Non-patent Document 1 In a static memory cell, it is known to ensure operational stability by making the current driving capability of a driver transistor twice that of an access transistor (Non-patent Document 1).
- the SGT manufacturing method forms a columnar semiconductor layer, then deposits a gate conductive film, planarizes it, and etch-back it to a desired length (Patent Document 4).
- the physical gate length of the SGT is constant for all transistors on the wafer.
- the gate capacitance of the MOS transistor connected to the storage node and the diffusion layer capacitance are reduced due to the size reduction.
- the static memory cell is irradiated with radiation from the outside.
- electron-hole pairs are generated along the radiation range in the semiconductor substrate, and at least one of the electron-hole pairs flows into the diffusion layer forming the drain, causing inversion of data and maintaining correct data.
- a soft error phenomenon occurs that cannot be performed. This soft error phenomenon is because the smaller the memory cell size is, the more the reduction of the gate capacity of the MOS transistor connected to the storage node and the capacity of the diffusion layer becomes more significant than the electron-hole pair generated by radiation.
- Patent Document 5 a capacitor is formed in a storage node of a static memory cell and a sufficient charge amount is secured in the storage node to avoid a soft error and to ensure operation stability.
- a semiconductor memory device includes: A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate, The six MOS transistors are First and second NMOS access transistors for accessing the memory, third and fourth NMOS driver transistors for driving the storage nodes holding the memory cell data, and holding the memory cell data
- the first and second PMOS load transistors for supplying electric charge to
- Each of the first and second NMOS access transistors for accessing the memory includes a first diffusion layer, a columnar semiconductor layer, and a second diffusion layer, wherein the columnar semiconductor layer is the first diffusion layer and the first diffusion layer.
- Each of the third and fourth NMOS driver transistors that drive the storage node to hold data in the memory cell includes a third diffusion layer, a columnar semiconductor layer, and a fourth diffusion layer, and the columnar semiconductor layer includes Hierarchically arranged in a direction perpendicular to the substrate to be arranged between the third diffusion layer and the fourth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
- Each of the first and second PMOS load transistors that supply charges to hold data in the memory cell includes a fifth diffusion layer, a columnar semiconductor layer, and a sixth diffusion layer, and the columnar semiconductor layer Hierarchically arranged in a direction perpendicular to the substrate so as to be arranged between the fifth diffusion layer and the sixth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
- the semiconductor memory device is A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate,
- the six MOS transistors are First and second NMOS access transistors for accessing the memory, third and fourth NMOS driver transistors for driving the storage node to hold the memory cell data, and holding the memory cell data
- the first and second PMOS load transistors for supplying electric charge to
- Each of the first and second NMOS access transistors for accessing the memory includes a first diffusion layer, a columnar semiconductor layer, and a second diffusion layer, wherein the columnar semiconductor layer includes the first diffusion layer and the first diffusion layer.
- Each of the third and fourth NMOS driver transistors that drive the storage node to hold data in the memory cell includes a third diffusion layer, a columnar semiconductor layer, and a fourth diffusion layer, and the columnar semiconductor layer includes the columnar semiconductor layer.
- Each of the first diffusion layer, the third diffusion layer, and the fifth diffusion layer is disposed to be electrically insulated from the substrate,
- Each of the first and second PMOS load transistors that supply charges to hold data in the memory cell includes a fifth diffusion layer, a columnar semiconductor layer, and a sixth diffusion layer, and the columnar semiconductor layer includes the columnar semiconductor layer.
- a semiconductor device characterized in that it is shorter than the length between the upper end of the fifth diffusion layer and the lower end of the sixth diffusion layer.
- the length between the upper end of the first diffusion layer that forms the first and second NMOS access transistors and the lower end of the second diffusion layer is the same as the length that forms the third and fourth NMOS driver transistors. It is desirable that the length be between 1.3 times and 3 times the length between the upper end of the third diffusion layer and the lower end of the fourth diffusion layer.
- the length between the upper end of the fifth diffusion layer that forms the first and second PMOS load transistors and the lower end of the sixth diffusion layer is the third length that forms the third and fourth NMOS driver transistors. It is desirable that the length is 1.3 to 3 times the length between the upper end of the diffusion layer and the lower end of the fourth diffusion layer.
- the length from the lower end to the upper end of the gate can be the same.
- the upper ends of the third diffusion layers of the third and fourth NMOS driver transistors may be higher than the upper ends of the first diffusion layers of the first and second NMOS access transistors.
- the lower ends of the fourth diffusion layers of the third and fourth NMOS driver transistors may be lower than the lower ends of the second diffusion layers of the first and second NMOS access transistors.
- the upper ends of the third diffusion layers of the third and fourth NMOS driver transistors are higher than the upper ends of the first diffusion layers of the first and second NMOS access transistors,
- the lower ends of the fourth diffusion layers of the third and fourth NMOS driver transistors may be lower than the lower ends of the second diffusion layers of the first and second NMOS access transistors.
- the first diffusion layer of each of the first and second NMOS access transistors can be formed.
- the fourth diffusion layer of the third and fourth NMOS driver transistors and the second diffusion layer of each of the first and second NMOS access transistors are formed by ion implantation, The amount of ion implantation energy for forming the fourth diffusion layer of each of the third and fourth NMOS driver transistors is formed, and the second diffusion layer of each of the first and second NMOS access transistors is formed.
- the amount of energy for ion implantation can be higher.
- Phosphorus can be included in the fourth diffusion layer of the third and fourth NMOS driver transistors.
- the channel length of the driver transistor can be made shorter than the channel length of the access transistor, and it is possible to provide a static memory cell that is highly integrated and ensures operational stability, and a method for manufacturing the same.
- FIG. 4A is a plan view of a static memory cell according to first and second embodiments of the present invention.
- FIG. 4B is a sectional view taken along line X-X ′ in FIG.
- (A) is sectional drawing of the static type memory cell based on the 3rd and 5th embodiment of this invention.
- (B) is sectional drawing of the static type memory cell which concerns on the 4th and 6th embodiment of this invention. It is sectional drawing of the static memory cell which concerns on the 7th Embodiment of this invention. It is sectional drawing of the static memory cell which concerns on the 8th Embodiment of this invention. It is sectional drawing of the static memory cell which concerns on the 9th Embodiment of this invention.
- FIG. 1 shows a plan view and a cross-sectional view of a static memory cell according to the first embodiment of the present invention.
- the third NMOS driver transistor 101 has a third diffusion layer 119, a columnar semiconductor layer 149, and a fourth diffusion layer 107.
- a gate 125 is formed on the side wall of the columnar semiconductor layer 149 of the third NMOS driver transistor 101, a part of the fourth diffusion layer 107 and a part of the third diffusion layer 119 with a gate insulating film 113 interposed therebetween. .
- the first NMOS access transistor 103 has a first diffusion layer 121, a columnar semiconductor layer 151, and a second diffusion layer 109.
- a gate 126 is formed on a side wall of a part of the columnar semiconductor layer 151, the second diffusion layer 109, and a part of the first diffusion layer 121 of the first NMOS access transistor 103 with a gate insulating film 115 interposed therebetween. .
- the gate 125 has a lower gate height in the vicinity of the third NMOS driver transistor, and the physical gate length is shorter than the gate 126.
- the length between the first diffusion layer 121 and the second diffusion layer 109 forming the first NMOS access transistor 103 is the same as the length of the third diffusion layer 119 and the fourth diffusion layer 109 forming the third NMOS driver transistor 101. This is twice the length between the diffusion layers 107. As a result, the current driving capability of the driver transistor can be double that of the access transistor without increasing the area, and operation stability can be ensured.
- the first PMOS load transistor 102 has a fifth diffusion layer 120, a columnar semiconductor layer 150, and a sixth diffusion layer 108.
- a gate 125 is formed on a side wall of a part of the columnar semiconductor layer 150, the fifth diffusion layer 120, and a part of the sixth diffusion layer 108 of the first PMOS load transistor 102 with a gate insulating film 114 interposed therebetween. .
- the third NMOS driver transistor 101 and the first PMOS load transistor 102 are connected by a gate 125.
- the third diffusion layer 119, the fifth diffusion layer 120, and the first diffusion layer 121 are connected by silicide (not shown in the drawing).
- an SOI substrate is used to electrically insulate the third diffusion layer 119, the fifth diffusion layer 120, and the first diffusion layer 121 from the substrate.
- a PN junction may be formed using a Si substrate, and electrical insulation may be formed using a reverse bias state of the PN junction.
- the fourth NMOS driver transistor 106 includes a third diffusion layer 124, a columnar semiconductor layer, and a fourth diffusion layer 112.
- a gate 128 is formed on a side wall of the columnar semiconductor layer of the fourth NMOS driver transistor 106, a part of the third diffusion layer 124 and a part of the fourth diffusion layer 112 with a gate insulating film 118 interposed therebetween.
- the second NMOS access transistor 104 has a first diffusion layer 122, a columnar semiconductor layer, and a second diffusion layer 110.
- a gate 127 is formed on the side wall of the columnar semiconductor layer of the second NMOS access transistor 104, a part of the first diffusion layer 112 and a part of the second diffusion layer 110 with a gate insulating film 116 interposed therebetween.
- the length between the first diffusion layer 122 that forms the second NMOS access transistor 104 and the second diffusion layer 110 is the third length that forms the fourth NMOS driver transistor 106. This is twice the length between the diffusion layer 124 and the fourth diffusion layer 112.
- the second PMOS load transistor 105 has a fifth diffusion layer 123, a columnar semiconductor layer, and a sixth diffusion layer 111.
- a gate 128 is formed on the side wall of the columnar semiconductor layer of the second PMOS load transistor 105, a part of the fifth diffusion layer 123 and a part of the sixth diffusion layer 111 with a gate insulating film 117 interposed therebetween.
- the fourth NMOS driver transistor 106 and the second PMOS load transistor 105 are connected by a gate 128.
- the first diffusion layer 122, the fifth diffusion layer 123, and the third diffusion layer 124 are connected by silicide (not shown in the drawing).
- an SOI substrate is used to electrically insulate the first diffusion layer 122, the fifth diffusion layer 123, and the third diffusion layer 124 from the substrate.
- a PN junction may be formed using a Si substrate, and electrical insulation may be formed using a reverse bias state of the PN junction.
- a contact 130 is formed on the gate 125, and a contact 137 is formed on the first diffusion layer 122 and the fifth diffusion layer 123. Contacts 130 and 137 are connected by metal 142.
- a contact 139 is formed on the gate 128, and a contact 132 is formed on the fifth diffusion layer 120 and the first diffusion layer 121. Contacts 139 and 132 are connected by metal 144.
- a contact 131 is formed on the sixth diffusion layer 108, a contact 138 is formed on the sixth diffusion layer 111, a metal 143 is connected to the contacts 131 and 138, and power is supplied.
- a contact 129 is formed on the fourth diffusion layer 107, a metal 141 is formed, and power is supplied.
- a contact 140 is formed on the fourth diffusion layer 112, a metal 148 is formed, and power is supplied.
- a contact 133 is formed on the second diffusion layer 109, a metal 145 is formed, and becomes a bit line.
- a contact 136 is formed on the second diffusion layer 110, and a metal 210 is formed to form a bit line.
- a contact 134 is formed on the gate 126, and a metal 146 is formed to form a word line.
- a contact 135 is formed on the gate 127, a metal 147 is formed, and becomes a word line.
- a plan view and a cross-sectional view of a static memory cell according to the second embodiment of the present invention are the same as those in FIG.
- the length between the third diffusion layer 119 and the fourth diffusion layer 107 forming the third NMOS driver transistor 101 is the same as the fifth PMOS transistor forming the first PMOS load transistor 102. It is shorter than the length between the diffusion layer 120 and the sixth diffusion layer 108.
- the PMOS load transistor is formed with a minimum size, and the current driving capability of the PMOS load transistor is smaller than the current driving capability of the NMOS access transistor. That is, the channel lengths of the NMOS access transistor and the PMOS load transistor are formed to be the same. Therefore, in the present invention, the channel length of the NMOS driver transistor 101 is shorter than the channel length of the PMOS driver transistor 102.
- FIGS. 2A and 2B are cross-sectional views of static memory cells according to the third and fourth embodiments of the present invention.
- the length between the upper end of the first diffusion layer 121 and the lower end of the second diffusion layer 109 forming the first NMOS access transistor 103 is the third NMOS driver transistor 101. Is 1.3 times the length between the upper end of the third diffusion layer 119 and the lower end of the fourth diffusion layer 107.
- the length between the upper end of the first diffusion layer 121 and the lower end of the second diffusion layer 109 forming the first NMOS access transistor 103 is the third NMOS driver transistor 101. 3 times the length between the upper end of the third diffusion layer 119 and the lower end of the fourth diffusion layer 107.
- the operational stability can be ensured.
- the driver transistor is shortened, a short channel effect occurs and the transistor cannot be cut off. Therefore, it may be selected as appropriate according to the required requirements. As an example, if the range is between 1.3 times and 3 times, the operational stability can be ensured and the short channel effect can be suppressed.
- the plan view and the cross-sectional view of the static memory cell according to the fifth and sixth embodiments of the present invention are the same as FIGS. 2 (a) and 2 (b).
- the length between the upper end of the fifth diffusion layer 120 and the lower end of the sixth diffusion layer 108 forming the first PMOS load transistor 102 is the third NMOS driver transistor 101. Is 1.3 times the length between the upper end of the third diffusion layer 119 and the lower end of the fourth diffusion layer 107.
- the length between the upper end of the fifth diffusion layer 120 and the lower end of the sixth diffusion layer 108 forming the first PMOS load transistor 102 is the third NMOS driver.
- the length between the upper end of the third diffusion layer 119 forming the transistor 101 and the lower end of the fourth diffusion layer 107 is set to three times. As the channel length of the driver transistor is shortened, the operational stability can be ensured. On the other hand, if the driver transistor is shortened, a short channel effect occurs and the transistor cannot be cut off. Therefore, it may be selected as appropriate according to the required requirements. As an example, if the range is between 1.3 times and 3 times, the operational stability can be ensured and the short channel effect can be suppressed.
- FIG. 3 is a cross-sectional view of a static memory cell according to the seventh embodiment of the present invention.
- the gates 125 and 126 have the same physical gate length. Since the length from the lower end to the upper end of the gates 125 and 126, that is, the physical gate length is the same, after forming the columnar semiconductor layer, the gate conductive film is deposited, planarized, and etched back to the desired length. The manufacturing method of SGT of this can be used.
- shortening the channel length means shortening the physical gate length as shown in FIG.
- the gate capacitance is reduced.
- the gate capacitance becomes small, a soft error occurs, and the operation stability cannot be secured.
- the current driving capability of the driver transistor can be double that of the access transistor, ensuring operational stability, further avoiding soft errors, and ensuring operational stability.
- FIG. 4 shows a cross-sectional view of a static memory cell according to the eighth embodiment of the present invention.
- the physical gate length is the same, and the upper end of the third diffusion layer 119 of the third NMOS driver transistor 101 is higher than the upper end of the first diffusion layer 121 of the first NMOS access transistor 103.
- the third NMOS driver transistor 101 can increase the overlap capacitance between the gate 125 and the third diffusion layer 119.
- the overlap capacitance between the gate 125 and the third diffusion layer 119 becomes a parasitic capacitance parasitic on the storage node, and the overlap capacitance is large. It is possible to avoid errors and ensure operational stability.
- FIG. 5 is a sectional view of a static memory cell according to the ninth embodiment of the present invention.
- the difference from FIG. 4 is that the upper end of the third diffusion layer 119 of the third NMOS driver transistor 101 is the same as the height of the upper end of the first diffusion layer 121 of the first NMOS access transistor 103.
- the lower end of the fourth diffusion layer 107 of the third NMOS driver transistor 101 is lower than the lower end of the second diffusion layer 109 of the first NMOS access transistor 103.
- the gate capacitance is not reduced even though the current driving capability of the driver transistor is doubled.
- the current driving capability of the driver transistor can be twice that of the access transistor, ensuring operational stability, avoiding soft errors, and ensuring operational stability.
- the overlap capacitance between the gate 125 and the third diffusion layer 119 is a parasitic capacitance parasitic to the storage node.
- the storage node when the storage node is designed to be above the transistor, it has an advantage of avoiding a soft error.
- a relatively long heat treatment is required after ion implantation for the third diffusion layer.
- the fourth diffusion layer 107 is formed by ion implantation, the lower end of the fourth diffusion layer 107 of the third NMOS driver transistor 101 is made higher by increasing the implantation energy or using phosphorus having a long diffusion length. It can be made lower than the lower end of the second diffusion layer 109 of one NMOS access transistor 103. That is, the heat treatment can be reduced as compared with FIG.
- FIG. 6 shows a cross-sectional view of a static memory cell according to the tenth embodiment of the present invention.
- the difference from FIG. 4 is that the upper end of the third diffusion layer 119 of the third NMOS driver transistor 101 is higher than the upper end of the first diffusion layer 121 of the first NMOS access transistor 103, and the third NMOS The lower end of the fourth diffusion layer 107 of the driver transistor 101 is lower than the lower end of the second diffusion layer 109 of the first NMOS access transistor 103.
- the operational stability can be ensured by making the channel length of the driver transistor shorter than the channel length of the access transistor. Further, it is possible to avoid a soft error, which is an advantage of FIG. Since the diffusion length of the third diffusion layer 119 is short, the third diffusion layer 119 can be formed with fewer heat treatments than the shape shown in FIG.
- the fourth diffusion layer 107 is formed by ion implantation, the lower end of the fourth diffusion layer 107 of the third NMOS driver transistor 101 is made higher by increasing the implantation energy or using phosphorus having a long diffusion length. It can be made lower than the lower end of the second diffusion layer 109 of one NMOS access transistor 103. That is, the heat treatment can be reduced as compared with FIG. 4, and soft errors can be avoided.
- the number of manufacturing steps is increased compared to the shape of FIG. 4 and the shape of FIG.
- an oxide film 157 is formed on silicon 152, a planar silicon 158 is formed thereon, and columnar silicon 159, 160, 161 having nitride film hard masks 162, 163, 164 on top are formed. It shows the state that was done.
- an oxide film is deposited and etched back as shown in FIG. 8 to form oxide film side walls 165, 166, and 167 as shown in FIG. Thereafter, a resist 168 for forming the third diffusion layer 119 is formed.
- arsenic is implanted to form a third diffusion layer 119.
- the resist 168 is peeled off, the oxide film side walls 165, 166, and 167 are peeled off, and the first heat treatment is performed.
- oxide film side walls 169, 170, and 171 are formed. Thereafter, a resist 172 for forming the first diffusion layer 121 is formed.
- arsenic is implanted to form the first diffusion layer 121.
- the resist 172 is peeled off, the oxide film side walls 169, 170, 171 are peeled off, and a second heat treatment is performed. Since the third diffusion layer 119 is subjected to two heat treatments, the upper end of the third diffusion layer 119 is higher than the upper end of the first diffusion layer 121. As a result, the channel length of the driver transistor is shorter than the channel length of the access transistor, and operation stability can be ensured.
- oxide film side walls 173, 174, and 175 are formed.
- a resist 176 for forming the fifth diffusion layer 120 is formed.
- boron is implanted to form the fifth diffusion layer 120.
- the resist 176 is peeled off, the oxide film side walls 173, 174, 175 are peeled off, and heat treatment is performed.
- a resist for element isolation formation is formed, silicon is etched, and the resist is peeled off.
- an oxide film 153 is formed so as to fill in between the elements, and then an atmospheric pressure CVD oxide film is deposited and etched back to form an oxide film 177.
- the oxide films 178, 179, 180 remain on the nitride film hard masks 162, 163, 164.
- gate insulating films 113, 114, and 115 are formed, and a gate conductive film 181 is deposited and planarized. After the oxide films 178, 179, and 180 are exposed, the oxide films 178, 179, and 180 are etched and further planarized, and the nitride film hard mask is used as a stopper.
- the gate insulating film is one of an oxide film, a nitride film, an oxynitride film, and a high dielectric film.
- the gate conductive film is one of polysilicon, a laminated film of metal and polysilicon, and a metal film.
- the gate conductive film 181 is etched back to obtain a desired physical gate length.
- the physical gate length is constant for all transistors.
- an oxide film is deposited, a nitride film is deposited, etched, and left in a sidewall shape.
- an insulating film sidewall including an oxide film 184 and a nitride film 185, an oxide film 186, An insulating film sidewall made of the nitride film 187, an insulating film sidewall made of the oxide film 188, and the nitride film 189 are formed.
- resists 182 and 183 for etching the gate are formed as shown in FIG.
- the gate conductive film 181 is etched to form the gates 125 and 126, the oxide film 177 is etched, the oxide films 154 and 155 are formed, and the resists 182 and 183 are peeled off.
- an insulating film sidewall made of an oxide film 184 and a nitride film 185, an insulating film sidewall made of an oxide film 186 and a nitride film 187, an insulating film side made of an oxide film 188 and a nitride film 189 Etch the wall.
- nitride film sidewalls 190, 191, 192, 193, 194 are formed as shown in FIG.
- a resist 195 for forming the second diffusion layers 107 and 109 is formed.
- arsenic ions are implanted to form a fourth diffusion layer 107 and a second diffusion layer 109.
- the resist 195 is removed and heat treatment is performed.
- a resist 196 for forming the sixth diffusion layer 108 is formed.
- boron is ion-implanted to form a sixth diffusion layer 108.
- the resist 196 is removed and heat treatment is performed.
- an interlayer film 156 is deposited, contacts 129, 130, 131, 132, 133, and 134 are formed, and metals 141, 142, 143, 144, 145, and 146 are formed.
- silicide may be formed on the third diffusion layer 119, the fifth diffusion layer 120, and the first diffusion layer 121. Further, silicide may be formed over the fourth diffusion layer 107, the sixth diffusion layer 108, and the second diffusion layer 109.
- the channel length of the driver transistor shorter than the channel length of the access transistor.
- the SGT manufacturing method described above can be used.
- the current driving capability of the driver transistor can be double that of the access transistor, ensuring operational stability, further reducing only the channel length of the driver transistor, and the same physical gate length. Therefore, although the current driving capability of the driver transistor is doubled, the gate capacitance is not reduced, so that soft errors can be avoided and operational stability can be ensured.
- the upper end of the third diffusion layer of the driver transistor is positioned higher than the upper end of the first diffusion layer of the access transistor, so that the driver transistor increases the overlap capacitance between the gate and the third diffusion layer. Further, a manufacturing method for forming a structure capable of further avoiding a soft error and ensuring operational stability has been shown.
- an oxide film 157 is formed on silicon 152, a planar silicon 158 is formed thereon, and columnar silicon 159, 160, and 161 having nitride film hard masks 162, 163, and 164 formed thereon are formed. It is a structure that has been.
- an oxide film is deposited and etched back to form oxide film side walls 165, 166, and 167.
- a resist 172 for forming the third diffusion layer 119 and the first diffusion layer 121 is formed.
- arsenic is implanted to form a third diffusion layer 119 and a first diffusion layer 121.
- the resist 172 is peeled off, the oxide film side walls 165, 166, 167 are peeled off, and heat treatment is performed.
- oxide film side walls 173, 174, and 175 are formed. Thereafter, a resist 176 for forming the fifth diffusion layer 120 is formed.
- boron is implanted to form a fifth diffusion layer 120.
- the resist 176 is peeled off, the oxide film side walls 173, 174, 175 are peeled off, and heat treatment is performed.
- a resist for element isolation formation is formed, silicon is etched, and the resist is peeled off.
- an oxide film 153 is formed so as to fill in between the elements, and then an atmospheric pressure CVD oxide film is deposited and etched back to form an oxide film 177.
- the oxide films 178, 179, 180 remain on the nitride film hard masks 162, 163, 164.
- gate insulating films 113, 114, and 115 are formed, and a gate conductive film 181 is deposited and planarized.
- a gate conductive film 181 is deposited and planarized.
- the oxide films 178, 179, and 180 are exposed, the oxide films 178, 179, and 180 are etched and further planarized, and the nitride film hard mask is used as a stopper.
- the gate insulating film is one of an oxide film, a nitride film, an oxynitride film, and a high dielectric film.
- the gate conductive film is one of polysilicon, a laminated film of metal and polysilicon, and a metal film.
- the gate conductive film 181 is etched back to obtain a desired physical gate length.
- the physical gate length is constant for all transistors.
- an oxide film is deposited, a nitride film is deposited, etched, and left in the shape of a sidewall to form an oxide film 184, an insulating film sidewall made of a nitride film 185, an oxide film 186, An insulating film sidewall made of the nitride film 187, an insulating film sidewall made of the oxide film 188, and the nitride film 189 are formed.
- resists 182 and 183 for etching the gate are formed.
- the gate conductive film 181 is etched to form the gates 125 and 126, the oxide film 177 is etched, the oxide films 154 and 155 are formed, and the resists 182 and 183 are peeled off.
- a nitride film is deposited and etched to remain in a sidewall shape, thereby forming nitride film sidewalls 190, 191, 192, 193, and 194.
- a resist 201 for forming the fourth diffusion layer 107 is formed.
- arsenic or phosphorus is ion-implanted to form a fourth diffusion layer 107.
- the ion implantation energy may be increased.
- the lower end of the fourth diffusion layer 107 of the third NMOS driver transistor 101 is made lower than the lower end of the second diffusion layer 109 of the first NMOS access transistor 103.
- Can be. Whether to use arsenic or phosphorus may be selected as appropriate.
- the resist 201 is removed and heat treatment is performed.
- a resist 202 for forming the second diffusion layer 109 is formed.
- ions of arsenic are implanted to form a second diffusion layer 109.
- the resist 202 is removed and heat treatment is performed.
- a resist 203 for forming the sixth diffusion layer 108 is formed.
- boron is ion-implanted to form the second diffusion layer 108.
- the resist 203 is removed and heat treatment is performed.
- an interlayer film 156 is deposited, contacts 129, 130, 131, 132, 133, 134 are formed, and metals 141, 142, 143, 144, 145, 146 are formed.
- silicide may be formed on the third diffusion layer 119, the fifth diffusion layer 120, and the first diffusion layer 121. Further, silicide may be formed over the fourth diffusion layer 107, the sixth diffusion layer 108, and the second diffusion layer 109.
- the structure shown in FIG. 6 includes the method for forming the third diffusion layer 119 and the first diffusion layer 121 shown in FIG. 5 can be formed by combining the methods for forming the fourth diffusion layer 107 and the second diffusion layer 109 in FIG.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
6個のMOSトランジスタが基板上に配列されたスタティック型メモリセルを備えた半導体記憶装置であって、
前記6個のMOSトランジスタは、
メモリをアクセスするための第1及び第2のNMOSのアクセストランジスタと、メモリセルのデータを保持する記憶ノードを駆動するための第3及び第4のNMOSのドライバトランジスタと、メモリセルのデータを保持するための電荷を供給する第1及び第2のPMOSのロードトランジスタから構成され、
メモリをアクセスするための第1及び第2のNMOSのアクセストランジスタのそれぞれは、第1の拡散層、柱状半導体層及び第2の拡散層が、前記柱状半導体層が前記第1の拡散層と前記第2の拡散層の間に配置されよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
メモリセルのデータを保持するために記憶ノードを駆動する第3及び第4のNMOSのドライバトランジスタのそれぞれは、第3の拡散層、柱状半導体層及び第4の拡散層が、前記柱状半導体層が前記第3の拡散層と前記第4の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
メモリセルのデータを保持するために電荷を供給する第1及び第2のPMOSのロードトランジスタのそれぞれは、第5の拡散層、柱状半導体層及び第6の拡散層が、前記柱状半導体層が前記第5の拡散層と前記第6の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にゲートが形成されており、
前記第1の拡散層、第3の拡散層、第5の拡散層のそれぞれは、基板に対して電気的に絶縁して配置され、
前記第3及び第4のNMOSのドライバトランジスタを形成する第3の拡散層の上端と第4の拡散層の下端の間の長さは、第1及び第2のNMOSのアクセストランジスタを形成する第1の拡散層の上端と第2の拡散層の下端の間の長さより短いことを特徴とする。 A semiconductor memory device according to the present invention includes:
A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate,
The six MOS transistors are
First and second NMOS access transistors for accessing the memory, third and fourth NMOS driver transistors for driving the storage nodes holding the memory cell data, and holding the memory cell data The first and second PMOS load transistors for supplying electric charge to
Each of the first and second NMOS access transistors for accessing the memory includes a first diffusion layer, a columnar semiconductor layer, and a second diffusion layer, wherein the columnar semiconductor layer is the first diffusion layer and the first diffusion layer. The gates are formed on the side walls of the columnar semiconductor layers in a hierarchical manner in a direction perpendicular to the substrate so as to be disposed between the second diffusion layers,
Each of the third and fourth NMOS driver transistors that drive the storage node to hold data in the memory cell includes a third diffusion layer, a columnar semiconductor layer, and a fourth diffusion layer, and the columnar semiconductor layer includes Hierarchically arranged in a direction perpendicular to the substrate to be arranged between the third diffusion layer and the fourth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
Each of the first and second PMOS load transistors that supply charges to hold data in the memory cell includes a fifth diffusion layer, a columnar semiconductor layer, and a sixth diffusion layer, and the columnar semiconductor layer Hierarchically arranged in a direction perpendicular to the substrate so as to be arranged between the fifth diffusion layer and the sixth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
Each of the first diffusion layer, the third diffusion layer, and the fifth diffusion layer is disposed to be electrically insulated from the substrate,
The length between the upper end of the third diffusion layer that forms the third and fourth NMOS driver transistors and the lower end of the fourth diffusion layer is the same as the length that forms the first and second NMOS access transistors. It is shorter than the length between the upper end of one diffusion layer and the lower end of the second diffusion layer.
6個のMOSトランジスタが基板上に配列されたスタティック型メモリセルを備えた半導体記憶装置であって、
前記6個のMOSトランジスタは、
メモリにアクセスするための第1及び第2のNMOSのアクセストランジスタと、メモリセルのデータを保持するために記憶ノードを駆動する第3及び第4のNMOSのドライバトランジスタと、メモリセルのデータを保持するために電荷を供給する第1及び第2のPMOSのロードトランジスタから構成され、
メモリにアクセスするための第1及び第2のNMOSのアクセストランジスタのそれぞれは、第1の拡散層、柱状半導体層及び第2の拡散層が、前記柱状半導体層が前記第1の拡散層と前記第2の拡散層の間に配置されよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
メモリセルのデータを保持するために記憶ノードを駆動する第3及び第4のNMOSのドライバトランジスタのそれぞれは第3の拡散層、柱状半導体層及び第4の拡散層が、前記柱状半導体層が前記第3の拡散層と前記第4の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にゲートが形成されており、
前記第1の拡散層、第3の拡散層、第5の拡散層のそれぞれは、基板に対して電気的に絶縁して配置され、
メモリセルのデータを保持するために電荷を供給する第1及び第2のPMOSのロードトランジスタのそれぞれは、第5の拡散層、柱状半導体層及び第6の拡散層が、前記柱状半導体層が前記第5の拡散層と前記第6の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
前記第3及び第4のNMOSのドライバトランジスタを形成する第3の拡散層の上端と第4の拡散層の下端の間の長さは、第1及び第2のPMOSのロードトランジスタを形成する第5の拡散層の上端と第6の拡散層の下端の間の長さより短いことを特徴とする半導体装置。 The semiconductor memory device according to the present invention is
A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate,
The six MOS transistors are
First and second NMOS access transistors for accessing the memory, third and fourth NMOS driver transistors for driving the storage node to hold the memory cell data, and holding the memory cell data The first and second PMOS load transistors for supplying electric charge to
Each of the first and second NMOS access transistors for accessing the memory includes a first diffusion layer, a columnar semiconductor layer, and a second diffusion layer, wherein the columnar semiconductor layer includes the first diffusion layer and the first diffusion layer. The gates are formed on the side walls of the columnar semiconductor layers in a hierarchical manner in a direction perpendicular to the substrate so as to be disposed between the second diffusion layers,
Each of the third and fourth NMOS driver transistors that drive the storage node to hold data in the memory cell includes a third diffusion layer, a columnar semiconductor layer, and a fourth diffusion layer, and the columnar semiconductor layer includes the columnar semiconductor layer. Hierarchically arranged in a direction perpendicular to the substrate to be arranged between the third diffusion layer and the fourth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
Each of the first diffusion layer, the third diffusion layer, and the fifth diffusion layer is disposed to be electrically insulated from the substrate,
Each of the first and second PMOS load transistors that supply charges to hold data in the memory cell includes a fifth diffusion layer, a columnar semiconductor layer, and a sixth diffusion layer, and the columnar semiconductor layer includes the columnar semiconductor layer. Hierarchically arranged in a direction perpendicular to the substrate to be arranged between the fifth diffusion layer and the sixth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
The length between the upper end of the third diffusion layer that forms the third and fourth NMOS driver transistors and the lower end of the fourth diffusion layer is the same as the length that forms the first and second PMOS load transistors. 5. A semiconductor device characterized in that it is shorter than the length between the upper end of the fifth diffusion layer and the lower end of the sixth diffusion layer.
前記第3及び第4のNMOSのドライバトランジスタの第4の拡散層の下端は、前記第1及び第2のNMOSのアクセストランジスタの第2の拡散層の下端より低くすることもできる。 The upper ends of the third diffusion layers of the third and fourth NMOS driver transistors are higher than the upper ends of the first diffusion layers of the first and second NMOS access transistors,
The lower ends of the fourth diffusion layers of the third and fourth NMOS driver transistors may be lower than the lower ends of the second diffusion layers of the first and second NMOS access transistors.
前記第3及び第4のNMOSのドライバトランジスタそれぞれの第4の拡散層を形成するためのイオン注入のエネルギー量を、前記第1及び第2のNMOSのアクセストランジスタそれぞれの第2の拡散層を形成するためのイオン注入のエネルギー量より高くすることができる。 The fourth diffusion layer of the third and fourth NMOS driver transistors and the second diffusion layer of each of the first and second NMOS access transistors are formed by ion implantation,
The amount of ion implantation energy for forming the fourth diffusion layer of each of the third and fourth NMOS driver transistors is formed, and the second diffusion layer of each of the first and second NMOS access transistors is formed. The amount of energy for ion implantation can be higher.
Claims (11)
- 6個のMOSトランジスタが基板上に配列されたスタティック型メモリセルを備えた半導体記憶装置であって、
前記6個のMOSトランジスタは、
メモリをアクセスするための第1及び第2のNMOSのアクセストランジスタと、メモリセルのデータを保持する記憶ノードを駆動するための第3及び第4のNMOSのドライバトランジスタと、メモリセルのデータを保持するための電荷を供給する第1及び第2のPMOSのロードトランジスタから構成され、
メモリをアクセスするための第1及び第2のNMOSのアクセストランジスタのそれぞれは、第1の拡散層、柱状半導体層及び第2の拡散層が、前記柱状半導体層が前記第1の拡散層と前記第2の拡散層の間に配置されよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
メモリセルのデータを保持するために記憶ノードを駆動する第3及び第4のNMOSのドライバトランジスタのそれぞれは、第3の拡散層、柱状半導体層及び第4の拡散層が、前記柱状半導体層が前記第3の拡散層と前記第4の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
メモリセルのデータを保持するために電荷を供給する第1及び第2のPMOSのロードトランジスタのそれぞれは、第5の拡散層、柱状半導体層及び第6の拡散層が、前記柱状半導体層が前記第5の拡散層と前記第6の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にゲートが形成されており、
前記第1の拡散層、第3の拡散層、第5の拡散層のそれぞれは、基板に対して電気的に絶縁して配置され、
前記第3及び第4のNMOSのドライバトランジスタを形成する第3の拡散層の上端と第4の拡散層の下端の間の長さは、第1及び第2のNMOSのアクセストランジスタを形成する第1の拡散層の上端と第2の拡散層の下端の間の長さより短いことを特徴とする半導体装置。 A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate,
The six MOS transistors are
First and second NMOS access transistors for accessing the memory, third and fourth NMOS driver transistors for driving the storage nodes holding the memory cell data, and holding the memory cell data The first and second PMOS load transistors for supplying electric charge to
Each of the first and second NMOS access transistors for accessing the memory includes a first diffusion layer, a columnar semiconductor layer, and a second diffusion layer, wherein the columnar semiconductor layer includes the first diffusion layer and the first diffusion layer. The gates are formed on the side walls of the columnar semiconductor layers in a hierarchical manner in a direction perpendicular to the substrate so as to be disposed between the second diffusion layers,
Each of the third and fourth NMOS driver transistors that drive the storage node to hold data in the memory cell includes a third diffusion layer, a columnar semiconductor layer, and a fourth diffusion layer, and the columnar semiconductor layer includes Hierarchically arranged in a direction perpendicular to the substrate to be arranged between the third diffusion layer and the fourth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
Each of the first and second PMOS load transistors that supply charges to hold data in the memory cell includes a fifth diffusion layer, a columnar semiconductor layer, and a sixth diffusion layer, and the columnar semiconductor layer includes the columnar semiconductor layer. Hierarchically arranged in a direction perpendicular to the substrate so as to be arranged between the fifth diffusion layer and the sixth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
Each of the first diffusion layer, the third diffusion layer, and the fifth diffusion layer is disposed to be electrically insulated from the substrate,
The length between the upper end of the third diffusion layer that forms the third and fourth NMOS driver transistors and the lower end of the fourth diffusion layer is the same as the length that forms the first and second NMOS access transistors. A semiconductor device, characterized by being shorter than the length between the upper end of one diffusion layer and the lower end of a second diffusion layer. - 6個のMOSトランジスタが基板上に配列されたスタティック型メモリセルを備えた半導体記憶装置であって、
前記6個のMOSトランジスタは、
メモリにアクセスするための第1及び第2のNMOSのアクセストランジスタと、メモリセルのデータを保持するために記憶ノードを駆動する第3及び第4のNMOSのドライバトランジスタと、メモリセルのデータを保持するために電荷を供給する第1及び第2のPMOSのロードトランジスタから構成され、
メモリにアクセスするための第1及び第2のNMOSのアクセストランジスタのそれぞれは、第1の拡散層、柱状半導体層及び第2の拡散層が、前記柱状半導体層が前記第1の拡散層と前記第2の拡散層の間に配置されよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
メモリセルのデータを保持するために記憶ノードを駆動する第3及び第4のNMOSのドライバトランジスタのそれぞれは第3の拡散層、柱状半導体層及び第4の拡散層が、前記柱状半導体層が前記第3の拡散層と前記第4の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にゲートが形成されており、
前記第1の拡散層、第3の拡散層、第5の拡散層のそれぞれは、基板に対して電気的に絶縁して配置され、
メモリセルのデータを保持するために電荷を供給する第1及び第2のPMOSのロードトランジスタのそれぞれは、第5の拡散層、柱状半導体層及び第6の拡散層が、前記柱状半導体層が前記第5の拡散層と前記第6の拡散層の間に配置されるよう基板に垂直な方向に階層的に配置され、かつ、前記柱状半導体層の側壁にはゲートが形成されており、
前記第3及び第4のNMOSのドライバトランジスタを形成する第3の拡散層の上端と第4の拡散層の下端の間の長さは、第1及び第2のPMOSのロードトランジスタを形成する第5の拡散層の上端と第6の拡散層の下端の間の長さより短いことを特徴とする半導体装置。 A semiconductor memory device having a static memory cell in which six MOS transistors are arranged on a substrate,
The six MOS transistors are
First and second NMOS access transistors for accessing the memory, third and fourth NMOS driver transistors for driving the storage node to hold the memory cell data, and holding the memory cell data The first and second PMOS load transistors for supplying electric charge to
Each of the first and second NMOS access transistors for accessing the memory includes a first diffusion layer, a columnar semiconductor layer, and a second diffusion layer, wherein the columnar semiconductor layer includes the first diffusion layer and the first diffusion layer. The gates are formed on the side walls of the columnar semiconductor layers in a hierarchical manner in a direction perpendicular to the substrate so as to be disposed between the second diffusion layers,
Each of the third and fourth NMOS driver transistors that drive the storage node to hold the data of the memory cell includes a third diffusion layer, a columnar semiconductor layer, and a fourth diffusion layer, and the columnar semiconductor layer includes the columnar semiconductor layer. Hierarchically arranged in a direction perpendicular to the substrate to be arranged between the third diffusion layer and the fourth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
Each of the first diffusion layer, the third diffusion layer, and the fifth diffusion layer is disposed to be electrically insulated from the substrate,
Each of the first and second PMOS load transistors that supply charges to hold data in the memory cell includes a fifth diffusion layer, a columnar semiconductor layer, and a sixth diffusion layer, and the columnar semiconductor layer includes the columnar semiconductor layer. Hierarchically arranged in a direction perpendicular to the substrate to be arranged between the fifth diffusion layer and the sixth diffusion layer, and a gate is formed on a side wall of the columnar semiconductor layer,
The length between the upper end of the third diffusion layer that forms the third and fourth NMOS driver transistors and the lower end of the fourth diffusion layer is the same as the length that forms the first and second PMOS load transistors. 5. A semiconductor device characterized in that it is shorter than the length between the upper end of the fifth diffusion layer and the lower end of the sixth diffusion layer. - 前記第1及び第2のNMOSのアクセストランジスタを形成する第1の拡散層の上端と第2の拡散層の下端の間の長さは、第3及び第4のNMOSのドライバトランジスタを形成する第3の拡散層の上端と第4の拡散層の下端の間の長さの1.3倍から3倍の範囲であることを特徴とする請求項1に記載の半導体装置。 The length between the upper end of the first diffusion layer that forms the first and second NMOS access transistors and the lower end of the second diffusion layer is the same as the length that forms the third and fourth NMOS driver transistors. 2. The semiconductor device according to claim 1, wherein the length is between 1.3 times and 3 times the length between the upper end of the third diffusion layer and the lower end of the fourth diffusion layer.
- 第1及び第2のPMOSのロードトランジスタを形成する第5の拡散層の上端と第6の拡散層の下端の間の長さは、第3及び第4のNMOSのドライバトランジスタを形成する第3の拡散層の上端と第4の拡散層の下端の間の長さの1.3倍から3倍の範囲であることを特徴とする請求項2に記載の半導体装置。 The length between the upper end of the fifth diffusion layer that forms the first and second PMOS load transistors and the lower end of the sixth diffusion layer is the third length that forms the third and fourth NMOS driver transistors. 3. The semiconductor device according to claim 2, wherein the length is 1.3 to 3 times the length between the upper end of the diffusion layer and the lower end of the fourth diffusion layer.
- 前記ゲートの下端から上端までの長さが同じであることを特徴とする請求項1に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the length from the lower end to the upper end of the gate is the same.
- 前記第3及び第4のNMOSのドライバトランジスタの第3の拡散層の上端は、前記第1及び第2のNMOSのアクセストランジスタの第1の拡散層の上端より高いことを特徴とする請求項5に記載の半導体装置。 6. The upper ends of the third diffusion layers of the third and fourth NMOS driver transistors are higher than the upper ends of the first diffusion layers of the first and second NMOS access transistors. A semiconductor device according to 1.
- 前記第3及び第4のNMOSのドライバトランジスタの第4の拡散層の下端は、前記第1及び第2のNMOSのアクセストランジスタの第2の拡散層の下端より低いことを特徴とする請求項5に記載の半導体装置。 6. The lower end of the fourth diffusion layer of the third and fourth NMOS driver transistors is lower than the lower end of the second diffusion layer of the first and second NMOS access transistors. A semiconductor device according to 1.
- 前記第3及び第4のNMOSのドライバトランジスタの第3の拡散層の上端は、前記第1及び第2のNMOSのアクセストランジスタの第1の拡散層の上端より高く、
前記第3及び第4のNMOSのドライバトランジスタの第4の拡散層の下端は、前記第1及び第2のNMOSのアクセストランジスタの第2の拡散層の下端より低いことを特徴とする請求項5に記載の半導体装置。 The upper ends of the third diffusion layers of the third and fourth NMOS driver transistors are higher than the upper ends of the first diffusion layers of the first and second NMOS access transistors,
6. The lower end of the fourth diffusion layer of the third and fourth NMOS driver transistors is lower than the lower end of the second diffusion layer of the first and second NMOS access transistors. A semiconductor device according to 1. - 前記第3及び第4のNMOSのドライバトランジスタそれぞれの第3の拡散層を形成した後に、前記第1及び第2のNMOSのアクセストランジスタそれぞれの第1の拡散層を形成したことを特徴とする請求項6に記載の半導体装置。 The first diffusion layer of each of the first and second NMOS access transistors is formed after the third diffusion layer of each of the third and fourth NMOS driver transistors is formed. Item 7. The semiconductor device according to Item 6.
- 前記第3及び第4のNMOSのドライバトランジスタの第4の拡散層と、前記第1及び第2のNMOSのアクセストランジスタそれぞれの第2の拡散層は、イオン注入によって形成され、
前記第3及び第4のNMOSのドライバトランジスタそれぞれの第4の拡散層を形成するためのイオン注入のエネルギー量は、前記第1及び第2のNMOSのアクセストランジスタそれぞれの第2の拡散層を形成するためのイオン注入のエネルギー量より高いことを特徴とする請求項7に記載の半導体装置。 The fourth diffusion layer of the third and fourth NMOS driver transistors and the second diffusion layer of each of the first and second NMOS access transistors are formed by ion implantation,
The amount of ion implantation energy for forming the fourth diffusion layer of each of the third and fourth NMOS driver transistors forms the second diffusion layer of each of the first and second NMOS access transistors. The semiconductor device according to claim 7, wherein the energy amount is higher than an ion implantation energy amount. - 前記第3及び第4のNMOSのドライバトランジスタの第4の拡散層にリンが含まれることを特徴とする請求項7に記載の半導体装置。 8. The semiconductor device according to claim 7, wherein phosphorus is contained in the fourth diffusion layer of the third and fourth NMOS driver transistors.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010800555749A CN102714181A (en) | 2010-12-07 | 2010-12-07 | Semiconductor device |
KR1020127014703A KR20130020761A (en) | 2010-12-07 | 2010-12-07 | Semiconductor device |
PCT/JP2010/071885 WO2012077178A1 (en) | 2010-12-07 | 2010-12-07 | Semiconductor device |
JP2012526557A JP5432379B2 (en) | 2010-12-07 | 2010-12-07 | Semiconductor device |
TW100142865A TW201230304A (en) | 2010-12-07 | 2011-11-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2010/071885 WO2012077178A1 (en) | 2010-12-07 | 2010-12-07 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012077178A1 true WO2012077178A1 (en) | 2012-06-14 |
Family
ID=46206700
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/071885 WO2012077178A1 (en) | 2010-12-07 | 2010-12-07 | Semiconductor device |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP5432379B2 (en) |
KR (1) | KR20130020761A (en) |
CN (1) | CN102714181A (en) |
TW (1) | TW201230304A (en) |
WO (1) | WO2012077178A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015019444A1 (en) * | 2013-08-07 | 2015-02-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device manufacturing method and semiconductor device |
JP2017183759A (en) * | 2017-07-05 | 2017-10-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Method for manufacturing semiconductor device, and semiconductor device |
WO2019087328A1 (en) * | 2017-11-01 | 2019-05-09 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Columnar semiconductor device and method for manufacturing same |
JP2020521319A (en) * | 2017-05-23 | 2020-07-16 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | Very long channel device in VFET architecture |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08148582A (en) * | 1994-11-21 | 1996-06-07 | Sanyo Electric Co Ltd | Semiconductor memory cell and its manufacturing method |
JP2002237529A (en) * | 2001-02-07 | 2002-08-23 | Seiko Epson Corp | Semiconductor device, memory system and electronic apparatus |
WO2009095998A1 (en) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor storage device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4855786B2 (en) * | 2006-01-25 | 2012-01-18 | 株式会社東芝 | Semiconductor device |
US8378425B2 (en) * | 2008-01-29 | 2013-02-19 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor storage device |
-
2010
- 2010-12-07 CN CN2010800555749A patent/CN102714181A/en active Pending
- 2010-12-07 KR KR1020127014703A patent/KR20130020761A/en not_active Application Discontinuation
- 2010-12-07 JP JP2012526557A patent/JP5432379B2/en active Active
- 2010-12-07 WO PCT/JP2010/071885 patent/WO2012077178A1/en active Application Filing
-
2011
- 2011-11-23 TW TW100142865A patent/TW201230304A/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08148582A (en) * | 1994-11-21 | 1996-06-07 | Sanyo Electric Co Ltd | Semiconductor memory cell and its manufacturing method |
JP2002237529A (en) * | 2001-02-07 | 2002-08-23 | Seiko Epson Corp | Semiconductor device, memory system and electronic apparatus |
WO2009095998A1 (en) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor storage device |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015019444A1 (en) * | 2013-08-07 | 2015-02-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Semiconductor device manufacturing method and semiconductor device |
JP5759077B1 (en) * | 2013-08-07 | 2015-08-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Semiconductor device manufacturing method and semiconductor device |
US9520473B2 (en) | 2013-08-07 | 2016-12-13 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device |
US9640637B2 (en) | 2013-08-07 | 2017-05-02 | Unisantis Electronics Signapore Pte. Ltd. | Method for producing semiconductor device |
US9876087B2 (en) | 2013-08-07 | 2018-01-23 | Unisantis Electronics Singapore Pte. Ltd. | Surround gate transistor device and contact structure for same |
JP2020521319A (en) * | 2017-05-23 | 2020-07-16 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | Very long channel device in VFET architecture |
JP7018963B2 (en) | 2017-05-23 | 2022-02-14 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Ultra-long channel device in VFET architecture |
JP2017183759A (en) * | 2017-07-05 | 2017-10-05 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Method for manufacturing semiconductor device, and semiconductor device |
WO2019087328A1 (en) * | 2017-11-01 | 2019-05-09 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Columnar semiconductor device and method for manufacturing same |
JPWO2019087328A1 (en) * | 2017-11-01 | 2019-11-14 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Columnar semiconductor device and manufacturing method thereof |
US10825822B2 (en) | 2017-11-01 | 2020-11-03 | Unisantis Electronics Singapore Pte. Ltd. | Pillar-shaped semiconductor device and method for producing the same |
Also Published As
Publication number | Publication date |
---|---|
TW201230304A (en) | 2012-07-16 |
KR20130020761A (en) | 2013-02-28 |
JPWO2012077178A1 (en) | 2014-05-19 |
CN102714181A (en) | 2012-10-03 |
JP5432379B2 (en) | 2014-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20150132903A1 (en) | Structure and Method For SRAM Cell Circuit | |
JP2004214379A (en) | Semiconductor device, method for manufacturing the same dynamic type semiconductor storage device, | |
JP2002329798A (en) | Semiconductor device | |
KR101812036B1 (en) | Semiconductor device including metal silicide layer and fabrication method thereof | |
JP2006278674A (en) | Field effect transistor and its manufacturing method, and semiconductor device | |
US20170077105A1 (en) | Semiconductor device | |
US20070057303A1 (en) | Method For Forming Trench Capacitor and Memory Cell | |
US7244977B2 (en) | Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device | |
JP5432379B2 (en) | Semiconductor device | |
US8530960B2 (en) | Semiconductor device | |
US8513717B2 (en) | Semiconductor device and method for manufacturing the same | |
US7776659B2 (en) | Semiconductor device manufacturing method | |
JP5861196B2 (en) | Semiconductor device | |
JPH11284146A (en) | Semiconductor storage device and its manufacture | |
JP2008071861A (en) | Semiconductor memory and manufacturing method thereof | |
JP5426032B2 (en) | Semiconductor device and manufacturing method thereof | |
JP5725679B2 (en) | Semiconductor device | |
JP2005236135A (en) | Method for manufacturing semiconductor device | |
US7977723B2 (en) | Semiconductor device | |
TWI803217B (en) | Memory device having word lines with reduced leakage | |
JP2011071173A (en) | Semiconductor device, method of manufacturing the same, and method of controlling semiconductor device | |
KR20050024099A (en) | method of fabricating SRAM device and SRAM device fabricated thereby | |
JP4757317B2 (en) | Manufacturing method of semiconductor integrated circuit device | |
CN110707086A (en) | Semiconductor device with a plurality of semiconductor chips | |
US20150371992A1 (en) | Semiconductor device and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080055574.9 Country of ref document: CN |
|
ENP | Entry into the national phase |
Ref document number: 20127014703 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012526557 Country of ref document: JP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10860579 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 10860579 Country of ref document: EP Kind code of ref document: A1 |