JPH08148582A - Semiconductor memory cell and its manufacturing method - Google Patents

Abstract

PURPOSE: To stabilize the operation of the memory cell of an SRAM and to miniaturize the memory cell. CONSTITUTION: MOS transistors Qt1 and Qt2 for transfer are formed by a normal LDD transistor but MOS transistors Qd1 and Qd2 for drive are formed by an LDD transistor with a large gate overlapping. The gate overlapping indicates that a low-concentration source/drain region and a gate electrode overlap. However, the amount of overlap matters. The overlapping of the MOS transistors Qd1 and Qd2 for drive is larger than that of the MOS transistors Qt1 and Qt2 for transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell and a manufacturing method thereof, and more particularly to a semiconductor memory cell which stabilizes the operation of an SRAM memory cell and enables miniaturization, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional SRAM memory cell is a generally known high resistance load type memory cell shown in FIGS. This is a flip-flop circuit in which two inverter circuits are connected to each other for feedback, and a pair of cross-connected driving MOS transistors Qd1 and Qd are provided.
One bit is composed of d2, the transfer MOS transistors Qt1 and Qt2, and the load high resistances R1 and R2.
The operation of this cell is described below.

For example, in a memory cell selected by the address decoder circuit, a memory cell to which data is input from the bit lines DL and * DL is shown in FIG.
Through the transfer MOS transistor Qt1 on the left side, enters the gate of the drive MOS transistor Qd1 on the right side, is inverted by the inverter on the right side and appears in the drain, and at the same time joins the gate of the drive MOS transistor Qd2 on the left side.
It is amplified and inverted by the left inverter, added to the drain of the driving MOS transistor Qd1, and stored and held. The stored information is used as the driving MOS transistors Qd1 and Q.
It is held by the minute currents of the load high resistances R1 and R2 connected to the drain of d2.

On the other hand, for reading, a voltage is applied to the gates of the transfer MOS transistors Qt1 and Qt2 by a common word line WL, and the difference in drain potential between the drive MOS transistors Qd1 and Qd2 is read. The semiconductor memory cell is
JP-A-4-127470 (H01L 27/1
1) etc. By the way, in order to stabilize the operation of the memory cell, the driving MOS transistor Qd
It is necessary to increase the β ratio of 1 and Qd2 to the transfer MOS transistors Qt1 and Qt2. Therefore, conventionally, the β ratio has been secured by making the respective transistor sizes different in design. For example, the size (gate width / gate length) of the transfer MOS transistors Qt1 and Qt2 is 0.8 / 1.5, and the drive MOS transistors Qd1 and
Qd2 was set to 2.0 / 0.8.

The above β is β = μCoxWeff / Leff
Is a carrier mobility, Cox is a gate oxide film capacitance, Weff is an effective channel width, and Leff is an effective channel length.

[0006]

However, there is a limit in securing the β ratio depending on the transistor size because of the restriction that the memory cell is miniaturized. Therefore, a sufficient β ratio could not be obtained, and the cell operation was unstable. The present invention aims to eliminate such problems.

[0007]

In order to solve the above-mentioned problems, a semiconductor memory cell of the present invention comprises a pair of cross-connected driving MOS transistors and a pair of transfer MOS transistors.
What is claimed is: 1. A semiconductor memory cell comprising a transistor and a pair of load elements, wherein the driving MOS transistor gate and the transfer MOS transistor gate extend at right angles. The gate overlap of the driving MOS transistor is formed larger than that of the transfer MOS transistor.

The semiconductor memory cell manufacturing method according to the present invention is a semiconductor memory cell comprising a pair of cross-connected driving MOS transistors, a pair of transfer MOS transistors, and a pair of load elements. MOS
In a method of manufacturing a semiconductor memory cell in which a gate extension direction of a transistor and a gate extension direction of a transfer MOS transistor are arranged at a right angle, a drive MOS is provided.
In the ion implantation step of forming the low-concentration source / drain regions of the transistor and the transfer MOS transistor, two oblique ion implantations are performed left and right from a direction perpendicular to the extending direction of the gate of the driving MOS transistor. The gate overlap of the driving MOS transistor is formed larger than that of the transfer MOS transistor.

[0009]

According to the semiconductor memory cell of the present invention, the driving M
In the OS transistor, since the gate overlap is large, the effective channel length is reduced by that amount, and the resistance of the low concentration source / drain region in the overlap portion is lowered by the gate electric field. It is possible to obtain a high β, and as a result, it is possible to realize a higher β ratio than before while keeping the size of the designed transistor constant.

Further, according to the manufacturing of the semiconductor memory cell of the present invention, since the respective gate electrode layers are arranged so that their extending directions are at right angles, the low concentration source / drain regions are formed. In the ion implantation process, oblique ion implantation is performed twice right and left from the direction perpendicular to the extending direction of the gate of the driving MOS transistor, so that the driving MOS transistor can be formed as shown in FIGS. The shadowing effect due to the oblique ion implantation appears, and the gate overlap of the driving MOS transistor is formed larger than the gate overlap of the transfer MOS transistor.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory cell and a method of manufacturing the same according to one embodiment of the present invention will be described below with reference to the drawings.
The circuit configuration itself of the semiconductor memory cell according to this embodiment is as shown in FIG. 4 and is not different from the conventional one.
A feature of the present invention is that the transfer MOS transistor Q
This is because the structures of t1 and Qt2 are different from those of the driving MOS transistors Qd1 and Qd2. That is, as shown in FIG. 3, the transfer MOS transistors Qt1 and Qt2 have the normal L level.
Although it is formed of a DD transistor, the driving MOS transistors Qd1 and Qd2 are formed of LDD transistors having a large gate overlap. The gate overlap means that the low-concentration source / drain regions and the gate electrode overlap each other. However, in the present invention, the difference in the degree of overlap is a problem, and the driving MOS transistor Q
The d1 and Qd2 are characterized in that they have a larger overlap than the transfer MOS transistors Qt1 and Qt2.

Therefore, the driving MOS transistor Q
In d1 and Qd2, the effective channel length is reduced by the difference in gate overlap, and the resistance of the low-concentration source / drain regions in the overlap portion is lowered by the gate electric field. Therefore, compared to the transfer MOS transistors Qt1 and Qt2. It is possible to obtain a high β, and as a result, it is possible to realize a higher β ratio than before while keeping the size of the designed transistor constant.

Next, a method of manufacturing the above semiconductor memory cell will be described with reference to FIGS. 1 to 3
4 is a perspective view of the left side portion of FIG. 4, showing a portion where a transfer MOS transistor Qt1 and a drive MOS transistor Qd1 are formed. In FIG. 1, L for separating the transfer MOS transistor Qt1 formation region and the drive MOS transistor Qd1 formation region on the P-type silicon substrate (1).
The OCOS oxide film (2) is formed, and the gate electrode layers (4A) and (4B) are formed of polysilicon layers with the gate oxide film (3) interposed therebetween. Here, the two gate electrode layers (4A) and (4B) are arranged so that the extending directions thereof are at right angles. Then, from the direction perpendicular to the extending direction of the gate electrode layer (4B) of the driving MOS transistor (from the left side in FIG. 1), the first oblique ion implantation is performed, and the low-concentration source of the transfer MOS transistor Qt1 Drain regions (5A) (6A) and driving MOS transistor Qd1
Forming low concentration source / drain regions (5B) and (6B). Here, the oblique ion implantation is performed on the silicon substrate (1).
Inclined by an angle θ from the vertical direction of the plane, phosphorus ion (31P
+) Is injected under the conditions of an injection amount of 2E12 / cm2 and an acceleration voltage of 50 KeV.

According to the above-mentioned oblique ion implantation, since the respective gate electrode layers (4A) and (4B) are arranged so that their extending directions are at right angles, the driving MOS is formed.
The shadowing effect appears only for the transistor Qd1. That is, since the lightly doped source / drain regions (5A) and (6A) of the transfer MOS transistor Qt1 have no shadowing effect, they are formed symmetrically with respect to the gate electrode layer (4A), but the drive MOS transistor Qd1. The low-concentration source / drain regions (5B) and (6B) are asymmetric due to the shadowing effect of the gate electrode layer (4B), and the overlap between the source region (5B) and the gate electrode layer (4B) is large. Meanwhile, the drain region (6B) is offset from the gate electrode layer (4B).

Next, in FIG. 2, the second oblique ion implantation is performed from the direction perpendicular to the extending direction of the gate electrode layer (4B) of the driving MOS transistor (from the right side in FIG. 2). The implantation amount of this ion implantation is the same as that of the first implantation, and the only difference is that the implantation direction is the opposite direction. As a result, the low-concentration source / drain regions (51A) (61A) of the transfer MOS transistor Qt1 and the low-concentration source / drain regions (51B) (61B) of the drive MOS transistor Qd1 are both symmetrical, and the drive MOS The transistor Qd1 has a larger overlap than the transfer MOS transistor Qt1. Qd2
And Qt2 are exactly the same.

Therefore, the driving MOS transistor Q
The effective channel length Leff2 with respect to d1 and Qd2 is smaller than the effective channel length Leff1 with respect to the transfer MOS transistors Qt1 and Qt2 by the difference in gate overlap, and the resistance of the low concentration source / drain region in the overlap portion is the gate electric field. Therefore, a higher β can be obtained as compared with the transfer MOS transistors Qt1 and Qt2, and as a result, a higher β ratio than the conventional one can be realized while keeping the designed transistor size constant.

Then, in FIG. 3, the gate electrode layer (4
A) Spacer film (9A) made of SiO2 on the side wall of (4B)
(9B) is formed, and arsenic ion (75As +) is injected at 5E
Ion implantation is performed under the conditions of 15 / cm2 and an acceleration voltage of 50 KeV, and the high-concentration source / drain regions (10A) (11A) of the transfer MOS transistor Qt1 and the high-concentration source / drain regions (10B) of the driving MOS transistor Qd1.
(11B) are formed.

[0018]

As described above, according to the semiconductor memory cell of the present invention, since the driving MOS transistor has a larger gate overlap than the transfer MOS transistor, the effective channel length is correspondingly smaller. In addition, since the resistance of the low concentration source / drain regions in the overlap portion is lowered by the gate electric field, β higher than that of the transfer MOS transistor can be obtained, and as a result, the size of the designed transistor is constant. It is possible to realize a higher β ratio than before. This makes it possible to stabilize the operation of the memory cell and realize miniaturization.

Further, according to the method of manufacturing a semiconductor memory cell of the present invention, since the respective gate electrode layers are arranged so that their extending directions are at right angles, a low concentration source / drain region is formed. In the ion implantation step, the oblique implantation of ions is performed twice right and left from the direction perpendicular to the direction in which the gate of the driving MOS transistor extends, as shown in FIGS. The shadowing effect due to the oblique ion implantation appears only in the case of, and the gate overlap of the drive MOS transistor is formed larger than that of the transfer MOS transistor. Therefore, there is an advantage that a β ratio higher than the conventional one can be easily realized only by performing the ion implantation process twice.

[Brief description of drawings]

FIG. 1 is a first perspective view illustrating a semiconductor memory cell and a method of manufacturing the same according to an exemplary embodiment of the present invention.

FIG. 2 is a second perspective view illustrating the method for manufacturing the semiconductor memory cell according to the embodiment of the present invention.

FIG. 3 is a third perspective view illustrating a semiconductor memory cell and a method of manufacturing the same according to an exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an SRAM memory cell.

FIG. 5 is a plan view illustrating an SRAM memory cell.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 27/088

Claims (2)

[Claims] 1. A semiconductor memory cell comprising a pair of cross-connected drive MOS transistors, a pair of transfer MOS transistors, and a pair of load elements, wherein the gate extending direction of the drive MOS transistor and the transfer direction. For MO
In a semiconductor memory cell arranged such that the extending direction of the gate of the S transistor is at a right angle, the gate overlap of the driving MOS transistor is formed larger than the gate overlap of the transfer MOS transistor. cell. 2. A semiconductor memory cell comprising a pair of cross-connected drive MOS transistors, a pair of transfer MOS transistors, and a pair of load elements, wherein the gate extending direction of the drive MOS transistor and the transfer direction. For MO
In a method of manufacturing a semiconductor memory cell arranged so that the extending direction of the gate of an S transistor is at a right angle, driving is performed in an ion implantation step of forming low-concentration source / drain regions of a driving MOS transistor and a transfer MOS transistor. The gate overlap of the drive MOS transistor is made larger than that of the transfer MOS transistor by performing oblique ion implantation twice right and left from a direction perpendicular to the extending direction of the gate of the use MOS transistor. A method for manufacturing a semiconductor memory cell characterized by the above.