JP3223531B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a method for arranging memory cells.

[0002]

2. Description of the Related Art Generally, when an impurity region is formed on a silicon substrate having a crystal orientation of (100) by ion implantation, for example, the impurity region is not perpendicular to the silicon substrate in order to suppress a problem due to a tunneling effect. Ion implantation is performed with an angle offset. FIG. 6 is a diagram showing a cross-sectional structure of a MOS transistor arranged such that the channel direction is parallel to the direction in which the above-described angular offset occurs. FIG. 6 shows an LDD (Lig)
An N-channel transistor having an (htly-Doped-Drain) structure, the regions 8 and 9 having a low N-type impurity concentration are ion-implanted using the gate electrode 1 made of, for example, polysilicon as a mask, and then the sidewalls 2 and 3 are formed. Then, N type high concentration impurity regions 10 and 11 are implanted. Here, the source electrode or the drain electrode of the MOS transistor is extracted from the impurity region 10 or 11, respectively. Since these ion implantations are not performed perpendicular to the channel, the thin impurity region 8 is shifted from the left end of the gate electrode 1 toward the high-concentration impurity region 10, and the gate electrode and the N-type impurity region do not overlap at the left end of the channel. An offset area 12 occurs. FIG. 7 shows an equivalent circuit when the N-channel transistor of FIG. 6 uses the high-concentration impurity region 10 as a source electrode. As shown in FIG. 7, the offset region 12 becomes a parasitic resistance, and is connected in cascade between the source electrode S2 of the ideal transistor and the source electrode ST2 extracted from the high-concentration impurity region 10.

FIG. 5 is a layout diagram of a memory cell of a conventional semiconductor memory device, and is an example of a memory cell of a static random access memory (SRAM). FIG.
In the figure, only the field layer and the polysilicon layer excluding the contact layer, the metal wiring layer, and the like are shown, and the transistor T1
T2 is a transfer transistor for data access, and transistors T3 and T4 are driver transistors for driving. Here, the ion implantation is performed by tilting from the direction indicated by the arrow in FIG.

FIG. 8 is an equivalent circuit of the memory cell shown in FIG. 5, and includes bit line load transistors T5 and T5.
6 and a bit line pair BL, BLB. In FIG. 8, parasitic resistances such as polysilicon resistance, diffusion resistance, and contact resistance are omitted. In the memory cell layout of FIG. 5, since the channel direction of the transistors T3 and T4 is also parallel to the ion implantation direction indicated by the arrow in FIG. The resulting parasitic resistances RL3 and RL4 are respectively connected.

[0005]

Since the conventional semiconductor device is configured as described above, it has the following problems. In the memory cell equivalent circuit of FIG. 8, one storage node N1 has a High level and the other storage node N2 has a high level.
When the reading operation is performed in a state where the low level is stored in the memory cell, the driver transistor T4 conducts, so that a through current flows from the power supply line to the ground line via the bit line load transistor T6, the transfer transistor T2, and the driver transistor T4. This causes a voltage drop in the parasitic resistance RL4. Therefore, the effective gate-source voltage of the conductive driver transistor T4 is N
The potential difference between 1 and S4 decreases by the voltage drop of the parasitic resistance RL4. Generally, the absolute value of the difference between the gate-source voltage of one of the conducting driver transistors and the gate-source voltage of the other non-conducting driver transistor, that is, the difference between the potential difference between N1 and S4 and the potential difference between N2 and S3 is stored in the memory. This is an index indicating the operation stability of the cell. The larger the value, the higher the stability of the memory cell. For example, when the power supply voltage is 4 V, the through current is 100 microamps, and R
Since L4 is about 1 kΩ, the transistor T4
The gate-source voltage of the transistor decreases by 0.1V. At this time, the potential of the storage node N1 is about 2 V, and the difference between the gate-source voltage of the driver transistor pair is 7%.
10%. That is, the configuration of the conventional memory cell has a problem that the potential difference between N1 and S4 is reduced by the parasitic resistance RL4, and the operation stability of the memory cell is deteriorated.

Contrary to the above description, when a read operation is performed in a state where a low level is stored in N1 and a high level is stored in N2, the driver transistor T3 is turned on, and the load transistor T5 and the transfer transistor T1 are turned on. In addition, a through current flows from the power supply line to the ground line via the driver transistor T3. At this time, the source potential of the driver transistor T3 is constant, and
Since the driver transistor T4 becomes non-conductive, RL4
No voltage drop occurs, the difference between the gate-source voltages of the driver transistor pair does not change, and the operation stability does not deteriorate. Therefore, in the configuration of the conventional memory cell, there is a difference in stability depending on information stored in the memory cell.
That is, there was also a problem of being asymmetric.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device having a memory cell having high stability and symmetry.

[0008]

A semiconductor memory device according to the present invention includes a driver transistor and a transfer transistor each having an impurity region formed by oblique ion implantation, and the driver transistor and the transfer transistor have a channel length of each other. A semiconductor device formed so that directions are orthogonal to each other,
The driver transistor is arranged so that its channel length direction is orthogonal to the direction in which the angle offset occurs at the time of the oblique ion implantation, and the transfer transistor has its channel length direction of the angle offset at the time of the oblique ion implantation. It is characterized by being arranged so as to be parallel to the direction in which it occurs.

[0009]

In the semiconductor memory device of the present invention, the parasitic resistance in the memory cell due to the ion implantation angle becomes symmetrical in circuit.

[0010]

FIG. 1 shows an example of an embodiment according to the present invention.
FIG. 3 is a layout diagram of a memory cell of a RAM. In FIG. 1, the memory cell layout includes only the field layer and the polysilicon layer excluding the contact layer, the metal wiring layer, and the like.
The transistors T1 and T2 are transfer transistors for data access, and the transistors T3 and T4 are driver transistors for driving. Here, the ion implantation is performed while being inclined from the direction indicated by the arrow in FIG.
In the embodiment shown in FIG. 1, the layout of the conventional example shown in FIG. 5 is arranged by rotating 90 degrees clockwise without changing the ion implantation angle.

FIG. 2 shows the driver transistor T in FIG.
It is a figure which shows the cross-section of 3 or T4. Since the driver transistor of the memory cell in the semiconductor memory device of the present invention is arranged so that the channel direction is perpendicular to the direction in which the above-mentioned angular offset occurs, the edges of the regions 8 and 9 where the N-type impurity concentration is low are the gate electrodes 1. Is almost coincident with the edge of the channel, and the offset region at the channel end as shown in FIG. 6 does not occur. FIG. 3 is FIG.
Is an equivalent circuit of the transistor having the configuration described above, but the parasitic resistance caused by the offset region described above is not connected.

FIG. 4 is an equivalent circuit of the memory cell of the present invention shown in FIG. 1, and includes bit line load transistors T5 and T5.
6, bit line pairs BL and BLB. Here, parasitic resistances such as polysilicon resistance, diffusion resistance, and contact resistance are omitted. In the memory cell layout of FIG. 1, the parasitic resistance is not connected to both ends of the transistors T3 and T4 as described above, but the transfer transistors T1 and T2 have channel directions corresponding to the ion implantation directions indicated by arrows in FIG. Since they are parallel to each other, the parasitic resistance caused by the offset region is connected to one of the conductive electrodes as shown in FIG. In the memory cell equivalent circuit of FIG. 4, the driver transistor T3,
Since no parasitic resistance is generated at the source terminals of both T4, the deterioration of the memory cell stability due to the reduction of the potential difference between N1-S4 and N2-S3, which are the effective gate-source voltages, does not occur. A parasitic resistance is connected to one conductive electrode of each of the transfer transistors T1 and T2. However, since the circuit is completely symmetrical, the operation does not become asymmetrical.

In the above-described embodiment, only the driver transistors T3 and T4 are arranged so as not to be affected by the ion implantation angle.
It is clear that the T1 and T2 may be similarly arranged so as not to be affected by the ion implantation angle.

[0014]

As described above, in the present invention, since at least the channel direction of the driver transistor of the memory cell is arranged to be perpendicular to the direction in which the angular offset occurs at the time of ion implantation, the parasitic region caused by the offset region is obtained. A semiconductor memory device including a memory cell having high stability and symmetry without generating resistance can be realized.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a memory cell of a RAM according to the present invention.

FIG. 2 is a sectional structural view of a memory cell driver transistor of the present invention.

FIG. 3 is an equivalent circuit diagram of a memory cell driver transistor of the present invention.

FIG. 4 is an equivalent circuit diagram of a memory cell of the present invention.

FIG. 5 is a layout diagram of a memory cell of a conventional RAM.

FIG. 6 is a sectional structural view of a conventional memory cell driver transistor.

FIG. 7 is an equivalent circuit diagram of a conventional memory cell driver transistor.

FIG. 8 is an equivalent circuit diagram of a conventional memory cell.

[Explanation of symbols]

T1, T2: memory cell transfer transistors T3, T4: memory cell driver transistors T5, T6: bit line load transistors N1, N2: memory cell storage nodes RLDD, RL1, RL2, RL3, RL4. ..Parasitic resistance 1: gate electrode 2, 3, sidewall 4, 5, 8, 9 ... thin N-type impurity region 6, 7, 10, 11 ... dense N-type impurity region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8244 H01L 21/336 H01L 27/11 H01L 29/78

Claims (1)

(57) [Claims] 1. A semiconductor device comprising a driver transistor and a transfer transistor each having an impurity region formed by oblique ion implantation, wherein the driver transistor and the transfer transistor are formed such that their channel length directions are orthogonal to each other. The driver transistor is arranged such that a channel length direction thereof is orthogonal to a direction in which an angle offset occurs at the time of the oblique ion implantation. The transfer transistor has a channel length direction at the time of the oblique ion implantation. Wherein the semiconductor memory device is arranged so as to be parallel to the direction in which the angular offset occurs.