201230304 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置。 【先前技術】 使用半導體積體電路、特別是使用M0S電晶體之積體 電路係邁向高積體化。隨著該高積體化，其中所使用之M〇s 電晶體之微細化係進展至奈米領域。數位電路之基本電路 雖係為換流器電路（i nverter c i rcu i t)，但若構成該換流 器電路之MOS電晶體進一步細微化，則會有以下問題：漏 電流之抑制困難，因熱載子效應而造成可靠性降低，且因 要求確保所需之電流量而無法縮小電路之佔有面積。為了 解決以上之問題，係提案一種對基板在垂直方向配置源 極、閘極、汲極，且閘極圍繞島狀半導體層之構造的 Surrounding Gate TransistoKSGT)(參照例如專利文獻 1、專利文獻2、專利文獻3)。 在靜態型記憶體單元中，已知藉由將驅動電晶體之電 流驅動力設為存取電晶體之電流驅動力的 作穩定性（非專利文獻1 )。 2倍，而確保動 以上述SGT中右欲構成靜態型記憶體單元時，為了確 保動作穩定性， 而欲實現將驅動電晶體之雷治酿叙六設為201230304 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device. [Prior Art] The integrated circuit using a semiconductor integrated circuit, in particular, a MOS transistor, is highly integrated. With this high integration, the miniaturization of the M〇s transistor used therein progressed to the nanometer field. Although the basic circuit of the digital circuit is an inverter circuit, if the MOS transistor constituting the converter circuit is further miniaturized, there is a problem that the suppression of the leakage current is difficult due to heat. The carrier effect causes a decrease in reliability, and the area occupied by the circuit cannot be reduced because it is required to ensure the amount of current required. In order to solve the above problems, a Surrounding Gate Transisto KSGT is proposed in which a source, a gate, and a drain are arranged in a vertical direction, and a gate is surrounded by an island-shaped semiconductor layer (see, for example, Patent Document 1, Patent Document 2) Patent Document 3). In the static type memory cell, it is known that the current driving force of the driving transistor is set as the stability of the current driving force of the access transistor (Non-Patent Document 1). 2 times, and to ensure that the static memory unit is formed by the right side of the above SGT, in order to ensure the stability of the operation, it is desired to set the control of the driving transistor to six.
製造方法係㈣有—種在形成柱狀半導 再者，SGT之 323445 6 201230304 體層後，堆積閘極導電膜，並使之平坦化，進行蝕刻而作 成所希望之長度的技術（專利文獻4)。依據以該高積體且 高性能而獲得高良率之SGT的製造方法，SGT之物理間極 長度係在晶圓上之全部的電晶體中為一定。 此外，若靜態型記憶體單元更進一步微細化，因尺寸 縮小’連接於記憶節點之M0S電晶體之閘極電容及擴散層 電容會減少，此時若將放射線從外部照射至靜態型記憶體 單元時，會在半導體基板内沿著放射線之射程，產生電子 電洞對，該電子電洞對之至少一方會流入形成汲極之擴散 層而產生資料之反轉，並產生無法保持正確資料之軟性錯 誤現象。該軟性錯誤現象係記憶體單元之微細化越進展， 連接於記憶節點之Μ 0 S電晶體之閘極電容及擴散層電容之 減少會比在放射線產生之電子電洞對更顯著，因此近年來 在微細化進展之靜態型記憶體單元中成為重大之問題。因 ，，已有報導在靜態型記憶體單元之記憶節點形成電容 a ’以確保記憶節點所需之充分電荷量，藉此避免軟性錯 誤，以確保動作穩定性（專利文獻5)。 (先前技術文獻） (專利文獻） 專利文獻1:日本特開平2-71556號公報 專利文獻2 :曰本特開平2-188966號公報 專利文獻3 :日本特開平3-145761號公報 專利文獻4 :日本特開2009-182317號公報 專利文獻5 :日本特開2008-227344號公報 323445 7 201230304 (非專利文獻）H. Kawasaki, M. Khater, Μ· Guillorn, Ν. Fuller, J. Chang , S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski , R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, "Demonstration of Highly Scaled FinFET SRAM Cells with High-/c/Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond" , IEDM, pp. 237-240, 2008. 【發明内容】 (發明所欲解決之課題） 因此，本發明之目的在於提供一種以利用SGT之高積 體確保動作穩定性之靜態型記憶體單元。 (解決課題之手段） 本發明之半導體記憶裝置，係為具備在基板上排列有 6個M0S電緒之靜態型記憶體單元的半導體記 其中， 則述6個M0S電晶體係由用以存取記憶體之第 2 _S存取電晶體、心織用來簡記,㈣單元之資剩 的及第4NM0S驅動電晶體、及供給_ 電祕1川刪負載_ 用以存取記憶體之第1及第2咖S存取電晶體之名 323445 8 201230304 者’係以使柱狀半導體層配置在第1擴散層與第2擴散層 之間的:式在與基板垂直之方向階層地配 置有前述第1擴 散層、前述柱狀半導體層及前述第2擴散層，且在前述枉 狀半導體層之側壁形成有間極； 用乂保持α己隐體單元之資料而驅動記憶節點之第3及 第4_S驅動電晶體之各者，係以使柱狀半導體層配置在 第^散層與第4擴散層之間的方式在與基板垂直之方向 階層地配置有前述第3班私a ^ 擴散層、前述柱狀半導體層及前述 第4擴散層’且在前述柱狀半導體層之側壁形成有間極； 用以保持記憶體單元之資料而供給電荷之第i及第2 臓負載電晶體之各者，係以錄狀半導體層配置在第5 擴散層與第6擴散層之間的方式在與基板垂直之方向階層 地配置有前述第5擴散層、前述柱狀半導體層及前述第θ6 擴散f且在剛述柱狀半導體層之側㈣成有間極； 前，第1擴散層、第3擴散層、第5擴散層 相對於基板電性絕緣地配置； 考係 广2述第3及第4_驅動電晶體 =擴散層之下端之間的長度，係比形成= 下端之間1擴散層的上端與第2擴散層之 本發明之半導體記憶裝置 6個MGS電晶體之魅荆〜 輝土板上排列有 其中， 龍單㈣半導體記憶裝置， 前述6個M0S雷曰锕总丄m 電曰曰體係由用以存取記憶體之第1及第 323445 9 201230304 2 NM0S存取電晶體、為了保持記憶體單元之資料而驅動記 憶節點的第3及第4 NM0S驅動電晶體、及為了保持記憶體 單元之資料而供給電荷的第1及第2 PM0S負載電晶體所構 成， 用以存取記憶體之第1及第2 NM0S存取電晶體之各 者，係以使桎狀半導體層配置在第丨擴散層與第2擴散層 之間的方式在與基板垂直之方向階層地配置有前述第1擴 散層、前述柱狀半導體層及前述第2擴散層，且在前述柱 狀半導體層之侧壁形成有閘極； 用以保持記憶體單元之資料而驅動記憶節點之第3及 第4 NM0S驅動電晶體之各者，係以使柱狀半導體層配置在 第3擴散層與第4擴散層之間的方式在與基板垂直之方向 P白層地，置有前述第3擴散層、前述柱狀半導體層及前述 第4,散層’且在前述柱狀半導體層之側壁形成有閉極； 月1J述第1擴散層、第3擴散層、第5擴散層之各者係 相對於基板電性絕緣地配置； 用以保持§己憶體單元之資料而供給電荷之第i及第2 體之各者’係以使柱狀半導體層配置在第5 祕西=义6擴散層之間的方式在與基板垂直之方向階層 ㈣層、前述柱狀半導體層及前述第6 二士在Μ述柱狀半導體層之側壁形成有閘極； 形成前述第3及笛1 Λ 的上媸盥笛… _S驅動電晶體之第3擴散層 的上端與第4擴散層之下 第2PM0S負載雷曰駚“ 刃我度成弟i及 、曰曰體之第5擴散層的上端與第6擴散層之 323445 10 201230304 下端之間的長度為短。 形成前述第1及第2 _s存取電晶體之第i擴散層 的上端與第2擴散層之下端之間的長度，較佳為在形成第 3及第4腦S驅動電晶體之第3擴散層的上端與第4擴散 層之下端之間的長度之1· 3倍至3倍之範圍。 形成第1及第2臓負載電晶體之第5擴散層的上 端與第6擴散層之下端之間的長度，較佳為在形成第3及 第4 NMQS驅動電晶體之第3擴散層的上端與第4擴散層之 下端之間的長度之1.3倍至3倍之範圍。 曰 亦可將前述閘極之從下端至上端之長度設為相同。 前述第3及帛4 NM0S_電晶體之第3擴散層的上 端，亦可比前述第i及第2 _S存取電晶體之第i擴散声 的上端為高。 曰 前述第3及第4丽0S驅動電晶體之第4擴散層的下 端’亦可比前述第i及第2NMGS存取電晶體之第2擴散屏 的下端為低。 ^ 前述第3及第4丽0S驅動電晶體之第3擴散層的上 端，亦可比前述第i及第2丽os存取電晶體之第i擴散層 的上端為南， 、 前述第3及第4 NM0S驅動電晶體之第4擴散層的下 端，亦可比前述第i及第2丽0S存取電晶體之第2擴散屛 的下端為低。 曰 在幵>成前述第3及第4 NM0S驅動電晶體各者之第3 擴散層後，可形成前述第1及第2 NM0S存取電晶體各者之 323445 11 201230304 第1擴散層。 前述第3及第4 NM0S驅動電晶體之第4擴散層、與 前述第1及第2 NM0S存取電晶體各者之第2擴散層係藉由 離子注入而形成， 可使用以形成前述第3及第4 NM0S驅動電晶體各者 之第4擴散層之離子注入的能量，比用以形成前述第1及 第2丽0S存取電晶體各者之第2擴散層之離子注入的能量 為面。 可在前述第3及第4 NM0S驅動電晶體之第4擴散層 包含有磷。 (發明之效果） 依據本發明，可提供一種可使驅動電晶體之通道長度 比存取電晶體之通道長度為短，且以高積體確保動作穩定 性之靜態型記憶體單元及其製造方法。 【實施方式】 以下，參照圖式說明本發明之實施形態。此外，本發 明並非由以下所示之實施形態所限定者。 第1圖係顯示本發明第1實施形態之靜態型記憶體單 元之平面圖及剖面圖。第3丽0S驅動電晶體101係具備第 3擴散層119、柱狀半導體層149、及第4擴散層107。在 第3丽OS驅動電晶體101之柱狀半導體層149、第4擴散 層107之一部分及第3擴散層119之一部分的側壁，隔著 閘極絕緣膜113形成有閘極125。 第1丽0S存取電晶體103係具備第1擴散層121、柱 12 323445 201230304 狀半導體層151、及第2擴散層109。在第1丽0S存取電 晶體103之桂狀半導體層151、第2擴散層109之一部分 及第1擴散層121之一部分的側壁，隔著閘極絕緣膜ι15 形成有閘極126。 閑極125之閘極高度係在第3 NM0S驅動電晶體之附 近變低’物理閘極長度比閘極126短。形成第1 NM0S存取 電晶體103之第1擴散層121與第2擴散層109之間的長 度，係為形成第3丽〇S驅動電晶體1〇1之第3擴散層ι19 與第4擴散層1Q7之間的長度之2倍。藉此，驅動電晶體 之電流驅動力係在未增加面積之情形下可設為存取電晶體 之電流驅動力的2彳立，且可墟 ^ u且了確保動作穩定性。 第1 PM〇S負載電晶體1〇2係 狀半導體層150、及第β料β #第擴散層120、检 第擴層1Q8。在第1 PMGS負载電 日曰體之柱狀丰導體声κ a ^ e ^ 千導體層150、苐5擴散層120之一部分 及第6擴散層1 〇8之一邱八 、 卟之口p刀的側壁，隔著閘極絕緣膜114 形成有閘極125。 第3嶋驅動電晶體101與第1麵負载電晶體⑽ 係以閘極125連接。此外1 3擴散層119、第5擴散斧 120、第i擴散層121係以矽化物（未圖示）連接。在本圖 式中’為了使第3擴散層119、第5擴散層12〇、第丄擴散 層121分別對於基板電性絕緣，雖使用s〇I基板，但只要 可電性絕緣即可’例如亦可使用s i基板，以形成p N接/合， 並利用PN接合之反偏壓狀態而形成電性絕緣。 第4_3驅動電晶Μ 106係具備第3擴散層124、柱 323445 201230304 狀半導體層、及第4擴散層112。在第4丽0S驅動電晶體 106之柱狀半導體層、第3擴散層124之一部分及第4擴 散層112之一部分的側壁，隔著閘極絕緣膜118形成有閘 極 128。 第2腿0S存取電晶體1〇4係具備第i擴散層122、柱 狀半導體層、及第2擴散層11〇。在第2 NM0S存取電晶體 104之柱狀半導體層、第1擴散層Η?之一部分及第2擴 散層11〇之一部分的側壁，隔著閘極絕緣膜116形成有閘 極127。雖未圖示，但形成第2NM〇s存取電晶體ι〇4之第 1擴散層122與第2擴散層11〇之間的長度，係為形成第4 丽0S驅動電晶體1〇6之第3擴散層124與第4擴散層112 之間的長度之2倍。 第2PM0S負载電晶體105係具備第5擴散層123、柱 狀半導體層、及第6擴散層ill。在第2 PM〇s負載電晶體 105之柱狀半導體層、第5擴散層丨23之一部分及第6擴 散層ill之一部分的側壁，隔著閘極絕緣臈117形成有閘 極 128。 第4NM0S驅動電晶體106與第2PM〇s負載 係以閑極125連接。此外，第！擴散層122载第電 123、第3擴散層124係以矽化物（未圖示）連接。 再者，在本圖式中，為了使第丨擴散層122、第5擴 散層123、第3擴散層124分別對於基板電性絕緣，雖使 用SOI基板，但只要可電性絕緣即可，例如亦可使用以 基板’以形成PN接合，並利用洲接合之反偏壓狀態而形 323445 14 201230304 成電性絕緣。 在閘極125上形成有接觸件13〇，在第丨擴散層122、 第5擴散層123上形成有接觸件137。接觸件13〇、137係 以金屬142連接。在閘極128上形成有接觸件丨39，在第 5擴散層120、第1擴散層121上形成有接觸件132。接觸 件139、132係以金屬144連接。在第6擴散層⑽上形 成有接觸件131，在第6擴散層111上形成有接觸件138, 在接觸件131、138連接有金屬143，且供給有電源。 在第4擴散層107上形成有接觸件129，且形成有金 屬141，且供給有電源。在第4擴散層U2上形成有接觸 件140 ’且形成有金屬148 ’且供給有電源。在第2擴散層 109上形成有接觸件133 ’且形成有金屬145，以作為位元 線。在第2擴散層11〇上形成有接觸件136，且形成有金 屬210,以作為位元線。在閘極126上形成有接觸件134， 且形成有金屬146，以作為字元線。在閘極127上形成有 接觸件135，且形成有金屬147，以作為字元線。 本發明第2實施形態之靜態型記憶體單元之平面圖及 剖面圖係與第1圖相同。在該實施形態中，形成第3_s 驅動電晶體101之第3擴散層119與第4擴散層1〇7之間 的長度，係比形成第1 PMOS負載電晶體1〇2之第5擴散層 120與第6擴散層108之間的長度為短。在SRAM中，pM〇s 之負載電晶體係以最小尺寸形成，且形成為pM〇s之負載電 晶體的電流驅動力比NMOS之存取電晶體的電流驅動力 小。亦即，丽OS之存取電晶體及PM〇s之負載電晶體之通 323445 201230304 f長度係形成為相同。因此，在本發明中腦s之驅動電 曰曰體101之通道長度係比pM〇s之驅動電晶體之通道長 度為知L。 a第2圖（a)及（b)係顯示本發明第3及第4實施形 態之靜態型記憶體單元之剖面圖。在第2圖（a)中，形成 第1NM0S存取電晶體103之第i擴散層121的上端與第2 擴散層109之下端之間的長度，係設為形成第3 NM〇s驅動 電曰 =體101之第3擴散層119的上端與第4擴散層1〇7之 下端之間的長度之1.3倍。在第2圖（b)中，形成第丄NM〇s 存取電晶體103之第1擴散層121的上端與第2擴散層1〇9 之下端之間的長度，係設為形成第3NM〇s驅動電晶體1〇1 之第3擴散層119的上端與第4擴散層1〇7之下端之間的 長度之3倍。將驅動電晶體之通道長度設為越短，越能確 保動作穩定性，但若-方變短時，則會產生短通道效應， 而無法截斷電晶體。因此，雖可依所要之要求適當選擇， 但就一例而言，若設為上述之13倍至3倍之間的範圍， 則可謀求動作穩定性之破保及短通道效應之抑制。 本發明第5及第6實施形態之靜態型記憶體單元之平 面圖及剖面圖係與第2圖（a)及（b)相同。在第5實施 形態中，形成第1PMOS負載電晶體1〇2之第5擴散層12〇 的上端與第6擴散層108之下端之間的長度，係設為形成 第3NMOS驅動電晶體1〇1之第3擴散層119的上端與第4 擴散層107之下端之間的長度之h3倍。在第6實施形態 中’形成第1 PMOS負載電晶體1〇2之第5擴散層120的上 323445 16 201230304 端與第6擴散層108之下端之間的長度，係設為形成第3 丽0S驅動電晶體i〇i之第3擴散層119的上端與第4擴散 層1〇7之下端之間的長度之3倍。將驅動電晶體之通道長 度設為越短，越能確保動作穩定性，但若一方變短時，則 會產生短通道效應，而無法截斷電晶體。因此，雖可依所 要之要求適當選擇，但就一例而言’若設為上述之1.3倍 至3倍之間的範圍，則可謀求動作穩定性之確保及短通道 效應之抑制。 第3圖係顯示本發明第7實施形態之靜態型記憶體攀 元之剖面圖。將閘極125、126之物理閘極長度設為相閱 者。由於閘極125、126之從下端至上端之長度（亦即物该 問極長度）為相同，因此可使用前述之SGT之製造方法， 該方法係在形成柱狀半導體層後，堆積閘極導電膜，並像 之平垣化，進行回蝕刻而作成所希望之長度。 通常，使通道長度變短者係如第1圖所示，使物理閘 極長度變短。若使物理閘極長度變短，則閘極電容會變小。 若間極電容變小，則會發生軟性錯誤（soft. error)，而# 確保動作穩定性。另一方面，第3圖係僅使驅動電晶雜 =流驅動力變短，物理閘極長度則相同，因此雖將驅動 。曰曰體之通道長度設為2倍，閘極電容亦不會變小。亦即， 力動電晶體的電流驅動力係可設為存取電晶體的電流驅動 、仑，以確保動作穩定性，且避免軟性錯誤，而可漆 保動作穩定性。 第4圖係顯示本發明第8實施形態之靜態型記憶體弟 17 323445 201230304 元之剖面圖。在第4圖之實施形態中，物理閘極長度相同， 第3 NM0S驅動電晶體101之第3擴散層119之上端，係位 於比第1丽0S存取電晶體103之第1擴散層121的上端更 高之位置。藉此，第3丽0S驅動電晶體101係可增大閘極 125與第3擴散層119之間的重疊電容。當第2丽0S驅動 電晶體101截斷時，閘極125與第3擴散層119間之重疊 電容係成為寄生在記憶節點之寄生電容，由於重疊電容較 大，因此可進一步避免軟性錯誤，而可確保動作穩定性。 第5圖係顯示本發明第9實施形態之靜態型記憶體單 元之刮面圖。與第4圖不同的是，第3 NMOS驅動電晶體 101之第3擴散層119的上端、與第1丽OS存取電晶體103 之第1擴散層121的上端之高度為相同，第3丽OS驅動電 晶體101之第4擴散層107的下端，係比第1丽OS存取電 晶體103之第2擴散層109的下端為低。 即使在第5實施形態中，由於僅使驅動電晶體之通道 長度變短，物理閘極長度則相同，因此雖將驅動電晶體之 電流驅動力設為2倍，閘極電容亦不會變小，因此驅動電 晶體的電流驅動力係可設為存取電晶體的電流驅動力的·一 倍，以確保動作穩定性，且復避免軟性錯誤，而可確保動 作穩定性。然而，並沒有如第4圖之更進一步之優點，即 當第2丽OS驅動電晶體101截斷時，閘極125與第3擴散 層119間之重疊電容係成為寄生在記憶節點之寄生電容， 由於重疊電容較大，因此可進一步避免軟性錯誤，而可確 保動作穩定性。然而，當將記憶節點設計成來到電晶體之 18 323445 201230304 在製造方二厂f更加避免軟性錯誤之優點。但是，之後會 擴散層用之ίι說為了製作第4圖之形狀，係在第3 入#Μ Λ /主入後，需要比較長之熱處理。以離子注 擴散長度較，107時’藉由使用提高注入之能量、或 4擴散層107# Ρ即可使第3_驅動電晶體101之第 擴散層：的下:::：ΓΝ廳存取電晶體103之第2 第6 ^缟為低。亦即，可使熱處理比第4圖為少。 1〇1 ^ '、第4圖不同的是，第3 NM0S驅動電晶體 103之第1擴散層119的上端，係比第1 _S存取電晶體 擴散層12ι的上端為高’第3藝驅動電晶體 103之第散層1〇7的下端，係比第1隱存取電晶體 103之第2擴散層1〇9的下端為低。 在第6圖的實施形態中，由於使驅動電晶體之诵 二=存:電晶體之通道長度短，因此可確保動作穩定 Μ㈣/、可作到第4圖之優點的避免軟性錯誤。由於 ’ θ 119之擴散長度較短，因此與製作第4 形 狀相比較，能以較少之祕理來形成。當以離子注: 第：擴散：107時，藉由使用提高注入之能量、或擴散長 度較長之磷’即可使第3 NM0S驅動電晶體1〇1之第4; 層107的下端，比第1NM0S存取電晶體1〇3之第2擴& 109的下端為低。亦即，可使熱處理比第4圖為少，且二 <避免軟性錯誤。然而，與第4圖之雜及第5圖之形狀 相比較，製造步驟會增加。雖顯示以上各式各樣之形熊， 323445 19 201230304 但依所要之要求適當地選擇即可。 以下，參照第7圖至第32圖說明用以形成本發明實 施形態之第4圖之靜態型記憶體單元構造的製造步驟之一 例。 第7圖係顯示在矽152上形成有氧化膜157，並在氧 化膜上形成平面狀矽158，且形成分別在上部具有氮化膜 硬遮罩162、163、164的柱狀矽159、160、161的狀態。 從第7圖的狀態藉由堆積氧化膜，並進行回蝕刻，如 第8圖所示形成氧化膜侧壁165、166、167。然後，形成 用以形成第3擴散層119之阻劑168。 在此狀態下，如第9圖所示注入砷，以形成第3擴散 層 119。 然後，如第10圖所示，剝離阻劑168，並剝離氧化膜 侧壁165、166、167，以進行第一次之熱處理。 再者，如第11圖所示，形成氧化膜側壁169、170、 171。之後，形成用以形成第1擴散層121之阻劑172。 在該狀態下，如第12圖所示，注入砷而形成第1擴 散層121。 然後，如第13圖所示，剝離阻劑172，並剝離氧化膜 側壁169、170、171，以進行第二次之熱處理。第3擴散 層119係由於接受二次之熱處理，因此第3擴散層119之 上端係比第1擴散層121之上端為高。藉此，驅動電晶體 之通道長度係比存取電晶體之通道長度為短，而可確保動 作穩定性。 20 323445 201230304 接著，如第14圖所示，形成氧化膜侧壁173、174、 175。然後，形成用以形成第5擴散層120之阻劑176。 在該狀態下’如第15圖所示，注入硼而形成第5擴 散層120。 從該狀態，如第16圖所示，剝離阻劑176，並剝離氧 化膜側壁173、174、175，以進行熱處理。 然後’如第17圖所示，形成形成元件分離用之阻劑， 進行石夕之蚀刻，以剝離阻劑。 接著，如第18圖所示，以埋設元件間之方式形成氧 化膜153 ’然後堆積常壓CVD氧化膜，並進行回蝕刻，藉 此形成氧化膜177。此時，氧化膜178、179、180會殘留 在氮化膜硬遮罩162、163、164上。 再者’如第19圖所示，形成閘極絕緣膜113、114、 115，堆積閘極導電膜181，並使之平坦化。氧化膜178、 179、180露出後，蝕刻氧化膜178、179、180，且復進行 平坦化，將氮化膜硬遮罩作為擔止件。閘極絕緣膜係為氧 化膜、氮化膜、氧氮化膜、高電介質膜中之一種。閘極導 電膜係多晶石夕、金屬與多晶石夕之積層膜、金屬膜中之一種。 接著，如第20圖所示，對閘極絕緣膜181進行回餘 刻，而獲得所希望之物理閘極長度。結果，在全部之電晶 體中物理閘極長度為一定。 然後，堆積氧化膜’並堆積氮化膜，進行蝕刻，而殘 存為侧壁狀，如第21圖所示，形成由氧化膜184、氮化膜 185所構成之絕緣膜側壁、由氧化膜186、氮化膜187所構 323445 21 201230304 成之絕緣膜侧壁、及由氧化膜188、氮化膜189所構成之 絕緣膜側壁。 接著，如第22圖所示，形成用以對閘極進行蝕刻之 阻劑 182、183。 然後，如第23圖所示，對閘極導電膜181進行蝕刻， 形成閘極125、126，對氧化膜177進行蝕刻’形成氧化膜 154、155，並剝離阻劑 182、183。 接著，如第24圖所示，對由氧化膜184、氮化骐185 所構成之絕緣膜側壁、由氧化膜186、氮化膜187所構成 之絕緣膜侧壁、及由氧化膜188、氮化膜189所構成之絕 緣獏側壁進行蝕刻。 再者，堆積氮化膜，進行蚀刻，而殘存為側壁狀，如 第25圖所示，形成氮化膜側壁190、19卜192、193、194。 接著’如第26圖所示，形成用以形成第2擴散層1〇7、 109之阻劑195。 然後，如第27圖所示，離子注入砷而形成第4擴散 層107、S 2擴散層1〇9。 然後，如第28圖所示，剝離阻劑195，以進行熱處理。 如第29圖所示，形成用以形成第6擴散層108之阻 劑 196 〇 接著’如第3〇圖所示，離子注入硼而形成第6擴散 層 108。 然後’如第31圖所示’剝離阻劑196,以進行熱處理。 然後，如第32圖所示，堆積層間膜156，以形成接觸 22 323445 201230304 件 129、130、131、132、133、134，並形成金屬 141、142、 143、144、145、146。在形成層間膜之前，亦可在第3擴 散層119、第5擴散層12〇、第1擴散層121上形成矽化物。 此外’亦可在第4擴散層1〇7、第6擴散層108、第2擴散 層109上形成碎化物。 由以上得知，藉由使驅動電晶體之通道長度比存取電 晶體之通道長度為短，而確保動作穩定性。再者，藉由將 驅動電晶體之物理閘極長度與存取電晶體之物理閘極長度 設為相同，可使用前述SGT之製造方法。亦即，驅動電晶 體之電流驅動力係可設為存取電晶體之電流驅動力的二 倍’以確保動作穩定性，見由於僅使驅動電晶體之通道長 度變短，物理閘極長度相同，因此儘管將驅動電晶體之電 流驅動力設為二倍’閘極電容亦不會變小，因此可避免軟 性錯誤，且確保動作穩定性。再者，顯示一種用以形成以 下構之製造方法，該構造為.驅動電晶體之第3擴散層 的上端係設為位於比存取電晶體之第1擴散層的上端更高 之位置’因此，驅動電晶體係可將閘極與第3擴散層間之 重疊電容增大，且復可避免軟性錯誤，且確保動作穩定性。 以下，參照第33圖至笫58圖說明用以形成本發明實 靶形態之第5圖之靜態型記憶體單元構造的製造步驟之一 例〇 第3 3圖係為以下構造 157,且在氧化膜157上形成平 百氣化 w ^ 办成十面狀之矽158，且形忐古 別在上部具有氮化膜硬遮罩16 t成有 皁叫吻、164之柱狀石夕15丨 323445 23 201230304 160 、 16卜 接著，如第34圖所示，堆積氧化膜’並進行回蝕刻， 而形成氧化膜侧壁165、166、167。然後’形成用以形成 第3擴散層119、第1擴散層121之阻劑172。 再者，如第35圖所示，注入砷而形成第3擴散層119、 第1擴散層12卜 然後，如第36圖所示，剝離阻劑172，並剝離氧化膜 側壁165、166、167，以進行熱處理。 接著，如第37圖所示，形成氧化膜側壁Π3、174、 175。之後，形成用以形成第5擴散層120之阻劑176。 然後，如第38圖所示，注入硼而形成第5擴散層120。 然後，如第39圖所示，剝離阻劑Π6，並剝離氧化膜 側壁17 3、17 4、17 5，以進行熱處理。 然後，如第40圖所示，形成元件分離形成用之阻劑， 進行矽之蝕刻，以剝離阻劑。 接著’如第41圖所示，.以埋設元件間之方式形成氧 化膜153，然後堆積常壓CVD氧化膜，並進行回蝕刻，藉 此形成氧化膜177。此時，氧化膜178、179、180會殘留 在氮化膜硬遮罩162、163、164上。 再者，如第42圖所示，形成閘極絕緣膜113、114、 115，堆積閘極導電膜181，並使之平坦化。氧化膜178、 179、180露出後，蝕刻氧化膜178、179、180，且進行平 坦化，將氮化膜硬遮罩作為擂止件。閘極絕緣膜係為氧化 膜、氮化膜、氧氮化膜、高電介質膜中之一種。閘極導電 24 323445 201230304 膜係多晶矽、金屬與多晶矽之積層膜、金屬膜中之一種。 接著’如第43圖所示，對閘極絕緣膜181進行回# 刻，而獲得所希望之物理閘極長度。結果’在全部之電晶 體中物理閘極長度為一定。 然後，如第44圖所示，堆積氧化膜，並堆積氮化膜， 進行蝕刻，而殘存為側壁狀，以形成由氧化膜I84、氮化 膜185所構成之絕緣膜側壁、由氧化膜186、氮化膜 所構成之絕緣膜側壁、及由氧化膜188、氮化膜189所構 成之絕緣膜側壁。 接著，如第45圖所示’形成用以對閘極邊行蝕刻之 阻劑 182、183。 然後，如第46圖所示’對閘極導電膜181進行姓刻， 形成閘極125、126，對氧化膜177進行蝕刻’形成氧化膜 154、155，並剝離阻劑 182、183。 接著，如第47圖所示，對由氧化膜184、氮化膜ι85 所構成之絕緣膜側壁、由氧化膜186、氮化膜187所構成 之絕緣膜侧壁、及由氧化膜188、氮化膜189所構成之絕 緣膜側壁進行蝕刻。 再者，如第48圖所示，堆積氮化膜’進行蝕刻，而 殘存為侧壁狀，以形成氮化膜侧壁190、191、192、193、 194。 接著，如第49圖所示，形成用以形成第4擴散層1〇7 之阻劑201。 然後，如第50圖所示，離子注入砷或磷而形成第4 323445 25 201230304 擴散層107。使用砷時係只要增大離子注入之能量即可。 此外’藉由使用擴散長度較長之磷，即可使第3丽的驅動 電晶體101之第4擴散層107的下端，比第1 NM〇s存取電 晶體103之第2擴散層109的下端為低。可適當地選擇使 用砷，或使用磷。 然後，如第51圖所示，剝離阻劑2〇1，以進行熱處理。 如第52圖所不，形成用以形成第2擴散層1〇9之阻 劑 202。 接著，如第53圖所示，離子注入砷而形成第2擴散 層 109。 然後，如第54圖所示，剝離阻劑2〇2，以進行熱處理。 然後，如第55圖所示，形成用以形成第6擴散層1〇8 之阻劑203。 接著，如第56圖所不，離子注入硼而形成第2擴散 層 108 〇 然後，如第57圖所示，剝離阻劑2〇3,以進行熱處理。 此外，如第58圖所示，堆積層間膜156，以形成接觸 件 129、130、13卜 132、133、134,並形成金屬 14卜 142、 143、144、145、146。在形成層間膜之前，亦可在第3擴 散層119、第5擴散層120、第丨擴散層121上形成矽化物。 此外’亦可在第4擴散層107、第6擴散層1〇8、第2擴散 層109上形成矽化物。 如以上所述，藉由使驅動電晶體之通道長度比存取電 晶體之通道長度為短’即可確保動作穩定性，使熱處理比 323445 26 201230304 第1圖更少。 以上，雖顯示用以形成第4圖及第5圖之構造的製造 方法’但針對帛6圖所示之構造，可藉由、組合形成第4圖 之第3擴政層119、帛1擴散層121之方法與形成第5圖 之第4擴散層1〇7、第2擴散層1〇9之方法而形成。 匕卜本發明係可在不脫離本發明之廣義之精神及範 圍的情形下進行各式各樣之實施形態及變形。此外，上述 之實施形態係用以說明本發明之一實施例者，並非由上述 之實施形態來限定本發明之技術範圍者。 【圖式簡單說明】 第1圖（a)係顯示本發明第1及第2實施形態之靜 態型記憶體單元之平面圖，冑1圖（b)係（a)之χ-χ，線 之剖面圖。 第2圖（a)係顯示本發明第3及第5實施形態之靜 態型記憶體單元之剖面圖。第2圖（b)係顯示本發明第4 及第6實施形態之靜態型記憶體單元之剖面圖。 第3圖係顯示本發明第7實施形態之靜態型記憶體單 元之剖面圖。 第4圖係顯示本發明第8實施形態之靜態型記憶體單 元之剖面圖。 第5圖係顯示本發明第9實施形態之靜態型記憶體單 元之剖面圖。 第6圖係顯示本發明第1〇實施形態之靜態型記憶體 早凡之剖面圖。 27 323445 201230304 弟7圖係說明本發明實施形癌之靜態型記憶體單元之 製造方法的剖面圖。 第8圖係說明本發明實施形態之靜態型記憶體單元之 製造方法的剖面圖。 第9圖係說明本發明實施形態之靜態型記憶體單元之 製造方法的剖面圖。 第10圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第11圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第12圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第13圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第14圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的刮面圖。 第15圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第16圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第Π圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第18圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 28 323445 201230304 第W圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第2〇圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第21圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第22圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第23圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第24圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第25圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第26圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第27圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第28圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第29圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第30圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 29 323445 201230304 第31圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第32圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第33圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第34圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第35圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第36圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第37圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第39圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第40圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第4丨圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第42圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 323445 30 201230304 第43圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第44圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第45圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第46圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第4 7圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第48圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第49圖係说明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第50圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第51圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第52圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第53圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第54圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 31 323445 201230304 第55圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第56圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第57圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 第58圖係說明本發明實施形態之靜態型記憶體單元 之製造方法的剖面圖。 【主要元件符號說明】 101 102 103 104 105 106 107 108 109 110 111 112 113 119 120 114、115 124 123 第3 NMOS驅動電晶體 第1 PMOS負載電晶體 第1丽OS驅動電晶體 第2丽OS存取電晶體 第2 PMOS負載電晶體 第4丽OS驅動電晶體 第4擴散層 第6擴散層 第2擴散層 第2擴散層 第6擴散層 第4擴散層 116、117、118閘極絕緣膜 第3擴散層 第5擴散層 32 323445 201230304 121 ' 122 第1擴散層 125、126、127、128 閘極 129、130、13卜 132、133、134 接觸件 135、136、137、138、139、140 接觸件 14卜 142、143、144、145、146、147、148、210 金屬 149、150、151 柱狀半導體層 152、 158、160、161 矽 153、 154、155、177、178、179、180、184、186、188 氧化膜 156 堆積層間膜 157 氧化膜 162、163、164 氮化膜硬遮罩 165、166、167、169、170、171、173、174、175 氧化膜侧壁 168、172、176、195 阻劑 185、187、189 氮化膜 190、191、192、193、194 氮化膜侧壁 33 323445(4) A technique in which a gate conductive film is formed, a gate conductive film is formed, and a gate conductive film is deposited and planarized, and etching is performed to obtain a desired length (Patent Document 4) ). According to the manufacturing method of the SGT which achieves high yield with such a high product and high performance, the physical inter-electrode length of the SGT is constant in all the transistors on the wafer. In addition, if the static memory cell is further miniaturized, the gate capacitance and the diffusion layer capacitance of the MOS transistor connected to the memory node are reduced due to the size reduction. At this time, the radiation is radiated from the outside to the static memory cell. At this time, an electron hole pair is generated along the range of the radiation in the semiconductor substrate, and at least one of the electron holes flows into the diffusion layer forming the drain to generate data inversion, and the softness of the data cannot be maintained. Wrong phenomenon. The soft error phenomenon is that the progress of the miniaturization of the memory cell is progressed, and the reduction of the gate capacitance and the diffusion layer capacitance of the NMOS transistor connected to the memory node is more remarkable than that of the electron hole pair generated by the radiation. It has become a major problem in the development of static memory cells that are progressing. Therefore, it has been reported that the capacitance a ' is formed at the memory node of the static memory cell unit to secure a sufficient amount of charge required for the memory node, thereby avoiding soft errors and ensuring operational stability (Patent Document 5). (Prior Art Document) (Patent Document 1) Japanese Patent Laid-Open No. Hei 2- No. Hei. Japanese Patent Laid-Open Publication No. 2009-182317 Patent Document 5: JP-A-2008-227344, No. 323445 7 201230304 (Non-Patent Document) H. Kawasaki, M. Khater, Μ· Guillorn, Ν. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, "Demonstration of Highly Scaled FinFET SRAM Cells with High-/c/Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond" IEDM, pp. 237-240, 2008. [Problem to be Solved by the Invention] Therefore, an object of the present invention is to provide a static memory unit that ensures operational stability by using an SGT high product. . (Means for Solving the Problem) The semiconductor memory device of the present invention is a semiconductor having a static memory cell in which six MOS circuits are arranged on a substrate, and the six MOS electro-crystal systems are used for access. The second _S access transistor of the memory, the heart woven is used for shorthand, (4) the remaining of the unit and the 4th NM0S drive transistor, and the supply _ the secret 1 load _ used to access the first and The name of the second coffee S access transistor 323445 8 201230304 is such that the columnar semiconductor layer is disposed between the first diffusion layer and the second diffusion layer: the above-described first layer is arranged hierarchically in a direction perpendicular to the substrate a diffusion layer, the columnar semiconductor layer, and the second diffusion layer, wherein a sidewall is formed on a sidewall of the germanium-shaped semiconductor layer; and the third and fourth_s of the memory node are driven by the data of the alpha-hidden cell Each of the driving transistors is arranged such that the third semiconductor layer is disposed hierarchically in a direction perpendicular to the substrate such that the columnar semiconductor layer is disposed between the second layer and the fourth diffusion layer. a columnar semiconductor layer and the aforementioned fourth diffusion layer 'and a sidewall of the columnar semiconductor layer is formed with a mesopole; and each of the i-th and the second 臓-loaded transistor for supplying electric charge to hold the data of the memory cell is disposed in the fifth diffusion layer by the recording semiconductor layer In the manner between the sixth diffusion layers, the fifth diffusion layer, the columnar semiconductor layer, and the θ6 diffusion f are arranged hierarchically in a direction perpendicular to the substrate, and a side electrode is formed on the side (four) of the columnar semiconductor layer. Before the first diffusion layer, the third diffusion layer, and the fifth diffusion layer are electrically insulated from each other, the length of the third and fourth_driving transistors = the lower end of the diffusion layer is The ratio is the upper end of the diffusion layer between the lower end and the second diffusion layer of the semiconductor memory device of the present invention, and the six MGS transistors are arranged on the enchantment-emergency plate, the Longdan (four) semiconductor memory device, the aforementioned 6 The M0S Thunder 曰锕m electric system consists of the first and third 323445 9 201230304 2 NM0S access transistors for accessing the memory, and the third and the third to drive the memory nodes in order to maintain the data of the memory cells. 4 NM0S drive transistor, and in order to keep in mind The first and second PMOS load transistors that supply electric charge by the data of the body unit, and the first and second NMOS input crystals for accessing the memory are arranged such that the germanium-shaped semiconductor layer is disposed. The first diffusion layer, the columnar semiconductor layer, and the second diffusion layer are layered in a direction perpendicular to the substrate in a manner between the second diffusion layer and the second diffusion layer, and are on the side of the columnar semiconductor layer a wall is formed with a gate; each of the third and fourth NMOS drive crystals for driving the memory node for holding the data of the memory cell is such that the columnar semiconductor layer is disposed on the third diffusion layer and the fourth diffusion layer In a method of forming a third diffusion layer, the columnar semiconductor layer, and the fourth and third layers, and forming a closed electrode on a sidewall of the columnar semiconductor layer, in a white layer perpendicular to the substrate P; Each of the first diffusion layer, the third diffusion layer, and the fifth diffusion layer is electrically insulated from the substrate, and the first and second bodies for supplying electric charge to hold the data of the § memory unit are provided. Each of them is arranged such that the columnar semiconductor layer is placed in the fifth a method of forming a gate between the diffusion layer and the layer 6 in the direction perpendicular to the substrate, the columnar semiconductor layer, and the sixth and second sides forming a gate on the side wall of the columnar semiconductor layer; And the whistle of the flute 1 ...... The upper end of the third diffusion layer of the _S drive transistor and the second PMOS load thunder under the fourth diffusion layer "The blade is the second diffusion of the scorpion i and the corpuscle The length between the upper end of the layer and the lower end of the 316445 10 201230304 of the sixth diffusion layer is short. The length between the upper end of the i-th diffusion layer forming the first and second _s access transistors and the lower end of the second diffusion layer is preferably the third diffusion forming the third and fourth brain S-drive transistors The length between the upper end of the layer and the lower end of the fourth diffusion layer is in the range of 1.3 times to 3 times. The length between the upper end of the fifth diffusion layer forming the first and second 臓 load transistors and the lower end of the sixth diffusion layer is preferably at the upper end of the third diffusion layer forming the third and fourth NMQS driving transistors. The range from 1.3 times to 3 times the length between the lower end of the fourth diffusion layer.亦可 The length of the gate from the lower end to the upper end can also be set to be the same. The upper end of the third diffusion layer of the third and fourth NMOS transistors may be higher than the upper end of the ith diffusion of the first and second _S access transistors.下 The lower end of the fourth diffusion layer of the third and fourth NMOS driving transistors may be lower than the lower end of the second diffusion screen of the i-th and second NMGS access transistors. ^ The upper end of the third diffusion layer of the third and fourth NMOS driving transistors may be souther than the upper ends of the ith diffusion layers of the first and second os access transistors, and the third and third 4 The lower end of the fourth diffusion layer of the NM0S driving transistor may be lower than the lower end of the second diffusion port of the first and second NMOS transistors.幵 After forming the third diffusion layer of each of the third and fourth NM0S driving transistors, 323445 11 201230304 first diffusion layer of each of the first and second NMOS transistors can be formed. The fourth diffusion layer of the third and fourth NMOS drive crystals and the second diffusion layer of each of the first and second NMOS OSs are formed by ion implantation, and can be used to form the third And the energy of ion implantation of the fourth diffusion layer of each of the fourth NM0S driving transistors is higher than the energy of ion implantation of the second diffusion layer for forming each of the first and second NMOS transistors. . Phosphorus may be contained in the fourth diffusion layer of the third and fourth NM0S driving transistors. Advantageous Effects of Invention According to the present invention, it is possible to provide a static type memory cell which can make a channel length of a driving transistor shorter than a channel length of an access transistor, and ensure operation stability with a high integrated body, and a method of manufacturing the same . [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Further, the present invention is not limited to the embodiments described below. Fig. 1 is a plan view and a cross-sectional view showing a static memory unit according to a first embodiment of the present invention. The third NMOS driving transistor 101 includes a third diffusion layer 119, a columnar semiconductor layer 149, and a fourth diffusion layer 107. A gate 125 is formed via a gate insulating film 113 on a side wall of a portion of the columnar semiconductor layer 149, the fourth diffusion layer 107, and the third diffusion layer 119 of the third OS driving transistor 101. The first NMOS transistor 103 includes a first diffusion layer 121, a pillar 12 323445 201230304 semiconductor layer 151, and a second diffusion layer 109. A gate electrode 126 is formed via a gate insulating film ι15 on a side wall of a portion of the first semiconductor layer 151, a portion of the second diffusion layer 109, and a portion of the first diffusion layer 121 of the first NMOS transistor 101. The gate height of the idler 125 is low near the third NM0S drive transistor. The physical gate length is shorter than the gate 126. The length between the first diffusion layer 121 and the second diffusion layer 109 forming the first NM0S access transistor 103 is the third diffusion layer ι19 and the fourth diffusion which form the third Radisson S drive transistor 1〇1. 2 times the length between layers 1Q7. Thereby, the current driving force of the driving transistor can be set to 2 poles of the current driving force of the access transistor without increasing the area, and the operation stability can be ensured. The first PM 〇 S load transistor 1 〇 2 semiconductor layer 150, the βth material β # diffusion layer 120, and the detection first layer 1Q8. In the first PMGS-loaded electric corrugated body, the columnar-rich conductor sound κ a ^ e ^ thousand conductor layer 150, one of the 苐5 diffusion layer 120, and the sixth diffusion layer 1 〇8 one of Qiu Ba, 卟之口 p-knife The sidewall is formed with a gate 125 via a gate insulating film 114. The third driving transistor 101 and the first surface carrying transistor (10) are connected by a gate 125. Further, the 13 diffusion layer 119, the fifth diffusion axe 120, and the i-th diffusion layer 121 are connected by a telluride (not shown). In the present drawing, 'in order to electrically insulate the third diffusion layer 119, the fifth diffusion layer 12, and the second diffusion layer 121 from the substrate, the s〇I substrate is used, but it may be electrically insulated. The si substrate can also be used to form p N junctions and to form electrical insulation using the reverse bias state of the PN junction. The fourth semiconductor driving transistor 106 includes a third diffusion layer 124, a pillar 323445 201230304 semiconductor layer, and a fourth diffusion layer 112. A gate electrode 128 is formed on the sidewall of a portion of the columnar semiconductor layer, one of the third diffusion layer 124, and the fourth diffusion layer 112 of the fourth NMOS driving transistor 106 via the gate insulating film 118. The second leg OS access transistor 1〇4 includes an i-th diffusion layer 122, a columnar semiconductor layer, and a second diffusion layer 11〇. A gate 127 is formed via a gate insulating film 116 on a side wall of a portion of the columnar semiconductor layer, the first diffusion layer, and the second diffusion layer 11 of the second NM0S access transistor 104. Although not shown, the length between the first diffusion layer 122 and the second diffusion layer 11 that forms the second NM〇s access transistor 〇4 is formed to form the fourth NMOS drive transistor 1〇6. The length between the third diffusion layer 124 and the fourth diffusion layer 112 is twice. The second PMOS load transistor 105 includes a fifth diffusion layer 123, a columnar semiconductor layer, and a sixth diffusion layer ill. A gate 128 is formed via a gate insulating barrier 117 on a side wall of a portion of the columnar semiconductor layer, one of the fifth diffusion layer 丨23, and the sixth diffusion layer ill of the second PM 〇 load transistor 105. The 4th NM0S driving transistor 106 and the 2nd PM〇s load are connected by the idler 125. Also, the first! The diffusion layer 122 carries the first electricity 123 and the third diffusion layer 124 is connected by a telluride (not shown). In the present embodiment, in order to electrically insulate the second diffusion layer 122, the fifth diffusion layer 123, and the third diffusion layer 124 from the substrate, an SOI substrate is used, but it may be electrically insulated, for example. It is also possible to use a substrate 'to form a PN junction, and to form an electrical insulation by using the reverse bias state of the continent joint to form 323445 14 201230304. A contact 13 is formed on the gate 125, and a contact 137 is formed on the second diffusion layer 122 and the fifth diffusion layer 123. The contacts 13A, 137 are connected by a metal 142. A contact member 39 is formed on the gate 128, and a contact 132 is formed on the fifth diffusion layer 120 and the first diffusion layer 121. The contacts 139, 132 are connected by a metal 144. A contact member 131 is formed on the sixth diffusion layer (10), a contact member 138 is formed on the sixth diffusion layer 111, and a metal 143 is connected to the contacts 131 and 138, and a power source is supplied. A contact member 129 is formed on the fourth diffusion layer 107, and a metal 141 is formed, and a power source is supplied. A contact 140' is formed on the fourth diffusion layer U2 and a metal 148' is formed and supplied with a power source. A contact 133' is formed on the second diffusion layer 109 and a metal 145 is formed as a bit line. A contact member 136 is formed on the second diffusion layer 11'', and a metal 210 is formed as a bit line. A contact 134 is formed on the gate 126, and a metal 146 is formed as a word line. A contact 135 is formed on the gate 127, and a metal 147 is formed as a word line. The plan view and the cross-sectional view of the static memory cell according to the second embodiment of the present invention are the same as those in Fig. 1. In this embodiment, the length between the third diffusion layer 119 and the fourth diffusion layer 1〇7 forming the third_s driving transistor 101 is the fifth diffusion layer 120 forming the first PMOS load transistor 1〇2. The length between the sixth diffusion layer 108 and the sixth diffusion layer 108 is short. In the SRAM, the load cell system of pM〇s is formed in a minimum size, and the current driving force of the load transistor formed as pM〇s is smaller than the current driving force of the access transistor of the NMOS. That is, the access transistor of the MN OS and the load transistor of the PM 〇s are 323445 201230304 f lengths are formed identically. Therefore, in the present invention, the channel length of the driving body 101 of the brain s is longer than the channel length of the driving transistor of pM 〇s. a (a) and (b) are cross-sectional views showing a static type memory cell in the third and fourth embodiments of the present invention. In the second diagram (a), the length between the upper end of the i-th diffusion layer 121 and the lower end of the second diffusion layer 109 forming the first NMOS OS 103 is set to form a third NM〇s driving power. = 1.3 times the length between the upper end of the third diffusion layer 119 of the body 101 and the lower end of the fourth diffusion layer 1〇7. In Fig. 2(b), the length between the upper end of the first diffusion layer 121 forming the second NM〇s access transistor 103 and the lower end of the second diffusion layer 1〇9 is set to form a third NM〇 s is three times the length between the upper end of the third diffusion layer 119 of the driving transistor 101 and the lower end of the fourth diffusion layer 1〇7. The shorter the channel length of the driving transistor is, the more stable the operation is, but if the square becomes shorter, a short channel effect is generated and the transistor cannot be cut off. Therefore, although it is possible to appropriately select according to the required requirements, for example, if it is set to the range of 13 times to 3 times as described above, the stability of the operation stability and the suppression of the short channel effect can be achieved. The plan view and the cross-sectional view of the static memory cell of the fifth and sixth embodiments of the present invention are the same as those of Figs. 2(a) and 2(b). In the fifth embodiment, the length between the upper end of the fifth diffusion layer 12A of the first PMOS load transistor 1〇2 and the lower end of the sixth diffusion layer 108 is set to form the third NMOS drive transistor 1〇1. The length between the upper end of the third diffusion layer 119 and the lower end of the fourth diffusion layer 107 is h3 times. In the sixth embodiment, the length between the upper end 323445 16 201230304 of the fifth diffusion layer 120 forming the first PMOS load transistor 1〇2 and the lower end of the sixth diffusion layer 108 is set to form the third CMOS 0S. The length between the upper end of the third diffusion layer 119 of the driving transistor i〇i and the lower end of the fourth diffusion layer 1〇7 is three times. The shorter the channel length of the driving transistor is, the more stable the operation is, but if one becomes shorter, a short channel effect is generated and the transistor cannot be cut off. Therefore, it can be appropriately selected according to the requirements. However, if the range is between 1.3 times and 3 times as described above, the stability of the operation and the suppression of the short-channel effect can be achieved. Fig. 3 is a cross-sectional view showing a static type memory climbing device according to a seventh embodiment of the present invention. The physical gate lengths of the gates 125, 126 are set as the viewers. Since the lengths of the gates 125 and 126 from the lower end to the upper end (that is, the length of the object) are the same, the above-described manufacturing method of the SGT can be used. After the columnar semiconductor layer is formed, the stacked gate is electrically conductive. The film is flattened and etched back to a desired length. Generally, the length of the channel is shortened as shown in Fig. 1, and the physical gate length is shortened. If the physical gate length is shortened, the gate capacitance will become smaller. If the capacitance between the electrodes becomes smaller, a soft error (soft. error) occurs, and # ensures the stability of the operation. On the other hand, in the third figure, only the driving electric crystal noise = flow driving force is shortened, and the physical gate length is the same, so that it will be driven. The channel length of the carcass is set to 2 times, and the gate capacitance is not reduced. That is, the current driving force of the force transistor can be set to the current drive of the access transistor, to ensure the stability of the operation, and to avoid soft errors, and to improve the stability of the action. Fig. 4 is a cross-sectional view showing the static type memory device of the eighth embodiment of the present invention, which is 133,445, and 30,230,304. In the embodiment of Fig. 4, the physical gate length is the same, and the upper end of the third diffusion layer 119 of the third NMOS drive crystal 101 is located above the first diffusion layer 121 of the first NMOS transistor 103. The upper end is higher. Thereby, the third NMOS driving transistor 101 can increase the overlapping capacitance between the gate 125 and the third diffusion layer 119. When the second NMOS driving transistor 101 is cut off, the overlapping capacitance between the gate 125 and the third diffusion layer 119 becomes a parasitic capacitance parasitic at the memory node, and since the overlapping capacitance is large, soft errors can be further avoided. Ensure the stability of the action. Fig. 5 is a plan view showing a static type memory unit according to a ninth embodiment of the present invention. The difference between the upper end of the third diffusion layer 119 of the third NMOS drive transistor 101 and the upper end of the first diffusion layer 121 of the first NMOS access transistor 103 is the same as that of the fourth embodiment. The lower end of the fourth diffusion layer 107 of the OS drive transistor 101 is lower than the lower end of the second diffusion layer 109 of the first OS access transistor 103. In the fifth embodiment, since only the channel length of the driving transistor is shortened, the physical gate length is the same. Therefore, although the current driving force of the driving transistor is doubled, the gate capacitance does not become small. Therefore, the current driving force of the driving transistor can be set to double the current driving force of the access transistor to ensure the stability of the operation, and the softness error can be avoided to ensure the stability of the operation. However, there is no further advantage as in FIG. 4, that is, when the second NMOS driving transistor 101 is cut off, the overlapping capacitance between the gate 125 and the third diffusion layer 119 becomes a parasitic capacitance parasitic at the memory node. Since the overlapping capacitance is large, soft errors can be further avoided, and the stability of the operation can be ensured. However, when the memory node is designed to come to the transistor 18 323445 201230304 in the manufacturer's second plant f is more to avoid the advantages of soft errors. However, it will be used later in the diffusion layer. In order to make the shape of Fig. 4, after the third entry #Μ Λ / main entry, a longer heat treatment is required. When the ion diffusion length is longer than 107, 'the diffusion layer of the third driving crystal 101 can be made by using the energy of the implantation or the diffusion layer 107# Ρ: the lower:::: The second 6th 缟 of the transistor 103 is low. That is, the heat treatment can be made less than that of Fig. 4. 1〇1 ^ ', the fourth figure is different, the upper end of the first diffusion layer 119 of the third NM0S driving transistor 103 is higher than the upper end of the first _S access transistor diffusion layer 12 ι '3rd art drive The lower end of the first diffusion layer 1〇7 of the transistor 103 is lower than the lower end of the second diffusion layer 1〇9 of the first recessed access transistor 103. In the embodiment of Fig. 6, since the length of the channel of the transistor is short: the channel length of the transistor is short, it is possible to ensure stable operation (4)/, and it is possible to avoid the soft error by the advantage of the fourth figure. Since ' θ 119 has a short diffusion length, it can be formed with lesser complexity than the fourth shape. When ion implantation: 1: diffusion: 107, the third NM0S driving transistor 1〇1 can be made to use the fourth, and the lower end of the layer 107 is used. The lower end of the second extension & 109 of the first NM0S access transistor 1〇3 is low. That is, the heat treatment can be made less than in Figure 4, and two <avoid soft errors. However, the manufacturing steps are increased as compared with the shape of Fig. 4 and the shape of Fig. 5. Although the above various types of bears are displayed, 323445 19 201230304 can be appropriately selected according to the requirements. Hereinafter, an example of a manufacturing procedure for forming the static memory cell structure of Fig. 4 of the embodiment of the present invention will be described with reference to Figs. 7 to 32. Fig. 7 shows that an oxide film 157 is formed on the crucible 152, and a planar crucible 158 is formed on the oxide film, and columnar crucibles 159, 160 having nitride film hard masks 162, 163, and 164 at the upper portions are formed, respectively. , the state of 161. From the state of Fig. 7, by depositing an oxide film and performing etch back, the oxide film sidewalls 165, 166, and 167 are formed as shown in Fig. 8. Then, a resist 168 for forming the third diffusion layer 119 is formed. In this state, arsenic is implanted as shown in Fig. 9 to form the third diffusion layer 119. Then, as shown in Fig. 10, the resist 168 is peeled off, and the oxide film side walls 165, 166, and 167 are peeled off to perform the first heat treatment. Further, as shown in Fig. 11, oxide film sidewalls 169, 170, and 171 are formed. Thereafter, a resist 172 for forming the first diffusion layer 121 is formed. In this state, as shown in Fig. 12, arsenic is implanted to form the first diffusion layer 121. Then, as shown in Fig. 13, the resist 172 is peeled off, and the oxide film side walls 169, 170, and 171 are peeled off to perform the second heat treatment. Since the third diffusion layer 119 is subjected to the secondary heat treatment, the upper end of the third diffusion layer 119 is higher than the upper end of the first diffusion layer 121. Thereby, the length of the channel of the driving transistor is shorter than the length of the channel of the access transistor, and the stability of the operation is ensured. 20 323445 201230304 Next, as shown in Fig. 14, oxide film sidewalls 173, 174, and 175 are formed. Then, a resist 176 for forming the fifth diffusion layer 120 is formed. In this state, as shown in Fig. 15, boron is implanted to form the fifth diffusion layer 120. From this state, as shown in Fig. 16, the resist 176 is peeled off, and the oxide film side walls 173, 174, and 175 are peeled off to perform heat treatment. Then, as shown in Fig. 17, a resist for forming element separation is formed, and etching is performed to remove the resist. Next, as shown in Fig. 18, an oxide film 153' is formed between the buried elements, and then a normal pressure CVD oxide film is deposited and etched back, whereby an oxide film 177 is formed. At this time, the oxide films 178, 179, and 180 remain on the nitride film hard masks 162, 163, and 164. Further, as shown in Fig. 19, the gate insulating films 113, 114, and 115 are formed, and the gate conductive film 181 is deposited and planarized. After the oxide films 178, 179, and 180 are exposed, the oxide films 178, 179, and 180 are etched and planarized, and the nitride film is hard-masked as a supporting member. The gate insulating film is one of an oxide film, a nitride film, an oxynitride film, and a high dielectric film. The gate conductive film is one of a polycrystalline stone, a laminated film of a metal and a polycrystalline stone, and a metal film. Next, as shown in Fig. 20, the gate insulating film 181 is reciprocated to obtain a desired physical gate length. As a result, the physical gate length is constant in all of the electromorphs. Then, an oxide film is deposited and a nitride film is deposited and etched to remain in a sidewall shape. As shown in FIG. 21, an insulating film sidewall formed of an oxide film 184 and a nitride film 185 is formed, and an oxide film 186 is formed. The nitride film 187 is formed by 323445 21 201230304 as an insulating film sidewall, and an insulating film sidewall formed of an oxide film 188 and a nitride film 189. Next, as shown in Fig. 22, resists 182, 183 for etching the gate are formed. Then, as shown in Fig. 23, the gate conductive film 181 is etched to form gates 125 and 126, and the oxide film 177 is etched to form oxide films 154 and 155, and the resists 182 and 183 are peeled off. Next, as shown in Fig. 24, the side wall of the insulating film made of the oxide film 184 and the tantalum nitride 185, the side wall of the insulating film made of the oxide film 186 and the nitride film 187, and the oxide film 188 and nitrogen are used. The sidewall of the insulating layer formed by the film 189 is etched. Further, a nitride film is deposited and etched to remain in a sidewall shape, and as shown in Fig. 25, nitride film sidewalls 190, 19, 192, 193, and 194 are formed. Next, as shown in Fig. 26, a resist 195 for forming the second diffusion layers 1?, 109 is formed. Then, as shown in Fig. 27, arsenic is ion-implanted to form the fourth diffusion layer 107 and the S 2 diffusion layer 1〇9. Then, as shown in Fig. 28, the resist 195 is peeled off to perform heat treatment. As shown in Fig. 29, a resist 196 for forming the sixth diffusion layer 108 is formed. Next, as shown in Fig. 3, boron is ion-implanted to form a sixth diffusion layer 108. Then, the resist 196 is peeled off as shown in Fig. 31 to perform heat treatment. Then, as shown in Fig. 32, the interlayer film 156 is deposited to form contacts 22 323445 201230304 pieces 129, 130, 131, 132, 133, 134, and metal 141, 142, 143, 144, 145, 146 are formed. The telluride may be formed on the third diffusion layer 119, the fifth diffusion layer 12A, and the first diffusion layer 121 before the formation of the interlayer film. Further, a small amount of the compound may be formed on the fourth diffusion layer 1A7, the sixth diffusion layer 108, and the second diffusion layer 109. From the above, it is known that the operation stability is ensured by making the channel length of the driving transistor shorter than the channel length of the access transistor. Furthermore, the manufacturing method of the aforementioned SGT can be used by making the physical gate length of the driving transistor the same as the physical gate length of the access transistor. That is, the current driving force of the driving transistor can be set to twice the current driving force of the access transistor to ensure the stability of the operation. See that the physical gate length is the same because only the channel length of the driving transistor is shortened. Therefore, although the current driving force of the driving transistor is doubled, the gate capacitance does not become small, so that soft errors can be avoided and the operation stability can be ensured. Furthermore, there is shown a manufacturing method for forming a structure in which the upper end of the third diffusion layer of the driving transistor is positioned higher than the upper end of the first diffusion layer of the access transistor. The driving electro-crystal system can increase the overlapping capacitance between the gate and the third diffusion layer, and can avoid soft errors and ensure the stability of operation. Hereinafter, an example of a manufacturing procedure for forming a static memory cell structure of Fig. 5 for forming a real target form of the present invention will be described with reference to Figs. 33 to 58, and Fig. 3 is a structure 157 in which an oxide film is formed. On the 157, a flat gasification w ^ is formed into a ten-faced 矽 158, and the shape of the 忐 忐 is in the upper part with a nitride film hard mask 16 t into a soap called kiss, 164 column-shaped stone eve 15 丨 323445 23 201230304 160, 16b Next, as shown in Fig. 34, the oxide film is deposited and etched back to form oxide film sidewalls 165, 166, and 167. Then, a resist 172 for forming the third diffusion layer 119 and the first diffusion layer 121 is formed. Further, as shown in Fig. 35, arsenic is implanted to form the third diffusion layer 119 and the first diffusion layer 12, and then, as shown in Fig. 36, the resist 172 is peeled off, and the oxide film sidewalls 165, 166, 167 are peeled off. To heat treatment. Next, as shown in Fig. 37, oxide film sidewalls 、3, 174, and 175 are formed. Thereafter, a resist 176 for forming the fifth diffusion layer 120 is formed. Then, as shown in Fig. 38, boron is implanted to form the fifth diffusion layer 120. Then, as shown in Fig. 39, the resist crucible 6 is peeled off, and the oxide film side walls 17 3, 17 4, 17 5 are peeled off to perform heat treatment. Then, as shown in Fig. 40, a resist for forming an element is formed, and etching is performed to remove the resist. Then, as shown in Fig. 41, the oxide film 153 is formed by embedding the elements, and then the atmospheric pressure CVD oxide film is deposited and etched back, whereby the oxide film 177 is formed. At this time, the oxide films 178, 179, and 180 remain on the nitride film hard masks 162, 163, and 164. Further, as shown in Fig. 42, the gate insulating films 113, 114, and 115 are formed, and the gate conductive film 181 is deposited and planarized. After the oxide films 178, 179, and 180 are exposed, the oxide films 178, 179, and 180 are etched and planarized, and the nitride film is hard masked as a stopper. The gate insulating film is one of an oxide film, a nitride film, an oxynitride film, and a high dielectric film. Gate Conductivity 24 323445 201230304 Film-type polycrystalline germanium, one of laminated film and metal film of metal and polycrystalline germanium. Next, as shown in Fig. 43, the gate insulating film 181 is etched back to obtain a desired physical gate length. As a result, the physical gate length was constant in all of the electric crystals. Then, as shown in Fig. 44, an oxide film is deposited, and a nitride film is deposited and etched to remain in a sidewall shape to form an insulating film sidewall formed of an oxide film I84 and a nitride film 185, and an oxide film 186 is formed. The sidewall of the insulating film formed of the nitride film and the sidewall of the insulating film composed of the oxide film 188 and the nitride film 189. Next, as shown in Fig. 45, resists 182, 183 for etching the gate side are formed. Then, as shown in Fig. 46, the gate conductive film 181 is surnamed to form gates 125 and 126, and the oxide film 177 is etched to form oxide films 154 and 155, and the resists 182 and 183 are peeled off. Next, as shown in Fig. 47, the side wall of the insulating film composed of the oxide film 184 and the nitride film 185, the side wall of the insulating film composed of the oxide film 186 and the nitride film 187, and the oxide film 188 and nitrogen are used. The sidewall of the insulating film formed by the film 189 is etched. Further, as shown in Fig. 48, the deposited nitride film is etched and left as a sidewall to form nitride film sidewalls 190, 191, 192, 193, and 194. Next, as shown in Fig. 49, a resist 201 for forming the fourth diffusion layer 1?7 is formed. Then, as shown in Fig. 50, arsenic or phosphorus is ion-implanted to form a fourth 323445 25 201230304 diffusion layer 107. When using arsenic, it is only necessary to increase the energy of ion implantation. Further, by using phosphorus having a long diffusion length, the lower end of the fourth diffusion layer 107 of the driving transistor 101 of the third semiconductor can be accessed from the second diffusion layer 109 of the transistor 103 by the first NM〇s. The lower end is low. Arsenic may be suitably used, or phosphorus may be used. Then, as shown in Fig. 51, the resist 2〇1 was peeled off to perform heat treatment. As shown in Fig. 52, a resist 202 for forming the second diffusion layer 1〇9 is formed. Next, as shown in Fig. 53, ion implantation of arsenic forms the second diffusion layer 109. Then, as shown in Fig. 54, the resist 2 2 was peeled off to perform heat treatment. Then, as shown in Fig. 55, a resist 203 for forming the sixth diffusion layer 1〇8 is formed. Next, as shown in Fig. 56, boron is ion-implanted to form a second diffusion layer 108. Then, as shown in Fig. 57, the resist 2〇3 is peeled off to perform heat treatment. Further, as shown in Fig. 58, the interlayer film 156 is deposited to form the contacts 129, 130, 13 132, 133, 134, and the metal 14 142, 143, 144, 145, 146 is formed. The telluride may be formed on the third diffusion layer 119, the fifth diffusion layer 120, and the second diffusion layer 121 before the formation of the interlayer film. Further, a telluride may be formed on the fourth diffusion layer 107, the sixth diffusion layer 1〇8, and the second diffusion layer 109. As described above, the operation stability can be ensured by making the channel length of the driving transistor shorter than the channel length of the access transistor, making the heat treatment less than the first drawing of 323445 26 201230304. As described above, the manufacturing method for forming the structures of FIGS. 4 and 5 is shown. However, for the structure shown in FIG. 6, the third expansion layer 119 of FIG. 4 and the diffusion of 帛1 can be formed by combination. The method of the layer 121 is formed by a method of forming the fourth diffusion layer 1〇7 and the second diffusion layer 1〇9 of Fig. 5 . Various embodiments and modifications can be made without departing from the spirit and scope of the invention. Further, the above-described embodiments are for explaining one embodiment of the present invention, and the technical scope of the present invention is not limited by the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(a) is a plan view showing a static type memory cell according to the first and second embodiments of the present invention, and Fig. 1(b) is a cross section of the line (a) of Fig. Figure. Fig. 2(a) is a cross-sectional view showing a static type memory cell according to the third and fifth embodiments of the present invention. Fig. 2(b) is a cross-sectional view showing a static type memory cell according to the fourth and sixth embodiments of the present invention. Fig. 3 is a cross-sectional view showing a static type memory unit according to a seventh embodiment of the present invention. Fig. 4 is a cross-sectional view showing a static type memory unit according to an eighth embodiment of the present invention. Fig. 5 is a cross-sectional view showing a static type memory unit according to a ninth embodiment of the present invention. Fig. 6 is a cross-sectional view showing the static type memory of the first embodiment of the present invention. 27 323 445 201230304 Figure 7 is a cross-sectional view showing a method of manufacturing a static type memory cell for performing cancer in the present invention. Figure 8 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Fig. 9 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Fig. 10 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 11 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 12 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 13 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Fig. 14 is a plan view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 15 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 16 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 18 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. 28 323445 201230304 Figure W is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Fig. 2 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 21 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 22 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 23 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 24 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 25 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 26 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 27 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 28 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 29 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 30 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. 29 323445 201230304 FIG. 31 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 32 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 33 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 34 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 35 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 36 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 37 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 39 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 40 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Fig. 4 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 42 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. 323445 30 201230304 Figure 43 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 44 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 45 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 46 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Fig. 47 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 48 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 49 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 50 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 51 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 52 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 53 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 54 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. 31 323445 201230304 Fig. 55 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. Figure 56 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 57 is a cross-sectional view showing a method of manufacturing a static memory cell in accordance with an embodiment of the present invention. Figure 58 is a cross-sectional view showing a method of manufacturing a static memory cell according to an embodiment of the present invention. [Main component symbol description] 101 102 103 104 105 106 107 108 109 110 111 112 113 119 120 114, 115 124 123 3rd NMOS drive transistor 1st PMOS load transistor 1st MOS drive crystal 2nd OS save The second PMOS-loaded transistor, the fourth PMOS-loaded transistor, the fourth diffusion layer, the sixth diffusion layer, the second diffusion layer, the second diffusion layer, the sixth diffusion layer, the fourth diffusion layer 116, 117, and 118, the gate insulating film 3 diffusion layer 5th diffusion layer 32 323445 201230304 121 '122 1st diffusion layer 125, 126, 127, 128 gate 129, 130, 13 128 132, 133, 134 contact 135, 136, 137, 138, 139, 140 Contact member 14 142, 143, 144, 145, 146, 147, 148, 210 metal 149, 150, 151 columnar semiconductor layer 152, 158, 160, 161 矽 153, 154, 155, 177, 178, 179, 180 184, 186, 188 oxide film 156 deposition interlayer film 157 oxide film 162, 163, 164 nitride film hard mask 165, 166, 167, 169, 170, 171, 173, 174, 175 oxide film sidewalls 168, 172 176, 195 Resistor 185, 187, 189 nitride film 190, 191, 192, 193, 194 nitride film sidewall 33 323445