Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/62—Capacitors having potential barriers
  • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors

Definitions

• This invention relates to the field of electronic capacitors.
• Electronic capacitors may operate over a range of temperatures. It may be desirable to form a capacitor which exhibits substantially constant capacitance over an operational temperature range.
• FIGS. 1A through 1H are cross-sectional views of an integrated circuit having ZTC capacitors formed according to embodiments, depicted in successive stages of fabrication.
• FIG. 2 is a chart of measured temperature coefficients of capacitors as a function of phosphorus density in dielectric layers of the capacitors.
• a zero temperature coefficient (ZTC) capacitor may include a lower conducting plate, a capacitor dielectric layer and an upper conducting plate.
• a capacitance of the ZTC capacitor may vary over a temperature range.
• a temperature coefficient K T of the ZTC capacitor may be estimated by fitting measured capacitance values of the ZTC capacitor at more than one temperature in the temperature range to the expression of Equation 1 :
• C (T) C (T REF ) X [ 1 + ( K T X ( T - T REF ) ] ] ; Equation 1 wherein C (T) is a capacitance value at a temperature T, and T REF is a reference temperature, for example 27 °C.
• Phosphorus may be placed into the capacitor dielectric layer to obtain a phosphorus atom density between 1.7 ⁇ 10 20 atoms/cm 3 and 2.3 ⁇ 1020 atoms/cm 3.
• Work performed in association with the instant invention indicate the temperature coefficient ⁇ of the ZTC capacitor may be between -1 ppm/°C and 1 ppm/°C.
• the ZTC capacitor may be formed as part of an integrated circuit.
• the bottom plate may include gate material used to form a gate of a metal oxide semiconductor (MOS) transistor in the integrated circuit.
• MOS metal oxide semiconductor
• the bottom plate may include metal used to form interconnects in the integrated circuit.
• TiSiN describes a material containing titanium (Ti), silicon (Si) and nitrogen (N), not necessarily having a Ti:Si:N atomic ratio of 1 : 1 : 1.
• Terms describing elemental formulas of materials with subscripts imply a stoichiometry given by the subscripts.
• Si0 2 describes a material containing silicon and oxygen (O) having a Si:0 atomic ratio substantially equal to 1 :2.
• the integrated circuits containing a ZTC capacitor substantially the entire integrated circuit is dedicated to the ZTC capacitor.
• the integrated circuits may contain another active component such as a metal oxide semiconductor (MOS) transistor.
• MOS metal oxide semiconductor
• FIGS. 1A-1H illustrate an integrated circuit containing ZTC capacitors formed according to embodiments, depicted in successive stages of fabrication.
• the integrated circuit 1000 is formed in and on a substrate 1002, which may be a single crystal silicon wafer, but may be a silicon-on- insulator (SOI) wafer, a hybrid orientation technology (HOT) wafer with regions of different crystal orientations, a semiconductor wafer of another material such as gallium arsenide, or other material appropriate for fabrication of the IC 1000.
• the substrate 1002 may include an electrically insulating layer such as ceramic, crystalline aluminum oxide, glass, plastic or other non-conducting material.
• a first electrically conducting layer 1008 is formed on the substrate 1002, possibly contacting the field oxide elements 1004 if present and possibly contacting the gate dielectric layer 1006 if present.
• the first electrically conducting layer 1008 may include material such as polycrystalline silicon for forming a gate of the MOS transistor.
• a MOS gate 1012 may be formed from the first electrically conducting layer 1008 of FIG. 1A, concurrently with the first capacitor lower plate 1010.
• sidewall spacers 1014 may be formed, for example of silicon nitride or layers of silicon nitride and silicon dioxide, on lateral surfaces of the first capacitor lower plate 1010, and on lateral surfaces of the MOS gate 1012 if formed.
• source and drain regions 1016 may be formed in the substrate 1002 adjacent to the MOS gate 1012.
• an optional metal silicide layer 1018 may be formed at a top surface of the first capacitor lower plate 1010.
• a metal silicide layer 1020 may be formed at a top surface of the MOS gate 1012.
• the metal silicide layers 1018 and 1020 if present may be formed by depositing a layer of metal, such as nickel, cobalt or titanium, on a top surface of the integrated circuit 1000, heating the integrated circuit 1000 to react a portion of the metal with exposed polycrystalline silicon, and selectively removing unreacted metal from the integrated circuit 1000 surface, for example by exposing the integrated circuit 1000 to wet etchants including a mixture of an acid and hydrogen peroxide.
• a first capacitor dielectric layer 1022 is formed on the integrated circuit 1000.
• the first capacitor dielectric layer 1022 is composed of silicon dioxide, possibly including other elements such as carbon or fluorine.
• a total density of atoms in the first capacitor dielectric layer 1022 other than silicon and oxygen is less than l x lO 18 atoms/cm 3 .
• the first capacitor dielectric layer 1022 may be between 10 and 200 nanometers thick. In one realization of the instant embodiment, the first capacitor dielectric layer 1022 may be between 45 and 55 nanometers thick.
• the first capacitor dielectric layer 1022 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), high density plasma (HDP), an ozone based thermal chemical vapor deposition (CVD) process, also known as the high aspect ratio process (HARP), or other suitable silicon dioxide layer formation process deposition.
• the first capacitor dielectric layer 1022 may be formed by decomposition of tetraethyl orthosilicate, also known as tetraethoxysilane or TEOS, or deposition of methylsilsesquioxane (MSQ).
• a first phosphorus placement process 1024 is performed which places phosphorus atoms in the first capacitor dielectric layer 1022.
• the first phosphorus placement process 1024 is adjusted to provide an average density of phosphorus atoms in
• the first phosphorus placement process 1024 may be an ion implantation process; an implantation energy of the first phosphorus placement process 1024 may be adjusted to place a peak of a distribution of the implanted phosphorus atoms approximately in a center of the first capacitor dielectric layer 1022.
• the implantation energy of the first phosphorus placement process 1024 may be set between 10 and 20 kiloelectron-volts (keV).
• the first phosphorus placement process 1024 may include exposing the integrated circuit 1000 to a phosphorus containing gas at a temperature above 300 C. In another realization, the first phosphorus placement process 1024 may include exposing the integrated circuit 1000 to a phosphorus containing plasma. In a further realization, phosphorus may be placed in the first capacitor dielectric layer 1022 by other means.
• the first capacitor dielectric layer 1022 may optionally be patterned and etched to form a boundary proximate to a boundary of the first capacitor lower plate 1010, as depicted in FIG. IE.
• a first capacitor upper plate 1026 is formed on the first capacitor dielectric layer 1022.
• the first capacitor upper plate 1026 is formed of electrically conducting material, such as metal or doped semiconductor material.
• the first capacitor upper plate 1026 may include Ti, TiN, TiSiN, Ta, TaN, TaSiN, W, WN, WSiN, or any combination thereof, between 50 and 400 nanometers thick.
• the first capacitor upper plate 1026 may include aluminum, copper, gold or other metal used for interconnects in the integrated circuit 1000, between 50 and 500 nanometers thick.
• the gate dielectric layer 1006, MOS gate 1012 and source and drain regions 1016, if present, are part of a MOS transistor 1030 formed in and on the substrate 1002.
• a second ZTC capacitor may be formed in the integrated circuit 1000 in an interconnect region above the substrate 1002, as described in reference to FIG. IF through FIG. 1H.
• a first interconnect dielectric layer 1032 is formed on the integrated circuit 1000.
• the first interconnect dielectric layer 1032 may include one or more layers of silicon dioxide, silicon nitride, organo-silicate glass (OSG), carbon-doped silicon oxides (SiCO or CDO), fluorosilicate glass (FSG), or other dielectric material.
• the first interconnect dielectric layer 1032 may include one or more layers of metal interconnect elements such as metal lines of aluminum, copper and/or gold, and vias of aluminum, copper, gold, and/or tungsten. Metal interconnect elements in the first interconnect dielectric layer 1032 are not shown in FIG. IF.
• a second capacitor lower plate 1034 is formed on the first interconnect dielectric layer 1032.
• the second capacitor lower plate 1034 is formed of electrically conductive material, such as metal or doped semiconductor material.
• An optional metal interconnect line 1036 may be formed on the first interconnect dielectric layer 1032.
• the second capacitor lower plate 1034 may be formed concurrently with the metal interconnect line 1036.
• the second capacitor lower plate 1034 and metal interconnect line 1036 if formed may include aluminum, copper and/or gold.
• a second capacitor dielectric layer 1038 is formed on the integrated circuit 1000 as described in reference to FIG. ID. Material properties and possible formation processes of the second capacitor dielectric layer 1038 are as described in reference to FIG. ID.
• a thickness of the second capacitor dielectric layer 1038 may be different from the thickness of the first capacitor dielectric layer 1022. In an alternate realization, the thickness of the second capacitor dielectric layer 1038 may substantially equal to the thickness of the first capacitor dielectric layer 1022.
• the formation process of the second capacitor dielectric layer 1038 may use process parameters different from those of the first capacitor dielectric layer 1022.
• a second phosphorus placement process 1040 is performed which places phosphorus atoms into the second capacitor dielectric layer 1038.
• the second phosphorus placement process 1040 is adjusted to provide a phosphorus density as described in reference to FIG. ID.
• the second phosphorus placement process 1040 may be an ion implantation process, as described in reference to FIG. ID.
• the second phosphorus placement process 1040 may be a diffusion process from a phosphorus containing gas as described in reference to FIG. ID.
• the second phosphorus placement process 1040 may be include exposure to a phosphorus containing plasma, as described in reference to FIG. ID.
• the phosphorus may be placed in the second capacitor dielectric layer 1038 by other means.
• the second capacitor dielectric layer 1038 may optionally be patterned and etched to form a boundary proximate to a boundary of the second capacitor lower plate 1034, as depicted in FIG. 1H.
• a second capacitor upper plate 1042 is formed on the second capacitor dielectric layer 1038.
• the second capacitor upper plate 1042 is formed of electrically conductive material such as metal or doped semiconductor material.
• the second capacitor upper plate 1042 may include Ti, TiN, TiSiN, Ta, TaN, TaSiN, W, WN, WSiN, or any combination thereof, between 50 and 400 nanometers thick.
• the second capacitor upper plate 1042 may include aluminum, copper, gold or other metal used for interconnects in the integrated circuit 1000, between 100 and 2000 nanometers thick.
• the second capacitor lower plate 1034, the second capacitor dielectric layer 1038 with a phosphorus density between 1.7 ⁇ 10 20 atoms/cm 3 and 2.3x 1020 atoms/cm 3 and the second capacitor upper plate 1042 form a second ZTC capacitor 1044.
• An optional second interconnect dielectric layer 1046 may be formed over the second ZTC capacitor 1044.
• the second interconnect dielectric layer 1046 if formed may include materials described in reference to the first interconnect dielectric layer 1032.
• the second interconnect dielectric layer 1046 may include one or more layers of metal interconnect elements such as metal lines of aluminum, copper and/or gold, and vias of aluminum, copper, gold, and/or tungsten. Metal interconnect elements are not shown in FIG. 1H.
• FIG. 2 is a chart of measured temperature coefficients of capacitors as a function of phosphorus density in dielectric layers of the capacitors. Data in FIG. 2 are from work performed in association with the instant invention, using a capacitor dielectric layer approximately 50 nanometers thick, and ion implanted with phosphorus at an ion implant energy of 16 keV. It will be recognized by one familiar with fabricating capacitors, having reference to the data shown in FIG. 2, that providing a phosphorus
• density between 1.7 X 10 atoms/cm and 2.3x 10 atoms/cm may provide a temperature coefficient between -1 ppm/°C and 1 ppm/°C.

Landscapes

• Semiconductor Integrated Circuits (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Priority Applications (2)

Applications Claiming Priority (4)

Publications (2)

Family

ID=45972260

Family Applications (1)

Country Status (4)

Cited By (1)

Families Citing this family (6)

Family Cites Families (15)

• 2011
  • 2011-10-06 US US13/267,674 patent/US8373215B2/en active Active
  • 2011-10-25 WO PCT/US2011/057672 patent/WO2012061126A2/en not_active Ceased
  • 2011-10-25 CN CN201180051289.4A patent/CN103180947B/zh active Active
  • 2011-10-25 JP JP2013536720A patent/JP5961618B2/ja active Active

Also Published As

Similar Documents

Legal Events