WO2012042442A1 - Semiconductor device with a gate stack - Google Patents

Semiconductor device with a gate stack Download PDF

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Publication number
WO2012042442A1
WO2012042442A1 PCT/IB2011/054162 IB2011054162W WO2012042442A1 WO 2012042442 A1 WO2012042442 A1 WO 2012042442A1 IB 2011054162 W IB2011054162 W IB 2011054162W WO 2012042442 A1 WO2012042442 A1 WO 2012042442A1
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WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor device
dopant
passivation layer
gate stack
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PCT/IB2011/054162
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French (fr)
Inventor
Caroline Andersson
Jean Fompeyrine
Chiara Marchiori
David J. Webb
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International Business Machines Corporation
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Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Priority to GB1306306.0A priority Critical patent/GB2497257B/en
Priority to DE112011103249.8T priority patent/DE112011103249B4/en
Priority to CN201180046652.3A priority patent/CN103125014B/en
Priority to JP2013529752A priority patent/JP5752254B2/en
Publication of WO2012042442A1 publication Critical patent/WO2012042442A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the present invention relates to a semiconductor device comprising a gate stack structure and a method of fabrication therefor.
  • the present invention also extends to the use of a gate stack structure in a semiconductor device.
  • MOSFETs metal oxide semiconductor field effect transistors
  • germanium has proved an attractive candidate. Due to its higher charge carrier mobility as compared to Si, Ge provides a relatively increased scope of downscaling and integration per chip.
  • Another factor is that, for the fabrication of Ge-based MOSFETs, lower processing temperatures are used as compared to Si- based MOSFETs, for example, approximately 400 - 500°C in the case of Ge-based MOSFETs as compared to approximately 900 - 1000°C for Si-based MOSFETs, which feature makes such devices attractive for integration in advanced semiconductor devices.
  • germanium oxide (Ge0 2 ) is less stable on Ge compared to silicon dioxide (Si0 2 ) on Si.
  • a material that has a dielectric constant (k) relative to a vacuum, which is greater in magnitude than 7 is used, such a material being hereinafter referred to as a "high k” material and an example of which is, hafnium oxide (Hf0 2 ).
  • the Si interfacial layer is partially oxidised to yield an upper Si0 2 layer at the processing temperatures, approximately 150°C, at which the high k material is deposited. In this way, a gate structure of Ge/Si/Si0 2 /Hf0 2 is made.
  • Ge-based p- channel MOSFETs incorporating such a gate structure have exhibited improved device characteristics, such as, for example, a lower equivalent oxide thickness (EOT), over previously-proposed Ge-based p-channel devices in which such a structure is absent.
  • EOT equivalent oxide thickness
  • a consideration for such devices is that the channel is not substantially turned off when no voltage is applied to the gate, i.e. at zero gate bias. This may, amongst other things, make such devices unattractive for use in applications and/or incorporation into advanced devices where controllable and reliable switching between on and off states may be desired, for example.
  • a further consideration for such devices is that, whilst the observed shift in V m may be counteracted by, for example, increasing the thickness of the Si interfacial layer, such an action may cause a correspondingly increased EOT value, which is undesirable from the viewpoint of the current trend towards reducing the lateral sizing of field effect transistors (FETs).
  • V T H is substantially constant for different Si monolayer thicknesses.
  • the V T H values in this case, approximately -20mV, are still not considered to be beneficial for p-MOSFETs, for example.
  • US7446380B2 discloses a material stack comprising: a hafnium-based dielectric; an electrically conductive capping layer comprising at least one of Ce, Y, Sm, Er and Tb located above the hafnium-based dielectric; and a Si-containing conductor located directly on the electrically conductive capping layer.
  • the disclosed material stack addresses the problem of the non-ideal threshold voltages obtained in, for example, Si-based n-type MOSFETs fabricated with a hafnium-based dielectric when the material stack is incorporated in such a MOSFET.
  • the rare-earth containing capping layer is formed on the hafnium-based dielectric in the disclosed material stack, a consideration may be that this may introduce structural and/or fabrication complexity in that, the suitability of the rare- earth metal relative to the underlying hafnium-based dielectric and overlying gate material has to be assessed - such issues may also, of course, impact the ease with which such structures may be integrated in advanced semiconductor devices and/or use in related applications, for example.
  • a further consideration may be that the performance of the rare-earth metal is dependent on the chemical nature of the hafnium-based dielectric.
  • a still further consideration may be that, since the rare-earth metal is diffused through the gate stack, this may introduce further processing issues.
  • a semiconductor device comprising a gate stack structure, the gate stack structure comprising: at least a substrate comprising a semiconductor that is substantially doped with n-type carriers; at least a passivation layer comprising silicon formed on the substrate , and at least an insulator layer formed on the passivation layer, wherein the gate stack structure further comprises: at least an interlayer dopant provided between the substrate and the passivation layer, the interlayer dopant comprising an n-type dopant that is selected to facilitate control of a threshold voltage applicable to the gate stack structure when the semiconductor device is in use.
  • an interlayer dopant is provided between the substrate and the passivation layer in the layer configuration of an embodiment of the present invention.
  • the interlayer dopant comprises n-type dopant atoms, which ionise to yield a fixed sheet of positively-charged dopant ions.
  • a more negative value of threshold voltage is applicable to an embodiment of the present invention in order to induce a conducting channel in the substrate compared to previously-proposed devices and/or in the absence of the interlayer dopant in an embodiment of the present invention.
  • an embodiment of the present invention is suited for applications and/or advanced devices where controllable and reliable switching between on and off states may be desired.
  • An advantage of an embodiment of the present invention compared to previously-proposed devices is that a shift in the threshold voltage to a desired value is not achieved by changing the gate metal in order to manipulate the metal work function, which action would have undesirable consequences such as, for example, increasing the number of processing steps and constraints being placed on the choice of gate metal that is used since the compatibility of the gate metal with the materials of the layers in the gate stack may need to be assessed.
  • a further advantage of an embodiment of the present invention is that the desired shift in the threshold voltage is not facilitated by adding a layer of an oxide with fixed charges to, for example, the insulator layer which action would restrict scaling of such a layer.
  • the n-type dopant is substantially provided in a region adjacent to a conducting channel formed in the substrate when the semiconductor device is in use.
  • the mobility of carriers in the substrate may be substantially preserved since the conducting channel need not be counter-doped in order to facilitate control of the threshold voltage. The latter would lower the carrier mobility on account of the Coulomb scattering which would occur due to ionised impurities.
  • a concentration of the n-type dopant is chosen to control a magnitude of the threshold voltage.
  • a magnitude of the shift of the threshold voltage is dependent on the number of n-type dopant atoms per unit area.
  • a threshold voltage value that ensures a lower off current may be preferable.
  • the threshold voltage value of the first-described performance version would be lower than the latter described version.
  • An embodiment of the present invention offers the advantage that the threshold voltage value may be tuned to the appropriate value for each version via the concentration of n-type dopant, i.e. an extent of the shift of the threshold voltage to be more positive or negative as required by the different performance versions may be tailored by choosing a corresponding concentration of n-type dopant.
  • the n-type dopant is selected to at least compensate for interfacial charges present at an interface between the substrate and the passivation layer.
  • the n-type dopant is selected to at least compensate for interfacial charges at an interface between the passivation layer and the insulator layer.
  • interfacial charges atoms may diffuse from the substrate to the interface between the passivation layer and the insulator layer and result in the formation of negatively-charged traps at that interface. These negatively-charged traps have been implicated in contributing to the observation of the above-described positive shift in the threshold voltage.
  • An embodiment of the present invention provides the advantage that the positively-charged dopant ions substantially compensate for the negative charge on these traps and, therefore, facilitate a negative shift in the threshold voltage.
  • the n-type dopant is selected to at least compensate for charges in the passivation layer, insulator layer or a combination thereof.
  • An embodiment of the present invention offers the advantage of substantially compensating for the charges in the passivation layer, in the insulator layer or a combination thereof, which charges may be implicated in causing a positive shift in the threshold voltage.
  • the n-type dopant comprises one of: arsenic (As), phosphorous (P), antimony (Sb) and bismuth (Bi).
  • As arsenic
  • P phosphorous
  • Sb antimony
  • Bi bismuth
  • compensation of the negatively-charged interfacial charges and/or defects between and/or in the different layers in an embodiment of the present invention by the fixed sheet of positively-charged dopant ions does not necessitate the diffusion of the n-type dopant across the gate stack structure or specific layers thereof by, for example, thermal processing.
  • the n-type dopant material is also chosen on account of having a reduced diffusion coefficient value in the substrate and/or passivation layer, such that it remains at the substrate-passivation layer interface during the possible high-temperature processing in subsequent steps after provision of the interlayer dopant.
  • the n-type dopant is chosen to comprise one of the following elements from Group V of the Periodic Table: As, P, Sb and Bi. These materials have the following diffusivity (D) characteristics in Ge: D(As)>D(Sb)>D(P).
  • n-type dopant offers the particular advantage that, since the technology for its implantation in source and drain electrodes is developed, the step to introduce it as a surface dopant of the channel region, as is done in an embodiment of the present invention, would not unduly cause fabrication complications.
  • the semiconductor device comprises a field-effect transistor.
  • a desired shift in the threshold voltage is achieved by incorporating an interlayer dopant comprising an n-type dopant in the gate stack rather than, for example, increasing the number of silicon monolayers in the passivation layer.
  • the thickness of the layers in the gate stack, in particular, the passivation layer may be further reduced in an embodiment of the present invention compared to previously-proposed devices.
  • This feature supports the general trend in the semiconductor industry towards reducing the lateral sizing of semiconductor devices, in particular, FETs, since a reduced physical stack thickness and lower EOTs may be attainable with an embodiment of the present invention compared to previously- proposed devices.
  • An embodiment of the present invention is particularly applicable to MOSFETs, for example, p-channel MOSFETs.
  • the insulator layer comprises a dielectric material having an effective dielectric constant that is greater in magnitude than 7.
  • a high-k material is chosen on account of, for example, being thermally stable over a broad range of temperatures.
  • hafnium-based dielectrics such as hafnium oxide are used for the high-k material in the insulator layer.
  • an embodiment of the present invention is not limited to the use of hafnium-based dielectrics and, indeed, any other dielectric material having an effective dielectric constant that is greater in magnitude than 7, may be used in the insulator layer.
  • the insulator layer may further comprise an Si0 2 layer disposed between the passivation layer and the high-k material. It may be formed due to the processing conditions used for the deposition of the high-k material on the passivation layer.
  • An embodiment of the present invention also encompasses the scenario where the insulator layer does not further comprise such an oxide layer.
  • the substrate comprises germanium (Ge), germanium-on-insulator (GOI), silicon-germanium-on-insulator (SiGe-OI) or any combination thereof.
  • germanium Ge
  • germanium-on-insulator GOI
  • SiGe-OI silicon-germanium-on-insulator
  • a method for fabricating a gate stack structure in a semiconductor device comprising the steps of: forming at least a substrate comprising a semiconductor that is substantially doped with n-type carriers; forming at least a passivation layer comprising silicon on the substrate, and forming at least an insulator layer on the passivation layer, the method further comprising the step of: providing at least an interlayer dopant between the substrate and the passivation layer, the interlayer dopant comprising an n-type dopant that is selected to facilitate control of a threshold voltage applicable to the gate stack structure when the semiconductor device is in use.
  • a gate stack structure in a semiconductor device, the gate stack structure comprising: at least a substrate comprising a semiconductor that is substantially doped with n-type carriers; at least a passivation layer comprising silicon formed on the substrate, and at least an insulator layer formed on the passivation layer, wherein the gate stack structure further comprises: at least an interlayer dopant provided between the substrate and the passivation layer, the interlayer dopant comprising an n-type dopant that is selected to facilitate control of a threshold voltage applicable to the gate stack structure when the semiconductor device is in use.
  • FIG. 1 schematically illustrates an embodiment of the present invention
  • Figure 2 schematically illustrates the drain-current versus gate-voltage characteristics for a Ge-based p-channel MOSFET incorporating a previously-proposed gate-stack structure
  • Figure 3 schematically illustrates the drain-current versus gate-voltage characteristics for a Ge-based p-channel MOSFET according to an embodiment of the present invention
  • FIG. 4 schematically illustrates an embodiment of a method aspect of the present invention. Detailed description of preferred embodiments
  • Figure 1 schematically illustrates a gate stack structure 1 according to an embodiment of the present invention.
  • a substrate 10 comprising a semiconductor that is substantially doped with n-type carriers; a passivation layer 12 comprising silicon formed on the substrate; an insulator layer 13 comprising a high-k material formed atop the passivation layer 12 and, provided between the substrate 10 and the passivation layer 12 is an interlayer dopant, which comprises an n-type dopant 1 1.
  • the substrate 10 comprises Ge doped with, for example, between 1 e15 and 1 e18 n-type carriers and for the high-k material in the insulator layer 13, Hf0 2 is used.
  • the different layers in the gate stack structure 1 are formed at room temperature. At this temperature, the As dopant atoms ionise to form a fixed sheet of positively-charged dopant ions.
  • the positive charge of the dopant ions substantially compensates for the negative charges associated with interfacial charges and/or defects at the different interfaces between the layers of the gate stack structure 1.
  • the positive charge of the dopant ions compensates for the negative charge associated with charged defects caused by the migration of, for example, Ge from the substrate 10 to an interface between the passivation layer 12 and the insulator layer 13 and for dipoles present at the same interface.
  • the negative charges associated with the charged defects and/or dipoles have been implicated in causing a positive shift of the threshold voltage in previously-proposed devices and so the compensation thereof in an embodiment of the present invention is desirable from the viewpoint that this effect causes a negative shift of the threshold voltage.
  • the compensation effect of an embodiment of the present invention also extends to the compensation of charges/defects/dipoles at the substrate 10-passivation layer 12 interface and/or within the different layers of the gate stack structure 1 either respectively or in combination.
  • An embodiment of the present invention may also address other phenomena that cause the undesirable positive shift in the threshold voltage to be observed, for example, correction for the metal work functions, etc.
  • an embodiment of the present invention also facilitates control of the magnitude of this shift, that is, the extent to which it is positive or negative. This is because the magnitude of the shift of the threshold voltage is dependent on the number of n-type dopant atoms 1 1 per unit area. Thus, by raising or lowering the concentration of n-type dopant atoms 1 1 , a shift of the threshold voltage to a desired extent can be controlled in an embodiment of the present invention.
  • n-type dopant 11 a material that facilitates the above-described compensation effect whilst also having a reduced diffusion coefficient value in the substrate and/or passivation layer is desirable.
  • Materials that satisfy these criteria and that are chosen for the n-type dopant in an embodiment of the present invention comprise As, P, Sb and Bi from Group V of the Periodic Table.
  • the gate stack structure 1 has been described with reference to the use of Ge for the substrate 10, an embodiment of the present invention is, of course, not only limited to the use of such a material.
  • the substrate 10 may comprise Ge, GOI, SiGe-OI or any combination thereof.
  • the gate stack structure 1 has been described with reference to the use of Hf0 2 for the dielectric material in the insulator layer 13
  • an embodiment of the present invention is not limited to the use of Hf0 2 and any other hafnium-based dielectric may be used.
  • any dielectric material having an effective dielectric constant that is greater in magnitude than 7 may be used.
  • Figure 2 illustrates the drain-current (Id) versus gate-voltage (Vg) characteristics of a Ge-based p-channel MOSFET incorporating a previously-proposed gate stack structure.
  • the layer configuration of the previously-proposed gate stack structure from bottom to top is: a substrate comprising n-doped Ge, a passivation layer comprising Si and an insulator layer comprising Hf0 2 .
  • Figure 3 illustrates the Id versus Vg characteristics of a Ge-based p-channel MOSFET incorporating a gate stack structure 1 according to an embodiment of the present invention, such as that shown in Figure 1 and hereinbefore described in which an interlayer dopant comprising As for the n-type dopant 1 1 is provided between the substrate 10 and the passivation layer 12.
  • an interlayer dopant comprising As for the n-type dopant 1 1 is provided between the substrate 10 and the passivation layer 12.
  • the respective devices were fabricated in a self-aligned gate first ring FET process with source and drain contacts being made out of nickel (Ni) and the gate contact being made of platinum (Pt).
  • n-type dopant 1 1 in this case, facilitates a negative shift in the threshold voltage by compensating for the negative charges/defects/dipoles at and/or in the different layers in the gate stack structure 1.
  • a substrate 10 comprising a semiconductor substantially doped with n-type carriers is provided.
  • the substrate 10 comprises n-type doped Ge.
  • a step S1 in-situ cleaning of a surface of the n-type doped Ge substrate 10 is done.
  • an interlayer dopant comprising an n-type dopant 1 1 , which in the present example is As, is provided on the cleaned surface of the n-type doped Ge substrate 10.
  • approximately up to one monolayer of the As atoms may be deposited, this being effectuated by a deposition time of, for example, 2 seconds.
  • a step S3 formation of the passivation layer 12 comprising silicon is done atop the substrate 10 modified by the provision of the n-type dopant 1 1 .
  • the passivation layer 12 may have a thickness of approximately 1.5nm, for example.
  • deposition of an insulator layer 13 comprising a high-k material is done.
  • An example of a high-k material in an embodiment of the present invention is a hafnium-based dielectric, such as, for example, Hf0 2 .
  • a thickness of the Hf0 2 layer is 4nm, for example.
  • the insulator layer 13 may also comprise a silicon dioxide layer that is disposed between the passivation layer 12 and the high-k dielectric material.
  • the silicon dioxide layer in the insulator layer 13 is formed by the oxidation of the silicon in the passivation layer 12 due to the processing conditions that are used for the deposition of the high-k material in step S4.
  • Steps S1 to S4 are performed in a vacuum environment, specifically an ultra-high vacuum (UHV) environment, without breaking such an environment, so that contamination may be reduced and/or avoided.
  • At least one of the steps S1 to S4 may be performed with molecular beam epitaxy (MBE), which offers the advantage of enabling controllable deposition of small amounts of material at reduced temperatures, such as, for example, room temperature.
  • MBE molecular beam epitaxy
  • steps S1 to S4 are performed at room temperature.
  • Si is deposited at 150 ° C for 1 minute and, in step S4, Hf0 2 is deposited at 225 ° C for 15 minutes.
  • Additional steps for source and drain activation anneals are performed at 350 ° C for 5 minutes.
  • the As atoms substantially remain at the Ge-Si interface.
  • a method according to an embodiment of the present invention is not limited to being performed once, i.e. after the completion of step S4, the process may loop back to the start of the method and steps S1 to S4 may be performed iteratively.
  • a layer configuration of a gate structure 1 according to an embodiment of the present invention is obtained, any of the steps S1 to S4 can be performed in parallel or without maintaining a strict order of sequence. Any suitable technique known to a skilled person can be used for any of these steps.
  • the thicknesses of the passivation layer 12 and the Hf0 2 layer in the insulator layer 13 have been given, by way of example, as 1.5nm and 4nm, respectively - they may of course have different values to, for example, suit the application and/or device in which an embodiment of the present invention is incorporated.

Abstract

The present invention relates to a semiconductor device comprising a gate stack structure (1), the gate stack structure (1) comprising: at least a substrate (10) comprising a semiconductor that is substantially doped with n-type carriers; at least a passivation layer (12) comprising silicon formed on the substrate (10), and at least an insulator layer (13) formed on the passivation layer (12), wherein the gate stack structure (1) further comprises: at least an interlayer dopant provided between the substrate (10) and the passivation layer (12), the interlayer dopant comprising an n-type dopant (11) that is selected to facilitate control of a threshold voltage applicable to the gate stack structure (1) when the semiconductor device is in use.

Description

SEMICONDUCTOR DEVICE WITH A GATE STACK
Field of the invention
The present invention relates to a semiconductor device comprising a gate stack structure and a method of fabrication therefor. The present invention also extends to the use of a gate stack structure in a semiconductor device.
Background of the invention
In semiconductor device technology, metal oxide semiconductor field effect transistors (MOSFETs) are attractive for use, for example, in digital circuits. This is because MOSFETs can be switched in a reliable and controllable manner between a conducting ("on") state and a non-conducting ("off") state and also on account of being integrable on a scale of millions on a single chip.
In order to overcome the limitations posed by silicon (Si) on the continued downscaling and performance of complementary metal oxide semiconductor (CMOS) technology, alternative device structures and/or materials have been investigated. For this purpose, and as reported, for example, by Shang et.al in IBM Journal of Research and Development, page 50, 2006, germanium (Ge) has proved an attractive candidate. Due to its higher charge carrier mobility as compared to Si, Ge provides a relatively increased scope of downscaling and integration per chip. Another factor is that, for the fabrication of Ge-based MOSFETs, lower processing temperatures are used as compared to Si- based MOSFETs, for example, approximately 400 - 500°C in the case of Ge-based MOSFETs as compared to approximately 900 - 1000°C for Si-based MOSFETs, which feature makes such devices attractive for integration in advanced semiconductor devices.
A drawback associated with the use of Ge as a channel in MOSFETs is that germanium oxide (Ge02) is less stable on Ge compared to silicon dioxide (Si02) on Si. This poses a challenge for the surface passivation of the Ge in such devices before the deposition of a gate insulator such that an interface with a reduced density of interface traps may be formed and the charge carrier mobility of Ge may be preserved. It has been proposed to overcome this drawback by the passivation of the Ge with a Si interfacial layer at reduced processing temperatures, approximately 400 - 500°C, before the gate insulator is deposited thereon. For the gate insulator, a material that has a dielectric constant (k) relative to a vacuum, which is greater in magnitude than 7 is used, such a material being hereinafter referred to as a "high k" material and an example of which is, hafnium oxide (Hf02). The Si interfacial layer is partially oxidised to yield an upper Si02 layer at the processing temperatures, approximately 150°C, at which the high k material is deposited. In this way, a gate structure of Ge/Si/Si02/Hf02 is made. As reported by Mitard et.al in the Technical Digest IEDM, page 873, San Francisco, 2008, Ge-based p- channel MOSFETs incorporating such a gate structure, for example, have exhibited improved device characteristics, such as, for example, a lower equivalent oxide thickness (EOT), over previously-proposed Ge-based p-channel devices in which such a structure is absent.
Reference is now made to Mitard et.al, Proceedings of ESSDERC 2009, page 411 ; Athens, 2009, Pourtois et.al, Applied Physics Letters, volume 91 , 023506, 2007, and Taoka et.al, Applied Physics Letters, volume 92, 1 1351 1 , 2008, wherein it is reported that a problem associated with the above-described Ge-based p-channel MOSFETs incorporating a passivating Si interfacial layer is the occurrence of an undesirable shift in the threshold voltage, VTH, and flatband voltage, VFB, specifically an increased shift towards positive values of VTH demonstrating a dependency on the thickness of the Si interfacial layer. Accordingly, a consideration for such devices is that the channel is not substantially turned off when no voltage is applied to the gate, i.e. at zero gate bias. This may, amongst other things, make such devices unattractive for use in applications and/or incorporation into advanced devices where controllable and reliable switching between on and off states may be desired, for example. A further consideration for such devices is that, whilst the observed shift in Vm may be counteracted by, for example, increasing the thickness of the Si interfacial layer, such an action may cause a correspondingly increased EOT value, which is undesirable from the viewpoint of the current trend towards reducing the lateral sizing of field effect transistors (FETs).
In order to reduce the above-described positive shift of V-m, it has been proposed at the weblink http://imec.be to deposit the Si interfacial layer on Ge at lower deposition temperatures compared to previously-proposed devices so that VTH is substantially constant for different Si monolayer thicknesses. However, the VTH values in this case, approximately -20mV, are still not considered to be beneficial for p-MOSFETs, for example.
US7446380B2 discloses a material stack comprising: a hafnium-based dielectric; an electrically conductive capping layer comprising at least one of Ce, Y, Sm, Er and Tb located above the hafnium-based dielectric; and a Si-containing conductor located directly on the electrically conductive capping layer. By way of the electronegativity differences between the rare-earth metal in the electrically conductive capping layer and the hafnium-based dielectric, the disclosed material stack addresses the problem of the non-ideal threshold voltages obtained in, for example, Si-based n-type MOSFETs fabricated with a hafnium-based dielectric when the material stack is incorporated in such a MOSFET. Since the rare-earth containing capping layer is formed on the hafnium-based dielectric in the disclosed material stack, a consideration may be that this may introduce structural and/or fabrication complexity in that, the suitability of the rare- earth metal relative to the underlying hafnium-based dielectric and overlying gate material has to be assessed - such issues may also, of course, impact the ease with which such structures may be integrated in advanced semiconductor devices and/or use in related applications, for example. A further consideration may be that the performance of the rare-earth metal is dependent on the chemical nature of the hafnium-based dielectric. A still further consideration may be that, since the rare-earth metal is diffused through the gate stack, this may introduce further processing issues.
Summary of the invention
According to an embodiment of a first aspect of the present invention, there is provided a semiconductor device comprising a gate stack structure, the gate stack structure comprising: at least a substrate comprising a semiconductor that is substantially doped with n-type carriers; at least a passivation layer comprising silicon formed on the substrate , and at least an insulator layer formed on the passivation layer, wherein the gate stack structure further comprises: at least an interlayer dopant provided between the substrate and the passivation layer, the interlayer dopant comprising an n-type dopant that is selected to facilitate control of a threshold voltage applicable to the gate stack structure when the semiconductor device is in use. In an embodiment of the present invention, an interlayer dopant is provided between the substrate and the passivation layer in the layer configuration of an embodiment of the present invention. The interlayer dopant comprises n-type dopant atoms, which ionise to yield a fixed sheet of positively-charged dopant ions. In response to the formation of the positively-charged dopant ions, a more negative value of threshold voltage is applicable to an embodiment of the present invention in order to induce a conducting channel in the substrate compared to previously-proposed devices and/or in the absence of the interlayer dopant in an embodiment of the present invention. Thus, the problem of an undesirable positive shift in the threshold voltage observed in previously-proposed devices, for example, Ge- based p-channel MOSFETs, is addressed by an embodiment of the present invention. An embodiment of the present invention is suited for applications and/or advanced devices where controllable and reliable switching between on and off states may be desired. An advantage of an embodiment of the present invention compared to previously-proposed devices is that a shift in the threshold voltage to a desired value is not achieved by changing the gate metal in order to manipulate the metal work function, which action would have undesirable consequences such as, for example, increasing the number of processing steps and constraints being placed on the choice of gate metal that is used since the compatibility of the gate metal with the materials of the layers in the gate stack may need to be assessed. A further advantage of an embodiment of the present invention is that the desired shift in the threshold voltage is not facilitated by adding a layer of an oxide with fixed charges to, for example, the insulator layer which action would restrict scaling of such a layer.
Preferably, the n-type dopant is substantially provided in a region adjacent to a conducting channel formed in the substrate when the semiconductor device is in use. Thus the mobility of carriers in the substrate may be substantially preserved since the conducting channel need not be counter-doped in order to facilitate control of the threshold voltage. The latter would lower the carrier mobility on account of the Coulomb scattering which would occur due to ionised impurities.
Desirably, a concentration of the n-type dopant is chosen to control a magnitude of the threshold voltage. In an embodiment of the present invention, a magnitude of the shift of the threshold voltage is dependent on the number of n-type dopant atoms per unit area. By raising or lowering the concentration of n-type dopant, a shift of the threshold voltage to a desired extent can be controlled. The attractiveness of this feature can be better understood by considering that, often, manufacturers may offer the same technology in different performance versions, for example. In one performance version, in which increased speed of operation may be paramount, a threshold voltage value that enables a faster turn-on and a higher drive current may be desirable. On the other hand, in another performance version that supports reduced power dissipation, a threshold voltage value that ensures a lower off current may be preferable. Thus, the threshold voltage value of the first-described performance version would be lower than the latter described version. An embodiment of the present invention offers the advantage that the threshold voltage value may be tuned to the appropriate value for each version via the concentration of n-type dopant, i.e. an extent of the shift of the threshold voltage to be more positive or negative as required by the different performance versions may be tailored by choosing a corresponding concentration of n-type dopant.
Preferably, the n-type dopant is selected to at least compensate for interfacial charges present at an interface between the substrate and the passivation layer. In an embodiment of the present invention, the n-type dopant atoms ionise to form a substantially fixed sheet of positively charged dopant ions. This fixed sheet of positive charge may substantially compensate for the interfacial charges and/or defects that may be present between the substrate and the passivation layer. In this way, a shift of the threshold voltage towards more negative values than is the case in previously-proposed devices may be obtained with an embodiment of the present invention.
Desirably, the n-type dopant is selected to at least compensate for interfacial charges at an interface between the passivation layer and the insulator layer. Studies have shown that atoms may diffuse from the substrate to the interface between the passivation layer and the insulator layer and result in the formation of negatively-charged traps at that interface. These negatively-charged traps have been implicated in contributing to the observation of the above-described positive shift in the threshold voltage. An embodiment of the present invention provides the advantage that the positively-charged dopant ions substantially compensate for the negative charge on these traps and, therefore, facilitate a negative shift in the threshold voltage. Preferably, the n-type dopant is selected to at least compensate for charges in the passivation layer, insulator layer or a combination thereof. An embodiment of the present invention offers the advantage of substantially compensating for the charges in the passivation layer, in the insulator layer or a combination thereof, which charges may be implicated in causing a positive shift in the threshold voltage.
Desirably, the n-type dopant comprises one of: arsenic (As), phosphorous (P), antimony (Sb) and bismuth (Bi). Contrary to the scenario in previously-proposed devices, compensation of the negatively-charged interfacial charges and/or defects between and/or in the different layers in an embodiment of the present invention by the fixed sheet of positively-charged dopant ions does not necessitate the diffusion of the n-type dopant across the gate stack structure or specific layers thereof by, for example, thermal processing. Thus, apart from being able to facilitate control of the threshold voltage, the n-type dopant material is also chosen on account of having a reduced diffusion coefficient value in the substrate and/or passivation layer, such that it remains at the substrate-passivation layer interface during the possible high-temperature processing in subsequent steps after provision of the interlayer dopant. In an embodiment of the present invention, the n-type dopant is chosen to comprise one of the following elements from Group V of the Periodic Table: As, P, Sb and Bi. These materials have the following diffusivity (D) characteristics in Ge: D(As)>D(Sb)>D(P). Regarding the use of As for the n-type dopant, it offers the particular advantage that, since the technology for its implantation in source and drain electrodes is developed, the step to introduce it as a surface dopant of the channel region, as is done in an embodiment of the present invention, would not unduly cause fabrication complications.
Preferably, the semiconductor device comprises a field-effect transistor. In an embodiment of the present invention, a desired shift in the threshold voltage is achieved by incorporating an interlayer dopant comprising an n-type dopant in the gate stack rather than, for example, increasing the number of silicon monolayers in the passivation layer. Thus, the thickness of the layers in the gate stack, in particular, the passivation layer, may be further reduced in an embodiment of the present invention compared to previously-proposed devices. This feature supports the general trend in the semiconductor industry towards reducing the lateral sizing of semiconductor devices, in particular, FETs, since a reduced physical stack thickness and lower EOTs may be attainable with an embodiment of the present invention compared to previously- proposed devices. An embodiment of the present invention is particularly applicable to MOSFETs, for example, p-channel MOSFETs.
Desirably, the insulator layer comprises a dielectric material having an effective dielectric constant that is greater in magnitude than 7. For the dielectric material, a high-k material is chosen on account of, for example, being thermally stable over a broad range of temperatures. Preferably, hafnium-based dielectrics such as hafnium oxide are used for the high-k material in the insulator layer. However, an embodiment of the present invention is not limited to the use of hafnium-based dielectrics and, indeed, any other dielectric material having an effective dielectric constant that is greater in magnitude than 7, may be used in the insulator layer. In an embodiment of the present invention, the insulator layer may further comprise an Si02 layer disposed between the passivation layer and the high-k material. It may be formed due to the processing conditions used for the deposition of the high-k material on the passivation layer. An embodiment of the present invention also encompasses the scenario where the insulator layer does not further comprise such an oxide layer.
Preferably, the substrate comprises germanium (Ge), germanium-on-insulator (GOI), silicon-germanium-on-insulator (SiGe-OI) or any combination thereof. An advantage that is offered is that, since the positively-charged dopant ions substantially compensate for interfacial charges and/or defects at the different interfaces between the layers in an embodiment of the present invention, the scope of preserving the mobility of carriers in the substrate is improved over the scenario in previously-proposed devices. Furthermore, an embodiment of the present invention is versatile on account of the chosen substrate materials being widely used in the semiconductor industry, particularly, in high-performance applications.
Corresponding method aspects are also provided and so according to an embodiment of a second aspect of the present invention, there is provided a method for fabricating a gate stack structure in a semiconductor device comprising the steps of: forming at least a substrate comprising a semiconductor that is substantially doped with n-type carriers; forming at least a passivation layer comprising silicon on the substrate, and forming at least an insulator layer on the passivation layer, the method further comprising the step of: providing at least an interlayer dopant between the substrate and the passivation layer, the interlayer dopant comprising an n-type dopant that is selected to facilitate control of a threshold voltage applicable to the gate stack structure when the semiconductor device is in use.
According to an embodiment of a third aspect of the present invention, there is provided a use of a gate stack structure in a semiconductor device, the gate stack structure comprising: at least a substrate comprising a semiconductor that is substantially doped with n-type carriers; at least a passivation layer comprising silicon formed on the substrate, and at least an insulator layer formed on the passivation layer, wherein the gate stack structure further comprises: at least an interlayer dopant provided between the substrate and the passivation layer, the interlayer dopant comprising an n-type dopant that is selected to facilitate control of a threshold voltage applicable to the gate stack structure when the semiconductor device is in use.
Any feature of one aspect of the invention may be applied to another aspect of the invention and vice versa. Features of one aspect of the invention may be applied to another aspect of the invention. Any disclosed embodiment may be combined with one or several of the other embodiments shown and/or described. This is also possible for one or more features of the embodiments.
Brief description of the drawings
Reference will now be made, by way of example, to the accompanying drawings, in which:
Figure 1 schematically illustrates an embodiment of the present invention;
Figure 2 schematically illustrates the drain-current versus gate-voltage characteristics for a Ge-based p-channel MOSFET incorporating a previously-proposed gate-stack structure;
Figure 3 schematically illustrates the drain-current versus gate-voltage characteristics for a Ge-based p-channel MOSFET according to an embodiment of the present invention, and
Figure 4 schematically illustrates an embodiment of a method aspect of the present invention. Detailed description of preferred embodiments
Within the description, the same reference numerals or signs have been used to denote the same parts or the like.
Reference is now made to Figure 1 , which schematically illustrates a gate stack structure 1 according to an embodiment of the present invention. As can be seen from Figure 1 , it comprises the following layer configuration from bottom to top: a substrate 10 comprising a semiconductor that is substantially doped with n-type carriers; a passivation layer 12 comprising silicon formed on the substrate; an insulator layer 13 comprising a high-k material formed atop the passivation layer 12 and, provided between the substrate 10 and the passivation layer 12 is an interlayer dopant, which comprises an n-type dopant 1 1. As depicted in Figure 1 , for the n-type dopant, As is used in the present example. In the present example, the substrate 10 comprises Ge doped with, for example, between 1 e15 and 1 e18 n-type carriers and for the high-k material in the insulator layer 13, Hf02 is used.
A principle of an embodiment of the present invention is now described with reference being made to Figure 1. The different layers in the gate stack structure 1 according to an embodiment of the present invention are formed at room temperature. At this temperature, the As dopant atoms ionise to form a fixed sheet of positively-charged dopant ions. The positive charge of the dopant ions substantially compensates for the negative charges associated with interfacial charges and/or defects at the different interfaces between the layers of the gate stack structure 1. For example, the positive charge of the dopant ions compensates for the negative charge associated with charged defects caused by the migration of, for example, Ge from the substrate 10 to an interface between the passivation layer 12 and the insulator layer 13 and for dipoles present at the same interface. The negative charges associated with the charged defects and/or dipoles have been implicated in causing a positive shift of the threshold voltage in previously-proposed devices and so the compensation thereof in an embodiment of the present invention is desirable from the viewpoint that this effect causes a negative shift of the threshold voltage. The compensation effect of an embodiment of the present invention also extends to the compensation of charges/defects/dipoles at the substrate 10-passivation layer 12 interface and/or within the different layers of the gate stack structure 1 either respectively or in combination. An embodiment of the present invention may also address other phenomena that cause the undesirable positive shift in the threshold voltage to be observed, for example, correction for the metal work functions, etc.
Notwithstanding the ability to cause a desired shift in the threshold voltage to be either positive or negative, for example, an embodiment of the present invention also facilitates control of the magnitude of this shift, that is, the extent to which it is positive or negative. This is because the magnitude of the shift of the threshold voltage is dependent on the number of n-type dopant atoms 1 1 per unit area. Thus, by raising or lowering the concentration of n-type dopant atoms 1 1 , a shift of the threshold voltage to a desired extent can be controlled in an embodiment of the present invention.
As discussed earlier, compensation of the negatively-charged interfacial charges and/or defects between and/or in the different layers in an embodiment of the present invention by the fixed sheet of positively-charged dopant ions does not necessitate the diffusion of the n-type dopant 1 1 across the gate stack structure 1 or specific layers thereof. For the n-type dopant 11 , a material that facilitates the above-described compensation effect whilst also having a reduced diffusion coefficient value in the substrate and/or passivation layer is desirable. Materials that satisfy these criteria and that are chosen for the n-type dopant in an embodiment of the present invention comprise As, P, Sb and Bi from Group V of the Periodic Table.
Although the gate stack structure 1 has been described with reference to the use of Ge for the substrate 10, an embodiment of the present invention is, of course, not only limited to the use of such a material. In fact, the substrate 10 may comprise Ge, GOI, SiGe-OI or any combination thereof. Furthermore, whilst the gate stack structure 1 has been described with reference to the use of Hf02 for the dielectric material in the insulator layer 13, an embodiment of the present invention is not limited to the use of Hf02 and any other hafnium-based dielectric may be used. In fact, for the dielectric material in the insulator layer 13, any dielectric material having an effective dielectric constant that is greater in magnitude than 7 may be used. For the sake of comparison between a previously-proposed gate stack structure and an embodiment of the present invention, reference is now made to Figures 2 and 3. Figure 2 illustrates the drain-current (Id) versus gate-voltage (Vg) characteristics of a Ge-based p-channel MOSFET incorporating a previously-proposed gate stack structure. The layer configuration of the previously-proposed gate stack structure from bottom to top is: a substrate comprising n-doped Ge, a passivation layer comprising Si and an insulator layer comprising Hf02. Figure 3 illustrates the Id versus Vg characteristics of a Ge-based p-channel MOSFET incorporating a gate stack structure 1 according to an embodiment of the present invention, such as that shown in Figure 1 and hereinbefore described in which an interlayer dopant comprising As for the n-type dopant 1 1 is provided between the substrate 10 and the passivation layer 12. In order to measure the threshold voltages, the respective devices were fabricated in a self-aligned gate first ring FET process with source and drain contacts being made out of nickel (Ni) and the gate contact being made of platinum (Pt).
As can be seen from the insets in Figure 2 and Figure 3, the Id versus Vg characteristics for both cases were plotted for drain voltages of 20mV, 40mV and 60mV. Corresponding to these respective drain voltages are plots 2a, 2b and 2c in Figure 2, and plots 3a, 3b and 3c in Figure 3. In order to compare the performance of an embodiment of the present invention with that obtained with the previously-proposed device, a threshold voltage was extracted from the Id-Vg plots shown in Figures 2 and 3. A threshold voltage of approximately -2V can be extracted from Figure 3 depicting the results pertaining to an embodiment of the present invention compared to a threshold value of approximately 2V for the previously-proposed device as can be seen from Figure 2. These results confirm that the n-type dopant 1 1 , in this case As, in an embodiment of the present invention facilitates a negative shift in the threshold voltage by compensating for the negative charges/defects/dipoles at and/or in the different layers in the gate stack structure 1.
Comparing the results of Figures 2 and 3, particularly the drain currents, it can be seen that the drain currents obtained with an embodiment of the present invention (Figure 3) are substantially lower than those obtained with a previously-proposed device (Figure 2). This result may be explained by the increased Coulomb scattering from the non- optimised As concentration, i.e. As over-doping had possibly occurred in this specific case. For the data shown in Figure 3, it is considered that the threshold voltage has most probably been overestimated, which means it could possibly be even more negative than -2V.
Reference is now made to Figure 4, which schematically illustrates a method according to an embodiment of the present invention. To begin with, a substrate 10 comprising a semiconductor substantially doped with n-type carriers is provided. In the present example, the substrate 10 comprises n-type doped Ge. In a step S1 , in-situ cleaning of a surface of the n-type doped Ge substrate 10 is done. In a step S2, an interlayer dopant comprising an n-type dopant 1 1 , which in the present example is As, is provided on the cleaned surface of the n-type doped Ge substrate 10. In the step S2, approximately up to one monolayer of the As atoms may be deposited, this being effectuated by a deposition time of, for example, 2 seconds. In a step S3, formation of the passivation layer 12 comprising silicon is done atop the substrate 10 modified by the provision of the n-type dopant 1 1 . In an embodiment of the present invention, the passivation layer 12 may have a thickness of approximately 1.5nm, for example. In a following step S4, deposition of an insulator layer 13 comprising a high-k material is done. An example of a high-k material in an embodiment of the present invention is a hafnium-based dielectric, such as, for example, Hf02. In an embodiment of the present invention, in which Hf02 is used in the insulator layer 13, a thickness of the Hf02 layer is 4nm, for example. As discussed earlier and although not depicted in Figure 1 , the insulator layer 13 may also comprise a silicon dioxide layer that is disposed between the passivation layer 12 and the high-k dielectric material. The silicon dioxide layer in the insulator layer 13 is formed by the oxidation of the silicon in the passivation layer 12 due to the processing conditions that are used for the deposition of the high-k material in step S4. Steps S1 to S4 are performed in a vacuum environment, specifically an ultra-high vacuum (UHV) environment, without breaking such an environment, so that contamination may be reduced and/or avoided. At least one of the steps S1 to S4 may be performed with molecular beam epitaxy (MBE), which offers the advantage of enabling controllable deposition of small amounts of material at reduced temperatures, such as, for example, room temperature.
In a method according to an embodiment of the present invention, steps S1 to S4 are performed at room temperature. In step S3, Si is deposited at 150 ° C for 1 minute and, in step S4, Hf02 is deposited at 225 ° C for 15 minutes. Additional steps for source and drain activation anneals are performed at 350 ° C for 5 minutes. At these processing temperatures, when As is used for the n-type dopant and Ge is used for the substrate, for example, the As atoms substantially remain at the Ge-Si interface.
A method according to an embodiment of the present invention is not limited to being performed once, i.e. after the completion of step S4, the process may loop back to the start of the method and steps S1 to S4 may be performed iteratively. Provided a layer configuration of a gate structure 1 according to an embodiment of the present invention is obtained, any of the steps S1 to S4 can be performed in parallel or without maintaining a strict order of sequence. Any suitable technique known to a skilled person can be used for any of these steps. Furthermore, the thicknesses of the passivation layer 12 and the Hf02 layer in the insulator layer 13 have been given, by way of example, as 1.5nm and 4nm, respectively - they may of course have different values to, for example, suit the application and/or device in which an embodiment of the present invention is incorporated.
The present invention has been described above purely by way of example and modifications of detail can be made within the scope of the invention.
Each feature disclosed in the description, and where appropriate, the claims and the drawings may be provided independently or in any appropriate combination.

Claims

Claims
1. A semiconductor device comprising a gate stack structure (1 ), the gate stack structure (1 ) comprising:
at least a substrate (10) comprising a semiconductor that is substantially doped with n- type carriers;
at least a passivation layer (12) comprising silicon formed on the substrate(I O), and at least an insulator layer (13) formed on the passivation layer (12),
wherein the gate stack structure (1 ) further comprises:
at least an interlayer dopant provided between the substrate (10) and the passivation layer (12), the interlayer dopant comprising an n-type dopant (11 ) that is selected to facilitate control of a threshold voltage applicable to the gate stack structure (1 ) when the semiconductor device is in use.
2. A semiconductor device as claimed in claim 1 wherein the n-type dopant (11 ) is substantially provided in a region adjacent to a conducting channel formed in the substrate (10) when the semiconductor device is in use.
3. A semiconductor device as claimed in claim 1 or 2 wherein a concentration of the n-type dopant (11 ) is chosen to control a magnitude of the threshold voltage.
4. A semiconductor device as claimed in claim 1 , 2 or 3 wherein the n-type dopant (1 1 ) is selected to at least compensate for interfacial charges present at an interface between the substrate (10) and the passivation layer (12).
5. A semiconductor device as claimed in any preceding claim wherein the n-type dopant (11 ) is selected to at least compensate for interfacial charges at an interface between the passivation layer (12) and the insulator layer (13).
6. A semiconductor device as claimed in any preceding claim wherein the n-type dopant (1 1 ) is selected to at least compensate for charges in the passivation layer (12), insulator layer (13) or a combination thereof.
7. A semiconductor device as claimed in any preceding claim wherein the n-type dopant (11 ) comprises one of: arsenic (As), phosphorous (P), antimony (Sb) and bismuth (Bi).
8. A semiconductor device as claimed in any preceding claim wherein the semiconductor device comprises a field-effect transistor.
9. A semiconductor device as claimed in any preceding claim wherein the insulator layer (13) comprises a dielectric material having an effective dielectric constant that is greater in magnitude than 7.
10. A semiconductor device as claimed in any preceding claim wherein the substrate (10) comprises germanium (Ge), germanium-on-insulator (GOI), silicon-germanium-on- insulator (SiGe-OI) or any combination thereof.
1 1 . A method for fabricating a gate stack structure (1 ) in a semiconductor device comprising the steps of:
forming at least a substrate (10) comprising a semiconductor that is substantially doped with n-type carriers (S1 );
forming at least a passivation layer (12) comprising silicon on the substrate (10) (S3), and
forming at least an insulator layer (13) on the passivation layer (12) (S4),
the method further comprising the step of:
providing at least an interlayer dopant between the substrate (10) and the passivation layer (12), the interlayer dopant comprising an n-type dopant (1 1 ) that is selected to facilitate control of a threshold voltage applicable to the gate stack structure (1 ) when the semiconductor device is in use (S2).
12. A method as claimed in claim 1 1 wherein, in the step of providing the interlayer dopant (S2), the n-type dopant (11 ) is substantially provided in a region adjacent to a conducting channel formed in the substrate (10) when the semiconductor device is in use.
13. A method as claimed in claim 1 1 or 12 wherein, in the step of providing the interlayer dopant (S2), a concentration of the n-type dopant (1 1 ) is chosen to control a magnitude of the threshold voltage.
14. A method as claimed in claim 1 1 , 12 or 13 wherein, in the step of providing the interlayer dopant (S2), the n-type dopant (1 1 ) is selected to at least compensate for interfacial charges present at an interface between the substrate (10) and the passivation layer (12).
15. A method as claimed in any one of claims 1 1 to 14 wherein, in the step of providing the interlayer dopant (S2), the n-type dopant (1 1 ) is selected to at least compensate for interfacial charges at an interface between the passivation layer (12) and the insulator layer (13).
16. A method as claimed in any one of claims 1 1 to 15 wherein, in the step of providing the interlayer dopant (S2), the n-type dopant (1 1 ) is selected to at least compensate for charges in the passivation layer (12), insulator layer (13) or a combination thereof.
17. A method as claimed in any one of claims 1 1 to 16 wherein, in the step of providing the interlayer dopant (S2), the n-type dopant (1 1 ) is selected to comprise one of: arsenic (As), phosphorous (P), antimony (Sb) and bismuth (Bi).
18. A method as claimed in any one of claims 1 1 to 17 wherein, in the step of forming the insulator layer (S4), the insulator layer (13) is selected to comprise a dielectric material having an effective dielectric constant that is greater in magnitude than 7.
19. A method as claimed in any one of claims 1 1 to 18 wherein, in the step of providing the substrate (S1 ), the substrate (10) is selected to comprise germanium (Ge), germanium-on-insulator (GOI), silicon germanium-on-insulator (SiGe-OI) or any combination thereof.
20. A method as claimed in any one of claims 1 1 to 19 wherein the steps (S1 , S2, S3, S4) are performed in a vacuum environment.
21 . A method as claimed in any one of claims 1 1 to 20 wherein at least one of the steps (S1 , S2, S3, S4) are performed using molecular-beam epitaxy.
22. Use of a gate stack structure (1 ) in a semiconductor device, the gate stack structure (1 ) comprising:
at least a substrate (10) comprising a semiconductor that is substantially doped with n- type carriers;
at least a passivation layer (12) comprising silicon formed on the substrate (10), and at least an insulator layer (13) formed on the passivation layer (12),
wherein the gate stack structure (1 ) further comprises:
at least an interlayer dopant provided between the substrate (10) and the passivation layer (12), the interlayer dopant comprising an n-type dopant (11 ) that is selected to facilitate control of a threshold voltage applicable to the gate stack structure (1 ) when the semiconductor device is in use.
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