CN103125014A - Semiconductor device with a gate stack - Google Patents
Semiconductor device with a gate stack Download PDFInfo
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- CN103125014A CN103125014A CN2011800466523A CN201180046652A CN103125014A CN 103125014 A CN103125014 A CN 103125014A CN 2011800466523 A CN2011800466523 A CN 2011800466523A CN 201180046652 A CN201180046652 A CN 201180046652A CN 103125014 A CN103125014 A CN 103125014A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
- H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Abstract
The present invention relates to a semiconductor device comprising a gate stack structure (1), the gate stack structure (1) comprising: at least a substrate (10) comprising a semiconductor that is substantially doped with n-type carriers; at least a passivation layer (12) comprising silicon formed on the substrate (10), and at least an insulator layer (13) formed on the passivation layer (12), wherein the gate stack structure (1) further comprises: at least an interlayer dopant provided between the substrate (10) and the passivation layer (12), the interlayer dopant comprising an n-type dopant (11) that is selected to facilitate control of a threshold voltage applicable to the gate stack structure (1) when the semiconductor device is in use.
Description
Technical field
The present invention relates to a kind of semiconductor device that comprises gate stack structure and preparation method thereof.The present invention also prolongs and uses gate stack structure at semiconductor device.
Background technology
In semiconductor device art, mos field effect transistor (MOSFET) is for for example attractive for the use in digital circuit.This be because can be between conducting (" connections ") state and non-conduction ("off") state with reliably and controlled manner switching mosfet and also owing to can being integrated on one single chip on 1,000,000 scales.
In order to overcome silicon (Si), the continuation of complementary metal oxide semiconductors (CMOS) (CMOS) technology is reduced restriction with performance in proportion, investigated alternative devices structure and/or material.For this purpose and as such as people such as Shang at IBM Journal of Research and Development, in page 50,2006 report like that, germanium (Ge) has proved attractive candidate.Ge provides reduction in proportion and the integrated scope of the relative increase of every chip due to it and Si higher charge carrier mobility relatively.Another factor is for making based on for the MOSFET of Ge, the lower part Li Wendu that uses as compare with MOSFET based on Si, for example as be used for based on approximate 900-1000 ℃ of comparison of the MOSFET of Si in the situation that based on approximate 400-500 ℃ of the MOSFET of Ge, this feature makes such device for attractive for integrated in advanced semiconductor devices.
Germanium oxide (GeO on Ge with using Ge as the related shortcoming of the raceway groove in MOSFET
2) and the silicon dioxide (SiO on Si
2) compare more unstable.Thereby this can form the interface that interface trap density reduces for the surface passivation of the Ge in such device before the deposition gate insulator and the charge carrier mobility that can keep Ge brings challenges.Proposed by overcoming this shortcoming in the treatment temperature that is similar to the minimizing of 400-500 ℃ with Si boundary layer passivation Ge before the deposition gate insulator on Ge.For gate insulator, use to have value greater than the material of 7 the dielectric constant with respect to vacuum (k), the example that hereinafter such material is called " high k " material and this material is hafnium oxide (HfO
2).Partly oxidation Si boundary layer is to produce SiO in the high k material of deposition, treatment temperatures approximate 150 ℃
2Layer.In this way, make grid structure Ge/Si/SiO
2/ HfO
2As people such as Mitard at Technical Digest IEDM, page 873, San Francisco, in 2008, report is such, for example incorporate into such grid structure, showed and wherein do not had such structure, the previous p channel device improved device property Comparatively speaking based on Ge that proposes based on the p channel mosfet of Ge, such as for example lower equivalent oxide thickness (EOT).
With reference now to people such as Mitard,, Proceedings of ESSDERC 2009, page 411; Athens, the people such as 2009, Pourtois, Applied Physics Letters, volume 91,023506,2007 and the people such as Taoka, Applied Physics Letters, volume 92,113511,2008, wherein the report with above-described incorporate into passivation Si boundary layer, be threshold of appearance threshold voltage V based on the related problem of the p channel mosfet of Ge
THWith flat band voltage V
FBUndesirable displacement, being specially increases towards V
THOn the occasion of displacement, this shows the dependence to the Si interfacial layer thickness.Thereby be when not applying voltage (namely in the no-voltage biasing) to grid for the consideration of such device, basically do not disconnect raceway groove.This may make such device for example in the use in application and/or may wish wherein to have no attraction for incorporating in the high-grade device of the controlled and reliable switching between the connecting and disconnecting state.Although the another consideration for such device is for example to offset by the thickness that increases the Si boundary layer V that observes
THBe shifted, but such action may cause the corresponding EOT value that increases, this is undesirable from the viewpoint towards the current trend that reduces the setting of field-effect transistor (FET) lateral dimension.
In order to reduce above-described V
THJust be shifted, propose to deposit the Si boundary layer in the more low deposition temperature of comparing with the device of previous proposition on Ge at network linking http://imec.be, thus V
THFor different Si thickness in monolayer substantial constant.Yet, still do not think to be approximately in this case-V of 20mV
THValue for example is of value to p-MOSFET.
US7446380B2 discloses a kind of material stacks, and this material stacks comprises: based on the dielectric of hafnium; Be positioned at the conductive cap layer based on the dielectric of hafnium top, comprise at least a in Ce, Y, Sm, Er and Tb; And the conductor that comprises Si, be located immediately on conductive cap layer.By the rare earth metal in conductive cap layer and based on the electronegativity difference between the dielectric of hafnium, disclosed material stacks solves the problem of the imperfect threshold voltage that obtains when incorporating material stacks in for example using, N-shaped MOSFET based on Si that make based on the dielectric of hafnium in such MOSFET.Due in disclosed material stacks based on forming the cap rock comprise rare earth on the dielectric of hafnium, so consider it can is that this may introduce structure and/or make complexity because must assess rare earth metal with respect to below based on the dielectric of hafnium and the appropriateness for superincumbent grid material---such problem certainly also may for example affect can be in advanced semiconductor devices the integrated and/or simplicity such structure of use in relevant application.Another consideration can be that the performance of rare earth metal depends on the dielectric chemical character based on hafnium.Another consideration can be because rare earth metal diffuses through gate stack, so this can introduce further processing problem.
Summary of the invention
An embodiment according to a first aspect of the invention provides a kind of semiconductor device that comprises gate stack structure, and gate stack structure comprises: substrate at least comprises basically the semiconductor by the doping of N-shaped charge carrier; The passivation layer at least that comprises silicon, be formed on substrate, and insulator layer at least, be formed on passivation layer, wherein gate stack structure also comprises: the dopant of interlayer at least that provides between substrate and passivation layer, interlayer dopant comprise and are selected for the N-shaped dopant that helps in use to control the threshold voltage that can put on gate stack structure at semiconductor device.In one embodiment of the invention, provide the interlayer dopant between substrate and passivation layer in the layer configuration of one embodiment of the present of invention.The interlayer dopant comprises the N-shaped dopant atom, and these N-shaped dopant atoms ionize to produce the stator (fixed sheet) of the dopant ion of positively charged.In response to the dopant ion that forms positively charged, with the device of previous proposition and/or compare at the interlayer dopant that lacks one embodiment of the present of invention, more negative threshold voltage value can be applicable to one embodiment of the present of invention in order to produce communication channel in substrate.Therefore, one embodiment of the present of invention solve the undesirable threshold voltage that observes in the device that formerly proposes (for example based on Ge p channel mosfet) such problem that just is being shifted.One embodiment of the present of invention are suitable for wherein may wishing application and/or the high-grade device of the controlled and reliable switching between the connecting and disconnecting state.One embodiment of the present of invention are with the advantage that the device of previous proposition is compared: do not realize that threshold voltage is to the displacement of desirable value by changing gate metal in order to control metal work function, this action will have undesirable consequence, such as the number of the constraint that for example increases treatment step and the gate metal that uses is selected apply, because may need to assess the compatibility of the layer material in gate metal and gate stack.The another advantage of one embodiment of the present of invention is that this action will limit the convergent-divergent of such layer not by for example adding to insulator layer the required displacement that the oxide skin(coating) with fixed charge helps threshold voltage.
Preferably, basically provide the N-shaped dopant in the zone adjacent with conducting channel, this conducting channel forms in substrate when semiconductor device uses.Therefore, can basically keep the mobility of the charge carrier in substrate, because need not the contra-doping conduction in order to help to control threshold voltage.The latter will disperse to reduce carrier mobility due to following enclosed pasture, and this coulomb dispersion will occur due to the impurity of ionization.
It is desirable for that the concentration of selecting the N-shaped dopant is to control the value of threshold voltage.In one embodiment of the invention, the value of threshold voltage shift depends on the N-shaped dopant atom number of per unit area.By raising or reducing the n concentration of dopant, can control the displacement of threshold voltage on required degree.Can be for example by considering that manufacturer often can give the constructed attraction of understanding better this feature in the different performance version.The service speed that increases therein may a vital performance version in, can wish and realize the more threshold voltage value of Quick connecting pipe fitting and Geng Gao drive current.On the other hand, in another performance version of the power dissipation of supporting to reduce, can preferably guarantee the threshold voltage value of lower turn-off current.Therefore, the threshold voltage value of the performance version of first description will be lower than the version of a rear description.The advantage that one embodiment of the present of invention are given is can be via N-shaped concentration of dopant adjusting threshold voltage value to the appropriate value that adapt to be used for each version, namely can by select corresponding N-shaped concentration of dopant to customize to need as the different performance version, threshold voltage is to corrigendum or more negative displacement degree.
Preferably, the N-shaped dopant is selected for the interface charge of the interface existence that compensates at least between substrate and passivation layer.In one embodiment of the invention, the ionization of N-shaped dopant atom forms the sheet of basically fixing of the dopant ion of positively charged.The stator of positive charge can compensate interface charge and/or the defective that may exist basically between substrate and passivation layer.In this way, can obtain threshold voltage towards the displacement of the value more negative than the situation in the device that formerly proposes with one embodiment of the present of invention.
It is desirable for that the N-shaped dopant is selected for the interface charge at the interface that compensates at least between passivation layer and insulator layer.Research has shown that atom can be from substrate to the interfacial diffusion between passivation layer and insulator layer, and causes electronegative trap to be formed at this interface.These electronegative traps have been related to when causing observe threshold voltage above-described just being shifted.Therefore the advantage that one embodiment of the present of invention provide is that the dopant ion of positively charged basically compensates the negative electrical charge on these traps and helps the negative displacement of threshold voltage.
Preferably, the N-shaped dopant is selected for the electric charge that compensates at least in passivation layer, insulator layer or its combination.One embodiment of the present of invention are given and are basically compensated in passivation layer, in insulator layer or the such advantage of electric charge in its combination, may relate to these electric charges when the just displacement that causes threshold voltage.
It is desirable for that the N-shaped dopant comprises one of arsenic (As), phosphorus (P), antimony (Sb) and bismuth (Bi).Opposite with the situation in the device that formerly proposes, electronegative interface charge and/or the defective of stator compensation between different layers and/or in different layers of the dopant ion by positively charged need not for example to cross over gate stack structure or its concrete layer diffusion N-shaped dopant by heat treatment in one embodiment of the invention.Therefore, except helping to control threshold voltage, also because the diffusion coefficient value that has minimizing in substrate and/or passivation layer is selected the N-shaped dopant material, thereby remain in substrate during the possible high-temperature process in its subsequent step after the interlayer dopant is provided-the passivation layer interface.In one embodiment of the invention, the N-shaped dopant is selected for one of following element that comprises from the V family of periodic table: As, P, Sb and Bi.These materials have following diffusivity (D) characteristic: D (As) in Ge＞D (Sb)＞＞D (P).About As is used for the N-shaped dopant, the concrete advantage that it is given is: because exploitation is used for the technology that it injects at source electrode and drain electrode, can suitably causes as step of the surface doping agent of channel region and make complexity so be used for introducing its as completing in one embodiment of the invention.
Preferably, semiconductor device comprises field-effect transistor.In one embodiment of the invention, by incorporating the interlayer dopant that comprises the N-shaped dopant into rather than for example increase the required displacement that silicon single-layer number in passivation layer is realized threshold voltage in gate stack.Therefore, compare with the device of previous proposition, can further reduce in one embodiment of the invention the thickness of the layer (being specially passivation layer) in gate stack.This feature is supported the main trend of setting towards the lateral dimension that reduces semiconductor device (being specially FET) in semiconductor industry, because compare physics stack thickness and the lower EOT that can obtain to reduce with one embodiment of the present of invention with the device of previous proposition.One embodiment of the present of invention are specifically applicable to MOSFET, for example the p channel mosfet.
It is desirable for that insulator layer comprises having value greater than the dielectric substance of 7 effective dielectric constant.For dielectric substance, can be for example select high k material due to thermally-stabilised in wide temperature range.Preferably, the high k material that is used for insulator layer based on the dielectric (such as hafnium oxide) of hafnium.Yet one embodiment of the present of invention are not limited to use the dielectric based on hafnium, and replace, and can use to have value greater than any other dielectric substance of 7 effective dielectric constant in insulator layer.In one embodiment of the invention, insulator layer can also be included in the SiO that arranges between passivation layer and high k material
2Layer.Can be because the treatment conditions that are used for the high k material of deposition on passivation layer form it.One embodiment of the present of invention also contain wherein, and insulator layer does not further comprise the situation of such oxide skin(coating).
Preferably, substrate comprises germanium (Ge), germanium on insulator (GOI), sige-on-insulator (SiGe-OI) or its any combination.The another advantage of giving is: because the dopant ion of positively charged compensates difference interface charge and/or defective at the interface between layer in one embodiment of the invention basically, so the scene in the device that more formerly proposes improves the reserved-range of the carrier mobility in substrate.In addition, one embodiment of the present of invention due in the semiconductor industry, the backing material that specifically is widely used selection in performance application has multipurpose.
Some corresponding method aspects also is provided, so embodiment according to a second aspect of the invention, a kind of method of the gate stack structure for making semiconductor device is provided, the method comprises the following steps: form substrate at least, substrate comprises the semiconductor that is basically adulterated by the N-shaped charge carrier; Form the passivation layer at least that comprises silicon on substrate; And form insulator layer at least on passivation layer, the method is further comprising the steps of: interlayer dopant at least is provided between substrate and passivation layer, and the interlayer dopant comprises and is selected for the N-shaped dopant that helps to control the threshold voltage that is applicable to gate stack structure at semiconductor device in use the time.
An embodiment according to a third aspect of the invention we provides the purposes of a kind of gate stack structure in semiconductor device, and gate stack structure comprises: substrate at least comprises basically the semiconductor by the doping of N-shaped charge carrier; The passivation layer at least that comprises silicon, be formed on substrate, and insulator layer at least, be formed on passivation layer, wherein gate stack structure also comprises: the dopant of interlayer at least that provides between substrate and passivation layer, interlayer dopant comprise and are selected for the N-shaped dopant that helps to control the threshold voltage that is applicable to gate stack structure at semiconductor device in use the time.
Can be with any feature application of one aspect of the present invention in another aspect of the present invention, and vice versa.Can be with the feature application of one aspect of the present invention in another aspect of the present invention.One or more other embodiment in other embodiment that can make up any disclosed embodiment and illustrate and/or describe.This one or more feature for embodiment is also possible.
Description of drawings
Now will be by example with reference to the following drawings, wherein:
Fig. 1 schematically illustrates one embodiment of the present of invention;
Fig. 2 schematically illustrates for the drain current comparison grid voltage indicatrix based on the p channel mosfet of Ge, should incorporate based on the p channel mosfet of Ge the gate stack structure of previous proposition into;
Fig. 3 schematically illustrates the drain current comparison grid voltage indicatrix for the p channel mosfet based on Ge according to an embodiment of the invention; And
Fig. 4 schematically illustrates an embodiment of method of the present invention aspect.
Embodiment
In specification, used same numeral or symbolic representation identical portions to grade.
Referring now to Fig. 1, this figure schematically illustrates gate stack structure 1 according to an embodiment of the invention.As seen in Figure 1, it comprises from bottom to up with lower floor and configuring: substrate 10 comprises basically the semiconductor by the doping of N-shaped charge carrier; Passivation layer 12 is included in the silicon that forms on substrate; Insulator layer 13 is included in the high k material that passivation layer 12 forms above, and the interlayer that comprises N-shaped dopant 11 dopant is provided between substrate 10 and passivation layer 12.As describing in Fig. 1, for the N-shaped dopant, use in this example As.In this example, substrate 10 comprises the Ge that is for example adulterated by the N-shaped charge carrier between le15 and le18, and for the high k material in insulator layer 13, uses HfO
2
The principle of one embodiment of the present of invention is described referring now to Fig. 1.Form the different layers in gate stack structure 1 according to an embodiment of the invention when room temperature.When this temperature, the As dopant atom ionizes to form the stator of the dopant ion of positively charged.The positive charge of dopant ion compensates and the interface charge at different interfaces between the layer of gate stack structure 1 and/or the negative electrical charge of Defect Correlation basically.For example, the positive charge of the dopant ion compensation negative electrical charge relevant with for example migration caused charged defects of Ge from substrate 10 to the interface passivation layer 12 and insulator layer 13 and at the dipole of same interface existence.Relate to the negative electrical charge related with charged defects and/or dipole aspect the just displacement of the threshold voltage in causing the device of previous proposition, therefore cause that from this effect the such viewpoint of negative displacement of threshold voltage compensates them and wishes in one embodiment of the invention.
The compensation effect of one embodiment of the present of invention also prolongs and compensates respectively or in combination at substrate 10-passivation layer 12 interfaces and/or the electric charge/defective in the different layers of gate stack structure 1/dipole.One embodiment of the present of invention also can solve other phenomenon that undesirable threshold voltage just is being offset be observed, such as correcting metal work function etc.
For example, although the required displacement of having the ability to make threshold voltage for just or negative, one embodiment of the present of invention also help to control the value of this displacement, namely control it for just or negative degree.This is because the value of threshold voltage shift depends on the number of the N-shaped dopant atom 11 of per unit area.Therefore, by the concentration of rising or reduction N-shaped dopant atom, can control in one embodiment of the invention the required degree of being displaced to of threshold voltage.
As more early discussing like that, the stator compensation of the dopant ion by positively charged in one embodiment of the invention between different layers and/or in electronegative interface charge and/or defective may not need N-shaped dopant 11 to cross over gate stack structures 1 or its diffusion of concrete layer.For N-shaped dopant 11, wish following material, this material helps above-described compensation effect and have the diffusion coefficient value of minimizing in substrate and/or passivation layer.The material that satisfies in one embodiment of the invention these standards and be selected for the N-shaped dopant comprises As, P, Sb and the Bi from the V family of periodic table.
Although describe gate stack structure 1 with reference to Ge is used for substrate 10, one embodiment of the present of invention do not only limit to use such material certainly.In fact, substrate 10 can comprise Ge, GOI, SiGe-OI or its any combination.In addition, although reference is with HfO
2The dielectric substance that is used for insulator layer 13 is described gate stack structure 1, but one embodiment of the present of invention are not limited to use HfO
2, and can use any other dielectric based on hafnium.In fact, for the dielectric substance in insulator layer 13, can use to have value greater than any dielectric substance of 7 effective dielectric constant.
In order to compare between the gate stack structure that formerly proposes and one embodiment of the present of invention, referring now to Fig. 2 and Fig. 3.Fig. 2 diagram is used for the indicatrix based on drain current (Id) the comparison grid voltage (Vg) of the p channel mosfet of Ge, should incorporate based on the p channel mosfet of Ge the gate stack structure of previous proposition into.The layer configuration from bottom to up of the previous gate stack structure that proposes is: comprise the n doped with Ge substrate, comprise the passivation layer of Si and comprise HfO
2Insulator layer.Fig. 3 diagram is used for the indicatrix based on the Id comparison Vg of the p channel mosfet of Ge, should incorporate gate stack structure 1 according to an embodiment of the invention into based on the p channel mosfet of Ge, the gate stack structure as shown in Figure 1 all and preamble is described, in this gate stack structure, provide the interlayer dopant that comprises for the As of N-shaped dopant 11 between substrate 10 and passivation layer 12.In order to measure threshold voltage, make corresponding device with the preferential annular FET technique of self-aligning grid, wherein source electrode and draining contacts by nickel (Ni) and makes and gate contact is made by platinum (Pt).
As the illustration from Fig. 2 and Fig. 3 as seen, draw for the drain voltage of 20mV, 40mV and 60mV the Id comparison Vg indicatrix that is used for two kinds of situations.Drawing 2a in Fig. 2, drawing 2b and drawing 2c and the drawing 3a in Fig. 3, drawing 3b and drawing 3c are corresponding to these respective drain voltage.For the performance with one embodiment of the present of invention compares with the performance that obtains with the previous device that proposes, draw from Id-Vg shown in Fig. 2 and Fig. 3 and extract threshold voltage.Can extract from the Fig. 3 that describes following structure the threshold voltage of approximate-2V, these results relate to the threshold ratio one embodiment of the present of invention with as seen from Figure 2 the approximate 2V that is used for the previous device that proposes.These results verifications in this case for the N-shaped dopant 11 of As in one embodiment of the invention by compensation the different layers place in gate stack result 1 and/negative electrical charge/defective in different layers/dipole helps the negative displacement of threshold voltage.
The result (being specially drain current) of Fig. 2 and Fig. 3 is compared, can find out that the drain current (Fig. 3) that obtains with one embodiment of the present of invention is starkly lower than the drain current (Fig. 2) that obtains with the previous device that proposes.The increase enclosed pasture that disperses from unoptimizable As concentration can illustrate this result, and namely the As excessive doping may occur under this concrete condition.For data shown in Fig. 3, think too high estimation threshold voltage of most probable, this means it can be even than-2V is more negative.
Referring now to Fig. 4, this figure schematically illustrates method according to an embodiment of the invention.As beginning, provide to comprise the semi-conductive substrate 10 that is basically adulterated by the N-shaped charge carrier.In this example, substrate 10 comprises the N-shaped doped with Ge.In step S1, complete the original position cleaning to the surface of N-shaped doped with Ge substrate 10.In step S2, provide the interlayer dopant that comprises in this example for the N-shaped dopant 11 of As on the cleaning surface of N-shaped with reference to Ge substrate 10.In step S2, can deposit approximate upper As atom to an individual layer, this is realized by for example sedimentation time of 2 seconds.In step S3, complete the formation of the passivation layer 12 that comprises silicon on by the substrate 10 that provides N-shaped dopant 11 to retrofit.In one embodiment of the invention, passivation layer 12 can for example have the thickness of approximate 1.5nm.In later step S4, complete the insulator layer 13 that deposition comprises high k material.The example of high k material is based on the dielectric of hafnium in one embodiment of the invention, such as for example HfO
2Wherein use HfO in insulator layer 13 of the present invention
2An embodiment in, HfO
2The thickness of layer is 4nm for example.Although as more early discussing and do not describe in Fig. 1, insulator layer 13 also can be included in the silicon dioxide layer that arranges between passivation layer 12 and high-k dielectric material.By the silicon dioxide layer during the silicon in oxidation passivation layer 12 forms insulator layer 13 owing to being used in the treatment conditions of the high k material of step S4 deposition.Execution in step S1 to S4 in vacuum environment (being specially ultra high vacuum (UHV) environment) and do not destroy such environment, thus can reduce and/or avoid to pollute.Can use any one step in molecular beam epitaxy (MBE) execution in step S1 to S4, this gives the advantage that realizes controllably depositing in the temperature (such as such as room temperature) that reduces a small amount of material.
In method according to an embodiment of the invention, at room temperature execution in step S1 to S4.In step S3, continue 1 minute at 150 ℃ of deposition Si, and in step S4, at 225 ℃ of deposition HfO
2Continue 15 minutes.The additional step that is used for source electrode and drain electrode activation annealing 350 ℃ of execution continues 5 minutes.In these treatment temperatures, for example when As was used for N-shaped dopant and Ge and is used for substrate, the As atom remained in the Ge-Si interface basically.
Method according to an embodiment of the invention is not limited to be performed once, namely after completing steps S4, this process can be circulated back to the beginning of the method and execution in step S1 to S4 iteratively.If obtain the layer configuration of grid structure 1 according to an embodiment of the invention, can walk abreast or not keep so strict sequence order and come any step in execution in step S1 to S4.Any proper technology well known by persons skilled in the art can be used for any step of these steps.In addition, by example passivation layer 12 with insulating barrier 13 in HfO
2The thickness of layer is respectively 1.5nm and 4nm---and they can have different value certainly for example to be suitable for wherein incorporating into application and/or the device of one embodiment of the present of invention.
Above describe the present invention by example fully, and can carry out within the scope of the invention detail modifications.
Can independently or be provided in bright book in any appropriate combination and disclosed each feature in claims and accompanying drawing in due course.
Claims (22)
1. semiconductor device that comprises gate stack structure (1), described gate stack structure (1) comprising:
At least substrate (10), described substrate comprise basically the semiconductor by the doping of N-shaped charge carrier;
Comprise the passivation layer at least (12) of silicon, described passivation layer is formed on described substrate (10), and
At least insulator layer (13), described insulator layer is formed on described passivation layer (12),
Wherein said gate stack structure (1) also comprises:
The dopant of interlayer at least that provides between described substrate (10) and described passivation layer (12), described interlayer dopant comprises N-shaped dopant (11), and described N-shaped dopant (11) is selected as helping to control the threshold voltage that can put on described gate stack structure (1) when described semiconductor device uses.
2. semiconductor device according to claim 1, wherein provide described N-shaped dopant (11) basically in the zone adjacent with conduction, and described conduction forms in described substrate (10) when described semiconductor device uses.
3. according to claim 1 or 2 described semiconductor device, the concentration of wherein said N-shaped dopant (11) is selected for the value of controlling described threshold voltage.
4. according to claim 1,2 or 3 described semiconductor device, wherein said N-shaped dopant (11) are selected for the interface charge that exists at the interface that compensates at least between described substrate (10) and described passivation layer (12).
5. according to the described semiconductor device of arbitrary aforementioned claim, wherein said N-shaped dopant (11) is selected for the interface charge at the interface that compensates at least between described passivation layer (12) and described insulator layer (13).
6. according to the described semiconductor device of arbitrary aforementioned claim, wherein said N-shaped dopant (11) is selected for the electric charge that compensates at least in described passivation layer (12), described insulator layer (13) or its combination.
7. according to the described semiconductor device of arbitrary aforementioned claim, wherein said N-shaped dopant (11) comprises one of arsenic (As), phosphorus (P), antimony (Sb) and bismuth (Bi).
8. according to the described semiconductor device of arbitrary aforementioned claim, wherein said semiconductor device comprises field-effect transistor.
9. according to the described semiconductor device of arbitrary aforementioned claim, wherein said insulator layer (13) comprises having value greater than the dielectric substance of 7 effective dielectric constant.
10. according to the described semiconductor device of arbitrary aforementioned claim, wherein said substrate (10) comprises germanium (Ge), germanium on insulator (GOI), sige-on-insulator (SiGe-OI) or its any combination.
11. a method that is used for the gate stack structure (1) of making semiconductor device comprises the following steps:
Form substrate (10) at least, described substrate comprises the semiconductor (S1) that is basically adulterated by the N-shaped charge carrier;
Described substrate (10) upper form comprise silicon passivation layer at least (12) (S3); And
Form at least insulator layer (13) (S4) on described passivation layer (12),
Described method is further comprising the steps of:
Provide interlayer dopant at least between described substrate (10) and described passivation layer (12), described interlayer dopant comprise be selected as helping controlling the threshold voltage that can put on described gate stack structure (1) when described semiconductor device uses N-shaped dopant (11) (S2).
12. method according to claim 11, wherein in the described step (S2) that described interlayer dopant is provided, described N-shaped dopant (11) is provided in the zone adjacent with conduction basically, and described conduction forms in described substrate (10) when described semiconductor device uses.
13. according to claim 11 or 12 described methods, wherein in the described step (S2) that described interlayer dopant is provided, the concentration of described N-shaped dopant (11) is selected for the value of controlling described threshold voltage.
14. 12 or 13 described methods according to claim 11,, wherein in the described step (S2) that described interlayer dopant is provided, described N-shaped dopant (11) is selected for the interface charge that exists at the interface that compensates at least between described substrate (10) and described passivation layer (12).
15. according to claim 11 to the described method of arbitrary claim in 14, wherein in the described step (S2) that described interlayer dopant is provided, described N-shaped dopant (11) is selected for the interface charge at the interface that compensates at least between described passivation layer (12) and described insulator layer (13).
16. according to claim 11 to the described method of arbitrary claim in 15, wherein in the described step (S2) that described interlayer dopant is provided, described N-shaped dopant (11) is selected for the electric charge that compensates at least in described passivation layer (12), described insulator layer (13) or its combination.
17. according to claim 11 to the described method of arbitrary claim in 16, wherein in the described step (S2) that described interlayer dopant is provided, described N-shaped dopant (11) is selected as comprising one of arsenic (As), phosphorus (P), antimony (Sb) and bismuth (Bi).
18. according to claim 11 to the described method of arbitrary claim in 17, wherein in the step (S4) of the described insulator layer of described formation, described insulator layer (13) is selected as comprising to have value greater than the dielectric substance of 7 effective dielectric constant.
19. according to claim 11 to the described method of arbitrary claim in 18, wherein in the described step (S1) that described substrate is provided, described substrate (10) is selected as comprising germanium (Ge), germanium on insulator (GOI), sige-on-insulator (SiGe-OI) or its any combination.
20. according to claim 11 to the described method of arbitrary claim in 19, wherein carry out described step (S1, S2, S3, S4) in vacuum environment.
21. according to claim 11 to the described method of arbitrary claim in 20, wherein carry out at least one step in described step (S1, S2, S3, S4) with molecular beam epitaxy.
22. the purposes of a gate stack structure (1) in semiconductor device, described gate stack structure (1) comprising:
At least substrate (10), described substrate comprise basically the semiconductor by the doping of N-shaped charge carrier;
Comprise the passivation layer at least (12) of silicon, described passivation layer is formed on described substrate (10), and
At least insulator layer (13), described insulator layer is formed on described passivation layer (12),
Wherein said gate stack structure (1) also comprises:
The dopant of interlayer at least that provides between described substrate (10) and described passivation layer (12), described interlayer dopant comprise the N-shaped dopant (11) that is selected as helping to control the threshold voltage that can put on described gate stack structure (1) when described semiconductor device uses.
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| EP10180822.8 | 2010-09-28 | ||
| EP10180822 | 2010-09-28 | ||
| PCT/IB2011/054162 WO2012042442A1 (en) | 2010-09-28 | 2011-09-22 | Semiconductor device with a gate stack |
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| CN103125014B CN103125014B (en) | 2015-09-23 |
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| CN1366711A (en) * | 2000-02-17 | 2002-08-28 | 皇家菲利浦电子有限公司 | Semiconductor device with integrated CMOS circuit with MOS transistors having silicon-germanium (Sil-Gex) gate electrodes, and method for manufacturing same |
| EP1450395A2 (en) * | 2003-02-13 | 2004-08-25 | Texas Instruments Incorporated | High temperature interface layer growth for high-K gate dielectric |
| WO2009156954A1 (en) * | 2008-06-25 | 2009-12-30 | Nxp B.V. | Interfacial layer regrowth control in high-k gate structure for field effect transistor |
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| JP2004006959A (en) * | 2001-04-12 | 2004-01-08 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP4767843B2 (en) * | 2004-04-14 | 2011-09-07 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| EP1655767B1 (en) * | 2004-10-13 | 2017-03-22 | Imec | Method for making a passivated semiconductor substrate |
| CN100583450C (en) * | 2005-03-11 | 2010-01-20 | 富士通微电子株式会社 | Semiconductor device and its making method |
| US7446380B2 (en) | 2005-04-29 | 2008-11-04 | International Business Machines Corporation | Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS |
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| CN1366711A (en) * | 2000-02-17 | 2002-08-28 | 皇家菲利浦电子有限公司 | Semiconductor device with integrated CMOS circuit with MOS transistors having silicon-germanium (Sil-Gex) gate electrodes, and method for manufacturing same |
| EP1450395A2 (en) * | 2003-02-13 | 2004-08-25 | Texas Instruments Incorporated | High temperature interface layer growth for high-K gate dielectric |
| WO2009156954A1 (en) * | 2008-06-25 | 2009-12-30 | Nxp B.V. | Interfacial layer regrowth control in high-k gate structure for field effect transistor |
Non-Patent Citations (1)
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| MITARD.J ET AL: "Impact of Epi-Si Growth Temperature on Ge-pFET Performance", 《SOLID STATED DEVICE RESEARCH CONFERENCE, 2009. ESSDERC "09. PROCEEDINGS OF THE EUROPEAN》, 18 September 2009 (2009-09-18), pages 411 - 414 * |
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| GB201306306D0 (en) | 2013-05-22 |
| GB2497257A (en) | 2013-06-05 |
| JP2013543257A (en) | 2013-11-28 |
| JP5752254B2 (en) | 2015-07-22 |
| WO2012042442A1 (en) | 2012-04-05 |
| DE112011103249T5 (en) | 2013-08-14 |
| DE112011103249B4 (en) | 2014-01-23 |
| GB2497257B (en) | 2013-11-06 |
| CN103125014B (en) | 2015-09-23 |
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