Classifications

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  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/10—Arrangements for heating
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  • H10W90/00—Package configurations
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
  • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
  • H10W70/635—Through-vias
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  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
  • H05K1/0203—Cooling of mounted components
  • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09072—Hole or recess under component or special relationship between hole and component
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10378—Interposers
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
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  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10431—Details of mounted components
  • H05K2201/10507—Involving several components
  • H05K2201/10515—Stacked components
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  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10431—Details of mounted components
  • H05K2201/1056—Metal over component, i.e. metal plate over component mounted on or embedded in PCB
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/20—Arrangements for cooling
  • H10W40/231—Arrangements for cooling characterised by their places of attachment or cooling paths
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
  • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/221—Structures or relative sizes
  • H10W72/227—Multiple bumps having different sizes
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
  • H10W72/247—Dispositions of multiple bumps
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
  • H10W72/247—Dispositions of multiple bumps
  • H10W72/248—Top-view layouts, e.g. mirror arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/877—Bump connectors and die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/20—Configurations of stacked chips
  • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/20—Configurations of stacked chips
  • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
  • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

• This invention relates generally to semiconductor processing, and more particularly to thermal management structures for stacked semiconductor chips and to methods of assembling the same.
• Stacked semiconductor chip devices present a host of design and integration challenges for scientists and engineers. Common problems include providing adequate electrical interfaces between the stacked semiconductor chips themselves and between the individual chips and some type of circuit board, such as a motherboard or semiconductor chip package substrate, to which the semiconductor chips are mounted. Another critical design issue associated with stacked semiconductor chips is thermal management. Most electrical devices dissipate heat as a result of resistive losses, and semiconductor chips and the circuit boards that carry them are no exception. Still another technical challenge associated with stacked semiconductor chips is testing.
• a process flow to transform a bare semiconductor wafer into a collection of chips and then mount those chips on packages or other boards involves a large number of individual steps.
• B ecause the processing and mounting of a semiconductor chip proceeds in a generally
• Thermal management of a semiconductor chip or chips in a stacked arrangement remains a technical challenge during required electrical testing of one or more of the semiconductor chips.
• a given semiconductor chip in a stacked arrangement may dissipate heat to such an extent that active thermal management is necessary in order to either prevent the one or all of the semiconductor chips in the stack from entering thermal runaway or so that one or more of the semiconductor chips in the stack may be electrically tested at near or true operational power levels and frequencies.
• the present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
• a method of manufacturing includes coupling a first semiconductor chip to a first substrate.
• the first substrate includes a first aperture.
• a thermal management device is placed in thermal contact with the first semiconductor chip by way of the first aperture.
• a method manufacturing includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device.
• the semiconductor chip device includes a first substrate coupled to the first semiconductor chip.
• the first substrate has a first aperture.
• the thermal contact is by way of the first aperture.
• an apparatus in accordance with another aspect of an embodiment of the present invention, includes a semiconductor chip device that has a first semiconductor chip coupled to a first substrate.
• the first substrate includes a first aperture.
• a thermal management device is in thermal contact with the first semiconductor chip by way of the first aperture.
• FIG. 1 is a sectional view of an exemplary embodiment of semiconductor chip device that includes semiconductor chips connected to opposite sides of an interposer;
• FIG. 2 is a portion of FIG. 1 shown at greater magnification
• FIG. 3 is a sectional view like FIG. I , but of an alternate exemplary embodiment of a semiconductor chip device that includes semiconductor chips connected to opposite sides of an interposer and with an alternative thermal management device;
• FIG. 4 is a sectional view of an exemplary semiconductor chip device exploded from a circuit board with a thermal management device mounted thereto;
• FIG. 5 is a sectional view of an exemplary semiconductor chip device at a preliminary stag of assembly
• FIG. 6 is a sectional view like FIG. 5, but depicting additional assembly
• FIG. 7 is a sectional view like FIG. 6 depicting attachment of an exemplary thermal management device to the semiconductor chip device
• FIG. 8 is a sectional view depicting mounting of the exemplary semiconductor chip device on a exemplary circuit board
• FIG. 9 is a sectional view of an alternate exemplary embodiment of a semiconductor chip device that includes semiconductor chips connected to opposite sides of an interposer;
• FIG. 10 is a pictorial view of the interposer depicted in FIG. 9.
• Various stacked semiconductor chip arrangements are disclosed.
• the disclosed embodiments incorporate a substrate or circuit board with an aperture to accommodate at least a portion of one of the semiconductor chips and/or a thermal management device.
• the thermal management device is operable to dissipate heat from a lowermost semiconductor chip in the chip stack.
• the aperture reduces the form factor of the stack while still providing thermal management. Additional details will now be described.
• FIG. 1 therein is shown a sectional view of an exemplary embodiment of semiconductor chip device 10 that includes a semiconductor chip 15 connected to a side 17 of an interposer 20 and plural semiconductor chips 25, 30 and 35 connected to the opposite side 37 of the interposer 20.
• the exemplary structures of the semiconductor chip device 10 and alternatives thereof disclosed herein are and associated with the semiconductor chips 15, 25, 30 and 35 disclosed herein are not dependent on a particular electronic functionality or particular types of semiconductor chips or interposers.
• the semiconductor chips 15, 25, 30 and 35 may be any of a myriad of different types of circuit devices used in electronics, such as, for example, microprocessors, graphics processors, combined
• microprocessor/graphics processors application specific integrated circuits, memory devices, active optical devices, such as lasers, passive optical devices or the like, and may be single or multi-core or even stacked laterally with additional dice. Furthermore, any or all of the semiconductor chips 15, 25,
• the interposer 20 could be a semiconductor chip.
• the term "chip” includes an interposer and vice versa.
• the semiconductor chips 15, 25, 30 and 35 and the interposer 20 may be constructed of bulk
• the interposer 20 may be composed of a variety of materials suitable for use in a stacked semiconductor chip arrangement. Some desirable properties include, for example, a coefficient of thermal expansion that is relatively close to the CTE's of the semiconductor chips 15, 25, 30 and 35, ease of manufacture, and thermal conductivity. Exemplary materials include, for example, silicon, germanium, sapphire, diamond, carbon nanotubes in a polymer matrix, or the like.
• the semiconductor chip 15 may be electrically connected to the interposer 20 by way of plural interconnect structures 45.
• the interconnect structures 45 may be conductive pillars, solder joints or other types of interconnects.
• the semiconductor chip 25 may be similarly connected to the interposer 20 by way of plural interconnect structures 50 which may be conductive pillars, solder joints or other types of interconnects.
• the dashed oval 55 circumscribes portions of the interposer 20, the semiconductor chips 25, 30 and 35 and other structures. That portion circumscribed by the dashed oval 55 will be shown at greater magnification in FIG. 2.
• the interposer 20 may be mounted to a substrate or circuit board 60 and electrically connected thereto by way of plural interconnect structures 65.
• the interconnect structure 65 may be conductive pillars, solder joints or other types of interconnects.
• the exemplary structures of the semiconductor chip device 10 disclosed herein are not dependent on a particular electronic circuit board functionality.
• the circuit board 60 may be a semiconductor chip package substrate, a motherboard, a circuit card, or virtually any other type of printed circuit board.
• the circuit board 60 may consist of a central core upon which one or more buildup layers are formed and below which an additional one or more buildup layers are formed.
• the core itself may consist of a stack of one or more layers. If implemented as a semiconductor chip package substrate, the number of layers in the circuit board 60 can vary from four to sixteen or more, although less than four may be used. So-called “coreless" designs may be used as well.
• the layers of the circuit board 60 may consist of an insulating material, such as various well-known epoxies, interspersed with metal interconnects. A multi-layer configuration other than buildup could be used.
• the circuit board 20 may be composed of well-known ceramics or other materials suitable for package substrates or other printed circuit boards.
• the circuit board 60 is provided with a number of conductor traces and vias and other structures (not visible) in order to provide power, ground and signals transfers between the semiconductor chips 15, 25, 30 and 35 and the interposer 20 and another device, such as another circuit board for example.
• the circuit board 60 may be provided with an aperture 70 in which one or more of the semiconductor chips 25, 30 and 35 may project.
• the aperture 70 advantageously projects entirely through the thickness of the circuit board 60 to enable an optional thermal management device 75 to be placed in thermal contact with at least the semiconductor chip 30.
• the positions of the semiconductor chips 25, 30 and 35 and the thermal management device 75 relative to the aperture 70 may be varied to provide some desirable height for the semiconductor chip device 10.
• at least one of the semiconductor chips 25, 30 and 35 could be partially or completely positioned in the aperture 70 and/or a portion of the thermal management device 75 could be similarly positioned.
• the thermal management device 75 is in thermal contact with the semiconductor chip 35 by way of the aperture 70.
• the thermal management device 75 may take on a myriad of configurations such as the heat- finned heat spreader arrangement as shown or virtually any other type of heat transfer device design. If desired, the thermal management device 75 may include a vapor chamber and/or a solid state thermoelectric cooler. Various types of materials suitable for heat transfer devices may be used, such as copper, nickel, aluminum, steel, combinations of these or the like. Somewhat more exotic materials, such as diamond or sapphire, could also be used for extreme thermal environments.
• An optional heat spreader 80 may be mounted on the semiconductor chip 15 to provide thermal management for the upper reaches of the semiconductor chip device 10.
• the heat spreader 80 may take on a myriad of configurations, such as the finned design as shown, a more traditional semiconductor chip package lid, combinations of the two or virtually any other type of heat conveyance device.
• exemplary materials include copper, nickel, aluminum, steel,
• the semiconductor chip device 10 may be mounted to a variety of different types of electronic structures.
• the semiconductor chip device 10 is mounted to a circuit board 85, which may be a circuit card, a motherboard or virtually any type of circuit board, and connected thereto by way of plural interconnect structures 90, which bond the circuit board 60 to the circuit board 85.
• the interconnect structures 90 in this illustrative embodiment may be an array of solder balls.
• other types of interconnect structures such as pin grid arrays, land grid arrays or other interconnect structures could be used as well.
• the thermal management device 75 that is in thermal contact with at least the semiconductor chips 35 may have a thickness large enough to require projection either into or through the circuit board 85.
• the thermal management device 75 in this circuit board 85 may be provided with a suitable aperture 95 to accommodate the thermal management device 75. If the thermal management device 75 has sufficient dimension along the z-axis then convective cooling may be accomplished if there is air or other gaseous flow in the x-y plane.
• a thermal interface material 100 may be positioned in the aperture 70 and in thermal contact with the thermal management device 75 and at least the semiconductor chip 35. If desired, the thermal interface material 100 may be extensive enough to completely fill the aperture 70 as desired.
• the thermal interface material 100 may be composed of a variety of different types of thermal interface material suitable for thermal management, such as, silicone rubber, silicone greases, acrylic polymers or the like. Even metallic materials, such indium, gallium, various solders or the like could be used.
• the semiconductor chip 35 may have to fabricated with a suitable wetting film or even a stack if a metallic material is used. Such a stack might include an aluminum film formed on the semiconductor chip 35, a titanium film formed on the aluminum film, a
• the aluminum film provides advantageous adhesion with silicon.
• the titanium film provides a barrier layer to prevent gold and indium from migrating into the semiconductor chip 35 and to facilitate adhesion with the nickel-vanadium film, and thenickel-vanadium film provides desirable adhesion with gold and a barrier to inhibit diffusion into the titanium layer.
• the gold film provides a desirable wetting surface for indium.
• FIG. 2 Attention is now turned to FIG. 2, which as noted above is the portion of FIG. 1
• the interposer 20 may be provided with numerous internal wiring structures, such as the wiring structure represented schematically by the black line 105.
• the semiconductor chips 25, 30 and 35 may be similarly provided with multiple internal wiring structures which are represented schematically by the black lines 1 10, 1 15 and 120 respectively.
• the wiring structures 105, 1 10, 1 15 and 120 may be single wiring lines or multiple conductor layers interconnected by conductive vias or other types of structures as desired.
• the interposer 20 may be electrically connected to the semiconductor chip 25 as described above by way of plural interconnect structures 50.
• the interconnect structures 50 may be microbumps, conductive pillars or the like.
• the interconnect structures 50 may be electrically connected to respective conductor structures or pads 125 and 130 of the interposer 20 and the semiconductor chip 25.
• semiconductor chips 25 and 30 may be connected electrically by conductor structures 135 and the semiconductor chips 30 and 35 may be connected electrically by conductor structures 140.
• the conductor structures 135 and 140 may be microbumps, conductive pillars or the like.
• the conductor structures 135 may be electrically connected to respective conductor structures or pads 145 and 146 of the semiconductor chips 25 and 30 and the conductor structures may be electrically connected to respective conductor structures or pads 147 and 148 of the semiconductor chips 30 and 35.
• Any of the conductor structures disclosed herein as possibly being composed of solder may be composed of various types of solders, such as lead-free or lead-based solders.
• solders examples include tin-silver (about 97.3% Sn 2.7% Ag), tin-copper (about 99% Sn 1 % Cu), tin-silver-copper (about 96.5 % Sn 3% Ag 0.5% Cu) or the like.
• lead-based solders examples include tin-lead solders at or near eutectic proportions or the like.
• the various pads 125, 130, 145, 146, 147 and 148, or conductive pillars referenced above, may be composed of copper, aluminum, silver, gold, platinum, titanium, refractory metals, refractory metal compounds, alloys of these or the like.
• the pads 125, 130, 145, 146, 147 and 148 may consist of underbump metallization structures, which provide a barrier functionality to inhibit solder infusion.
• a laminate of plural metal layers such as a titanium layer followed by a nickel-vanadium layer followed by a copper layer.
• a titanium layer may be covered with a copper layer followed by a top coating of nickel.
• conducting materials may be used for the conductors.
• Various well-known techniques for applying metallic materials may be used, such as plating, physical vapor deposition, chemical vapor deposition, or the like.
• the thermal interface material 100 may be partially coextensive with the aperture 170 as depicted in FIG. 2 or even completely coextensive. Indeed, the thermal interface material 100 could be provided in such quantity that all of the semiconductor chips 25, 30 and 35 are in contact therewith.
• FIG. 3 is a sectional view like FIG. 1.
• the semiconductor chip device 10 ' may be understood by referring now to FIG. 3 , which is a sectional view like FIG. 1.
• the semiconductor chip device 10 ' may be understood by referring now to FIG. 3 , which is a sectional view like FIG. 1.
• the semiconductor chip device 10 ' may be understood by referring now to FIG. 3 , which is a sectional view like FIG. 1.
• semiconductor chip device 10 ' may be configured substantially like the semiconductor chip device 10 with a few notable exceptions. Thus, semiconductor chips 15, 25, 30 and 35 may be connected to opposite sides of the interposer 20. A heat sink spreader 75 ' may be placed in thermal contact with at least the semiconductor chip 35 and the chips 25, 30 and 35 may be positioned partially or entirely in an aperture 70 in the circuit board 60. However, the thermal management device 75 ' in this illustrative embodiment has a shorter height than the thermal management device 75 depicted in FIG. 1. Thus, there is no need to provide the circuit board 85 ' with an aperture to accommodate the thermal management device 75 '. All that is required is for a sufficient gap Z , to be provided to accommodate the alternate thermal management device 75 '.
• the thermal management device 75 or 75 ' is secured to the semiconductor chip device 10 largely by the inherent tackiness of the thermal interface material 100.
• the skilled artisan will appreciate that a variety of mechanisms may be used to position a thermal management device relative to the semiconductor chips of any of the disclosed embodiments of a semiconductor chip device.
• FIG. 2 is a sectional view depicting the semiconductor chip device 10 exploded from an alternate exemplary embodiment of a circuit board 85 " .
• a thermal management device 75 " may be secured to the circuit board 85 " and project downwardly through an aperture 95 therein by way of one or more brackets 150 and 155.
• the brackets 150 and 155 may be secured to the circuit board 85 " by any of a myriad of known fastening techniques, such as screws, solder, adhesives, etc.
• the thermal management device 75 " may be secured to the brackets 150 and 155 by way of the depicted screws 160 and 165 or by adhesives, clips, even solder or any of a variety of well-known fastening techniques.
• the thermal management device 75 " may be secured to the circuit board 85 " first and thereafter the semiconductor chip device 10 may be mounted to the circuit board 85 " so that thermal contact is established between the thermal interface material 100 and at least the
• a suitable reflow process may be performed as necessary in order to establish metallurgical bonding associated with the interconnect structures 90 and the circuit board 85 ".
• FIGS. 1 and 2 may be understood by referring now to FIGS. 5, 6 and 7 and initially to FIG. 5.
• FIG. 5 is a sectional view of the semiconductor chip device 10 prior to the mounting thereto of the semiconductor chips 25, 30 and 35 depicted in FIGS. 1 and 2.
• the semiconductor chip 15, if produced en masse as part of a semiconductor wafer or other work piece may be first singulated and thereafter mounted to the interposer 20 and electrically connected thereto by the interconnect structures 45.
• the interposer 20 may similarly be fabricated en masse and singulated prior to or after the mounting thereto of the semiconductor chip 15.
• the interconnect structures 45 may be subjected to a solder reflow process as necessary depending upon their composition.
• the interconnect structures 65 may be fabricated and connected to the interposer 20 prior to mounting the interposer 20 to the circuit board 60 or in the event that the interconnect structure 65 constitute the union between two structures such as two solder bumps or a pillar and a bump, etc. then the interconnect structure 65 may be separately formed in their respective haves on the interposer 20 and the circuit board 60 and thereafter joined together in a mounting/re flow process.
• the interconnect structures 50 that are designed to electrically interface and bond with the semiconductor chip 25 depicted in FIGS. 1 and 2 may be positioned on the interposer 20 at this point or at a later stage if desired.
• the aperture 70 may be established in the circuit board 60 in a variety of ways.
• the circuit board 60 may be fully formed and thereafter a suitable material removal process may be performed in order to establish the aperture. This may constitute, for example, a suitable etch process, laser ablation or some other material removal process.
• the circuit board 60 may be formed in successive build up processes in which the aperture 70 is simply patterned and thus formed as part of the build up process.
• the interconnect structures 90 may be attached to the circuit board 60 at this stage or, such structures may actually be positioned on, for example, the circuit board 85 and thereafter connected to the circuit board 60.
• interconnect structures 90 will depend upon their composition such is the case if the interconnect structures 90 consist of a solder joint formed by the mating of two solder structures such as bumps.
• the semiconductor chip 15 and the interposer 20 are both in electrical contact with the circuit board 60.
• the entire semiconductor chip device consisting of the chip 15, the interposer 20 and the circuit board 60 may be subjected to electrical testing to verify the integrity of those three major components. This is advantageous since failure in any of those major components may be detected at this stage without having to go through the time and expense and possible material costs associated with performing such testing only after the semiconductor chips 25, 30 and 35 depicted in FIGS. 1 and 2 are mounted thereto.
• the semiconductor chips 25, 30 and 35 may be mounted to the interposer 20 by establishing the respective interconnect structures (135 and 140 shown in FIG. 2). This may entail, for example, a suitable reflow process or processes. With the semiconductor chips 25, 30 and 35 in position, the semiconductor chip device 10 may again undergo electrical testing to verify not only the functionality of the semiconductor chips 25, 30 and 35, but also the various combined electrical functionality of the entire semiconductor chip device 10.
• the thermal management device 75 may be supplied with a quantity of the thermal interface material 100 and thereafter brought into contact with at least the semiconductor chip 35 of the semiconductor chip device 10.
• the aperture 70 enables the semiconductor chips 25, 30 and 35 to be readily moved into engagement with the interposer 20 after the interposer 20 has been mounted to the circuit board 60.
• a portion or all of the thermal interface material 100 may be applied to the semiconductor chip 35 and the other semiconductor chips 30 and 25 as desired and thereafter the thermal management device 75 may be brought into contact therewith in order to establish the requisite thermal contact.
• the semiconductor chip device 10 including the thermal management device 75 may be positioned on the circuit board 85 so that the thermal management device 75 projects at least partially and possibly all the way through the aperture 95 and a reflow if necessary performed in order to bond the circuit board 85 by way of the interconnect structures 90.
• one or more semiconductor chips may be stacked on an underside of an interposer and project downwardly in or through a single aperture in a circuit board.
• FIG. 9 is a sectional view like FIG.
• thermal management device 75 may be in thermal contact with respective thermal interface material portions 200 and 205 that are positioned in the apertures 180 and 185.
• multiple thermal management devices 75 one for each of the stacks 170 and 175 could be placed in thermal contact therewith as desired.
• the circuit board 85 may be provided with the aperture 95 to accommodate the thermal management device 75.
• FIG. 10 is a pictorial view of the circuit board 195 depicted in FIG. 9, various electrical routing structures such as traces and conductive vias will have to be routed around the apertures 180 and 185.
• FIG. 10 which is a pictorial view of the circuit board 195 depicted in FIG. 9, various electrical routing structures such as traces and conductive vias will have to be routed around the apertures 180 and 185.
• FIG. 10 which is a pictorial view of the circuit board 195 depicted in FIG. 9
• various electrical routing structures such as traces and conductive vias will have to be routed around the apertures 180 and 185.
• FIG. 10 which is a pictorial view of the circuit board 195 depicted in FIG. 9
• FIG. 10 various electrical routing structures such as traces and conductive vias will have to be routed around the apertures 180 and 185.
• FIG. 10 which is a pictorial view of the circuit board 195 depicted in FIG. 9
• FIG. 10 which is
• any of the exemplary embodiments disclosed herein may be embodied in instructions disposed in a computer readable medium, such as, for example, semiconductor, magnetic disk, optical disk or other storage medium or as a computer data signal.
• the instructions or software may be capable of synthesizing and/or simulating the circuit structures disclosed herein.
• an electronic design automation program such as Cadence APD, Encore or the like, may be used to synthesize the disclosed circuit structures.
• the resulting code may be used to fabricate the disclosed circuit structures.

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• 2010
  • 2010-09-24 US US12/889,590 patent/US8472190B2/en active Active
• 2011
  • 2011-09-21 WO PCT/US2011/052466 patent/WO2012040271A1/en not_active Ceased
  • 2011-09-21 JP JP2013530242A patent/JP2013538012A/ja active Pending
  • 2011-09-21 EP EP11764639.8A patent/EP2619795A1/en not_active Withdrawn
  • 2011-09-21 CN CN2011800435900A patent/CN103098207A/zh active Pending
  • 2011-09-21 KR KR1020137007014A patent/KR20130102052A/ko not_active Ceased

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