WO2012034345A1 - 一种石墨烯器件及其制造方法 - Google Patents

一种石墨烯器件及其制造方法 Download PDF

Info

Publication number
WO2012034345A1
WO2012034345A1 PCT/CN2011/000291 CN2011000291W WO2012034345A1 WO 2012034345 A1 WO2012034345 A1 WO 2012034345A1 CN 2011000291 W CN2011000291 W CN 2011000291W WO 2012034345 A1 WO2012034345 A1 WO 2012034345A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
layer
graphene
region
semiconductor
Prior art date
Application number
PCT/CN2011/000291
Other languages
English (en)
French (fr)
Inventor
梁擎擎
金智
王文武
钟汇才
刘新宇
朱慧珑
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US13/140,141 priority Critical patent/US8703558B2/en
Publication of WO2012034345A1 publication Critical patent/WO2012034345A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Definitions

  • the present invention generally relates to a semiconductor device and a method of fabricating the same, and, in particular, to a semiconductor device of graphene and a method of fabricating the same. Background technique .
  • CMOS devices can still be based on silicon semiconductor substrates as they are now after l lnm-16nm technology generation.
  • a research hotspot is the development of new material systems with higher carrier mobility and new technologies to further extend Moore's Law and beyond silicon CMOS (Beyond Si-CMOS) to advance the development of integrated circuit technology.
  • Graphene materials have received extensive attention due to their excellent physical properties, such as high carrier mobility, high electrical conductivity, and high thermal conductivity. They are a carbon-based material that is highly regarded. Although graphene materials exhibit many excellent physical properties, their use as high mobility channel materials in CMOS devices faces many challenges due to their almost zero bandgap. At present, some studies have shown that the switching ratio of graphene devices can be increased to some extent by increasing the band gap of graphene, but at the same time, graphene carrier mobility or device speed will be sacrificed more or less.
  • the present invention provides a graphene device structure, the device structure comprising: a graphene layer; a gate region in contact with the graphene layer; and a graphene layer formed on both sides of the gate region a semiconductor doped region in contact, wherein the semiconductor doped region is isolated from the gate region; a contact formed on the gate region and a contact formed on the semiconductor doped region.
  • the present invention also provides a method for fabricating the above graphene device, the method comprising: A. providing a SOI substrate, the SOI substrate comprising a top silicon, a buried oxide layer, and a back a substrate; a back gate region including a gate electrode and a gate dielectric layer thereon is formed on the top silicon, buried oxide layer, the gate electrode sidewall is surrounded by the isolation layer, and the gate electrode Forming a semiconductor doped region in the top silicon on both sides; (: partially covering the back gate region and the semiconductor doped region to form a graphene layer; D, forming an insulating layer on the device; E, in the A contact is formed on the gate electrode not covered by the graphene in the insulating layer, and a contact is formed on the semiconductor doped region not covered by the graphene in the insulating layer.
  • a semiconductor doped region in contact with the graphene layer is formed on both sides of the gate region, and the switching ratio of the graphene device is improved by the semiconductor doped region without increasing
  • the band gap of the large graphene does not reduce the mobility of the graphene material, that is, the speed of the device, so that the graphene material can be better applied in CMOS devices.
  • FIG. 1 shows a schematic view of a structure of a graphene device according to an embodiment of the present invention
  • FIG. 2 shows an energy band diagram of an n-type graphene device in each mode of operation according to an embodiment of the present invention
  • FIG. 3 shows an energy band diagram of a p-type graphene device in various modes of operation in accordance with an embodiment of the present invention
  • Figures 4-9B show schematic views of various stages of fabrication of an embodiment of a graphene device in accordance with the present invention. detailed description
  • the present invention generally relates to a graphene device and a method of fabricating the same.
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed in the first and second features. Between the embodiments, such first and second features may not be in direct contact.
  • the device structure includes: a graphene layer 202, which may include a single or multiple layers of graphene atoms a gate region 204 in contact with the graphene layer 202, the gate region including a gate dielectric layer 204-1 and a gate electrode 204-2, the gate dielectric layer including Si0 2 , SiON or high-k dielectric material (and compared si0 2, having a high dielectric constant), examples of the high-k dielectric material comprises: Hf0 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3, La 2 0 3, Zr0 2, LaAlO, which In combination and/or other suitable materials, the gate electrode comprises polysilicon or a metal material (eg, TiN); a semiconductor doped region 206 formed on both sides of the gate region 204 in contact with the graphene layer
  • the energy band diagrams of the n-type and p-type graphene devices will be described in detail below.
  • the n-type graphene device means that the semiconductor doped region is n-type doped.
  • the p-type graphene device refers to a semiconductor doped region which is p-type doped, wherein: Vgs is a gate-source voltage, Vds is a drain-source voltage, and Vthn and Vthp are threshold voltages of an n-type, p-type device, respectively.
  • FIG. 2 is an energy band diagram of the n-type graphene device in each working mode.
  • the gate bias is lower than the threshold voltage (in this case, Vgs ⁇ 0)
  • the device is in an off state, referring to FIG. 2
  • the energy band diagram of the cut-off state shown in Fig. in which the Fermi level in the graphene is lower than the Dirac point, and thus the carrier is a hole, and since the semiconductor doped region at both ends is n-type, the space in the graphene is empty.
  • the hole needs to cross the higher barrier to reach the source and drain regions, so the device is turned off and the leakage current is inversely proportional to the barrier height.
  • the gate bias is higher than the threshold voltage (Vgs>0)
  • the Fermi level in the graphene is higher than the Dirac point
  • the carrier is the electron
  • the n-type semiconductor doped region at both ends does not form a potential for the electron.
  • the barrier, and thus the device is turned on refer to the band diagram of the linear conductive or saturated state shown in Figure 2. Since there is no limit to the band gap of graphene in this device, very high mobility can be achieved.
  • FIG. 3 is an energy band diagram of the p-type graphene device in each working mode.
  • the gate bias is higher than the threshold voltage (Vgs ⁇ 0)
  • the device is in the off state, as shown in FIG.
  • the Fermi level in the graphene is lower than the Dirac point, the carrier is a hole, and the p-type semiconductor doping region at both ends is substantially not A barrier is formed, and thus the device is turned on, referring to the band diagram of the linear conductive or saturated state shown in FIG. Since there is no limit to the band gap of graphene in this device, very high mobility can be achieved.
  • the graphene device and the energy band diagram of the present invention are described in detail above.
  • the switching ratio of the graphene device is improved by the n-type or p-type semiconductor doping region without affecting
  • FIGS. 4-9B there are schematic diagrams of intermediate steps of an embodiment of a method for fabricating a graphene device according to the present invention, including a top view, an AA' view, and BB. To the view.
  • a substrate is provided, the substrate including an insulating layer and a semiconductor layer thereon.
  • the substrate may be an SOI substrate 200, as shown in FIG. 4A,
  • the SOI substrate 200 includes a top silicon 200-3, a buried oxide layer 200-2, and a back substrate 200-1.
  • the buried oxide layer 200-2 is an insulating layer of the substrate, and the top silicon 200-3 is A semiconductor layer of the substrate.
  • a back gate region 204 including a gate electrode 204-2 and a gate dielectric layer 204-1 thereon is formed on the insulating layer 200-2 in the semiconductor layer 200-3 of the substrate, the gate The sidewall of the electrode 204-2 is surrounded by the isolation layer 207, and a semiconductor doped region 206 is formed in the semiconductor layer 200-3 on both sides of the gate electrode 204-2, referring to FIG. 5 (top view), FIG. 5A (AA, direction) View).
  • the top silicon 200-3 is etched to form a gate trench, and heavily ion doped to form a semiconductor doping on the top silicon 200-3 on both sides of the gate trench.
  • the impurity region 206 is then formed with an isolation layer 207, such as SiO 2 or Si 3 N 4 , etc., on the sidewall of the gate trench, and then a gate electrode 204-2 is formed in the gate trench.
  • the gate electrode 204- 2 includes polysilicon.
  • the gate electrode 204-2 may further comprise a suitable material such as metal.
  • the gate may be formed in the gate trench by depositing polysilicon on the device and then planarizing, such as CMP.
  • Electrode 204-2 optionally, the same type of doping as the semiconductor doped region may be formed in the gate electrode of the polysilicon, refer to FIG. 4 (top view), Figure 4A (AA, to the view) is shown. Then, the isolation layer 207 on the semiconductor doping region 206 is further removed, and the gate dielectric layer 204-1 is formed on the gate electrode 204-2 to form the back gate region 204, referring to FIG. 5 (top view), FIG. 5A (AA) , to the view).
  • the gate dielectric layer includes a SiO 2 SiON or a high-k dielectric material (having a high dielectric constant compared to Si0 2 ).
  • step S03 the back gate region 204 and the semiconductor doping region 206 are partially covered to form a graphene layer 202.
  • the single or multiple layers of graphene material can be formed by CVD thermal decomposition, micromechanical stripping, and their bond transfer methods or other suitable methods.
  • an interlayer dielectric layer 208 is formed on the device.
  • a dielectric material such as Si0 2 may be deposited on the device, and then flattened.
  • a CMP (Chemical Mechanical Polishing) method forming an interlayer dielectric layer 208, which may be, but not limited to, for example, undoped silicon oxide (SiO 2 ), doped silicon oxide (eg, Borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si 3 N 4 )
  • a contact 212 is formed on the gate electrode 204-2 not covered by the graphene layer 206 in the interlayer dielectric layer 208, and is not covered by the graphene layer 206 in the interlayer dielectric layer 208.
  • Contact 212 is formed on semiconductor doped region 206, with reference to Figure 9 (top view), Figure 9A (AA, to view), and Figure 9B (BB, to view).
  • the interlayer dielectric layer 208 and the gate dielectric layer 204-1 are etched by a mask, and the gate electrode 204-2 and the semiconductor doping region 206 are exposed to form a contact.
  • Hole 210 with reference to Fig. 8 (top view), Fig.
  • FIG. 8B (BB, view), wherein Fig. 8A (AA, view) is a schematic view of a device including a graphene layer portion at this step.
  • the contact hole 210 is filled with a metal material such as W Cu or the like to form a contact 212, see FIG. 9 (top view), FIG. 9B (BB, view), wherein FIG. 9A (AA, view) is A schematic of a device comprising a portion of a graphene layer in the step.
  • the semiconductor doped layer 206 and the polysilicon gate electrode 204-2 may be metal silicided prior to forming the contact 212 to form a metal silicide layer to reduce contact resistance.
  • the above is only one embodiment for realizing the structure of the graphene device of the present invention, which is a graphene device structure.
  • D The embodiments of the graphite germanium device structure and the manufacturing method for forming the present invention are described in detail above, and the switching ratio of the graphene device is improved by forming an n-type or p-type semiconductor doped layer in contact with the graphene layer. It is not necessary to increase the band gap of the graphite germanium material, and thus does not affect the mobility of carriers in the graphene device and thus does not have to sacrifice the speed of the device, thereby making the graphene material better used in CMOS devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Description

一种石墨烯器件及其制造方法 技术领域
本发明通常涉及一种半导体器件及其制造方法， 具体来说， 涉及 一种石墨烯的半导体器件及其制造方法。 背景技术 .
当前， 针对前瞻性先导研究， 国际上最关心的是 l lnm-16nm技术 代以后， CMOS 器件是否还能象现在这样基于硅半导体衬底。 一个研 究热点是开发新的具有更高载流子迁移率的材料体系和新的技术手段 来进一步延展摩尔定律和超越硅 CMOS ( Beyond Si-CMOS ) , 推进集 成电路技术的发展。
石墨烯材料以其优异的物理性质得到了广泛的关注， 比如其高的 载流子迁移率、 高导电性能以及高导热性能等， 是被人们很看好的一 种碳基材料。 虽然石墨烯材料展现出了很多优异的物理特性， 但由于 其几乎为零的带隙， 使其作为高迁移率沟道材料在 CMOS器件中的应 用还面临着许多挑战。 目前， 一些研究表明能够在一定程度上通过增 大石墨烯的带隙， 来提高石墨烯器件的开关比， 但同时， 都会或多或 少会牺牲石墨烯载流子迁移率或器件的速度。
因此， 有必要提出一种能增加石墨烯器件开关比而又无需增大石 墨烯材料的带隙， 从而不影响器件速度的石墨烯器件结构及其制造方 法。 发明内容
鉴于上述问题， 本发明提供了一种石墨烯器件结构， 所述器件结 构包括： 石墨烯层； 与石墨烯层相接触的栅极区； 形成于栅极区两侧 的、 与石墨烯层相接触的半导体掺杂区， 其中所述半导体掺杂区与所 述栅极区相互隔离； 形成于栅极区上的接触以及形成于半导体掺杂区 上的接触。
此外， 本发明还提供了上述石墨烯器件的制造方法， 所述方法包 括： A、 提供 SOI村底， 所述 SOI衬底包括顶层硅、 埋氧化层以及背 衬底； B、 在所述顶层硅内、 埋氧化层上形成包括栅电极和其上的栅介 质层的背栅极区， 所述栅电极侧壁由隔离层包围， 以及在所述栅电极 两侧的顶层硅内形成半导体掺杂区； （：、 部分覆盖所述背栅极区以及半 导体掺杂区以形成石墨烯层； D、 在所述器件上形成绝缘层； E、 在所 述绝缘层内、 未被石墨烯覆盖的栅电极上形成接触， 以及在所述绝缘 层内、 未被石墨烯覆盖的半导体掺杂区上形成接触。
通过采用本发明所述的器件结构， 在栅极区的两侧形成了与石墨 烯层相接触的半导体掺杂区， 通过所述半导体掺杂区来提高石墨烯器 件的开关比， 而不必增大石墨烯的带隙， 因而不会降低石墨烯材料的 迁移率即器件的速度， 从而使石墨烯材料在 CMOS器件中的得到更好 的应用。 附图说明
图 1示出了根据本发明实施例的石墨烯器件结构的示意图； 图 2示出了根据本发明的实施例的 n型石墨烯器件在各个工作模 式下的能带图；
图 3 示出了根据本发明的实施例的 p型石墨烯器件在各个工作模 式下的能带图；
图 4-图 9B示出了根据本发明石墨烯器件的实施例各个制造阶段的 示意图。 具体实施方式
本发明通常涉及一种石墨烯器件及其制造方法。 下文的公开提供 了许多不同的实施例或例子用来实现本发明的不同结构。 为了简化本 发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们 仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同 例子中重复参考数字和 /或字母。 这种重复是为了简化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明 提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可 以意识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描 述的第一特征在第二特征之 "上"的结构可以包括第一和第二特征形成 为直接接触的实施例， 也可以包括另外的特征形成在第一和第二特征 之间的实施例， 这样第一和第二特征可能不是直接接触。
参考图 1 , 图 1示出了根据本发明实施例的石墨烯器件结构的示意 图， 所述器件结构包括： 石墨烯层 202， 所述石墨烯层 202可以包括单 层或多层的石墨烯原子； 与石墨烯层 202相接触的栅极区 204， 所述栅 极区包括栅介质层 204-1和栅电极 204-2,所述栅介质层包括 Si02、SiON 或高 k介质材料 （和 Si02相比， 具有高的介电常数） ， 高 k介质材料 的例子包括： Hf02、 HfSiO, HfSiON , HfTaO, HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO, 其组合和 /或者其它适当的材料， 所述栅电极包 括多晶硅或金属材料（例如 TiN )； 形成于栅极区 204两侧的、 与石墨 烯层 202相接触的半导体掺杂区 206，所述半导体掺杂区包括半导体材 料， 且具有 n型或 p型掺杂， 所述 n型或 p型掺杂为重掺杂， 所述半 导体掺杂区 206与所述栅极区 204相互隔离， 所述半导体掺杂区 206 为器件的源极区和漏极区； 形成于栅极区 204上的接触 209以及形成 于半导体掺杂区 206上的接触 209。
为了更好理解本发明， 以下将详细介绍 n型和 p型石墨烯器件的 能带图， 参考图 2和图 3所示， 所述 n型石墨烯器件指半导体掺杂区 为 n型掺杂， 所述 p型石墨烯器件指半导体掺杂区为 p型摻杂， 其中： Vgs为栅-源电压， Vds为漏-源电压， Vthn、 Vthp分别为 n型、 p型器 件的阈值电压。
参考图 2， 图 2为 n型石墨烯器件在各个工作模式下的能带图， 当 栅极偏置低于阈值电压时（此例为 Vgs≤0 ) , 器件处于在截止状态， 参 考图 2 中所示截止状态的能带图， 此时石墨烯中费米能级低于狄拉克 点， 因而载流子为空穴， 而由于两端半导体掺杂区为 n 型， 石墨烯中 的空穴需要越过较高的势垒才能到达源漏区， 因此器件关断， 并且漏 电流大小与势垒高度成指数反比。 当栅极偏置高于阈值电压时 ( Vgs>0 ) , 石墨烯内费米能级高于狄拉克点， 载流子为电子， 两端 n 型半导体掺杂区对电子基本不会形成势垒， 因而器件导通， 参考图 2 中所示的线性导电或饱和状态的能带图。 而由于此器件中对石墨烯的 带隙没有限制， 因而可以达到非常高的迁移率。
参考图 3， 图 3为 p型石墨烯器件在各个工作模式下的能带图， 当 栅极偏置高于阈值电压时 （Vgs≥0 ) ， 器件处于在截止状态， 参考图 3 所示截止状态的能带图， 此时石墨烯中费米能级高于狄拉克点， 载流 子为电子， 而由于两端半导体掺杂区为 p 型， 石墨烯中的电子需要越 过较高的势垒才能到达源漏区， 因此器件关断， 并且漏电流大小与势 垒高度成指数反比。 当栅极偏置低于阈值电压时 （Vgs<0 ) , 石墨烯内 费米能级低于狄拉克点， 载流子为空穴， 两端 p 型半导体掺杂区对空 穴基本不会形成势垒， 因而器件导通， 参考图 3 中所示的线性导电或 饱和状态的能带图。 而由于此器件中对石墨烯的带隙没有限制， 因而 可以达到非常高的迁移率。
以上对本发明所述的石墨烯器件及能带图进行了详细介绍， 通过 采用本发明石墨烯器件结构， 通过 n型或 p型的半导体掺杂区来提高 石墨烯器件的开关比， 同时不影响石墨烯载流子迁移率亦即不牺牲器 件的速度， 从而使石墨烯材料在 CMOS器件中的得到更好的应用。
以下将详细描述形成上述石墨烯器件的制造方法的一个实施例， 具体参考图 4-图 9B为本发明石墨烯器件制造方法实施例的中间步骤的 示意图， 包括俯视图、 AA'向视图、 BB，向视图。
在步骤 S01 ,提供衬底，所述衬底包括绝缘层以及其上的半导体层。 在本实施例中， 所述衬底可以是 SOI衬底 200， 参考图 4A所示， 所述
SOI衬底 200包括顶层硅 200-3、埋氧化层 200-2以及背衬底 200-1 , 所 述埋氧化层 200-2即为衬底的绝缘层， 所述顶层硅 200-3即为衬底的半 导体层。
在步骤 S02, 在所述衬底的半导体层 200-3内、 绝缘层 200-2上形 成包括栅电极 204-2和其上的栅介质层 204-1的背栅极区 204 , 所述栅 电极 204-2侧壁由隔离层 207包围， 以及在所述栅电极 204-2两侧的半 导体层 200-3 内形成半导体掺杂区 206， 参考图 5 (俯视图） 、 图 5A ( AA，向视图） 。
在本发明实施例中， 具体来说， 首先， 刻蚀所述顶层硅 200-3形成 栅沟槽， 并进行重离子掺杂， 以在栅沟槽两侧的顶层硅 200-3形成半导 体掺杂区 206,而后在栅沟槽的侧壁形成隔离层 207 ,例如 Si02或 Si3N4 等，而后在栅沟槽内形成栅电极 204-2 ,在本发明实施例中栅电极 204-2 包括多晶硅，在其他实施例中栅电极 204-2还可以包括金属等合适的材 料， 可以通过在所述器件上沉积多晶硅， 而后进行平坦化， 例如 CMP 的方法， 在栅沟槽内形成栅电极 204-2 , 可选地， 可以在所述多晶硅的 栅电极内形成与半导体掺杂区相同类型的掺杂， 参考图 4 (俯视图） 、 图 4A ( AA，向视图） 所示。 而后， 进一步去除半导体掺杂区 206上的 隔离层 207， 并在栅电极 204-2上形成栅介质层 204-1 , 从而形成背栅 极区 204, 参考图 5 (俯视图） 、 图 5A ( AA，向视图） 。 所述栅介质层 包括 Si02 SiON或高 k介质材料（和 Si02相比， 具有高的介电常数）。
在步骤 S03 , 部分覆盖所述背栅极区 204 以及半导体掺杂区 206 以形成石墨烯层 202。 在所述器件上形成石墨烯层， 并进行图形化， 在 栅长方向上形成部分覆盖所述背栅极区 204 以及半导体掺杂区 206的 石墨烯层， 参考图 6 (俯视图）、 图 6A ( AA，向视图）。 可以利用 CVD 热分解法、 微机械剥离法， 以及他们的键合转移法或其他合适的方法 来形成单层或多层的石墨烯材料。
在步骤 S04， 在所述器件上形成层间介质层 208 , 参考图 7 (俯视 图） 、 图 7A ( AA，向视图） 可以通过在所述器件上沉积介质材料， 例如 Si02 , 而后将其平坦化， 例如 CMP (化学机械抛光） 的方法， 形 成层间介质层 208 ,所述层间介质层 208可以是但不限于例如未掺杂的 氧化硅（ Si02 ) 、 掺杂的氧化硅（如硼硅玻璃、 硼磷硅玻璃等）和氮化 硅 ( Si3N4 )
在步骤 S05 , 在所述层间介质层 208内、 未被石墨烯层 206覆盖的 栅电极 204-2上形成接触 212, 以及在所述层间介质层 208内、 未被石 墨烯层 206覆盖的半导体摻杂区 206上形成接触 212， 参考图 9 (俯视 图） 、 图 9A ( AA，向视图） 和图 9B ( BB，向视图） 。 在本发明实施例 中， 具体来说， 首先， 通过掩膜刻蚀所述层间介质层 208 以及栅介质 层 204- 1 , 暴露所述栅电极 204-2以及半导体掺杂区 206以形成接触孔 210, 参考图 8 (俯视图） 、 图 8B ( BB，向视图 ) , 其中图 8A ( AA，向 视图） 为在该步骤时包括石墨烯层部分的器件的示意图。 而后， 用金 属材料， 例如 W Cu等， 填充所述接触孔 210以形成接触 212 , 参考 图 9 (俯视图） 、 图 9B ( BB，向视图） ， 其中图 9A ( AA，向视图 ) 为 在该步骤时包括石墨烯层部分的器件的示意图。 优选地， 在形成接触 212前可以对所述半导体掺杂层 206以及多晶硅栅电极 204-2进行金属 硅化， 形成金属硅化物层， 以减小接触电阻。
以上仅是实现本发明石墨烯器件结构的一个实施例， 所述制造方 所述石墨烯器件结构。 D 以上对形成本发明的石墨浠器件结构及制造方法的实施例进行了 详细的描述， 通过形成和石墨烯层接触的 n型或 p型的半导体掺杂层， 来提高石墨烯器件的开关比而不必增大石墨浠材料的带隙， 因而不影 响石墨烯器件中载流子的迁移率且由此不必牺牲器件的速度， 从而使 石墨烯材料在 CMOS器件中得到更好的应用。
虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离 本发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些 实施例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技 术人员应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次 序可以变化。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开 内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或 者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步 骤， 其中它们执行与本发明描述的对应实施例大体相同的功能或者获 得大体相同的结果， 依照本发明可以对它们进行应用。 因此, 本发明 所附权利要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法 或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种石墨烯器件结构， 所述结构包括：
石墨烯层；
与石墨烯层相接触的栅极区；
形成于栅极区两侧的、 与石墨烯层相接触的半导体掺杂区， 其中 所述半导体掺杂区与所述栅极区相互隔离；
形成于栅极区上的接触以及形成于半导体掺杂区上的接触。
2. 根据权利要求 1 所述的器件结构， 其中所述半导体掺杂区具有 n型或 p型掺杂。
3. 根据权利要求 1 所述的器件结构， 其中所述半导体掺杂区具有 重掺杂。
4. 根据权利要求 1 所述的器件结构， 其中所述栅极区包括栅介质 层和栅电极。
5. 根据权利要求 4所述的器件结构， 其中所述栅电极包括多晶硅 或金属材料。
6. 根据权利要求 1所述的器件结构，在所述器件施加特定电压时， 所述器件的工作电流的流向是从其一半导体掺杂区经石墨烯层到另一 半导体掺杂区。
7. 一种石墨烯器件的制造方法， 所述方法包括：
A、 提供衬底， 所述衬底包括绝缘层以及其上的半导体层；
B、 在所述衬底的半导体层内、 绝缘层上形成包括栅电极和其上的 栅介质层的背栅极区， 所述栅电极侧壁由隔离层包围， 以 在所述栅 电极两侧的半导体层内形成半导体掺杂区；
C、 部分覆盖所述背栅极区以及半导体掺杂区以形成石墨烯层；
D、 在所述器件上形成层间介质层；
E、在所述层间介质层内、未被石墨烯层覆盖的栅电极上形成接触， 以及在所述层间介质层内、 未被石墨烯层覆盖的半导体掺杂区上形成 接触。
8. 根据权利要求 7所述的方法， 其中所述衬底为 SOI衬底， 所述
SOI衬底包括顶层硅、 埋氧化层以及背衬底。
9. 根据权利要求 8所述的方法， 其中所述步骤 B包括： 刻蚀所述顶层硅， 以 ^成栅沟槽；
在栅沟槽两侧的顶层硅内形成半导体掺杂区；
在所述栅沟槽的侧壁形成隔离层， 以及栅沟槽内形成包括 电极 和其上的栅介质层的背栅极区。
10. 根据权利要求 7所述的方法，其中所述半导体掺杂区具有重掺 杂。
1 1. 根据权利要求 7所述的方法，其中所述半导体掺杂区具有 n型 或 p型掺杂。
12. 根据权利要求 7所述的方法，其中所述栅电极包括多晶硅或金 属材料。
PCT/CN2011/000291 2010-09-17 2011-02-24 一种石墨烯器件及其制造方法 WO2012034345A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/140,141 US8703558B2 (en) 2010-09-17 2011-02-24 Graphene device and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010287078.8 2010-09-17
CN2010102870788A CN102054869B (zh) 2010-09-17 2010-09-17 一种石墨烯器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2012034345A1 true WO2012034345A1 (zh) 2012-03-22

Family

ID=43959025

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/000291 WO2012034345A1 (zh) 2010-09-17 2011-02-24 一种石墨烯器件及其制造方法

Country Status (3)

Country Link
US (1) US8703558B2 (zh)
CN (1) CN102054869B (zh)
WO (1) WO2012034345A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL2649136T3 (pl) 2010-12-08 2016-04-29 Haydale Graphene Ind Plc Materiały rozdrobnione, kompozyty zawierające je oraz ich otrzymywanie i zastosowania
CN103107077B (zh) * 2011-11-14 2016-09-14 中国科学院微电子研究所 石墨烯器件及其制造方法
CN102566089B (zh) * 2012-01-10 2014-02-26 东南大学 基于石墨烯的表面等离子体极化波分束器
CN102593159A (zh) * 2012-03-20 2012-07-18 四川大学 一种增强型石墨烯场效应晶体管
US9472450B2 (en) * 2012-05-10 2016-10-18 Samsung Electronics Co., Ltd. Graphene cap for copper interconnect structures
CN102981060B (zh) * 2012-09-07 2014-12-03 清华大学 石墨烯量子电容测试器件及其制备方法
CN104867817A (zh) * 2015-05-21 2015-08-26 北京工业大学 一种薄膜平面化的半导体工艺
WO2017213929A1 (en) * 2016-06-07 2017-12-14 Board Of Regents, The University Of Texas System Integration of monolayer graphene with a semiconductor device
US10164018B1 (en) * 2017-05-30 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor interconnect structure having graphene-capped metal interconnects
CN109564921B (zh) * 2017-07-20 2022-01-11 华为技术有限公司 场效应管以及制造方法
US10304967B1 (en) 2018-03-02 2019-05-28 Texas Instruments Incorporated Integration of graphene and boron nitride hetero-structure device over semiconductor layer
CN112898953B (zh) * 2021-01-14 2021-12-28 扬州晟至宝新材料科技有限公司 一种石墨烯导热膜的制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101475160A (zh) * 2008-01-02 2009-07-08 国际商业机器公司 碳纳米管结构及其制造和操作方法
US20090236609A1 (en) * 2008-03-18 2009-09-24 Georgia Tech Research Corporation Method and Apparatus for Producing Graphene Oxide Layers on an Insulating Substrate
US20100006823A1 (en) * 2008-07-11 2010-01-14 International Business Machines Corporation Semiconducting Device Having Graphene Channel
US20100025660A1 (en) * 2008-07-31 2010-02-04 University Of Connecticut Semiconductor devices, methods of manufacture thereof and articles comprising the same
CN101783366A (zh) * 2010-02-11 2010-07-21 复旦大学 一种石墨烯mos晶体管的制备方法
CN101834206A (zh) * 2010-04-12 2010-09-15 清华大学 半导体器件结构及其形成方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285822A (ja) * 2004-03-26 2005-10-13 Fujitsu Ltd 半導体装置および半導体センサ
US8119032B2 (en) * 2006-02-07 2012-02-21 President And Fellows Of Harvard College Gas-phase functionalization of surfaces including carbon-based surfaces
US7619257B2 (en) * 2006-02-16 2009-11-17 Alcatel-Lucent Usa Inc. Devices including graphene layers epitaxially grown on single crystal substrates
US7714386B2 (en) * 2006-06-09 2010-05-11 Northrop Grumman Systems Corporation Carbon nanotube field effect transistor
US7732859B2 (en) * 2007-07-16 2010-06-08 International Business Machines Corporation Graphene-based transistor
US20090174435A1 (en) * 2007-10-01 2009-07-09 University Of Virginia Monolithically-Integrated Graphene-Nano-Ribbon (GNR) Devices, Interconnects and Circuits
JP5353009B2 (ja) * 2008-01-08 2013-11-27 富士通株式会社 半導体装置の製造方法および半導体装置
US7772059B2 (en) * 2008-01-16 2010-08-10 Texas Instruments Incorporated Method for fabricating graphene transistors on a silicon or SOI substrate
US7858989B2 (en) * 2008-08-29 2010-12-28 Globalfoundries Inc. Device and process of forming device with device structure formed in trench and graphene layer formed thereover
JP5544796B2 (ja) * 2009-09-10 2014-07-09 ソニー株式会社 ３端子型電子デバイス及び２端子型電子デバイス
US8124463B2 (en) * 2009-09-21 2012-02-28 International Business Machines Corporation Local bottom gates for graphene and carbon nanotube devices
US8673703B2 (en) * 2009-11-17 2014-03-18 International Business Machines Corporation Fabrication of graphene nanoelectronic devices on SOI structures

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101475160A (zh) * 2008-01-02 2009-07-08 国际商业机器公司 碳纳米管结构及其制造和操作方法
US20090236609A1 (en) * 2008-03-18 2009-09-24 Georgia Tech Research Corporation Method and Apparatus for Producing Graphene Oxide Layers on an Insulating Substrate
US20100006823A1 (en) * 2008-07-11 2010-01-14 International Business Machines Corporation Semiconducting Device Having Graphene Channel
US20100025660A1 (en) * 2008-07-31 2010-02-04 University Of Connecticut Semiconductor devices, methods of manufacture thereof and articles comprising the same
CN101783366A (zh) * 2010-02-11 2010-07-21 复旦大学 一种石墨烯mos晶体管的制备方法
CN101834206A (zh) * 2010-04-12 2010-09-15 清华大学 半导体器件结构及其形成方法

Also Published As

Publication number Publication date
US8703558B2 (en) 2014-04-22
US20120097923A1 (en) 2012-04-26
CN102054869A (zh) 2011-05-11
CN102054869B (zh) 2012-12-19

Similar Documents

Publication Publication Date Title
WO2012034345A1 (zh) 一种石墨烯器件及其制造方法
US10741646B2 (en) Field-effect transistors having contacts to 2D material active region
US11424244B2 (en) Integrated circuit having a vertical power MOS transistor
KR101729439B1 (ko) 매립된 절연체층을 가진 finfet 및 그 형성 방법
WO2012055196A1 (zh) 一种石墨烯器件及其制造方法
US9153657B2 (en) Semiconductor devices comprising a fin
US8445340B2 (en) Sacrificial offset protection film for a FinFET device
KR102528801B1 (ko) 상부 금속 루팅층에 리피터/버퍼를 포함하는 반도체 장치 및 그 제조 방법
TW202036662A (zh) 半導體裝置的形成方法
JP2006344836A (ja) 半導体装置及びその製造方法
KR20180036543A (ko) 반도체 소자 및 그 제조 방법
KR20140008225A (ko) 파워 ｍｏｓ 트랜지스터에 대한 장치 및 방법
CN105047711A (zh) 用于finfet器件的结构和方法
KR20220054777A (ko) 멀티 게이트 디바이스 및 관련 방법
WO2014029150A1 (zh) 一种半导体结构及其制造方法
WO2014056277A1 (zh) 半导体结构及其制造方法
US11581414B2 (en) Gate-all-around devices with optimized gate spacers and gate end dielectric
TW202133452A (zh) 半導體裝置之製造方法
US11239339B2 (en) Gate structure and method
CN105990229B (zh) 半导体器件及其制造工艺
US20120018739A1 (en) Body contact device structure and method of manufacture
CN103094217B (zh) 晶体管制作方法
US20140239387A1 (en) MOS Transistor Structure and Method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13140141

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11824416

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11824416

Country of ref document: EP

Kind code of ref document: A1