WO2012028077A1 - Ldmos device and method for manufacturing the same - Google Patents

Ldmos device and method for manufacturing the same Download PDF

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Publication number
WO2012028077A1
WO2012028077A1 PCT/CN2011/079041 CN2011079041W WO2012028077A1 WO 2012028077 A1 WO2012028077 A1 WO 2012028077A1 CN 2011079041 W CN2011079041 W CN 2011079041W WO 2012028077 A1 WO2012028077 A1 WO 2012028077A1
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WO
WIPO (PCT)
Prior art keywords
region
drift
ldmos device
gate
doping
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Application number
PCT/CN2011/079041
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English (en)
French (fr)
Inventor
Hsiao-Chia Wu
Tse-Huang Lo
Guipeng Sun
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Csmc Technologies Fab1 Co., Ltd
Csmc Technologies Fab2 Co., Ltd
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Application filed by Csmc Technologies Fab1 Co., Ltd, Csmc Technologies Fab2 Co., Ltd filed Critical Csmc Technologies Fab1 Co., Ltd
Publication of WO2012028077A1 publication Critical patent/WO2012028077A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect

Definitions

  • the present invention relates generally to a semiconductor device and more particularly to a Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) device and a method for manufacturing the same.
  • LDMOS Lateral Double-diffused Metal Oxide Semiconductor
  • the Lateral double-diffused MOS (LDMOS) transistor is a MOS device having a lightly doped drain. Because the LDMOS typically operates in a linear range and the electrical current thereof keeps constant, the power consumption of the LDMOS mainly depends upon the on-resistance value.
  • a drift region is arranged between an active region and the drain region.
  • the impurity concentration of the drift region is relatively low to keep electric fields low to improve the breakdown voltage. Therefore, when a high voltage is applied to the drain of the LDMOS, the depletion region in the drift region can spread out due to the low impurity concentration therein and thus keep electric fields low to improve the breakdown voltage of the device.
  • drift region is made by a relatively deep well to withstand the high voltage applied to the device. Since the well is relatively deep and the doping concentration at the surface relatively high, depletion of the whole drift region is difficult. Accordingly, the doping concentration of the drift region must be reduced to improve the withstand voltage, thus making device on-resistance and power consumption overly high under identical working current. Moreover, the dimensions of such lower-doped drift region devices are relatively large, which results in an increase in chip area, a lower degree of integration, and difficulty meeting the requirements of current circuit designs.
  • the present invention relates generally to a semiconductor device and more particularly to a Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) device and a method for manufacturing the same.
  • LDMOS Lateral Double-diffused Metal Oxide Semiconductor
  • a LDMOS device includes a source region, a gate region, a drain region, a body region located on a substrate region, and a drift region located between the drain region and the body region .
  • the doping type of the drift region is opposite to the doping type of the body region.
  • the LDMOS device further includes an insulation medium layer located on the drift region and under the gate region.
  • the LDMOS device further includes a graded channel doping P-body region located on the body region and under the source region.
  • t he insulation medium layer is a silicon dioxide layer .
  • the doping concentration of the drift region is between about 10 17 and about 10 18 cm -3
  • the junction depth of the drift region is between about 0.4 ⁇ m and about 2.0 ⁇ m.
  • the doping concentration of the body region is between about 10 17 and about 10 18 cm -3 .
  • the thickness of the insulation medium layer is not equal to that of a gate oxide layer.
  • a method of manufacturing a LDMOS device having a source region, a gate region, a drain region, a body region and a drift region with doping type opposite to the doping type of the body region.
  • the body region is located on a substrate region, the drift region is located between the drain region and the body region.
  • the method includes the step of growing an insulation medium layer on the drift region.
  • the LDMOS device further has a substrate contact region, a gate oxide layer, a gate side wall region located on both sides of the gate region, and a P-body region
  • the method of manufacturing a LDMOS device further includes the following steps.
  • a substrate is formed by standard well implantation process.
  • An isolation region is formed in the region of the LDMOS except where the channel region, the source region, the drain region, and the drift region may be later formed by layout of the active region by processing with a standard LOCOS or STI isolation process.
  • the drift region is lightly doped and the insulation medium layer is then grown to form the drift region of the LDMOS device.
  • the following steps are sequentially performed; forming the gate oxide layer, depositing and etching a gate material to form the gate region, implanting and annealing the P-body region, lightly doping the lightly doped drain region near the source contact region, forming the gate side wall, and performing implants of the source contact region, the drain contact region and the body contact region.
  • the following steps are sequentially performed; depositing an isolation layer, photo-lithographically etching a contact hole, depositing metal, photo-lithographically etching metal interconnects, depositing a passivation layer, and photo-lithographically etching contact pads.
  • a graded doping is performed for the drift region.
  • the surface region of the device is covered by silicon nitride except for the isolation region and the drift region.
  • FIG. 1 is a structural view of a LDMOS device, in accordance with a first embodiment of the present invention
  • FIG. 2 is a structural view of a LDMOS device, in accordance with a second embodiment of the present invention.
  • FIG. 3 is a structural view of a LDMOS device, in accordance with a third embodiment of the present invention.
  • a LDMOS device includes a substrate 101, a body region 103 (P-well), a body contact region 105, a source contact region 107, a drain contact region 109, a gate oxide layer 111, a gate region 113, a drift region 115, an insulation medium layer 117, a gate side wall region 119 located on both sides of the gate region 113, and a P-body region 121.
  • Insulation medium layer 117 may be located on drift region 115 and under gate region 113.
  • Insulation medium layer 117 may be an electrical insulating material such as silicon dioxide.
  • the thickness of insulation medium layer 117 may be relatively thin so as to improve the device's ability to withstand voltage breakdown.
  • the thickness of insulation medium layer 117 may be determined according to the requirements of the device and may be typically between the thickness of gate oxide layer 111 and the thickness of the field oxide isolation or STI. Thus, the thickness of insulation medium layer 117 may be in the range from tens of nanometers to several thousand angstroms thick.
  • the body region 103, p-body region 121, and body contact region 105 may be doped with impurities to form P-type conductivity regions, while source contact region 107, drain contact region 109, and drift region 115 may be doped with impurities to form N-type conductivity regions.
  • the conductivity type for each region may be opposite to that for the N-type LDMOS.
  • the concentration in body region 103 may be relatively high and may be between about 10 17 and 10 18 cm -3 so as to reduce body resistance and to prevent a parasitic bipolar device from conducting.
  • the doping concentration of drift region 115 may be between about 10 17 and about 10 18 cm -3 and the junction depth of drift region 115 may be between about 0.4 ⁇ m and about 2.0 ⁇ m deep.
  • the doping concentration in the drift region may be 7.5 x 10 16 cm -3 , and the junction depth of the drift region may be 2.0 ⁇ m.
  • a graded channel doped region may be formed in P-body region 121 so as to adjust the value of the threshold voltage, reduce substrate resistance, prevent the parasitic bipolar from conducting, increase the concentration in the body region, shorten channel length, reduce on-resistance, and decrease the area of the device.
  • the P-body region 121 is located on the body region and under the source region.
  • drift region 115 enhances the depletion of drift region 115 by means of insulation medium layer 117.
  • the depth of drift region 115 may be made shallower than the prior art devices while simultaneously the voltage breakdown ability of the device may be improved.
  • the doping concentration of the drift region may be higher, which may be advantageous to the reduction of on-resistance.
  • Fig. 2 shows a structural view of a LDMOS device, in accordance with a second embodiment of the present invention.
  • the P-body region 121 previously shown in Fig. 1 may be omitted so that the structure may be more simplified.
  • Fig. 3 shows a structural view of LDMOS device, in accordance with a third embodiment of the present invention.
  • the junction depth of body contact doping region 122 may be deeper than source contact region 107 or body contact region 105, which was shown in Figure 1 and Figure 2.
  • the doping concentration of body contact doping region 122 may be high so that the body resistance may be reduced and parasitic bipolar conduction may be prevented.
  • the manufacturing process for the LDMOS includes the following steps.
  • a body region is formed in the substrate by standard well implant processing.
  • an isolation region is formed in the region of the LDMOS except where the channel, source, drain, and drift regions may be later formed by layout of the active region and process ed with standard local oxidation of silicon (LOCOS) or shallow trench isolation (STI) process.
  • LOCOS local oxidation of silicon
  • STI shallow trench isolation
  • the following photo-etching steps are then performed on the silicon nitride to form the drift region with a mask for the drift region 115: (i) applying photoresist, (ii) exposing the photoresist, (iii) developing the photoresist, and (iv) etching the silicon nitride.
  • the lightly doped drift region is implanted and insulation medium layer 117 is grown annealing and driving the implant to form the drift region of the LDMOS device.
  • the doping of the drift region can be formed in a uniform manner, or by a graded doping in which the doping concentration slowly varies from the drain region to body region 103.
  • the depth of the grown insulation medium layer can be adjusted according to the requirements for the voltage withstand ability of the device. At this time, the surface region of the device is entirely covered by silicon nitride except for the isolation region and the drift region, and the growth of the insulation medium layer has little influence on other types of devices integrated with the LDMOS in an integrated circuit.
  • the gate, source and drain regions are formed by sequentially: (i) forming the gate oxide layer, (ii) depositing and etching the gate material to form the gate region, (iii) optionally implanting and annealing the P-body region, (iv) performing the lightly doped drain (LDD) doping implant only at the source end of the LDMOS, (v) forming the gate side walls, and (vii) then performing implants of the source contact region, the drain contact region and the body contact region to form the structure shown in Fig. 1.
  • the next steps sequentially, deposit an isolation layer, photo-lithographically etch contact holes, deposit a metal layer, photo-lithographically etch metal interconnects, depositing a passivation layer, and photo-lithographically etching contact pads.
  • Embodiments of the present invention provide a LDMOS device. It will be apparent to those with skill in the art that modifications to the above methods and apparatuses may occur without deviating from the scope of the present invention. All material types provided herein to describe various dimensions, doping concentrations, and different semiconducting or insulating layers are for illustrative purposes only and not intended to be limiting. For example, the doping polarity of various silicon regions in the embodiments described herein may be reversed to obtain the opposite polarity type device of the particular embodiment. Accordingly, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims along with their full scope of equivalents.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
PCT/CN2011/079041 2010-08-31 2011-08-29 Ldmos device and method for manufacturing the same WO2012028077A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010269279.5 2010-08-31
CN201010269279.5A CN102386211B (zh) 2010-08-31 2010-08-31 Ldmos器件及其制造方法

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150097238A1 (en) * 2013-10-07 2015-04-09 Freescale Semiconductor, Inc. Mergeable Semiconductor Device with Improved Reliability
CN112466955A (zh) * 2020-12-04 2021-03-09 重庆邮电大学 一种具有体内导电沟道的薄层soi-ldmos器件
CN115360230A (zh) * 2022-06-10 2022-11-18 广东省大湾区集成电路与系统应用研究院 Ldmos器件的制作方法和ldmos器件

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CN105448725B (zh) * 2014-08-26 2018-11-16 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN106158972B (zh) * 2015-09-03 2020-04-07 珀尔微斯电子有限公司 制造高压功率场效应管的系统及方法
KR102286013B1 (ko) * 2015-10-07 2021-08-05 에스케이하이닉스 시스템아이씨 주식회사 트랜치 절연 필드플레이트 및 금속 필드플레이트를 갖는 수평형 고전압 집적소자
CN107492497A (zh) * 2016-06-12 2017-12-19 中芯国际集成电路制造(上海)有限公司 晶体管的形成方法
WO2021128355A1 (zh) * 2019-12-27 2021-07-01 华为技术有限公司 横向扩散金属氧化物半导体晶体管及制造方法
CN112133740B (zh) * 2020-08-06 2024-05-24 互升科技(深圳)有限公司 一种多层外延mos管器件及其制备方法
CN111969038A (zh) * 2020-08-06 2020-11-20 互升科技(深圳)有限公司 一种场效应管制备方法及场效应管
CN113506743A (zh) * 2021-06-21 2021-10-15 上海华力集成电路制造有限公司 一种提高双扩散漏器件击穿电压的方法
CN117637840A (zh) * 2022-08-15 2024-03-01 无锡华润上华科技有限公司 横向扩散金属氧化物半导体器件及其制备方法

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150097238A1 (en) * 2013-10-07 2015-04-09 Freescale Semiconductor, Inc. Mergeable Semiconductor Device with Improved Reliability
US9117841B2 (en) * 2013-10-07 2015-08-25 Freescale Semiconductor, Inc. Mergeable semiconductor device with improved reliability
US9640635B2 (en) 2013-10-07 2017-05-02 Nxp Usa, Inc. Reliability in mergeable semiconductor devices
CN112466955A (zh) * 2020-12-04 2021-03-09 重庆邮电大学 一种具有体内导电沟道的薄层soi-ldmos器件
CN115360230A (zh) * 2022-06-10 2022-11-18 广东省大湾区集成电路与系统应用研究院 Ldmos器件的制作方法和ldmos器件
CN115360230B (zh) * 2022-06-10 2024-05-07 广东省大湾区集成电路与系统应用研究院 Ldmos器件的制作方法和ldmos器件

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CN102386211B (zh) 2014-01-08

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